From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 19464 invoked by alias); 21 Jun 2006 17:34:41 -0000 Received: (qmail 19043 invoked by uid 22791); 21 Jun 2006 17:34:39 -0000 X-Spam-Status: No, hits=-2.4 required=5.0 tests=AWL,BAYES_00,SPF_PASS X-Spam-Check-By: sourceware.org Received: from e4.ny.us.ibm.com (HELO e4.ny.us.ibm.com) (32.97.182.144) by sourceware.org (qpsmtpd/0.31) with ESMTP; Wed, 21 Jun 2006 17:34:37 +0000 Received: from d01relay02.pok.ibm.com (d01relay02.pok.ibm.com [9.56.227.234]) by e4.ny.us.ibm.com (8.12.11.20060308/8.12.11) with ESMTP id k5LHYZwX001019 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=FAIL) for ; Wed, 21 Jun 2006 13:34:35 -0400 Received: from d01av02.pok.ibm.com (d01av02.pok.ibm.com [9.56.224.216]) by d01relay02.pok.ibm.com (8.13.6/NCO/VER7.0) with ESMTP id k5LHYZcS207110 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Wed, 21 Jun 2006 13:34:35 -0400 Received: from d01av02.pok.ibm.com (loopback [127.0.0.1]) by d01av02.pok.ibm.com (8.12.11.20060308/8.13.3) with ESMTP id k5LHYZF8004425 for ; Wed, 21 Jun 2006 13:34:35 -0400 Received: from gorgor.pok.ibm.com (dyn9047021071.beaverton.ibm.com [9.47.21.71]) by d01av02.pok.ibm.com (8.12.11.20060308/8.12.11) with ESMTP id k5LHYYWO004302; Wed, 21 Jun 2006 13:34:34 -0400 Received: by gorgor.pok.ibm.com (Postfix, from userid 500) id DE27D808023; Wed, 21 Jun 2006 10:34:36 -0700 (PDT) Date: Wed, 21 Jun 2006 17:34:00 -0000 From: Mike Grundy To: Martin Schwidefsky Cc: jan.glauber@de.ibm.com, linux-kernel@vger.kernel.org, systemtap@sources.redhat.com Subject: Re: [PATCH] kprobes for s390 architecture Message-ID: <20060621173436.GA7834@localhost.localdomain> Mail-Followup-To: Martin Schwidefsky , jan.glauber@de.ibm.com, linux-kernel@vger.kernel.org, systemtap@sources.redhat.com References: <20060612131552.GA6647@localhost.localdomain> <1150141217.5495.72.camel@localhost> <20060621042804.GA20300@localhost.localdomain> <1150907920.8295.10.camel@localhost> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1150907920.8295.10.camel@localhost> User-Agent: Mutt/1.4.2.1i X-IsSubscribed: yes Mailing-List: contact systemtap-help@sourceware.org; run by ezmlm Precedence: bulk List-Subscribe: List-Post: List-Help: , Sender: systemtap-owner@sourceware.org X-SW-Source: 2006-q2/txt/msg00671.txt.bz2 On Wed, Jun 21, 2006 at 06:38:40PM +0200, Martin Schwidefsky wrote: > You misunderstood me here. I'm not talking about storing the same piece > of data to memory on each processor. I'm talking about isolating all > other cpus so that the initiating cpu can store the breakpoint to memory > without running into the danger that another cpu is trying to execute it > at the same time. But probably the store should be atomic in regard to > instruction fetching on the other cpus. It is only two bytes and it > should be aligned. So maybe something like this: void smp_replace_instruction(void *info) { struct ins_replace_args *parms; parms = (struct ins_replace_args *) info; *parms->addr = *parms->insn } void __kprobes arch_arm_kprobe(struct kprobe *p) { struct ins_replace_args parms; parms.addr = p->addr; parms.insn = BREAKPOINT_INSTRUCTION preempt_disable(); smp_call_function(smp_replace_instruction, &parms, 0, 1); preempt_enable(); } Thanks Mike