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* [SCM] archer-keiths-linespec-rewrite: * linespec.c (struct linespec): Add comment about the exclusivity of EXPRESSION. (linespec_keywords): Make static. (linespec_parse_basic): Stop processing input whenever a comma is seen as the first character of a token. (convert_linespec_to_sals): Merge function_symbols and minimal_symbols branches.
@ 2012-03-29 19:18 kseitz
0 siblings, 0 replies; only message in thread
From: kseitz @ 2012-03-29 19:18 UTC (permalink / raw)
To: archer-commits
The branch, archer-keiths-linespec-rewrite has been updated
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- Log -----------------------------------------------------------------
commit 94b015b421d5a7b29d82bd9ed322b8e7acabc42e
Author: Keith Seitz <keiths@redhat.com>
Date: Thu Mar 29 12:13:32 2012 -0700
* linespec.c (struct linespec): Add comment about the
exclusivity of EXPRESSION.
(linespec_keywords): Make static.
(linespec_parse_basic): Stop processing input whenever
a comma is seen as the first character of a token.
(convert_linespec_to_sals): Merge function_symbols and
minimal_symbols branches.
testsuite:
* gdb.cp/cplabel.exp: Add "c++" and "debug" flags for
compile. Check if skipping C++ tests.
commit f3482af10fcb2e76c955493c7afdb1f0bf05c34d
Merge: 6d860be 251109b
Author: Keith Seitz <keiths@redhat.com>
Date: Wed Mar 28 10:40:51 2012 -0700
Merge remote-tracking branch 'gdb/master' into archer-keiths-linespec-rewrite
-----------------------------------------------------------------------
Summary of changes:
bfd/version.h | 2 +-
gdb/ChangeLog | 75 ++-
gdb/MAINTAINERS | 2 +-
gdb/NEWS | 4 +
gdb/arm-linux-tdep.c | 5 +
gdb/arm-tdep.c | 2061 ++++++++++++++++++++++++++++++++++++++
gdb/arm-tdep.h | 5 +
gdb/breakpoint.c | 28 +-
gdb/cli/cli-setshow.c | 28 +-
gdb/disasm.c | 22 +-
gdb/doc/ChangeLog | 15 +
gdb/doc/gdb.texinfo | 22 +-
gdb/infcmd.c | 10 +-
gdb/linespec.c | 76 +-
gdb/m68klinux-nat.c | 10 +-
gdb/mi/mi-cmd-stack.c | 22 +-
gdb/mi/mi-main.c | 55 +-
gdb/osdata.c | 5 +-
gdb/stack.c | 34 +-
gdb/testsuite/gdb.cp/cplabel.exp | 4 +-
gdb/tracepoint.c | 3 -
gdb/ui-out.c | 37 +-
gdb/ui-out.h | 19 +-
gdb/version.in | 2 +-
sim/erc32/ChangeLog | 1 +
25 files changed, 2328 insertions(+), 219 deletions(-)
First 500 lines of diff:
diff --git a/bfd/version.h b/bfd/version.h
index 0912d1c..d9d8427 100644
--- a/bfd/version.h
+++ b/bfd/version.h
@@ -1,4 +1,4 @@
-#define BFD_VERSION_DATE 20120326
+#define BFD_VERSION_DATE 20120328
#define BFD_VERSION @bfd_version@
#define BFD_VERSION_STRING @bfd_version_package@ @bfd_version_string@
#define REPORT_BUGS_TO @report_bugs_to@
diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index 5304e17..0fb6602 100644
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,6 +1,77 @@
-2012-03-26 Oza Pawandeep <oza.pawandeep@gmail.com>
+2012-03-27 Pedro Alves <palves@redhat.com>
+
+ Eliminate struct ui_stream.
+
+ * ui-out.h (struct ui_stream): Delete.
+ (ui_out_field_stream): Adjust prototype.
+ (ui_out_stream_new, ui_out_stream_delete)
+ (make_cleanup_ui_out_stream_delete): Delete declarations.
+ * ui-out.c (ui_out_field_stream): Change prototype to take a
+ ui_file instead of a ui_stream. Adjust.
+ (ui_out_stream_new, ui_out_stream_delete, do_stream_delete)
+ (make_cleanup_ui_out_stream_delete): Delete.
+ * breakpoint.c (print_breakpoint_location)
+ (print_one_detail_ranged_breakpoint, print_it_watchpoint): Use
+ ui_file/mem_fileopen instead of ui_stream/ui_out_stream_new.
+ * disasm.c (dump_insns): Ditto.
+ (do_mixed_source_and_assembly, do_assembly_only): Adjust
+ prototype.
+ (gdb_disassembly): Use ui_file/mem_fileopen instead of
+ ui_stream/ui_out_stream_new.
+ * infcmd.c (print_return_value): Ditto.
+ * osdata.c (info_osdata_command): Don't allocate a local
+ ui_stream.
+ * stack.c (print_frame_arg, print_frame_args, print_frame): Use
+ ui_file/mem_fileopen instead of ui_stream/ui_out_stream_new.
+ * tracepoint.c (print_one_static_tracepoint_marker): Don't
+ allocate a local ui_stream.
+ * mi/mi-cmd-stack.c (list_arg_or_local): Use ui_file/mem_fileopen
+ instead of ui_stream/ui_out_stream_new.
+ (list_args_or_locals): Don't allocate a local ui_stream.
+ * mi/mi-main.c (get_register, mi_cmd_data_evaluate_expression)
+ (mi_cmd_data_read_memory): Use ui_file/mem_fileopen instead of
+ ui_stream/ui_out_stream_new.
+ * cli/cli-setshow.c (do_setshow_command): Ditto.
+
+2012-03-27 Oza Pawandeep <oza.pawandeep@gmail.com>
+
+ * arm-linux-tdep.c (arm_linux_init_abi): Call
+ set_gdbarch_process_record. Initialize `arm_swi_record' field.
+ * arm-tdep.c (arm_process_record): New function.
+ (deallocate_reg_mem): New function.
+ (decode_insn): New function.
+ (thumb_record_branch): New function.
+ (thumb_record_ldm_stm_swi(): New function.
+ (thumb_record_misc): New function.
+ (thumb_record_ld_st_stack): New function.
+ (thumb_record_ld_st_imm_offset): New function.
+ (thumb_record_ld_st_reg_offset(): New function.
+ (thumb_record_add_sub_cmp_mov): New function.
+ (thumb_record_shift_add_sub): New function.
+ (arm_record_coproc_data_proc): New function.
+ (arm_record_coproc): New function.
+ (arm_record_b_bl): New function.
+ (arm_record_ld_st_multiple): New function.
+ (arm_record_ld_st_reg_offset): New function.
+ (arm_record_ld_st_imm_offset): New function.
+ (arm_record_data_proc_imm): New function.
+ (arm_record_data_proc_misc_ld_str): New function.
+ (arm_record_extension_space): New function.
+ (arm_record_strx): New function.
+ (sbo_sbz): New function.
+ (struct insn_decode_record): New structure for arm insn record.
+ (REG_ALLOC): New macro for reg allocations.
+ (MEM_ALLOC): New macro for memory allocations.
+ * arm-tdep.h (struct gdbarch_tdep): New field 'arm_swi_record'.
+
+2012-03-27 Andreas Schwab <schwab@linux-m68k.org>
+
+ * m68klinux-nat.c (fetch_register): Fix strict-aliasing violation.
+ (store_register): Likewise.
+
+2012-03-26 Oza Pawandeep <oza.pawandeep@gmail.com>
- * MAINTAINERS (Write After Approval): Add myself to the list.
+ * MAINTAINERS (Write After Approval): Add myself to the list.
2012-03-25 Jan Kratochvil <jan.kratochvil@redhat.com>
diff --git a/gdb/MAINTAINERS b/gdb/MAINTAINERS
index 6dc5d67..3cf2c97 100644
--- a/gdb/MAINTAINERS
+++ b/gdb/MAINTAINERS
@@ -583,6 +583,7 @@ Hans-Peter Nilsson hp@bitrange.com
David O'Brien obrien@freebsd.org
Alexandre Oliva aoliva@redhat.com
Karen Osmond karen.osmond@gmail.com
+Pawandeep Oza oza.pawandeep@gmail.com
Denis Pilat denis.pilat@st.com
Kevin Pouget kevin.pouget@st.com
Paul Pluzhnikov ppluzhnikov@google.com
@@ -649,7 +650,6 @@ Jie Zhang jzhang918@gmail.com
Wu Zhou woodzltc@cn.ibm.com
Yoshinori Sato ysato@users.sourceforge.jp
Hui Zhu teawater@gmail.com
-Oza Pawandeep oza.pawandeep@gmail.com
Past Maintainers
diff --git a/gdb/NEWS b/gdb/NEWS
index f21921a..8ff7876 100644
--- a/gdb/NEWS
+++ b/gdb/NEWS
@@ -3,6 +3,10 @@
*** Changes since GDB 7.4
+* GDB now supports reversible debugging on ARM, it allows you to
+ debug basic ARM and THUMB instructions, and provides
+ record/replay support.
+
* The option "symbol-reloading" has been deleted as it is no longer used.
* Python scripting
diff --git a/gdb/arm-linux-tdep.c b/gdb/arm-linux-tdep.c
index e41205b..486e6ed 100644
--- a/gdb/arm-linux-tdep.c
+++ b/gdb/arm-linux-tdep.c
@@ -1155,8 +1155,13 @@ arm_linux_init_abi (struct gdbarch_info info,
simple_displaced_step_free_closure);
set_gdbarch_displaced_step_location (gdbarch, displaced_step_at_entry_point);
+ /* Reversible debugging, process record. */
+ set_gdbarch_process_record (gdbarch, arm_process_record);
tdep->syscall_next_pc = arm_linux_syscall_next_pc;
+
+ /* Syscall record. */
+ tdep->arm_swi_record = NULL;
}
/* Provide a prototype to silence -Wmissing-prototypes. */
diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
index a3cdc7c..08c5ed4 100644
--- a/gdb/arm-tdep.c
+++ b/gdb/arm-tdep.c
@@ -55,6 +55,8 @@
#include "gdb_assert.h"
#include "vec.h"
+#include "record.h"
+
#include "features/arm-with-m.c"
#include "features/arm-with-m-fpa-layout.c"
#include "features/arm-with-iwmmxt.c"
@@ -10444,3 +10446,2062 @@ vfp - VFP co-processor."),
NULL, /* FIXME: i18n: "ARM debugging is %s. */
&setdebuglist, &showdebuglist);
}
+
+/* ARM-reversible process record data structures. */
+
+#define ARM_INSN_SIZE_BYTES 4
+#define THUMB_INSN_SIZE_BYTES 2
+#define THUMB2_INSN_SIZE_BYTES 4
+
+
+#define INSN_S_L_BIT_NUM 20
+
+#define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
+ do \
+ { \
+ unsigned int reg_len = LENGTH; \
+ if (reg_len) \
+ { \
+ REGS = XNEWVEC (uint32_t, reg_len); \
+ memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
+ } \
+ } \
+ while (0)
+
+#define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
+ do \
+ { \
+ unsigned int mem_len = LENGTH; \
+ if (mem_len) \
+ { \
+ MEMS = XNEWVEC (struct arm_mem_r, mem_len); \
+ memcpy(&MEMS->len, &RECORD_BUF[0], \
+ sizeof(struct arm_mem_r) * LENGTH); \
+ } \
+ } \
+ while (0)
+
+/* Checks whether insn is already recorded or yet to be decoded. (boolean expression). */
+#define INSN_RECORDED(ARM_RECORD) \
+ (0 != (ARM_RECORD)->reg_rec_count || 0 != (ARM_RECORD)->mem_rec_count)
+
+/* ARM memory record structure. */
+struct arm_mem_r
+{
+ uint32_t len; /* Record length. */
+ CORE_ADDR addr; /* Memory address. */
+};
+
+/* ARM instruction record contains opcode of current insn
+ and execution state (before entry to decode_insn()),
+ contains list of to-be-modified registers and
+ memory blocks (on return from decode_insn()). */
+
+typedef struct insn_decode_record_t
+{
+ struct gdbarch *gdbarch;
+ struct regcache *regcache;
+ CORE_ADDR this_addr; /* Address of the insn being decoded. */
+ uint32_t arm_insn; /* Should accommodate thumb. */
+ uint32_t cond; /* Condition code. */
+ uint32_t opcode; /* Insn opcode. */
+ uint32_t decode; /* Insn decode bits. */
+ uint32_t mem_rec_count; /* No of mem records. */
+ uint32_t reg_rec_count; /* No of reg records. */
+ uint32_t *arm_regs; /* Registers to be saved for this record. */
+ struct arm_mem_r *arm_mems; /* Memory to be saved for this record. */
+} insn_decode_record;
+
+
+/* Checks ARM SBZ and SBO mandatory fields. */
+
+static int
+sbo_sbz (uint32_t insn, uint32_t bit_num, uint32_t len, uint32_t sbo)
+{
+ uint32_t ones = bits (insn, bit_num - 1, (bit_num -1) + (len - 1));
+
+ if (!len)
+ return 1;
+
+ if (!sbo)
+ ones = ~ones;
+
+ while (ones)
+ {
+ if (!(ones & sbo))
+ {
+ return 0;
+ }
+ ones = ones >> 1;
+ }
+ return 1;
+}
+
+typedef enum
+{
+ ARM_RECORD_STRH=1,
+ ARM_RECORD_STRD
+} arm_record_strx_t;
+
+typedef enum
+{
+ ARM_RECORD=1,
+ THUMB_RECORD,
+ THUMB2_RECORD
+} record_type_t;
+
+
+static int
+arm_record_strx (insn_decode_record *arm_insn_r, uint32_t *record_buf,
+ uint32_t *record_buf_mem, arm_record_strx_t str_type)
+{
+
+ struct regcache *reg_cache = arm_insn_r->regcache;
+ ULONGEST u_regval[2]= {0};
+
+ uint32_t reg_src1 = 0, reg_src2 = 0;
+ uint32_t immed_high = 0, immed_low = 0,offset_8 = 0, tgt_mem_addr = 0;
+ uint32_t opcode1 = 0;
+
+ arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
+ arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
+ opcode1 = bits (arm_insn_r->arm_insn, 20, 24);
+
+
+ if (14 == arm_insn_r->opcode || 10 == arm_insn_r->opcode)
+ {
+ /* 1) Handle misc store, immediate offset. */
+ immed_low = bits (arm_insn_r->arm_insn, 0, 3);
+ immed_high = bits (arm_insn_r->arm_insn, 8, 11);
+ reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
+ regcache_raw_read_unsigned (reg_cache, reg_src1,
+ &u_regval[0]);
+ if (ARM_PC_REGNUM == reg_src1)
+ {
+ /* If R15 was used as Rn, hence current PC+8. */
+ u_regval[0] = u_regval[0] + 8;
+ }
+ offset_8 = (immed_high << 4) | immed_low;
+ /* Calculate target store address. */
+ if (14 == arm_insn_r->opcode)
+ {
+ tgt_mem_addr = u_regval[0] + offset_8;
+ }
+ else
+ {
+ tgt_mem_addr = u_regval[0] - offset_8;
+ }
+ if (ARM_RECORD_STRH == str_type)
+ {
+ record_buf_mem[0] = 2;
+ record_buf_mem[1] = tgt_mem_addr;
+ arm_insn_r->mem_rec_count = 1;
+ }
+ else if (ARM_RECORD_STRD == str_type)
+ {
+ record_buf_mem[0] = 4;
+ record_buf_mem[1] = tgt_mem_addr;
+ record_buf_mem[2] = 4;
+ record_buf_mem[3] = tgt_mem_addr + 4;
+ arm_insn_r->mem_rec_count = 2;
+ }
+ }
+ else if (12 == arm_insn_r->opcode || 8 == arm_insn_r->opcode)
+ {
+ /* 2) Store, register offset. */
+ /* Get Rm. */
+ reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
+ /* Get Rn. */
+ reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
+ regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
+ regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
+ if (15 == reg_src2)
+ {
+ /* If R15 was used as Rn, hence current PC+8. */
+ u_regval[0] = u_regval[0] + 8;
+ }
+ /* Calculate target store address, Rn +/- Rm, register offset. */
+ if (12 == arm_insn_r->opcode)
+ {
+ tgt_mem_addr = u_regval[0] + u_regval[1];
+ }
+ else
+ {
+ tgt_mem_addr = u_regval[1] - u_regval[0];
+ }
+ if (ARM_RECORD_STRH == str_type)
+ {
+ record_buf_mem[0] = 2;
+ record_buf_mem[1] = tgt_mem_addr;
+ arm_insn_r->mem_rec_count = 1;
+ }
+ else if (ARM_RECORD_STRD == str_type)
+ {
+ record_buf_mem[0] = 4;
+ record_buf_mem[1] = tgt_mem_addr;
+ record_buf_mem[2] = 4;
+ record_buf_mem[3] = tgt_mem_addr + 4;
+ arm_insn_r->mem_rec_count = 2;
+ }
+ }
+ else if (11 == arm_insn_r->opcode || 15 == arm_insn_r->opcode
+ || 2 == arm_insn_r->opcode || 6 == arm_insn_r->opcode)
+ {
+ /* 3) Store, immediate pre-indexed. */
+ /* 5) Store, immediate post-indexed. */
+ immed_low = bits (arm_insn_r->arm_insn, 0, 3);
+ immed_high = bits (arm_insn_r->arm_insn, 8, 11);
+ offset_8 = (immed_high << 4) | immed_low;
+ reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
+ regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
+ /* Calculate target store address, Rn +/- Rm, register offset. */
+ if (15 == arm_insn_r->opcode || 6 == arm_insn_r->opcode)
+ {
+ tgt_mem_addr = u_regval[0] + offset_8;
+ }
+ else
+ {
+ tgt_mem_addr = u_regval[0] - offset_8;
+ }
+ if (ARM_RECORD_STRH == str_type)
+ {
+ record_buf_mem[0] = 2;
+ record_buf_mem[1] = tgt_mem_addr;
+ arm_insn_r->mem_rec_count = 1;
+ }
+ else if (ARM_RECORD_STRD == str_type)
+ {
+ record_buf_mem[0] = 4;
+ record_buf_mem[1] = tgt_mem_addr;
+ record_buf_mem[2] = 4;
+ record_buf_mem[3] = tgt_mem_addr + 4;
+ arm_insn_r->mem_rec_count = 2;
+ }
+ /* Record Rn also as it changes. */
+ *(record_buf) = bits (arm_insn_r->arm_insn, 16, 19);
+ arm_insn_r->reg_rec_count = 1;
+ }
+ else if (9 == arm_insn_r->opcode || 13 == arm_insn_r->opcode
+ || 0 == arm_insn_r->opcode || 4 == arm_insn_r->opcode)
+ {
+ /* 4) Store, register pre-indexed. */
+ /* 6) Store, register post -indexed. */
+ reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
+ reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
+ regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
+ regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
+ /* Calculate target store address, Rn +/- Rm, register offset. */
+ if (13 == arm_insn_r->opcode || 4 == arm_insn_r->opcode)
+ {
+ tgt_mem_addr = u_regval[0] + u_regval[1];
+ }
+ else
+ {
+ tgt_mem_addr = u_regval[1] - u_regval[0];
+ }
+ if (ARM_RECORD_STRH == str_type)
+ {
+ record_buf_mem[0] = 2;
+ record_buf_mem[1] = tgt_mem_addr;
+ arm_insn_r->mem_rec_count = 1;
+ }
+ else if (ARM_RECORD_STRD == str_type)
+ {
+ record_buf_mem[0] = 4;
+ record_buf_mem[1] = tgt_mem_addr;
+ record_buf_mem[2] = 4;
+ record_buf_mem[3] = tgt_mem_addr + 4;
+ arm_insn_r->mem_rec_count = 2;
+ }
+ /* Record Rn also as it changes. */
+ *(record_buf) = bits (arm_insn_r->arm_insn, 16, 19);
+ arm_insn_r->reg_rec_count = 1;
+ }
+ return 0;
+}
+
+/* Handling ARM extension space insns. */
+
+static int
+arm_record_extension_space (insn_decode_record *arm_insn_r)
+{
+ uint32_t ret = 0; /* Return value: -1:record failure ; 0:success */
+ uint32_t opcode1 = 0, opcode2 = 0, insn_op1 = 0;
+ uint32_t record_buf[8], record_buf_mem[8];
+ uint32_t reg_src1 = 0;
+ uint32_t immed_high = 0, immed_low = 0,offset_8 = 0, tgt_mem_addr = 0;
+ struct regcache *reg_cache = arm_insn_r->regcache;
+ ULONGEST u_regval = 0;
+
+ gdb_assert (!INSN_RECORDED(arm_insn_r));
+ /* Handle unconditional insn extension space. */
+
+ opcode1 = bits (arm_insn_r->arm_insn, 20, 27);
+ opcode2 = bits (arm_insn_r->arm_insn, 4, 7);
+ if (arm_insn_r->cond)
+ {
+ /* PLD has no affect on architectural state, it just affects
+ the caches. */
+ if (5 == ((opcode1 & 0xE0) >> 5))
+ {
+ /* BLX(1) */
+ record_buf[0] = ARM_PS_REGNUM;
+ record_buf[1] = ARM_LR_REGNUM;
+ arm_insn_r->reg_rec_count = 2;
+ }
+ /* STC2, LDC2, MCR2, MRC2, CDP2: <TBD>, co-processor insn. */
+ }
+
+
+ opcode1 = bits (arm_insn_r->arm_insn, 25, 27);
+ if (3 == opcode1 && bit (arm_insn_r->arm_insn, 4))
+ {
+ ret = -1;
+ /* Undefined instruction on ARM V5; need to handle if later
+ versions define it. */
+ }
+
+ opcode1 = bits (arm_insn_r->arm_insn, 24, 27);
+ opcode2 = bits (arm_insn_r->arm_insn, 4, 7);
+ insn_op1 = bits (arm_insn_r->arm_insn, 20, 23);
+
+ /* Handle arithmetic insn extension space. */
+ if (!opcode1 && 9 == opcode2 && 1 != arm_insn_r->cond
+ && !INSN_RECORDED(arm_insn_r))
+ {
+ /* Handle MLA(S) and MUL(S). */
+ if (0 <= insn_op1 && 3 >= insn_op1)
+ {
+ record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
+ record_buf[1] = ARM_PS_REGNUM;
+ arm_insn_r->reg_rec_count = 2;
+ }
+ else if (4 <= insn_op1 && 15 >= insn_op1)
+ {
+ /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
+ record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19);
+ record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15);
+ record_buf[2] = ARM_PS_REGNUM;
hooks/post-receive
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Repository for Project Archer.
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2012-03-29 19:18 [SCM] archer-keiths-linespec-rewrite: * linespec.c (struct linespec): Add comment about the exclusivity of EXPRESSION. (linespec_keywords): Make static. (linespec_parse_basic): Stop processing input whenever a comma is seen as the first character of a token. (convert_linespec_to_sals): Merge function_symbols and minimal_symbols branches kseitz
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