From: Philipp Tomsich <ptomsich@sourceware.org>
To: bfd-cvs@sourceware.org
Subject: [binutils-gdb] RISC-V: Add generic support for vendor extensions
Date: Thu, 22 Sep 2022 16:42:50 +0000 (GMT) [thread overview]
Message-ID: <20220922164250.69AB13858D38@sourceware.org> (raw)
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=fb1737381d886c7c0a4e870af078c473ac463fce
commit fb1737381d886c7c0a4e870af078c473ac463fce
Author: Christoph Müllner <christoph.muellner@vrull.eu>
Date: Tue Jun 28 17:42:58 2022 +0200
RISC-V: Add generic support for vendor extensions
This patch introduces changes that allow the integration of vendor ISA
extensions:
* Define a list of vendor extensions (riscv_supported_vendor_x_ext)
where vendor extensions can be added
* Introduce a section with a table in the documentation where vendor
extensions can be added
To add a vendor extension that consists of instructions only,
the following things need to be done:
* Add the extension to the riscv_supported_vendor_x_ext list
* Add lookup entry in riscv_multi_subset_supports
* Documenting the extension in c-riscv.texti
* Add test cases for all instructions
* Add MATCH*/MASK* constants and DECLARE_INSN() for all instructions
* Add new instruction class to enum riscv_insn_class
* Define the instructions in riscv_opcodes
* Additional changes if necessary (depending on the instructions)
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Diff:
---
bfd/elfxx-riscv.c | 9 +++++++--
gas/doc/c-riscv.texi | 14 ++++++++++++++
2 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 7eda177bd6e..cb3a980936d 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1222,12 +1222,18 @@ static struct riscv_supported_ext riscv_supported_std_zxm_ext[] =
{NULL, 0, 0, 0, 0}
};
+static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
+{
+ {NULL, 0, 0, 0, 0}
+};
+
const struct riscv_supported_ext *riscv_all_supported_ext[] =
{
riscv_supported_std_ext,
riscv_supported_std_z_ext,
riscv_supported_std_s_ext,
riscv_supported_std_zxm_ext,
+ riscv_supported_vendor_x_ext,
NULL
};
@@ -1483,8 +1489,7 @@ riscv_get_default_ext_version (enum riscv_spec_class *default_isa_spec,
case RV_ISA_CLASS_ZXM: table = riscv_supported_std_zxm_ext; break;
case RV_ISA_CLASS_Z: table = riscv_supported_std_z_ext; break;
case RV_ISA_CLASS_S: table = riscv_supported_std_s_ext; break;
- case RV_ISA_CLASS_X:
- break;
+ case RV_ISA_CLASS_X: table = riscv_supported_vendor_x_ext; break;
default:
table = riscv_supported_std_ext;
}
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 21d867e9cf0..30afd200b7d 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -20,6 +20,7 @@
* RISC-V-Modifiers:: RISC-V Assembler Modifiers
* RISC-V-Formats:: RISC-V Instruction Formats
* RISC-V-ATTRIBUTE:: RISC-V Object Attribute
+* RISC-V-CustomExts:: RISC-V Custom (Vendor-Defined) Extensions
@end menu
@node RISC-V-Options
@@ -692,3 +693,16 @@ the privileged specification. It will report errors if object files of
different privileged specification versions are merged.
@end table
+
+@node RISC-V-CustomExts
+@section RISC-V Custom (Vendor-Defined) Extensions
+@cindex custom (vendor-defined) extensions, RISC-V
+@cindex RISC-V custom (vendor-defined) extensions
+
+The following table lists the custom (vendor-defined) RISC-V
+extensions supported and provides the location of their
+publicly-released documentation:
+
+@table @r
+
+@end table
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