[binutils-gdb] aarch64: Restrict range of PRFM opcodes

[binutils-gdb] aarch64: Restrict range of PRFM opcodes

[Richard Sandiford]

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=89f55b440abdffea9046e225918b5ceb6a57ab85

commit 89f55b440abdffea9046e225918b5ceb6a57ab85
Author: Richard Sandiford <richard.sandiford@arm.com>
Date:   Thu Mar 30 11:09:02 2023 +0100

    aarch64: Restrict range of PRFM opcodes
    
    In the register-index forms of PRFM, the unallocated prefetch opcodes
    24-31 have been reused for the encoding of the new RPRFM instruction.
    The PRFM opcode space is now capped at 23 for these forms.  The other
    forms of PRFM are unaffected.

Diff:
---
 gas/testsuite/gas/aarch64/illegal.l |  6 +++++-
 gas/testsuite/gas/aarch64/illegal.s |  5 +++++
 gas/testsuite/gas/aarch64/system.d  | 18 ++----------------
 gas/testsuite/gas/aarch64/system.s  |  5 +++++
 opcodes/aarch64-opc.c               |  9 +++++++++
 5 files changed, 26 insertions(+), 17 deletions(-)

diff --git a/gas/testsuite/gas/aarch64/illegal.l b/gas/testsuite/gas/aarch64/illegal.l
index 65bd38afd7a..ae9bb939728 100644
--- a/gas/testsuite/gas/aarch64/illegal.l
+++ b/gas/testsuite/gas/aarch64/illegal.l
@@ -879,4 +879,8 @@
 [^:]*:593: Error: .*`st2 {v0\.16b-v1\.16b}\[1\],\[x0\]'
 [^:]*:594: Error: .*`st3 {v0\.16b-v2\.16b}\[2\],\[x0\]'
 [^:]*:595: Error: .*`st4 {v0\.8b-v3\.8b}\[4\],\[x0\]'
-[^:]*:597: Error: .*
+[^:]*:597: Error: the register-index form of PRFM does not accept opcodes in the range 24-31 at operand 1 -- `prfm #0x18,\[sp,x15,lsl#0\]'
+[^:]*:598: Error: the register-index form of PRFM does not accept opcodes in the range 24-31 at operand 1 -- `prfm #0x1f,\[sp,x15,lsl#0\]'
+[^:]*:599: Error: immediate value out of range 0 to 31 at operand 1 -- `prfm #0x20,\[sp,x15,lsl#0\]'
+[^:]*:600: Error: immediate value out of range 0 to 31 at operand 1 -- `prfm #0x20,FOO'
+[^:]*:602: Error: .*
diff --git a/gas/testsuite/gas/aarch64/illegal.s b/gas/testsuite/gas/aarch64/illegal.s
index 384b673e8fb..6fb637ab923 100644
--- a/gas/testsuite/gas/aarch64/illegal.s
+++ b/gas/testsuite/gas/aarch64/illegal.s
@@ -594,4 +594,9 @@ one_label:
 	st3 {v0.16b-v2.16b}[2],[x0]
 	st4 {v0.8b-v3.8b}[4],[x0]
 
+	prfm	#0x18, [sp, x15, lsl #0]
+	prfm	#0x1f, [sp, x15, lsl #0]
+	prfm	#0x20, [sp, x15, lsl #0]
+	prfm	#0x20, FOO
+
 	// End (for errors during literal pool generation)
diff --git a/gas/testsuite/gas/aarch64/system.d b/gas/testsuite/gas/aarch64/system.d
index 93c84a72982..7e4bafbf1ff 100644
--- a/gas/testsuite/gas/aarch64/system.d
+++ b/gas/testsuite/gas/aarch64/system.d
@@ -330,43 +330,27 @@ Disassembly of section \.text:
 .*:	f9800c77 	prfm	#0x17, \[x3, #24\]
 .*:	d8000018 	prfm	#0x18, 0 <LABEL1>
 .*: R_AARCH64_(P32_|)LD_PREL_LO19	LABEL1
-.*:	f8af6bf8 	prfm	#0x18, \[sp, x15\]
-.*:	f8be58f8 	prfm	#0x18, \[x7, w30, uxtw #3\]
 .*:	f9800c78 	prfm	#0x18, \[x3, #24\]
 .*:	d8000019 	prfm	#0x19, 0 <LABEL1>
 .*: R_AARCH64_(P32_|)LD_PREL_LO19	LABEL1
-.*:	f8af6bf9 	prfm	#0x19, \[sp, x15\]
-.*:	f8be58f9 	prfm	#0x19, \[x7, w30, uxtw #3\]
 .*:	f9800c79 	prfm	#0x19, \[x3, #24\]
 .*:	d800001a 	prfm	#0x1a, 0 <LABEL1>
 .*: R_AARCH64_(P32_|)LD_PREL_LO19	LABEL1
-.*:	f8af6bfa 	prfm	#0x1a, \[sp, x15\]
-.*:	f8be58fa 	prfm	#0x1a, \[x7, w30, uxtw #3\]
 .*:	f9800c7a 	prfm	#0x1a, \[x3, #24\]
 .*:	d800001b 	prfm	#0x1b, 0 <LABEL1>
 .*: R_AARCH64_(P32_|)LD_PREL_LO19	LABEL1
-.*:	f8af6bfb 	prfm	#0x1b, \[sp, x15\]
-.*:	f8be58fb 	prfm	#0x1b, \[x7, w30, uxtw #3\]
 .*:	f9800c7b 	prfm	#0x1b, \[x3, #24\]
 .*:	d800001c 	prfm	#0x1c, 0 <LABEL1>
 .*: R_AARCH64_(P32_|)LD_PREL_LO19	LABEL1
-.*:	f8af6bfc 	prfm	#0x1c, \[sp, x15\]
-.*:	f8be58fc 	prfm	#0x1c, \[x7, w30, uxtw #3\]
 .*:	f9800c7c 	prfm	#0x1c, \[x3, #24\]
 .*:	d800001d 	prfm	#0x1d, 0 <LABEL1>
 .*: R_AARCH64_(P32_|)LD_PREL_LO19	LABEL1
-.*:	f8af6bfd 	prfm	#0x1d, \[sp, x15\]
-.*:	f8be58fd 	prfm	#0x1d, \[x7, w30, uxtw #3\]
 .*:	f9800c7d 	prfm	#0x1d, \[x3, #24\]
 .*:	d800001e 	prfm	#0x1e, 0 <LABEL1>
 .*: R_AARCH64_(P32_|)LD_PREL_LO19	LABEL1
-.*:	f8af6bfe 	prfm	#0x1e, \[sp, x15\]
-.*:	f8be58fe 	prfm	#0x1e, \[x7, w30, uxtw #3\]
 .*:	f9800c7e 	prfm	#0x1e, \[x3, #24\]
 .*:	d800001f 	prfm	#0x1f, 0 <LABEL1>
 .*: R_AARCH64_(P32_|)LD_PREL_LO19	LABEL1
-.*:	f8af6bff 	prfm	#0x1f, \[sp, x15\]
-.*:	f8be58ff 	prfm	#0x1f, \[x7, w30, uxtw #3\]
 .*:	f9800c7f 	prfm	#0x1f, \[x3, #24\]
 .*:	f9800c60 	prfm	pldl1keep, \[x3, #24\]
 .*:	f9800c61 	prfm	pldl1strm, \[x3, #24\]
@@ -386,3 +370,5 @@ Disassembly of section \.text:
 .*:	f9800c73 	prfm	pstl2strm, \[x3, #24\]
 .*:	f9800c74 	prfm	pstl3keep, \[x3, #24\]
 .*:	f9800c75 	prfm	pstl3strm, \[x3, #24\]
+.*:	f8a04817 	prfm	#0x17, \[x0, w0, uxtw\]
+.*:	f8a04818 	\.inst	0xf8a04818 ; undefined
diff --git a/gas/testsuite/gas/aarch64/system.s b/gas/testsuite/gas/aarch64/system.s
index 4d24d9a7614..48e7bfeb103 100644
--- a/gas/testsuite/gas/aarch64/system.s
+++ b/gas/testsuite/gas/aarch64/system.s
@@ -70,8 +70,10 @@
 
 	.macro	all_prefetchs op, from=0, to=31
 	\op	\from, LABEL1
+	.if	\from < 24
 	\op	\from, [sp, x15, lsl #0]
 	\op	\from, [x7, w30, uxtw #3]
+	.endif
 	\op	\from, [x3, #24]
 	.if	\to-\from
 	all_prefetchs \op, "(\from+1)", \to
@@ -91,3 +93,6 @@
 	.endr
 	.endr
 	.endr
+
+	.inst	0xf8a04817
+	.inst	0xf8a04818
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index e271b0d5e8e..a0e6240592c 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -2599,6 +2599,15 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
 	      return 0;
 	    }
 	  break;
+	case AARCH64_OPND_PRFOP:
+	  if (opcode->iclass == ldst_regoff && opnd->prfop->value >= 24)
+	    {
+	      set_other_error (mismatch_detail, idx,
+			       _("the register-index form of PRFM does"
+				 " not accept opcodes in the range 24-31"));
+	      return 0;
+	    }
+	  break;
 	default:
 	  break;
 	}