[binutils-gdb] aarch64: Fix SVE2 register/immediate distinction

[binutils-gdb] aarch64: Fix SVE2 register/immediate distinction

[Richard Sandiford]

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=eee2ecccdaa37d6c5d283d6346f70897ba27166b

commit eee2ecccdaa37d6c5d283d6346f70897ba27166b
Author: Richard Sandiford <richard.sandiford@arm.com>
Date:   Thu Mar 30 11:09:02 2023 +0100

    aarch64: Fix SVE2 register/immediate distinction
    
    GAS refuses to interpret register names like x0 as unadorned
    immediates, due to the obvious potential for confusion with
    register operands.  (An explicit #x0 is OK.)
    
    For compatibility reasons, we can't extend the set of registers
    that GAS rejects for existing instructions.  For example:
    
       mov x0, z0
    
    was valid code before SVE was added, so it needs to stay valid
    code even when SVE is enabled.  But we can make GAS reject newer
    registers in newer instructions.  The SVE instruction:
    
       and z0.s, z0.s, z0.h
    
    is therefore invalid, rather than z0.h being an immediate.
    
    This patch extends the SVE behaviour to SVE2.  The old call
    to AARCH64_CPU_HAS_FEATURE was technically the wrong way around,
    although it didn't matter in practice for base SVE instructions
    since their avariants only set SVE.

Diff:
---
 gas/config/tc-aarch64.c                  | 4 +++-
 gas/testsuite/gas/aarch64/illegal-sve2.l | 7 +++++++
 gas/testsuite/gas/aarch64/illegal-sve2.s | 3 +++
 3 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index eb28ea3dce2..67b0e61a7ff 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -6350,7 +6350,9 @@ parse_operands (char *str, const aarch64_opcode *opcode)
   clear_error ();
   skip_whitespace (str);
 
-  if (AARCH64_CPU_HAS_FEATURE (AARCH64_FEATURE_SVE, *opcode->avariant))
+  if (AARCH64_CPU_HAS_ANY_FEATURES (*opcode->avariant,
+				    AARCH64_FEATURE_SVE
+				    | AARCH64_FEATURE_SVE2))
     imm_reg_type = REG_TYPE_R_Z_SP_BHSDQ_VZP;
   else
     imm_reg_type = REG_TYPE_R_Z_BHSDQ_V;
diff --git a/gas/testsuite/gas/aarch64/illegal-sve2.l b/gas/testsuite/gas/aarch64/illegal-sve2.l
index 7656c2f91b1..c3ef21aa6d9 100644
--- a/gas/testsuite/gas/aarch64/illegal-sve2.l
+++ b/gas/testsuite/gas/aarch64/illegal-sve2.l
@@ -3328,3 +3328,10 @@
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 4 -- `xar z0\.s,z0\.s,z0\.s,#0'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 4 -- `xar z0\.s,z0\.s,z0\.s,#33'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 64 at operand 4 -- `xar z0\.d,z0\.d,z0\.d,#0'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqshl z1\.s,p0/m,z1\.s,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqshl z1\.s, p0/m, z1\.s, z0\.s
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqshl z1\.b, p0/m, z1\.b, z0\.b
+[^ :]+:[0-9]+: Info:    	sqshl z1\.h, p0/m, z1\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	sqshl z1\.d, p0/m, z1\.d, z0\.d
diff --git a/gas/testsuite/gas/aarch64/illegal-sve2.s b/gas/testsuite/gas/aarch64/illegal-sve2.s
index 8ad7fbf1d1b..3f3602a8474 100644
--- a/gas/testsuite/gas/aarch64/illegal-sve2.s
+++ b/gas/testsuite/gas/aarch64/illegal-sve2.s
@@ -2072,3 +2072,6 @@ xar z0.s, z0.s, z0.s, #0
 xar z0.s, z0.s, z0.s, #33
 xar z0.d, z0.d, z0.d, #0
 xar z0.d, z0.d, z0.d, #64
+
+.equ z0.h, 1
+sqshl z1.s, p0/m, z1.s, z0.h