* [binutils-gdb] aarch64: Improve errors for malformed register lists
@ 2023-03-30 10:12 Richard Sandiford
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From: Richard Sandiford @ 2023-03-30 10:12 UTC (permalink / raw)
To: bfd-cvs
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=b9ca389690810dd03e96a6d11470539f923d03b9
commit b9ca389690810dd03e96a6d11470539f923d03b9
Author: Richard Sandiford <richard.sandiford@arm.com>
Date: Thu Mar 30 11:09:06 2023 +0100
aarch64: Improve errors for malformed register lists
parse_typed_reg is used for parsing both bare registers and
registers that occur in lists. If it doesn't see a register,
or sees an unexpected kind of register, it queues a default
error to report the problem. These default errors have the form
"operand N must be an X", where X comes from the operand table.
If there are multiple opcode entries that report default errors,
GAS tries to pick the most appropriate one, using the opcode
table order as a tiebreaker. But this can lead to cases where
a syntax error in a register list is reported against an opcode
that doesn't accept register lists. For example, the unlikely
error:
ext z0.b,{,},#0
is reported as:
operand 2 must be an SVE vector register -- `ext z0.b,{,},#0'
even though operand 2 can be a register list.
If we've parsed the opening '{' of a register list, and then see
something that isn't remotely register-like, it seems better to
report that directly as a syntax error, rather than rely on the
default error. The operand won't be a valid list of anything,
so there's no need to pick a specific Y in "operand N must be
a list of Y".
Diff:
---
gas/config/tc-aarch64.c | 35 +++++++++++++++++++------------
gas/testsuite/gas/aarch64/illegal-sve2.l | 1 +
gas/testsuite/gas/aarch64/illegal-sve2.s | 1 +
gas/testsuite/gas/aarch64/sme-4-illegal.l | 16 +++++++-------
gas/testsuite/gas/aarch64/sve-invalid.l | 4 ++++
gas/testsuite/gas/aarch64/sve-invalid.s | 5 +++++
6 files changed, 41 insertions(+), 21 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index e8dfcb81bdf..596cc0f0813 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -1083,6 +1083,7 @@ parse_typed_reg (char **ccp, aarch64_reg_type type,
struct vector_type_el *typeinfo, unsigned int flags)
{
char *str = *ccp;
+ bool isalpha = ISALPHA (*str);
const reg_entry *reg = parse_reg (&str);
struct vector_type_el atype;
struct vector_type_el parsetype;
@@ -1098,7 +1099,10 @@ parse_typed_reg (char **ccp, aarch64_reg_type type,
{
if (typeinfo)
*typeinfo = atype;
- set_default_error ();
+ if (!isalpha && (flags & PTR_IN_REGLIST))
+ set_fatal_syntax_error (_("syntax error in register list"));
+ else
+ set_default_error ();
return NULL;
}
@@ -4361,15 +4365,16 @@ parse_bti_operand (char **str,
REG_TYPE.QUALIFIER
Side effect: Update STR with current parse position of success.
-*/
+
+ FLAGS is as for parse_typed_reg. */
static const reg_entry *
parse_reg_with_qual (char **str, aarch64_reg_type reg_type,
- aarch64_opnd_qualifier_t *qualifier)
+ aarch64_opnd_qualifier_t *qualifier, unsigned int flags)
{
struct vector_type_el vectype;
const reg_entry *reg = parse_typed_reg (str, reg_type, &vectype,
- PTR_FULL_REG);
+ PTR_FULL_REG | flags);
if (!reg)
return NULL;
@@ -4464,13 +4469,16 @@ parse_sme_za_index (char **str, struct aarch64_indexed_za *opnd)
<Pm>.<T>[<Wv>< #<imm>]
ZA[<Wv>, #<imm>]
<ZAn><HV>.<T>[<Wv>, #<imm>]
-*/
+
+ FLAGS is as for parse_typed_reg. */
+
static bool
parse_dual_indexed_reg (char **str, aarch64_reg_type reg_type,
struct aarch64_indexed_za *opnd,
- aarch64_opnd_qualifier_t *qualifier)
+ aarch64_opnd_qualifier_t *qualifier,
+ unsigned int flags)
{
- const reg_entry *reg = parse_reg_with_qual (str, reg_type, qualifier);
+ const reg_entry *reg = parse_reg_with_qual (str, reg_type, qualifier, flags);
if (!reg)
return false;
@@ -4494,7 +4502,8 @@ parse_sme_za_hv_tiles_operand_with_braces (char **str,
return false;
}
- if (!parse_dual_indexed_reg (str, REG_TYPE_ZATHV, opnd, qualifier))
+ if (!parse_dual_indexed_reg (str, REG_TYPE_ZATHV, opnd, qualifier,
+ PTR_IN_REGLIST))
return false;
if (!skip_past_char (str, '}'))
@@ -4527,7 +4536,7 @@ parse_sme_zero_mask(char **str)
do
{
const reg_entry *reg = parse_reg_with_qual (&q, REG_TYPE_ZA_ZAT,
- &qualifier);
+ &qualifier, PTR_IN_REGLIST);
if (!reg)
return PARSE_FAIL;
@@ -7028,7 +7037,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_SME_PnT_Wm_imm:
if (!parse_dual_indexed_reg (&str, REG_TYPE_PN,
- &info->indexed_za, &qualifier))
+ &info->indexed_za, &qualifier, 0))
goto failure;
info->qualifier = qualifier;
break;
@@ -7348,7 +7357,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_SME_ZAda_2b:
case AARCH64_OPND_SME_ZAda_3b:
- reg = parse_reg_with_qual (&str, REG_TYPE_ZAT, &qualifier);
+ reg = parse_reg_with_qual (&str, REG_TYPE_ZAT, &qualifier, 0);
if (!reg)
goto failure;
info->reg.regno = reg->number;
@@ -7363,7 +7372,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
&info->indexed_za,
&qualifier)
: !parse_dual_indexed_reg (&str, REG_TYPE_ZATHV,
- &info->indexed_za, &qualifier))
+ &info->indexed_za, &qualifier, 0))
goto failure;
info->qualifier = qualifier;
break;
@@ -7377,7 +7386,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_SME_ZA_array:
if (!parse_dual_indexed_reg (&str, REG_TYPE_ZA,
- &info->indexed_za, &qualifier))
+ &info->indexed_za, &qualifier, 0))
goto failure;
info->qualifier = qualifier;
break;
diff --git a/gas/testsuite/gas/aarch64/illegal-sve2.l b/gas/testsuite/gas/aarch64/illegal-sve2.l
index 6241de123db..2eab4120331 100644
--- a/gas/testsuite/gas/aarch64/illegal-sve2.l
+++ b/gas/testsuite/gas/aarch64/illegal-sve2.l
@@ -238,6 +238,7 @@
[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `eortb z32\.h,z0\.h,z0\.h'
[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `eortb z0\.s,z32\.s,z0\.s'
[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `eortb z0\.s,z0\.s,z32\.s'
+[^ :]+:[0-9]+: Error: syntax error in register list at operand 2 -- `ext z0\.b,{,},#0'
[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `ext z0\.b,{z0\.b,z2\.b},#0'
[^ :]+:[0-9]+: Error: operand mismatch -- `ext z0\.h,{z0\.b,z1\.b},#0'
[^ :]+:[0-9]+: Info: did you mean this\?
diff --git a/gas/testsuite/gas/aarch64/illegal-sve2.s b/gas/testsuite/gas/aarch64/illegal-sve2.s
index 3f3602a8474..4b6285c185e 100644
--- a/gas/testsuite/gas/aarch64/illegal-sve2.s
+++ b/gas/testsuite/gas/aarch64/illegal-sve2.s
@@ -166,6 +166,7 @@ eortb z32.h, z0.h, z0.h
eortb z0.s, z32.s, z0.s
eortb z0.s, z0.s, z32.s
+ext z0.b, {,}, #0
ext z0.b, { z0.b, z2.b }, #0
ext z0.h, { z0.b, z1.b }, #0
ext z0.b, { z0.h, z1.b }, #0
diff --git a/gas/testsuite/gas/aarch64/sme-4-illegal.l b/gas/testsuite/gas/aarch64/sme-4-illegal.l
index b61832e4223..72f62667768 100644
--- a/gas/testsuite/gas/aarch64/sme-4-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-4-illegal.l
@@ -8,16 +8,16 @@
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `zero {za0\.d,za3.s,za2.h}'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `zero {za1.b}'
[^:]*:[0-9]+: Error: unexpected comma after the mnemonic name `zero' -- `zero ,'
-[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {'
-[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {,'
+[^:]*:[0-9]+: Error: syntax error in register list at operand 1 -- `zero {'
+[^:]*:[0-9]+: Error: syntax error in register list at operand 1 -- `zero {,'
[^:]*:[0-9]+: Error: expected '{' at operand 1 -- `zero }'
-[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {,}'
-[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {,,}'
+[^:]*:[0-9]+: Error: syntax error in register list at operand 1 -- `zero {,}'
+[^:]*:[0-9]+: Error: syntax error in register list at operand 1 -- `zero {,,}'
[^:]*:[0-9]+: Error: missing ZA tile size at operand 1 -- `zero {za0}'
-[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {,za0.d}'
-[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {za0.d,}'
-[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {za0.d,za1.d,}'
-[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {za,}'
+[^:]*:[0-9]+: Error: syntax error in register list at operand 1 -- `zero {,za0.d}'
+[^:]*:[0-9]+: Error: syntax error in register list at operand 1 -- `zero {za0.d,}'
+[^:]*:[0-9]+: Error: syntax error in register list at operand 1 -- `zero {za0.d,za1.d,}'
+[^:]*:[0-9]+: Error: syntax error in register list at operand 1 -- `zero {za,}'
[^:]*:[0-9]+: Error: unexpected character `}' in element size at operand 1 -- `zero {za.}'
[^:]*:[0-9]+: Error: expected '}' at operand 1 -- `zero {za-}'
[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {za_}'
diff --git a/gas/testsuite/gas/aarch64/sve-invalid.l b/gas/testsuite/gas/aarch64/sve-invalid.l
index 32b7952436f..930d67328e6 100644
--- a/gas/testsuite/gas/aarch64/sve-invalid.l
+++ b/gas/testsuite/gas/aarch64/sve-invalid.l
@@ -1204,3 +1204,7 @@
.*: Error: operand mismatch -- `udot z0\.d,z1\.d,z2\.d\[0\]'
.*: Info: did you mean this\?
.*: Info: udot z0\.s, z1\.b, z2\.b\[0\]
+.*: Error: syntax error in register list at operand 1 -- `ld2b {},p0/z,\[x0\]'
+.*: Error: syntax error in register list at operand 1 -- `ld2b {.b},p0/z,\[x0\]'
+.*: Error: syntax error in register list at operand 1 -- `ld2b {z0.b-},p0/z,\[x0\]'
+.*: Error: syntax error in register list at operand 1 -- `ld2b {z0.b,},p0/z,\[x0\]'
diff --git a/gas/testsuite/gas/aarch64/sve-invalid.s b/gas/testsuite/gas/aarch64/sve-invalid.s
index 204721ee17a..ece2142b072 100644
--- a/gas/testsuite/gas/aarch64/sve-invalid.s
+++ b/gas/testsuite/gas/aarch64/sve-invalid.s
@@ -1324,3 +1324,8 @@
udot z0.h, z1.h, z2.h[0]
udot z0.s, z1.s, z2.s[0]
udot z0.d, z1.d, z2.d[0]
+
+ ld2b {}, p0/z, [x0]
+ ld2b {.b}, p0/z, [x0]
+ ld2b {z0.b-}, p0/z, [x0]
+ ld2b {z0.b,}, p0/z, [x0]
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