* [binutils-gdb] aarch64: Tweak register list errors
@ 2023-03-30 10:13 Richard Sandiford
0 siblings, 0 replies; only message in thread
From: Richard Sandiford @ 2023-03-30 10:13 UTC (permalink / raw)
To: bfd-cvs
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=8c2216b2773ee9e5a233fa29e12b61d1646af18e
commit 8c2216b2773ee9e5a233fa29e12b61d1646af18e
Author: Richard Sandiford <richard.sandiford@arm.com>
Date: Thu Mar 30 11:09:08 2023 +0100
aarch64: Tweak register list errors
The error for invalid register lists had the form:
invalid number of registers in the list; N registers are expected at operand M -- `insn'
This seems a bit verbose. Also, the "bracketing" is really:
(invalid number of registers in the list; N registers are expected) at operand M
but the semicolon works against that.
This patch goes for slightly shorter messages, setting a template
that later patches can use for more complex cases.
Diff:
---
gas/config/tc-aarch64.c | 6 ++----
gas/testsuite/gas/aarch64/diagnostic.l | 4 ++--
gas/testsuite/gas/aarch64/illegal-sve2.l | 26 +++++++++++++-------------
gas/testsuite/gas/aarch64/verbose-error.l | 2 +-
4 files changed, 18 insertions(+), 20 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index a57cc2bc080..0d2a04ddb16 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -5747,12 +5747,10 @@ output_operand_error_record (const operand_error_record *record, char *str)
case AARCH64_OPDE_REG_LIST:
if (detail->data[0].i == (1 << 1))
- handler (_("invalid number of registers in the list; "
- "only 1 register is expected at operand %d -- `%s'"),
+ handler (_("expected a single-register list at operand %d -- `%s'"),
idx + 1, str);
else if ((detail->data[0].i & -detail->data[0].i) == detail->data[0].i)
- handler (_("invalid number of registers in the list; "
- "%d registers are expected at operand %d -- `%s'"),
+ handler (_("expected a list of %d registers at operand %d -- `%s'"),
get_log2 (detail->data[0].i), idx + 1, str);
else
handler (_("invalid number of registers in the list"
diff --git a/gas/testsuite/gas/aarch64/diagnostic.l b/gas/testsuite/gas/aarch64/diagnostic.l
index 52365319283..6d59564a543 100644
--- a/gas/testsuite/gas/aarch64/diagnostic.l
+++ b/gas/testsuite/gas/aarch64/diagnostic.l
@@ -27,7 +27,7 @@
[^:]*:29: Error: shift amount out of range 0 to 31 at operand 3 -- `add w0,wzr,w7,asr#32'
[^:]*:30: Error: invalid post-increment amount at operand 2 -- `st2 \{v0.4s,v1.4s\},\[sp\],#24'
[^:]*:31: Error: invalid shift amount at operand 2 -- `ldr q0,\[x0,w0,uxtw#5\]'
-[^:]*:32: Error: invalid number of registers in the list; 2 registers are expected at operand 1 -- `st2 \{v0.4s,v1.4s,v2.4s,v3.4s\},\[sp\],#64'
+[^:]*:32: Error: expected a list of 2 registers at operand 1 -- `st2 \{v0.4s,v1.4s,v2.4s,v3.4s\},\[sp\],#64'
[^:]*:33: Error: shift amount must be 0 or 12 at operand 3 -- `adds x1,sp,2134,lsl#4'
[^:]*:34: Error: shift amount must be a multiple of 16 at operand 2 -- `movz w0,2134,lsl#8'
[^:]*:35: Error: shift amount out of range 0 to 16 at operand 2 -- `movz w0,2134,lsl#32'
@@ -77,7 +77,7 @@
[^:]*:79: Error: immediate value out of range 0 to 31 at operand 1 -- `prfm 0x2f,LABEL1'
[^:]*:80: Error: immediate value out of range 0 to 15 at operand 1 -- `dmb #16'
[^:]*:81: Error: immediate value out of range 0 to 31 at operand 2 -- `tbz w0,#40,0x17c'
-[^:]*:82: Error: invalid number of registers in the list; 2 registers are expected at operand 1 -- `st2 \{v4.2d,v5.2d,v6.2d\},\[x3\]'
+[^:]*:82: Error: expected a list of 2 registers at operand 1 -- `st2 \{v4.2d,v5.2d,v6.2d\},\[x3\]'
[^:]*:83: Error: invalid register list at operand 1 -- `ld2 \{v1.4h,v0.4h\},\[x1\]'
[^:]*:84: Error: the specified option is not accepted in ISB at operand 1 -- `isb osh'
[^:]*:85: Error: invalid address at operand 2 -- `st2 \{v4.2d,v5.2d,v6.2d\},\\\[x3\\\]'
diff --git a/gas/testsuite/gas/aarch64/illegal-sve2.l b/gas/testsuite/gas/aarch64/illegal-sve2.l
index 995440627d1..551440f3741 100644
--- a/gas/testsuite/gas/aarch64/illegal-sve2.l
+++ b/gas/testsuite/gas/aarch64/illegal-sve2.l
@@ -248,8 +248,8 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `ext z0\.b,{z0\.h,z1\.h},#0'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: ext z0\.b, {z0\.b, z1\.b}, #0
-[^ :]+:[0-9]+: Error: invalid number of registers in the list; 2 registers are expected at operand 2 -- `ext z0\.b,{z0\.b,z1\.b,z2\.b},#0'
-[^ :]+:[0-9]+: Error: invalid number of registers in the list; 2 registers are expected at operand 2 -- `ext z0\.b,{z0\.b},#0'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `ext z0\.b,{z0\.b,z1\.b,z2\.b},#0'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `ext z0\.b,{z0\.b},#0'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `ext z0\.b,z0\.b,#0'
[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `ext z0\.b,{z31\.b,z1\.b},#0'
[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `ext z0\.b,{z0\.b,z31\.b},#0'
@@ -488,7 +488,7 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `histseg z0\.b,z0\.b,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: histseg z0\.b, z0\.b, z0\.b
-[^ :]+:[0-9]+: Error: invalid number of registers in the list; only 1 register is expected at operand 1 -- `ldnt1b {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ldnt1b {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1b {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: ldnt1b {z0\.s}, p0/z, \[z0\.s, xzr\]
@@ -515,7 +515,7 @@
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1b {z0\.s},p0/z,\[z0\.s,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1b {z0\.s},p0/z,\[z0\.s,x32\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1b {z0\.s},p0/z,\[z0\.s,z0\.s\]'
-[^ :]+:[0-9]+: Error: invalid number of registers in the list; only 1 register is expected at operand 1 -- `ldnt1d {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ldnt1d {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1d {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: ldnt1d {z0\.d}, p0/z, \[z0\.d, xzr\]
@@ -535,7 +535,7 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1d {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: ldnt1d {z0\.d}, p0/z, \[z0\.d, xzr\]
-[^ :]+:[0-9]+: Error: invalid number of registers in the list; only 1 register is expected at operand 1 -- `ldnt1h {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ldnt1h {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1h {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: ldnt1h {z0\.s}, p0/z, \[z0\.s, xzr\]
@@ -556,7 +556,7 @@
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1h {z0\.s},p0/z,\[z0\.s,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1h {z0\.s},p0/z,\[z0\.s,x32\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1h {z0\.s},p0/z,\[z0\.s,z0\.s\]'
-[^ :]+:[0-9]+: Error: invalid number of registers in the list; only 1 register is expected at operand 1 -- `ldnt1sb {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ldnt1sb {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1sb {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: ldnt1sb {z0\.d}, p0/z, \[z0\.d, xzr\]
@@ -569,7 +569,7 @@
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sb {z0\.d},p0/z,\[z0\.d,x32\]'
[^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `ldnt1sb {z0\.d},p0/z,\[z0\.d,w16\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sb {z0\.d},p0/z,\[z0\.d,z0\.d\]'
-[^ :]+:[0-9]+: Error: invalid number of registers in the list; only 1 register is expected at operand 1 -- `ldnt1sh {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ldnt1sh {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1sh {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: ldnt1sh {z0\.d}, p0/z, \[z0\.d, xzr\]
@@ -582,7 +582,7 @@
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,x32\]'
[^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,w16\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,z0\.d\]'
-[^ :]+:[0-9]+: Error: invalid number of registers in the list; only 1 register is expected at operand 1 -- `ldnt1sh {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ldnt1sh {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1sh {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: ldnt1sh {z0\.d}, p0/z, \[z0\.d, xzr\]
@@ -595,7 +595,7 @@
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,x32\]'
[^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,w16\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,z0\.d\]'
-[^ :]+:[0-9]+: Error: invalid number of registers in the list; only 1 register is expected at operand 1 -- `ldnt1w {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ldnt1w {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1w {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: ldnt1w {z0\.s}, p0/z, \[z0\.s, xzr\]
@@ -2212,7 +2212,7 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: ssubwt z0\.s, z0\.s, z0\.h
[^ :]+:[0-9]+: Info: ssubwt z0\.d, z0\.d, z0\.s
-[^ :]+:[0-9]+: Error: invalid number of registers in the list; only 1 register is expected at operand 1 -- `stnt1b {z0\.d,z1\.d},p0,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `stnt1b {z0\.d,z1\.d},p0,\[z0\.d,x0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `stnt1b {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: stnt1b {z0\.s}, p0, \[z0\.s, xzr\]
@@ -2233,7 +2233,7 @@
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `stnt1b {z0\.s},p0,\[z0\.s,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1b {z0\.s},p0,\[z0\.s,x32\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1b {z0\.s},p0,\[z0\.s,z0\.s\]'
-[^ :]+:[0-9]+: Error: invalid number of registers in the list; only 1 register is expected at operand 1 -- `stnt1d {z0\.d,z1\.d},p0,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `stnt1d {z0\.d,z1\.d},p0,\[z0\.d,x0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `stnt1d {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: stnt1d {z0\.d}, p0, \[z0\.d, xzr\]
@@ -2247,7 +2247,7 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `stnt1d {z0\.s},p0,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: stnt1d {z0\.d}, p0, \[z0\.d, xzr\]
-[^ :]+:[0-9]+: Error: invalid number of registers in the list; only 1 register is expected at operand 1 -- `stnt1h {z0\.d,z1\.d},p0,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `stnt1h {z0\.d,z1\.d},p0,\[z0\.d,x0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `stnt1h {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: stnt1h {z0\.s}, p0, \[z0\.s, xzr\]
@@ -2268,7 +2268,7 @@
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `stnt1h {z0\.s},p0,\[z0\.s,sp\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1h {z0\.s},p0,\[z0\.s,x32\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1h {z0\.s},p0,\[z0\.s,z0\.s\]'
-[^ :]+:[0-9]+: Error: invalid number of registers in the list; only 1 register is expected at operand 1 -- `stnt1w {z0\.d,z1\.d},p0,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `stnt1w {z0\.d,z1\.d},p0,\[z0\.d,x0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `stnt1w {z0\.d},p0/m,\[z0\.d\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: stnt1w {z0\.s}, p0, \[z0\.s, xzr\]
diff --git a/gas/testsuite/gas/aarch64/verbose-error.l b/gas/testsuite/gas/aarch64/verbose-error.l
index 5696a5c4671..188dadfe87d 100644
--- a/gas/testsuite/gas/aarch64/verbose-error.l
+++ b/gas/testsuite/gas/aarch64/verbose-error.l
@@ -9,7 +9,7 @@
[^:]*:7: Error: invalid shift amount at operand 2 -- `strb w7,\[x30,x0,lsl#1\]'
[^:]*:8: Error: invalid addressing mode at operand 2 -- `st2 {v4.2d,v5.2d},\[x3,#3\]'
[^:]*:9: Error: the top half of a 128-bit FP/SIMD register is expected at operand 1 -- `fmov v1.D\[0\],x0'
-[^:]*:10: Error: invalid number of registers in the list; only 1 register is expected at operand 1 -- `ld1r \{v1.4s,v2.4s,v3.4s\},\[x3\],x4'
+[^:]*:10: Error: expected a single-register list at operand 1 -- `ld1r \{v1.4s,v2.4s,v3.4s\},\[x3\],x4'
[^:]*:11: Error: missing immediate expression at operand 1 -- `svc'
[^:]*:12: Error: operand mismatch -- `add v0.4s,v1.4s,v2.2s'
[^:]*:12: Info: did you mean this\?
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2023-03-30 10:13 [binutils-gdb] aarch64: Tweak register list errors Richard Sandiford
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