* [binutils-gdb] aarch64: Add support for predicate-as-counter registers
@ 2023-03-30 10:14 Richard Sandiford
0 siblings, 0 replies; only message in thread
From: Richard Sandiford @ 2023-03-30 10:14 UTC (permalink / raw)
To: bfd-cvs
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=503fae12992e5dbf48b4e30cea8d35f31d87effe
commit 503fae12992e5dbf48b4e30cea8d35f31d87effe
Author: Richard Sandiford <richard.sandiford@arm.com>
Date: Thu Mar 30 11:09:11 2023 +0100
aarch64: Add support for predicate-as-counter registers
SME2 adds a new format for the existing SVE predicate registers:
predicates as counters rather than predicates as masks. In assembly
code, operands that interpret predicates as counters are written
pn<N> rather than p<N>.
This patch adds support for these registers and extends some
existing instructions to support them. Since the new forms
are just a programmer convenience, there's no need to make them
more restrictive than the earlier predicate-as-mask forms.
Diff:
---
gas/config/tc-aarch64.c | 35 +-
gas/testsuite/gas/aarch64/sve-sme2-1-invalid.d | 3 +
gas/testsuite/gas/aarch64/sve-sme2-1-invalid.l | 51 +
gas/testsuite/gas/aarch64/sve-sme2-1-invalid.s | 25 +
gas/testsuite/gas/aarch64/sve-sme2-1-noarch.d | 3 +
gas/testsuite/gas/aarch64/sve-sme2-1-noarch.l | 25 +
gas/testsuite/gas/aarch64/sve-sme2-1.d | 33 +
gas/testsuite/gas/aarch64/sve-sme2-1.s | 27 +
gas/testsuite/gas/aarch64/sve2-sme2-1-invalid.d | 3 +
gas/testsuite/gas/aarch64/sve2-sme2-1-invalid.l | 9 +
gas/testsuite/gas/aarch64/sve2-sme2-1-invalid.s | 8 +
gas/testsuite/gas/aarch64/sve2-sme2-1-noarch.d | 3 +
gas/testsuite/gas/aarch64/sve2-sme2-1-noarch.l | 33 +
gas/testsuite/gas/aarch64/sve2-sme2-1.d | 41 +
gas/testsuite/gas/aarch64/sve2-sme2-1.s | 35 +
include/opcode/aarch64.h | 5 +
opcodes/aarch64-asm-2.c | 239 +-
opcodes/aarch64-asm.c | 1 +
opcodes/aarch64-dis-2.c | 2961 ++++++++++++-----------
opcodes/aarch64-opc-2.c | 17 +-
opcodes/aarch64-opc.c | 13 +
opcodes/aarch64-tbl.h | 13 +
22 files changed, 1983 insertions(+), 1600 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 5873fc754a3..8d5cc5194de 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -307,6 +307,7 @@ struct reloc_entry
BASIC_REG_TYPE(V) /* v[0-31] */ \
BASIC_REG_TYPE(Z) /* z[0-31] */ \
BASIC_REG_TYPE(P) /* p[0-15] */ \
+ BASIC_REG_TYPE(PN) /* pn[0-15] */ \
BASIC_REG_TYPE(ZA) /* za */ \
BASIC_REG_TYPE(ZAT) /* za[0-15] (ZA tile) */ \
BASIC_REG_TYPE(ZATH) /* za[0-15]h (ZA tile horizontal slice) */ \
@@ -440,6 +441,16 @@ get_reg_expected_msg (unsigned int mask, unsigned int seen)
| reg_type_masks[REG_TYPE_ZATHV])))
return N_("expected 'za' rather than a ZA tile at operand %d");
+ if ((mask & reg_type_masks[REG_TYPE_PN])
+ && (seen & reg_type_masks[REG_TYPE_P]))
+ return N_("expected a predicate-as-counter rather than predicate-as-mask"
+ " register at operand %d");
+
+ if ((mask & reg_type_masks[REG_TYPE_P])
+ && (seen & reg_type_masks[REG_TYPE_PN]))
+ return N_("expected a predicate-as-mask rather than predicate-as-counter"
+ " register at operand %d");
+
/* Integer, zero and stack registers. */
if (mask == reg_type_masks[REG_TYPE_R_64])
return N_("expected a 64-bit integer register at operand %d");
@@ -456,7 +467,12 @@ get_reg_expected_msg (unsigned int mask, unsigned int seen)
return N_("expected an Advanced SIMD vector register at operand %d");
if (mask == reg_type_masks[REG_TYPE_Z])
return N_("expected an SVE vector register at operand %d");
- if (mask == reg_type_masks[REG_TYPE_P])
+ if (mask == reg_type_masks[REG_TYPE_P]
+ || mask == (reg_type_masks[REG_TYPE_P] | reg_type_masks[REG_TYPE_PN]))
+ /* Use this error for "predicate-as-mask only" and "either kind of
+ predicate". We report a more specific error if P is used where
+ PN is expected, and vice versa, so the issue at this point is
+ "predicate-like" vs. "not predicate-like". */
return N_("expected an SVE predicate register at operand %d");
if (mask == reg_type_masks[REG_TYPE_VZ])
return N_("expected a vector register at operand %d");
@@ -1127,6 +1143,7 @@ aarch64_valid_suffix_char_p (aarch64_reg_type type, char ch)
return ch == '.';
case REG_TYPE_P:
+ case REG_TYPE_PN:
return ch == '.' || ch == '/';
default:
@@ -6609,6 +6626,13 @@ parse_operands (char *str, const aarch64_opcode *opcode)
reg_type = REG_TYPE_Z;
goto vector_reg;
+ case AARCH64_OPND_SVE_PNd:
+ case AARCH64_OPND_SVE_PNg4_10:
+ case AARCH64_OPND_SVE_PNn:
+ case AARCH64_OPND_SVE_PNt:
+ reg_type = REG_TYPE_PN;
+ goto vector_reg;
+
case AARCH64_OPND_Va:
case AARCH64_OPND_Vd:
case AARCH64_OPND_Vn:
@@ -6622,7 +6646,9 @@ parse_operands (char *str, const aarch64_opcode *opcode)
goto failure;
info->reg.regno = reg->number;
- if ((reg_type == REG_TYPE_P || reg_type == REG_TYPE_Z)
+ if ((reg_type == REG_TYPE_P
+ || reg_type == REG_TYPE_PN
+ || reg_type == REG_TYPE_Z)
&& vectype.type == NT_invtype)
/* Unqualified P and Z registers are allowed in certain
contexts. Rely on F_STRICT qualifier checking to catch
@@ -8343,9 +8369,12 @@ static const reg_entry reg_names[] = {
/* SVE vector registers. */
REGSET (z, Z), REGSET (Z, Z),
- /* SVE predicate registers. */
+ /* SVE predicate(-as-mask) registers. */
REGSET16 (p, P), REGSET16 (P, P),
+ /* SVE predicate-as-counter registers. */
+ REGSET16 (pn, PN), REGSET16 (PN, PN),
+
/* SME ZA. We model this as a register because it acts syntactically
like ZA0H, supporting qualifier suffixes and indexing. */
REGDEF (za, 0, ZA), REGDEF (ZA, 0, ZA),
diff --git a/gas/testsuite/gas/aarch64/sve-sme2-1-invalid.d b/gas/testsuite/gas/aarch64/sve-sme2-1-invalid.d
new file mode 100644
index 00000000000..82d3724e2f3
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-sme2-1-invalid.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a
+#source: sve-sme2-1-invalid.s
+#error_output: sve-sme2-1-invalid.l
diff --git a/gas/testsuite/gas/aarch64/sve-sme2-1-invalid.l b/gas/testsuite/gas/aarch64/sve-sme2-1-invalid.l
new file mode 100644
index 00000000000..7699801ed82
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-sme2-1-invalid.l
@@ -0,0 +1,51 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: operand mismatch -- `pfalse pn0\.h'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: pfalse pn0\.b
+[^ :]+:[0-9]+: Error: operand mismatch -- `pfalse pn0\.s'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: pfalse pn0\.b
+[^ :]+:[0-9]+: Error: operand mismatch -- `pfalse pn0\.d'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: pfalse pn0\.b
+[^ :]+:[0-9]+: Error: operand mismatch -- `pfalse pn0\.q'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: pfalse pn0\.b
+[^ :]+:[0-9]+: Error: operand mismatch -- `pfalse pn0'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: pfalse pn0\.b
+[^ :]+:[0-9]+: Error: expected a predicate-as-counter rather than predicate-as-mask register at operand 2 -- `mov pn0\.b,p0\.b'
+[^ :]+:[0-9]+: Error: expected a predicate-as-mask rather than predicate-as-counter register at operand 2 -- `mov p0\.b,pn0\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `mov pn0\.b,pn1\.h'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: mov pn0\.b, pn1\.b
+[^ :]+:[0-9]+: Error: operand mismatch -- `mov pn0\.h,pn1\.b'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: mov pn0\.b, pn1\.b
+[^ :]+:[0-9]+: Error: operand mismatch -- `mov pn0\.h,pn1\.h'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: mov pn0\.b, pn1\.b
+[^ :]+:[0-9]+: Error: operand mismatch -- `mov pn0\.s,pn1\.s'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: mov pn0\.b, pn1\.b
+[^ :]+:[0-9]+: Error: operand mismatch -- `mov pn0\.d,pn1\.d'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: mov pn0\.b, pn1\.b
+[^ :]+:[0-9]+: Error: operand mismatch -- `mov pn0\.q,pn1\.q'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: mov pn0\.b, pn1\.b
+[^ :]+:[0-9]+: Error: operand mismatch -- `mov pn0,pn1'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: mov pn0\.b, pn1\.b
+[^ :]+:[0-9]+: Error: operand mismatch -- `ldr pn0\.b,\[x0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: ldr pn0, \[x0\]
+[^ :]+:[0-9]+: Error: invalid base register at operand 2 -- `ldr pn0\.b,\[xzr\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range -256 to 255 at operand 2 -- `ldr pn0,\[x0,#-257,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range -256 to 255 at operand 2 -- `ldr pn0,\[x0,#256,mul vl\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `str pn0\.b,\[x0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: str pn0, \[x0\]
+[^ :]+:[0-9]+: Error: invalid base register at operand 2 -- `str pn0\.b,\[xzr\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range -256 to 255 at operand 2 -- `str pn0,\[x0,#-257,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range -256 to 255 at operand 2 -- `str pn0,\[x0,#256,mul vl\]'
diff --git a/gas/testsuite/gas/aarch64/sve-sme2-1-invalid.s b/gas/testsuite/gas/aarch64/sve-sme2-1-invalid.s
new file mode 100644
index 00000000000..e8410a64ed2
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-sme2-1-invalid.s
@@ -0,0 +1,25 @@
+ pfalse pn0.h
+ pfalse pn0.s
+ pfalse pn0.d
+ pfalse pn0.q
+ pfalse pn0
+
+ mov pn0.b, p0.b
+ mov p0.b, pn0.b
+ mov pn0.b, pn1.h
+ mov pn0.h, pn1.b
+ mov pn0.h, pn1.h
+ mov pn0.s, pn1.s
+ mov pn0.d, pn1.d
+ mov pn0.q, pn1.q
+ mov pn0, pn1
+
+ ldr pn0.b, [x0]
+ ldr pn0.b, [xzr]
+ ldr pn0, [x0, #-257, mul vl]
+ ldr pn0, [x0, #256, mul vl]
+
+ str pn0.b, [x0]
+ str pn0.b, [xzr]
+ str pn0, [x0, #-257, mul vl]
+ str pn0, [x0, #256, mul vl]
diff --git a/gas/testsuite/gas/aarch64/sve-sme2-1-noarch.d b/gas/testsuite/gas/aarch64/sve-sme2-1-noarch.d
new file mode 100644
index 00000000000..ead5641171d
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-sme2-1-noarch.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a
+#source: sve-sme2-1.s
+#error_output: sve-sme2-1-noarch.l
diff --git a/gas/testsuite/gas/aarch64/sve-sme2-1-noarch.l b/gas/testsuite/gas/aarch64/sve-sme2-1-noarch.l
new file mode 100644
index 00000000000..e624ac6c019
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-sme2-1-noarch.l
@@ -0,0 +1,25 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: selected processor does not support `pfalse pn0\.b'
+[^ :]+:[0-9]+: Error: selected processor does not support `pfalse PN0\.B'
+[^ :]+:[0-9]+: Error: selected processor does not support `pfalse pn5\.b'
+[^ :]+:[0-9]+: Error: selected processor does not support `pfalse pn15\.b'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov pn0\.b,pn0\.b'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov pn0\.b,pn15\.b'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov pn15\.b,pn0\.b'
+[^ :]+:[0-9]+: Error: selected processor does not support `mov pn3\.b,pn12\.b'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldr pn0,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldr pn15,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldr pn15,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldr pn0,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldr pn0,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldr pn0,\[x0,#-256,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldr pn0,\[x0,#255,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldr pn11,\[x14,#211,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `str pn0,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `str pn15,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `str pn15,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `str pn0,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `str pn0,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `str pn0,\[x0,#-256,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `str pn0,\[x0,#255,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `str pn5,\[x28,#-56,mul vl\]'
diff --git a/gas/testsuite/gas/aarch64/sve-sme2-1.d b/gas/testsuite/gas/aarch64/sve-sme2-1.d
new file mode 100644
index 00000000000..0dfb99c57d8
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-sme2-1.d
@@ -0,0 +1,33 @@
+#as: -march=armv8-a+sve
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+[^:]+: 2518e400 pfalse p0\.b
+[^:]+: 2518e400 pfalse p0\.b
+[^:]+: 2518e405 pfalse p5\.b
+[^:]+: 2518e40f pfalse p15\.b
+[^:]+: 25804000 mov p0\.b, p0\.b
+[^:]+: 258f7de0 mov p0\.b, p15\.b
+[^:]+: 2580400f mov p15\.b, p0\.b
+[^:]+: 258c7183 mov p3\.b, p12\.b
+[^:]+: 85800000 ldr p0, \[x0\]
+[^:]+: 8580000f ldr p15, \[x0\]
+[^:]+: 858003cf ldr p15, \[x30\]
+[^:]+: 858003e0 ldr p0, \[sp\]
+[^:]+: 85800000 ldr p0, \[x0\]
+[^:]+: 85a00000 ldr p0, \[x0, #-256, mul vl\]
+[^:]+: 859f1c00 ldr p0, \[x0, #255, mul vl\]
+[^:]+: 859a0dcb ldr p11, \[x14, #211, mul vl\]
+[^:]+: e5800000 str p0, \[x0\]
+[^:]+: e580000f str p15, \[x0\]
+[^:]+: e58003cf str p15, \[x30\]
+[^:]+: e58003e0 str p0, \[sp\]
+[^:]+: e5800000 str p0, \[x0\]
+[^:]+: e5a00000 str p0, \[x0, #-256, mul vl\]
+[^:]+: e59f1c00 str p0, \[x0, #255, mul vl\]
+[^:]+: e5b90385 str p5, \[x28, #-56, mul vl\]
diff --git a/gas/testsuite/gas/aarch64/sve-sme2-1.s b/gas/testsuite/gas/aarch64/sve-sme2-1.s
new file mode 100644
index 00000000000..c119363d6be
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-sme2-1.s
@@ -0,0 +1,27 @@
+ pfalse pn0.b
+ PFALSE PN0.B
+ pfalse pn5.b
+ pfalse pn15.b
+
+ mov pn0.b, pn0.b
+ mov pn0.b, pn15.b
+ mov pn15.b, pn0.b
+ mov pn3.b, pn12.b
+
+ ldr pn0, [x0]
+ ldr pn15, [x0]
+ ldr pn15, [x30]
+ ldr pn0, [sp]
+ ldr pn0, [x0, #0, mul vl]
+ ldr pn0, [x0, #-256, mul vl]
+ ldr pn0, [x0, #255, mul vl]
+ ldr pn11, [x14, #211, mul vl]
+
+ str pn0, [x0]
+ str pn15, [x0]
+ str pn15, [x30]
+ str pn0, [sp]
+ str pn0, [x0, #0, mul vl]
+ str pn0, [x0, #-256, mul vl]
+ str pn0, [x0, #255, mul vl]
+ str pn5, [x28, #-56, mul vl]
diff --git a/gas/testsuite/gas/aarch64/sve2-sme2-1-invalid.d b/gas/testsuite/gas/aarch64/sve2-sme2-1-invalid.d
new file mode 100644
index 00000000000..03f33afae8a
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2-sme2-1-invalid.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a
+#source: sve2-sme2-1-invalid.s
+#error_output: sve2-sme2-1-invalid.l
diff --git a/gas/testsuite/gas/aarch64/sve2-sme2-1-invalid.l b/gas/testsuite/gas/aarch64/sve2-sme2-1-invalid.l
new file mode 100644
index 00000000000..70cfd59b4c1
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2-sme2-1-invalid.l
@@ -0,0 +1,9 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: expected a predicate-as-counter rather than predicate-as-mask register at operand 2 -- `psel pn0,p0,p0\.b\[w12,0\]'
+[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `psel pn,pn0,p0\.b\[w12,0\]'
+[^ :]+:[0-9]+: Error: expected a predicate-as-mask rather than predicate-as-counter register at operand 3 -- `psel p0,p0,pn0\.b\[w12,0\]'
+[^ :]+:[0-9]+: Error: expected a predicate-as-mask rather than predicate-as-counter register at operand 3 -- `psel pn0,pn0,pn0\.b\[w12,0\]'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 3 -- `psel pn0,pn0,p0\.b\[w11,0\]'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 3 -- `psel pn0,pn0,p0\.b\[w16,0\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 3 -- `psel pn0,pn0,p0\.b\[w12,-1\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 3 -- `psel pn0,pn0,p0\.b\[w12,16\]'
diff --git a/gas/testsuite/gas/aarch64/sve2-sme2-1-invalid.s b/gas/testsuite/gas/aarch64/sve2-sme2-1-invalid.s
new file mode 100644
index 00000000000..c0da1d78587
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2-sme2-1-invalid.s
@@ -0,0 +1,8 @@
+ psel pn0, p0, p0.b[w12, 0]
+ psel pn, pn0, p0.b[w12, 0]
+ psel p0, p0, pn0.b[w12, 0]
+ psel pn0, pn0, pn0.b[w12, 0]
+ psel pn0, pn0, p0.b[w11, 0]
+ psel pn0, pn0, p0.b[w16, 0]
+ psel pn0, pn0, p0.b[w12, -1]
+ psel pn0, pn0, p0.b[w12, 16]
diff --git a/gas/testsuite/gas/aarch64/sve2-sme2-1-noarch.d b/gas/testsuite/gas/aarch64/sve2-sme2-1-noarch.d
new file mode 100644
index 00000000000..23022a09c88
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2-sme2-1-noarch.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a+sve2
+#source: sve2-sme2-1.s
+#error_output: sve2-sme2-1-noarch.l
diff --git a/gas/testsuite/gas/aarch64/sve2-sme2-1-noarch.l b/gas/testsuite/gas/aarch64/sve2-sme2-1-noarch.l
new file mode 100644
index 00000000000..e911c53d7ac
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2-sme2-1-noarch.l
@@ -0,0 +1,33 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: selected processor does not support `psel pn0,pn0,p0\.b\[w12,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `psel PN0,PN0,P0\.B\[W12,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `psel pn15,pn0,p0\.b\[w12,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `psel pn0,pn15,p0\.b\[w12,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `psel pn0,pn0,p15\.b\[w12,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `psel pn0,pn0,p0\.b\[w15,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `psel pn0,pn0,p0\.b\[w12,15\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `psel pn1,pn13,p6\.b\[w14,11\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `psel pn0,pn0,p0\.h\[w12,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `psel PN0,PN0,P0\.H\[W12,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `psel pn15,pn0,p0\.h\[w12,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `psel pn0,pn15,p0\.h\[w12,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `psel pn0,pn0,p15\.h\[w12,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `psel pn0,pn0,p0\.h\[w15,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `psel pn0,pn0,p0\.h\[w12,7\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `psel pn12,pn7,p14\.h\[w13,5\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `psel pn0,pn0,p0\.s\[w12,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `psel PN0,PN0,P0\.S\[W12,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `psel pn15,pn0,p0\.s\[w12,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `psel pn0,pn15,p0\.s\[w12,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `psel pn0,pn0,p15\.s\[w12,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `psel pn0,pn0,p0\.s\[w15,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `psel pn0,pn0,p0\.s\[w12,3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `psel pn6,pn11,p11\.s\[w13,2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `psel pn0,pn0,p0\.d\[w12,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `psel PN0,PN0,P0\.D\[W12,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `psel pn15,pn0,p0\.d\[w12,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `psel pn0,pn15,p0\.d\[w12,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `psel pn0,pn0,p15\.d\[w12,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `psel pn0,pn0,p0\.d\[w15,0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `psel pn0,pn0,p0\.d\[w12,1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `psel pn7,pn9,p5\.d\[w13,1\]'
diff --git a/gas/testsuite/gas/aarch64/sve2-sme2-1.d b/gas/testsuite/gas/aarch64/sve2-sme2-1.d
new file mode 100644
index 00000000000..4918481410c
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2-sme2-1.d
@@ -0,0 +1,41 @@
+#as: -march=armv8-a+sme
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+[^:]+: 25244000 psel p0, p0, p0\.b\[w12, 0\]
+[^:]+: 25244000 psel p0, p0, p0\.b\[w12, 0\]
+[^:]+: 2524400f psel p15, p0, p0\.b\[w12, 0\]
+[^:]+: 25247c00 psel p0, p15, p0\.b\[w12, 0\]
+[^:]+: 252441e0 psel p0, p0, p15\.b\[w12, 0\]
+[^:]+: 25274000 psel p0, p0, p0\.b\[w15, 0\]
+[^:]+: 25fc4000 psel p0, p0, p0\.b\[w12, 15\]
+[^:]+: 25be74c1 psel p1, p13, p6\.b\[w14, 11\]
+[^:]+: 25284000 psel p0, p0, p0\.h\[w12, 0\]
+[^:]+: 25284000 psel p0, p0, p0\.h\[w12, 0\]
+[^:]+: 2528400f psel p15, p0, p0\.h\[w12, 0\]
+[^:]+: 25287c00 psel p0, p15, p0\.h\[w12, 0\]
+[^:]+: 252841e0 psel p0, p0, p15\.h\[w12, 0\]
+[^:]+: 252b4000 psel p0, p0, p0\.h\[w15, 0\]
+[^:]+: 25f84000 psel p0, p0, p0\.h\[w12, 7\]
+[^:]+: 25b95dcc psel p12, p7, p14\.h\[w13, 5\]
+[^:]+: 25304000 psel p0, p0, p0\.s\[w12, 0\]
+[^:]+: 25304000 psel p0, p0, p0\.s\[w12, 0\]
+[^:]+: 2530400f psel p15, p0, p0\.s\[w12, 0\]
+[^:]+: 25307c00 psel p0, p15, p0\.s\[w12, 0\]
+[^:]+: 253041e0 psel p0, p0, p15\.s\[w12, 0\]
+[^:]+: 25334000 psel p0, p0, p0\.s\[w15, 0\]
+[^:]+: 25f04000 psel p0, p0, p0\.s\[w12, 3\]
+[^:]+: 25b16d66 psel p6, p11, p11\.s\[w13, 2\]
+[^:]+: 25604000 psel p0, p0, p0\.d\[w12, 0\]
+[^:]+: 25604000 psel p0, p0, p0\.d\[w12, 0\]
+[^:]+: 2560400f psel p15, p0, p0\.d\[w12, 0\]
+[^:]+: 25607c00 psel p0, p15, p0\.d\[w12, 0\]
+[^:]+: 256041e0 psel p0, p0, p15\.d\[w12, 0\]
+[^:]+: 25634000 psel p0, p0, p0\.d\[w15, 0\]
+[^:]+: 25e04000 psel p0, p0, p0\.d\[w12, 1\]
+[^:]+: 25e164a7 psel p7, p9, p5\.d\[w13, 1\]
diff --git a/gas/testsuite/gas/aarch64/sve2-sme2-1.s b/gas/testsuite/gas/aarch64/sve2-sme2-1.s
new file mode 100644
index 00000000000..3b7572b256d
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2-sme2-1.s
@@ -0,0 +1,35 @@
+ psel pn0, pn0, p0.b[w12, 0]
+ PSEL PN0, PN0, P0.B[W12, 0]
+ psel pn15, pn0, p0.b[w12, 0]
+ psel pn0, pn15, p0.b[w12, 0]
+ psel pn0, pn0, p15.b[w12, 0]
+ psel pn0, pn0, p0.b[w15, 0]
+ psel pn0, pn0, p0.b[w12, 15]
+ psel pn1, pn13, p6.b[w14, 11]
+
+ psel pn0, pn0, p0.h[w12, 0]
+ PSEL PN0, PN0, P0.H[W12, 0]
+ psel pn15, pn0, p0.h[w12, 0]
+ psel pn0, pn15, p0.h[w12, 0]
+ psel pn0, pn0, p15.h[w12, 0]
+ psel pn0, pn0, p0.h[w15, 0]
+ psel pn0, pn0, p0.h[w12, 7]
+ psel pn12, pn7, p14.h[w13, 5]
+
+ psel pn0, pn0, p0.s[w12, 0]
+ PSEL PN0, PN0, P0.S[W12, 0]
+ psel pn15, pn0, p0.s[w12, 0]
+ psel pn0, pn15, p0.s[w12, 0]
+ psel pn0, pn0, p15.s[w12, 0]
+ psel pn0, pn0, p0.s[w15, 0]
+ psel pn0, pn0, p0.s[w12, 3]
+ psel pn6, pn11, p11.s[w13, 2]
+
+ psel pn0, pn0, p0.d[w12, 0]
+ PSEL PN0, PN0, P0.D[W12, 0]
+ psel pn15, pn0, p0.d[w12, 0]
+ psel pn0, pn15, p0.d[w12, 0]
+ psel pn0, pn0, p15.d[w12, 0]
+ psel pn0, pn0, p0.d[w15, 0]
+ psel pn0, pn0, p0.d[w12, 1]
+ psel pn7, pn9, p5.d[w13, 1]
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 7ccbb0eda7c..34893584065 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -439,13 +439,17 @@ enum aarch64_opnd
AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor. */
AARCH64_OPND_SVE_PRFOP, /* SVE prefetch operation. */
AARCH64_OPND_SVE_Pd, /* SVE p0-p15 in Pd. */
+ AARCH64_OPND_SVE_PNd, /* SVE pn0-pn15 in Pd. */
AARCH64_OPND_SVE_Pg3, /* SVE p0-p7 in Pg. */
AARCH64_OPND_SVE_Pg4_5, /* SVE p0-p15 in Pg, bits [8,5]. */
AARCH64_OPND_SVE_Pg4_10, /* SVE p0-p15 in Pg, bits [13,10]. */
+ AARCH64_OPND_SVE_PNg4_10, /* SVE pn0-pn15 in Pg, bits [13,10]. */
AARCH64_OPND_SVE_Pg4_16, /* SVE p0-p15 in Pg, bits [19,16]. */
AARCH64_OPND_SVE_Pm, /* SVE p0-p15 in Pm. */
AARCH64_OPND_SVE_Pn, /* SVE p0-p15 in Pn. */
+ AARCH64_OPND_SVE_PNn, /* SVE pn0-pn15 in Pn. */
AARCH64_OPND_SVE_Pt, /* SVE p0-p15 in Pt. */
+ AARCH64_OPND_SVE_PNt, /* SVE pn0-pn15 in Pt. */
AARCH64_OPND_SVE_Rm, /* Integer Rm or ZR, alt. SVE position. */
AARCH64_OPND_SVE_Rn_SP, /* Integer Rn or SP, alt. SVE position. */
AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */
@@ -783,6 +787,7 @@ enum aarch64_op
OP_UXTL2,
OP_MOV_P_P,
+ OP_MOV_PN_PN,
OP_MOV_Z_P_Z,
OP_MOV_Z_V,
OP_MOV_Z_Z,
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index fd705bb8690..332b3f77846 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -479,124 +479,125 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 1236: /* wfit */
value = 1236; /* --> wfit. */
break;
- case 2049: /* bic */
- case 1299: /* and */
- value = 1299; /* --> and. */
+ case 2053: /* bic */
+ case 1300: /* and */
+ value = 1300; /* --> and. */
break;
- case 1282: /* mov */
- case 1301: /* and */
- value = 1301; /* --> and. */
+ case 1283: /* mov */
+ case 1302: /* and */
+ value = 1302; /* --> and. */
break;
- case 1286: /* movs */
- case 1302: /* ands */
- value = 1302; /* --> ands. */
+ case 1287: /* movs */
+ case 1303: /* ands */
+ value = 1303; /* --> ands. */
break;
- case 2050: /* cmple */
- case 1337: /* cmpge */
- value = 1337; /* --> cmpge. */
+ case 2054: /* cmple */
+ case 1338: /* cmpge */
+ value = 1338; /* --> cmpge. */
break;
- case 2053: /* cmplt */
- case 1340: /* cmpgt */
- value = 1340; /* --> cmpgt. */
+ case 2057: /* cmplt */
+ case 1341: /* cmpgt */
+ value = 1341; /* --> cmpgt. */
break;
- case 2051: /* cmplo */
- case 1342: /* cmphi */
- value = 1342; /* --> cmphi. */
+ case 2055: /* cmplo */
+ case 1343: /* cmphi */
+ value = 1343; /* --> cmphi. */
break;
- case 2052: /* cmpls */
- case 1345: /* cmphs */
- value = 1345; /* --> cmphs. */
+ case 2056: /* cmpls */
+ case 1346: /* cmphs */
+ value = 1346; /* --> cmphs. */
break;
- case 1279: /* mov */
- case 1367: /* cpy */
- value = 1367; /* --> cpy. */
- break;
- case 1281: /* mov */
+ case 1280: /* mov */
case 1368: /* cpy */
value = 1368; /* --> cpy. */
break;
- case 2060: /* fmov */
- case 1284: /* mov */
+ case 1282: /* mov */
case 1369: /* cpy */
value = 1369; /* --> cpy. */
break;
- case 1274: /* mov */
- case 1381: /* dup */
- value = 1381; /* --> dup. */
+ case 2064: /* fmov */
+ case 1285: /* mov */
+ case 1370: /* cpy */
+ value = 1370; /* --> cpy. */
break;
- case 1276: /* mov */
- case 1273: /* mov */
+ case 1274: /* mov */
case 1382: /* dup */
value = 1382; /* --> dup. */
break;
- case 2059: /* fmov */
- case 1278: /* mov */
+ case 1277: /* mov */
+ case 1273: /* mov */
case 1383: /* dup */
value = 1383; /* --> dup. */
break;
- case 1277: /* mov */
- case 1384: /* dupm */
- value = 1384; /* --> dupm. */
+ case 2063: /* fmov */
+ case 1279: /* mov */
+ case 1384: /* dup */
+ value = 1384; /* --> dup. */
break;
- case 2054: /* eon */
- case 1386: /* eor */
- value = 1386; /* --> eor. */
+ case 1278: /* mov */
+ case 1385: /* dupm */
+ value = 1385; /* --> dupm. */
+ break;
+ case 2058: /* eon */
+ case 1387: /* eor */
+ value = 1387; /* --> eor. */
break;
- case 1287: /* not */
- case 1388: /* eor */
- value = 1388; /* --> eor. */
+ case 1288: /* not */
+ case 1389: /* eor */
+ value = 1389; /* --> eor. */
break;
- case 1288: /* nots */
- case 1389: /* eors */
- value = 1389; /* --> eors. */
+ case 1289: /* nots */
+ case 1390: /* eors */
+ value = 1390; /* --> eors. */
break;
- case 2055: /* facle */
- case 1394: /* facge */
- value = 1394; /* --> facge. */
+ case 2059: /* facle */
+ case 1395: /* facge */
+ value = 1395; /* --> facge. */
break;
- case 2056: /* faclt */
- case 1395: /* facgt */
- value = 1395; /* --> facgt. */
+ case 2060: /* faclt */
+ case 1396: /* facgt */
+ value = 1396; /* --> facgt. */
break;
- case 2057: /* fcmle */
- case 1408: /* fcmge */
- value = 1408; /* --> fcmge. */
+ case 2061: /* fcmle */
+ case 1409: /* fcmge */
+ value = 1409; /* --> fcmge. */
break;
- case 2058: /* fcmlt */
- case 1410: /* fcmgt */
- value = 1410; /* --> fcmgt. */
+ case 2062: /* fcmlt */
+ case 1411: /* fcmgt */
+ value = 1411; /* --> fcmgt. */
break;
case 1271: /* fmov */
- case 1416: /* fcpy */
- value = 1416; /* --> fcpy. */
+ case 1417: /* fcpy */
+ value = 1417; /* --> fcpy. */
break;
case 1270: /* fmov */
- case 1439: /* fdup */
- value = 1439; /* --> fdup. */
+ case 1440: /* fdup */
+ value = 1440; /* --> fdup. */
break;
case 1272: /* mov */
- case 1770: /* orr */
- value = 1770; /* --> orr. */
- break;
- case 2061: /* orn */
- case 1771: /* orr */
- value = 1771; /* --> orr. */
+ case 1772: /* orr */
+ value = 1772; /* --> orr. */
break;
- case 1275: /* mov */
+ case 2065: /* orn */
case 1773: /* orr */
value = 1773; /* --> orr. */
break;
- case 1285: /* movs */
- case 1774: /* orrs */
- value = 1774; /* --> orrs. */
+ case 1276: /* mov */
+ case 1275: /* mov */
+ case 1775: /* orr */
+ value = 1775; /* --> orr. */
break;
- case 1280: /* mov */
- case 1836: /* sel */
- value = 1836; /* --> sel. */
+ case 1286: /* movs */
+ case 1776: /* orrs */
+ value = 1776; /* --> orrs. */
break;
- case 1283: /* mov */
- case 1837: /* sel */
- value = 1837; /* --> sel. */
+ case 1281: /* mov */
+ case 1839: /* sel */
+ value = 1839; /* --> sel. */
+ break;
+ case 1284: /* mov */
+ case 1840: /* sel */
+ value = 1840; /* --> sel. */
break;
default: return NULL;
}
@@ -651,20 +652,24 @@ aarch64_insert_operand (const aarch64_operand *self,
case 174:
case 175:
case 176:
- case 191:
- case 192:
- case 193:
- case 194:
+ case 177:
+ case 178:
+ case 179:
+ case 180:
case 195:
case 196:
case 197:
case 198:
case 199:
- case 205:
- case 208:
- case 210:
- case 211:
+ case 200:
+ case 201:
+ case 202:
+ case 203:
+ case 209:
+ case 212:
case 214:
+ case 215:
+ case 218:
return aarch64_ins_regno (self, info, code, inst, errors);
case 15:
return aarch64_ins_reg_extended (self, info, code, inst, errors);
@@ -676,7 +681,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 33:
case 34:
case 35:
- case 222:
+ case 226:
return aarch64_ins_reglane (self, info, code, inst, errors);
case 36:
return aarch64_ins_reglist (self, info, code, inst, errors);
@@ -713,18 +718,18 @@ aarch64_insert_operand (const aarch64_operand *self,
case 84:
case 164:
case 166:
- case 183:
- case 184:
- case 185:
- case 186:
case 187:
case 188:
case 189:
case 190:
- case 215:
- case 221:
- case 226:
- case 227:
+ case 191:
+ case 192:
+ case 193:
+ case 194:
+ case 219:
+ case 225:
+ case 230:
+ case 231:
return aarch64_ins_imm (self, info, code, inst, errors);
case 44:
case 45:
@@ -865,40 +870,40 @@ aarch64_insert_operand (const aarch64_operand *self,
return aarch64_ins_sve_limm_mov (self, info, code, inst, errors);
case 165:
return aarch64_ins_sve_scale (self, info, code, inst, errors);
- case 177:
- case 178:
- case 179:
- return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
- case 180:
case 181:
case 182:
+ case 183:
+ return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
+ case 184:
+ case 185:
+ case 186:
return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
- case 200:
- case 201:
- case 202:
- case 203:
case 204:
- return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
+ case 205:
case 206:
- return aarch64_ins_sve_index (self, info, code, inst, errors);
case 207:
- case 209:
- return aarch64_ins_sve_reglist (self, info, code, inst, errors);
- case 212:
+ case 208:
+ return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
+ case 210:
+ return aarch64_ins_sve_index (self, info, code, inst, errors);
+ case 211:
case 213:
+ return aarch64_ins_sve_reglist (self, info, code, inst, errors);
case 216:
- return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
case 217:
+ case 220:
+ return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
+ case 221:
return aarch64_ins_sme_za_array (self, info, code, inst, errors);
- case 218:
+ case 222:
return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
- case 219:
- return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
- case 220:
- return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
case 223:
+ return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
case 224:
- case 225:
+ return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
+ case 227:
+ case 228:
+ case 229:
return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
default: assert (0); abort ();
}
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index 5a9ca5a980d..10b70824b05 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -1643,6 +1643,7 @@ do_misc_encoding (aarch64_inst *inst)
encode_asisd_fcvtxn (inst);
break;
case OP_MOV_P_P:
+ case OP_MOV_PN_PN:
case OP_MOVS_P_P:
/* Copy Pn to Pm and Pg. */
value = extract_field (FLD_SVE_Pn, inst->value, 0);
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index ec2bed95d8e..53fc8122ac8 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -60,7 +60,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0000000100xxxxxxxxxxxxxxxx0xxxx
fmopa. */
- return 2361;
+ return 2365;
}
else
{
@@ -68,7 +68,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0000000100xxxxxxxxxxxxxxxx1xxxx
fmops. */
- return 2364;
+ return 2368;
}
}
}
@@ -80,7 +80,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0000000x10xxxxxxxxxxxxxxxx0xxxx
fmopa. */
- return 2362;
+ return 2366;
}
else
{
@@ -88,7 +88,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0000000x10xxxxxxxxxxxxxxxx1xxxx
fmops. */
- return 2365;
+ return 2369;
}
}
}
@@ -104,7 +104,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx000x0xxxxxxxxxxxxxxxxx
mov. */
- return 2385;
+ return 2389;
}
else
{
@@ -116,7 +116,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000x0010x00xxxxxxxxxxxxxxxx
addha. */
- return 2353;
+ return 2357;
}
else
{
@@ -124,7 +124,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000x1010x00xxxxxxxxxxxxxxxx
addha. */
- return 2354;
+ return 2358;
}
}
else
@@ -135,7 +135,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000x0010x01xxxxxxxxxxxxxxxx
addva. */
- return 2357;
+ return 2361;
}
else
{
@@ -143,7 +143,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000x1010x01xxxxxxxxxxxxxxxx
addva. */
- return 2358;
+ return 2362;
}
}
}
@@ -154,7 +154,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx0x1x0xxxxxxxxxxxxxxxxx
zero. */
- return 2388;
+ return 2392;
}
}
else
@@ -163,7 +163,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx0xxx1xxxxxxxxxxxxxxxxx
mov. */
- return 2384;
+ return 2388;
}
}
}
@@ -179,7 +179,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx100000000xxxxxxxxxxxxxxxx0xxxx
ld1b. */
- return 2389;
+ return 2393;
}
else
{
@@ -189,7 +189,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000100xxxxxxxxxxxxxxxx0xxxx
smopa. */
- return 2368;
+ return 2372;
}
else
{
@@ -197,7 +197,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1100000100xxxxxxxxxxxxxxxx0xxxx
ld1w. */
- return 2391;
+ return 2395;
}
}
}
@@ -209,7 +209,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx100000010xxxxxxxxxxxxxxxx0xxxx
ld1h. */
- return 2390;
+ return 2394;
}
else
{
@@ -219,7 +219,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000110xxxxxxxxxxxxxxxx0xxxx
smopa. */
- return 2369;
+ return 2373;
}
else
{
@@ -227,7 +227,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1100000110xxxxxxxxxxxxxxxx0xxxx
ld1d. */
- return 2392;
+ return 2396;
}
}
}
@@ -240,7 +240,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx100000x00xxxxxxxxxxxxxxxx1xxxx
smops. */
- return 2370;
+ return 2374;
}
else
{
@@ -248,7 +248,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx100000x10xxxxxxxxxxxxxxxx1xxxx
smops. */
- return 2371;
+ return 2375;
}
}
}
@@ -265,7 +265,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx00000001xxxxxxxxxxxxxxxx0xxxx
st1b. */
- return 2399;
+ return 2403;
}
else
{
@@ -275,7 +275,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000101xxxxxxxxxxxxxxxx0xxxx
sumopa. */
- return 2372;
+ return 2376;
}
else
{
@@ -283,7 +283,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1x00000101xxxxxxxxxxxxxxxx0xxxx
st1w. */
- return 2401;
+ return 2405;
}
}
}
@@ -295,7 +295,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx00000011xxxxxxxxxxxxxxxx0xxxx
st1h. */
- return 2400;
+ return 2404;
}
else
{
@@ -305,7 +305,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000111xxxxxxxxxxxxxxxx0xxxx
sumopa. */
- return 2373;
+ return 2377;
}
else
{
@@ -313,7 +313,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1x00000111xxxxxxxxxxxxxxxx0xxxx
st1d. */
- return 2402;
+ return 2406;
}
}
}
@@ -326,7 +326,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx00000x01xxxxxxxxxxxxxxxx1xxxx
sumops. */
- return 2374;
+ return 2378;
}
else
{
@@ -334,7 +334,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx00000x11xxxxxxxxxxxxxxxx1xxxx
sumops. */
- return 2375;
+ return 2379;
}
}
}
@@ -375,7 +375,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx00001000xxxxxxxxxxxxxxxx0xxxx
ldr. */
- return 2409;
+ return 2413;
}
else
{
@@ -385,7 +385,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000001100xxxxxxxxxxxxxxxx0xxxx
bfmopa. */
- return 2359;
+ return 2363;
}
else
{
@@ -393,7 +393,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx100001100xxxxxxxxxxxxxxxx0xxxx
usmopa. */
- return 2380;
+ return 2384;
}
}
}
@@ -405,7 +405,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00001x10xxxxxxxxxxxxxxxx0xxxx
usmopa. */
- return 2381;
+ return 2385;
}
else
{
@@ -413,7 +413,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1x00001x10xxxxxxxxxxxxxxxx0xxxx
ld1q. */
- return 2393;
+ return 2397;
}
}
}
@@ -427,7 +427,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx00001001xxxxxxxxxxxxxxxx0xxxx
str. */
- return 2410;
+ return 2414;
}
else
{
@@ -437,7 +437,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000001101xxxxxxxxxxxxxxxx0xxxx
fmopa. */
- return 2363;
+ return 2367;
}
else
{
@@ -445,7 +445,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx100001101xxxxxxxxxxxxxxxx0xxxx
umopa. */
- return 2376;
+ return 2380;
}
}
}
@@ -457,7 +457,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00001x11xxxxxxxxxxxxxxxx0xxxx
umopa. */
- return 2377;
+ return 2381;
}
else
{
@@ -465,7 +465,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1x00001x11xxxxxxxxxxxxxxxx0xxxx
st1q. */
- return 2403;
+ return 2407;
}
}
}
@@ -482,7 +482,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000001x00xxxxxxxxxxxxxxxx1xxxx
bfmops. */
- return 2360;
+ return 2364;
}
else
{
@@ -490,7 +490,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx100001x00xxxxxxxxxxxxxxxx1xxxx
usmops. */
- return 2382;
+ return 2386;
}
}
else
@@ -499,7 +499,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx00001x10xxxxxxxxxxxxxxxx1xxxx
usmops. */
- return 2383;
+ return 2387;
}
}
else
@@ -512,7 +512,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000001x01xxxxxxxxxxxxxxxx1xxxx
fmops. */
- return 2366;
+ return 2370;
}
else
{
@@ -520,7 +520,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx100001x01xxxxxxxxxxxxxxxx1xxxx
umops. */
- return 2378;
+ return 2382;
}
}
else
@@ -529,7 +529,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx00001x11xxxxxxxxxxxxxxxx1xxxx
umops. */
- return 2379;
+ return 2383;
}
}
}
@@ -2896,7 +2896,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00011001000xxxxxxxxx00xxxxxxxxxx
stlurb. */
- return 2455;
+ return 2460;
}
else
{
@@ -2904,7 +2904,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
10011001000xxxxxxxxx00xxxxxxxxxx
stlur. */
- return 2463;
+ return 2468;
}
}
else
@@ -2915,7 +2915,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01011001000xxxxxxxxx00xxxxxxxxxx
stlurh. */
- return 2459;
+ return 2464;
}
else
{
@@ -2923,7 +2923,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
11011001000xxxxxxxxx00xxxxxxxxxx
stlur. */
- return 2466;
+ return 2471;
}
}
}
@@ -2961,7 +2961,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001000xxxxx0000x1xxxxxxxxxx
cpyfp. */
- return 2515;
+ return 2520;
}
else
{
@@ -2969,7 +2969,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001000xxxxx1000x1xxxxxxxxxx
cpyfprn. */
- return 2521;
+ return 2526;
}
}
else
@@ -2980,7 +2980,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001000xxxxx0100x1xxxxxxxxxx
cpyfpwn. */
- return 2518;
+ return 2523;
}
else
{
@@ -2988,7 +2988,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001000xxxxx1100x1xxxxxxxxxx
cpyfpn. */
- return 2524;
+ return 2529;
}
}
}
@@ -3002,7 +3002,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001000xxxxx0010x1xxxxxxxxxx
cpyfprt. */
- return 2539;
+ return 2544;
}
else
{
@@ -3010,7 +3010,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001000xxxxx1010x1xxxxxxxxxx
cpyfprtrn. */
- return 2545;
+ return 2550;
}
}
else
@@ -3021,7 +3021,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001000xxxxx0110x1xxxxxxxxxx
cpyfprtwn. */
- return 2542;
+ return 2547;
}
else
{
@@ -3029,7 +3029,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001000xxxxx1110x1xxxxxxxxxx
cpyfprtn. */
- return 2548;
+ return 2553;
}
}
}
@@ -3046,7 +3046,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001000xxxxx0001x1xxxxxxxxxx
cpyfpwt. */
- return 2527;
+ return 2532;
}
else
{
@@ -3054,7 +3054,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001000xxxxx1001x1xxxxxxxxxx
cpyfpwtrn. */
- return 2533;
+ return 2538;
}
}
else
@@ -3065,7 +3065,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001000xxxxx0101x1xxxxxxxxxx
cpyfpwtwn. */
- return 2530;
+ return 2535;
}
else
{
@@ -3073,7 +3073,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001000xxxxx1101x1xxxxxxxxxx
cpyfpwtn. */
- return 2536;
+ return 2541;
}
}
}
@@ -3087,7 +3087,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001000xxxxx0011x1xxxxxxxxxx
cpyfpt. */
- return 2551;
+ return 2556;
}
else
{
@@ -3095,7 +3095,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001000xxxxx1011x1xxxxxxxxxx
cpyfptrn. */
- return 2557;
+ return 2562;
}
}
else
@@ -3106,7 +3106,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001000xxxxx0111x1xxxxxxxxxx
cpyfptwn. */
- return 2554;
+ return 2559;
}
else
{
@@ -3114,7 +3114,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001000xxxxx1111x1xxxxxxxxxx
cpyfptn. */
- return 2560;
+ return 2565;
}
}
}
@@ -3179,7 +3179,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00011001010xxxxxxxxx00xxxxxxxxxx
ldapurb. */
- return 2456;
+ return 2461;
}
else
{
@@ -3187,7 +3187,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
10011001010xxxxxxxxx00xxxxxxxxxx
ldapur. */
- return 2464;
+ return 2469;
}
}
else
@@ -3198,7 +3198,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01011001010xxxxxxxxx00xxxxxxxxxx
ldapurh. */
- return 2460;
+ return 2465;
}
else
{
@@ -3206,7 +3206,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
11011001010xxxxxxxxx00xxxxxxxxxx
ldapur. */
- return 2467;
+ return 2472;
}
}
}
@@ -3244,7 +3244,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001010xxxxx0000x1xxxxxxxxxx
cpyfm. */
- return 2516;
+ return 2521;
}
else
{
@@ -3252,7 +3252,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001010xxxxx1000x1xxxxxxxxxx
cpyfmrn. */
- return 2522;
+ return 2527;
}
}
else
@@ -3263,7 +3263,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001010xxxxx0100x1xxxxxxxxxx
cpyfmwn. */
- return 2519;
+ return 2524;
}
else
{
@@ -3271,7 +3271,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001010xxxxx1100x1xxxxxxxxxx
cpyfmn. */
- return 2525;
+ return 2530;
}
}
}
@@ -3285,7 +3285,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001010xxxxx0010x1xxxxxxxxxx
cpyfmrt. */
- return 2540;
+ return 2545;
}
else
{
@@ -3293,7 +3293,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001010xxxxx1010x1xxxxxxxxxx
cpyfmrtrn. */
- return 2546;
+ return 2551;
}
}
else
@@ -3304,7 +3304,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001010xxxxx0110x1xxxxxxxxxx
cpyfmrtwn. */
- return 2543;
+ return 2548;
}
else
{
@@ -3312,7 +3312,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001010xxxxx1110x1xxxxxxxxxx
cpyfmrtn. */
- return 2549;
+ return 2554;
}
}
}
@@ -3329,7 +3329,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001010xxxxx0001x1xxxxxxxxxx
cpyfmwt. */
- return 2528;
+ return 2533;
}
else
{
@@ -3337,7 +3337,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001010xxxxx1001x1xxxxxxxxxx
cpyfmwtrn. */
- return 2534;
+ return 2539;
}
}
else
@@ -3348,7 +3348,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001010xxxxx0101x1xxxxxxxxxx
cpyfmwtwn. */
- return 2531;
+ return 2536;
}
else
{
@@ -3356,7 +3356,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001010xxxxx1101x1xxxxxxxxxx
cpyfmwtn. */
- return 2537;
+ return 2542;
}
}
}
@@ -3370,7 +3370,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001010xxxxx0011x1xxxxxxxxxx
cpyfmt. */
- return 2552;
+ return 2557;
}
else
{
@@ -3378,7 +3378,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001010xxxxx1011x1xxxxxxxxxx
cpyfmtrn. */
- return 2558;
+ return 2563;
}
}
else
@@ -3389,7 +3389,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001010xxxxx0111x1xxxxxxxxxx
cpyfmtwn. */
- return 2555;
+ return 2560;
}
else
{
@@ -3397,7 +3397,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001010xxxxx1111x1xxxxxxxxxx
cpyfmtn. */
- return 2561;
+ return 2566;
}
}
}
@@ -3465,7 +3465,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00011001100xxxxxxxxx00xxxxxxxxxx
ldapursb. */
- return 2458;
+ return 2463;
}
else
{
@@ -3473,7 +3473,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
10011001100xxxxxxxxx00xxxxxxxxxx
ldapursw. */
- return 2465;
+ return 2470;
}
}
else
@@ -3482,7 +3482,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1011001100xxxxxxxxx00xxxxxxxxxx
ldapursh. */
- return 2462;
+ return 2467;
}
}
else
@@ -3493,7 +3493,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0011001110xxxxxxxxx00xxxxxxxxxx
ldapursb. */
- return 2457;
+ return 2462;
}
else
{
@@ -3501,7 +3501,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1011001110xxxxxxxxx00xxxxxxxxxx
ldapursh. */
- return 2461;
+ return 2466;
}
}
}
@@ -3563,7 +3563,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001100xxxxx0000x1xxxxxxxxxx
cpyfe. */
- return 2517;
+ return 2522;
}
else
{
@@ -3571,7 +3571,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001110xxxxx0000x1xxxxxxxxxx
setp. */
- return 2611;
+ return 2616;
}
}
else
@@ -3582,7 +3582,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001100xxxxx1000x1xxxxxxxxxx
cpyfern. */
- return 2523;
+ return 2528;
}
else
{
@@ -3590,7 +3590,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001110xxxxx1000x1xxxxxxxxxx
sete. */
- return 2613;
+ return 2618;
}
}
}
@@ -3604,7 +3604,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001100xxxxx0100x1xxxxxxxxxx
cpyfewn. */
- return 2520;
+ return 2525;
}
else
{
@@ -3612,7 +3612,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001110xxxxx0100x1xxxxxxxxxx
setm. */
- return 2612;
+ return 2617;
}
}
else
@@ -3621,7 +3621,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0110011x0xxxxx1100x1xxxxxxxxxx
cpyfen. */
- return 2526;
+ return 2531;
}
}
}
@@ -3637,7 +3637,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001100xxxxx0010x1xxxxxxxxxx
cpyfert. */
- return 2541;
+ return 2546;
}
else
{
@@ -3645,7 +3645,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001110xxxxx0010x1xxxxxxxxxx
setpn. */
- return 2617;
+ return 2622;
}
}
else
@@ -3656,7 +3656,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001100xxxxx1010x1xxxxxxxxxx
cpyfertrn. */
- return 2547;
+ return 2552;
}
else
{
@@ -3664,7 +3664,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001110xxxxx1010x1xxxxxxxxxx
seten. */
- return 2619;
+ return 2624;
}
}
}
@@ -3678,7 +3678,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001100xxxxx0110x1xxxxxxxxxx
cpyfertwn. */
- return 2544;
+ return 2549;
}
else
{
@@ -3686,7 +3686,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001110xxxxx0110x1xxxxxxxxxx
setmn. */
- return 2618;
+ return 2623;
}
}
else
@@ -3695,7 +3695,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0110011x0xxxxx1110x1xxxxxxxxxx
cpyfertn. */
- return 2550;
+ return 2555;
}
}
}
@@ -3714,7 +3714,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001100xxxxx0001x1xxxxxxxxxx
cpyfewt. */
- return 2529;
+ return 2534;
}
else
{
@@ -3722,7 +3722,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001110xxxxx0001x1xxxxxxxxxx
setpt. */
- return 2614;
+ return 2619;
}
}
else
@@ -3733,7 +3733,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001100xxxxx1001x1xxxxxxxxxx
cpyfewtrn. */
- return 2535;
+ return 2540;
}
else
{
@@ -3741,7 +3741,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001110xxxxx1001x1xxxxxxxxxx
setet. */
- return 2616;
+ return 2621;
}
}
}
@@ -3755,7 +3755,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001100xxxxx0101x1xxxxxxxxxx
cpyfewtwn. */
- return 2532;
+ return 2537;
}
else
{
@@ -3763,7 +3763,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001110xxxxx0101x1xxxxxxxxxx
setmt. */
- return 2615;
+ return 2620;
}
}
else
@@ -3772,7 +3772,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0110011x0xxxxx1101x1xxxxxxxxxx
cpyfewtn. */
- return 2538;
+ return 2543;
}
}
}
@@ -3788,7 +3788,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001100xxxxx0011x1xxxxxxxxxx
cpyfet. */
- return 2553;
+ return 2558;
}
else
{
@@ -3796,7 +3796,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001110xxxxx0011x1xxxxxxxxxx
setptn. */
- return 2620;
+ return 2625;
}
}
else
@@ -3807,7 +3807,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001100xxxxx1011x1xxxxxxxxxx
cpyfetrn. */
- return 2559;
+ return 2564;
}
else
{
@@ -3815,7 +3815,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx011001110xxxxx1011x1xxxxxxxxxx
setetn. */
- return 2622;
+ return 2627;
[...]
[diff truncated at 100000 bytes]
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2023-03-30 10:14 [binutils-gdb] aarch64: Add support for predicate-as-counter registers Richard Sandiford
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