* [binutils-gdb] aarch64: Add the SME2 ZT0 instructions
@ 2023-03-30 10:15 Richard Sandiford
0 siblings, 0 replies; only message in thread
From: Richard Sandiford @ 2023-03-30 10:15 UTC (permalink / raw)
To: bfd-cvs
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=cbd11b8818335007cf960e0cecc4dec445f80327
commit cbd11b8818335007cf960e0cecc4dec445f80327
Author: Richard Sandiford <richard.sandiford@arm.com>
Date: Thu Mar 30 11:09:12 2023 +0100
aarch64: Add the SME2 ZT0 instructions
SME2 adds lookup table instructions for quantisation. They use
a new lookup table register called ZT0.
LUTI2 takes an unsuffixed SVE vector index of the form Zn[<imm>],
which is the first time that this syntax has been used.
Diff:
---
gas/config/tc-aarch64.c | 73 ++-
gas/testsuite/gas/aarch64/sme-4-illegal.l | 6 +-
gas/testsuite/gas/aarch64/sme2-8-invalid.d | 3 +
gas/testsuite/gas/aarch64/sme2-8-invalid.l | 208 +++++++
gas/testsuite/gas/aarch64/sme2-8-invalid.s | 116 ++++
gas/testsuite/gas/aarch64/sme2-8-noarch.d | 3 +
gas/testsuite/gas/aarch64/sme2-8-noarch.l | 104 ++++
gas/testsuite/gas/aarch64/sme2-8.d | 112 ++++
gas/testsuite/gas/aarch64/sme2-8.s | 124 ++++
gas/testsuite/gas/aarch64/sve-invalid.l | 8 +
gas/testsuite/gas/aarch64/sve-invalid.s | 1 +
include/opcode/aarch64.h | 11 +
opcodes/aarch64-asm-2.c | 25 +-
opcodes/aarch64-asm.c | 12 +
opcodes/aarch64-dis-2.c | 902 +++++++++++++++++------------
opcodes/aarch64-dis.c | 15 +
opcodes/aarch64-opc-2.c | 9 +
opcodes/aarch64-opc.c | 59 +-
opcodes/aarch64-opc.h | 19 +-
opcodes/aarch64-tbl.h | 42 ++
20 files changed, 1443 insertions(+), 409 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index a433925e320..652fd4e6ff3 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -312,6 +312,7 @@ struct reloc_entry
BASIC_REG_TYPE(ZAT) /* za[0-15] (ZA tile) */ \
BASIC_REG_TYPE(ZATH) /* za[0-15]h (ZA tile horizontal slice) */ \
BASIC_REG_TYPE(ZATV) /* za[0-15]v (ZA tile vertical slice) */ \
+ BASIC_REG_TYPE(ZT0) /* zt0 */ \
/* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \
MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
/* Typecheck: same, plus SVE registers. */ \
@@ -483,11 +484,11 @@ get_reg_expected_msg (unsigned int mask, unsigned int seen)
if (mask == reg_type_masks[REG_TYPE_VZP])
return N_("expected a vector or predicate register at operand %d");
- /* ZA-related registers. */
+ /* SME-related registers. */
if (mask == reg_type_masks[REG_TYPE_ZA])
return N_("expected a ZA array vector at operand %d");
- if (mask == reg_type_masks[REG_TYPE_ZA_ZAT])
- return N_("expected 'za' or a ZA tile at operand %d");
+ if (mask == (reg_type_masks[REG_TYPE_ZA_ZAT] | reg_type_masks[REG_TYPE_ZT0]))
+ return N_("expected ZT0 or a ZA mask at operand %d");
if (mask == reg_type_masks[REG_TYPE_ZAT])
return N_("expected a ZA tile at operand %d");
if (mask == reg_type_masks[REG_TYPE_ZATHV])
@@ -1279,7 +1280,10 @@ parse_typed_reg (char **ccp, aarch64_reg_type type,
if (!(flags & PTR_FULL_REG) && skip_past_char (&str, '['))
{
/* Reject Sn[index] syntax. */
- if (reg->type != REG_TYPE_PN && !is_typed_vecreg)
+ if (reg->type != REG_TYPE_Z
+ && reg->type != REG_TYPE_PN
+ && reg->type != REG_TYPE_ZT0
+ && !is_typed_vecreg)
{
first_error (_("this type of register can't be indexed"));
return NULL;
@@ -6722,6 +6726,12 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_SVE_Zm4_11_INDEX:
case AARCH64_OPND_SVE_Zm4_INDEX:
case AARCH64_OPND_SVE_Zn_INDEX:
+ case AARCH64_OPND_SME_Zn_INDEX1_16:
+ case AARCH64_OPND_SME_Zn_INDEX2_15:
+ case AARCH64_OPND_SME_Zn_INDEX2_16:
+ case AARCH64_OPND_SME_Zn_INDEX3_14:
+ case AARCH64_OPND_SME_Zn_INDEX3_15:
+ case AARCH64_OPND_SME_Zn_INDEX4_14:
reg_type = REG_TYPE_Z;
goto vector_reg_index;
@@ -6735,14 +6745,23 @@ parse_operands (char *str, const aarch64_opcode *opcode)
reg = aarch64_reg_parse (&str, reg_type, &vectype);
if (!reg)
goto failure;
- if (vectype.type == NT_invtype || !(vectype.defined & NTA_HASINDEX))
+ if (!(vectype.defined & NTA_HASINDEX))
goto failure;
+ if (reg->type == REG_TYPE_Z && vectype.type == NT_invtype)
+ /* Unqualified Zn[index] is allowed in LUTI2 instructions. */
+ info->qualifier = AARCH64_OPND_QLF_NIL;
+ else
+ {
+ if (vectype.type == NT_invtype)
+ goto failure;
+ info->qualifier = vectype_to_qualifier (&vectype);
+ if (info->qualifier == AARCH64_OPND_QLF_NIL)
+ goto failure;
+ }
+
info->reglane.regno = reg->number;
info->reglane.index = vectype.index;
- info->qualifier = vectype_to_qualifier (&vectype);
- if (info->qualifier == AARCH64_OPND_QLF_NIL)
- goto failure;
break;
case AARCH64_OPND_SVE_ZnxN:
@@ -7740,6 +7759,39 @@ parse_operands (char *str, const aarch64_opcode *opcode)
goto failure;
break;
+ case AARCH64_OPND_SME_ZT0:
+ po_reg_or_fail (REG_TYPE_ZT0);
+ break;
+
+ case AARCH64_OPND_SME_ZT0_INDEX:
+ reg = aarch64_reg_parse (&str, REG_TYPE_ZT0, &vectype);
+ if (!reg || vectype.type != NT_invtype)
+ goto failure;
+ if (!(vectype.defined & NTA_HASINDEX))
+ {
+ set_syntax_error (_("missing register index"));
+ goto failure;
+ }
+ info->imm.value = vectype.index;
+ break;
+
+ case AARCH64_OPND_SME_ZT0_LIST:
+ if (*str != '{')
+ {
+ set_expected_reglist_error (REG_TYPE_ZT0, parse_reg (&str));
+ goto failure;
+ }
+ str++;
+ if (!parse_typed_reg (&str, REG_TYPE_ZT0, &vectype, PTR_IN_REGLIST))
+ goto failure;
+ if (*str != '}')
+ {
+ set_syntax_error (_("expected '}' after ZT0"));
+ goto failure;
+ }
+ str++;
+ break;
+
case AARCH64_OPND_SME_PNn3_INDEX1:
case AARCH64_OPND_SME_PNn3_INDEX2:
reg = aarch64_reg_parse (&str, REG_TYPE_PN, &vectype);
@@ -8462,7 +8514,10 @@ static const reg_entry reg_names[] = {
REGSET16S (za, h, ZATH), REGSET16S (ZA, H, ZATH),
/* SME ZA tile registers (vertical slice). */
- REGSET16S (za, v, ZATV), REGSET16S (ZA, V, ZATV)
+ REGSET16S (za, v, ZATV), REGSET16S (ZA, V, ZATV),
+
+ /* SME2 ZT0. */
+ REGDEF (zt0, 0, ZT0), REGDEF (ZT0, 0, ZT0)
};
#undef REGDEF
diff --git a/gas/testsuite/gas/aarch64/sme-4-illegal.l b/gas/testsuite/gas/aarch64/sme-4-illegal.l
index 86e315476dd..a9e98524067 100644
--- a/gas/testsuite/gas/aarch64/sme-4-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-4-illegal.l
@@ -22,11 +22,11 @@
[^:]*:[0-9]+: Error: syntax error in register list at operand 1 -- `zero {za,}'
[^:]*:[0-9]+: Error: unexpected character `}' in element size at operand 1 -- `zero {za.}'
[^:]*:[0-9]+: Error: expected '}' at operand 1 -- `zero {za-}'
-[^:]*:[0-9]+: Error: expected 'za' or a ZA tile at operand 1 -- `zero {za_}'
+[^:]*:[0-9]+: Error: expected ZT0 or a ZA mask at operand 1 -- `zero {za_}'
[^:]*:[0-9]+: Error: expected '}' at operand 1 -- `zero {za#}'
-[^:]*:[0-9]+: Error: expected 'za' or a ZA tile at operand 1 -- `zero {zaX}'
+[^:]*:[0-9]+: Error: expected ZT0 or a ZA mask at operand 1 -- `zero {zaX}'
[^:]*:[0-9]+: Error: missing ZA tile size at operand 1 -- `zero {za0}'
-[^:]*:[0-9]+: Error: expected 'za' or a ZA tile at operand 1 -- `zero {zax}'
+[^:]*:[0-9]+: Error: expected ZT0 or a ZA mask at operand 1 -- `zero {zax}'
[^:]*:[0-9]+: Error: expected '}' at operand 1 -- `zero {za{}'
[^:]*:[0-9]+: Error: unexpected characters following instruction at operand 1 -- `zero {za}}'
[^:]*:[0-9]+: Error: ZA tile masks do not operate at .Q granularity at operand 1 -- `zero {za0\.q}'
diff --git a/gas/testsuite/gas/aarch64/sme2-8-invalid.d b/gas/testsuite/gas/aarch64/sme2-8-invalid.d
new file mode 100644
index 00000000000..d9f587d6019
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-8-invalid.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a
+#source: sme2-8-invalid.s
+#error_output: sme2-8-invalid.l
diff --git a/gas/testsuite/gas/aarch64/sme2-8-invalid.l b/gas/testsuite/gas/aarch64/sme2-8-invalid.l
new file mode 100644
index 00000000000..afea8bb6735
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-8-invalid.l
@@ -0,0 +1,208 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: expected '{' at operand 1 -- `zero 0'
+[^ :]+:[0-9]+: Error: expected '{' at operand 1 -- `zero zt0'
+[^ :]+:[0-9]+: Error: syntax error in register list at operand 1 -- `zero {'
+[^ :]+:[0-9]+: Error: expected ZT0 or a ZA mask at operand 1 -- `zero {foo}'
+[^ :]+:[0-9]+: Error: expected ZT0 or a ZA mask at operand 1 -- `zero {zt}'
+[^ :]+:[0-9]+: Error: expected ZT0 or a ZA mask at operand 1 -- `zero {x0}'
+[^ :]+:[0-9]+: Error: expected ZT0 or a ZA mask at operand 1 -- `zero {z0}'
+[^ :]+:[0-9]+: Error: expected '}' after ZT0 at operand 1 -- `zero {zt0'
+[^ :]+:[0-9]+: Error: expected '}' after ZT0 at operand 1 -- `zero {zt0\.b}'
+[^ :]+:[0-9]+: Error: expected '}' after ZT0 at operand 1 -- `zero {zt0,zt0}'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `movt 0,zt0\[0\]'
+[^ :]+:[0-9]+: Error: expected a register at operand 2 -- `movt x0,0'
+[^ :]+:[0-9]+: Error: missing register index at operand 1 -- `movt zt0,x0'
+[^ :]+:[0-9]+: Error: unexpected register type at operand 1 -- `movt za\[0\],x0'
+[^ :]+:[0-9]+: Error: unexpected register type at operand 1 -- `movt za0\[0\],x0'
+[^ :]+:[0-9]+: Error: bad expression at operand 1 -- `movt zt0\[#0\],x0'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 56 at operand 1 -- `movt zt0\[-1\],x0'
+[^ :]+:[0-9]+: Error: byte index must be a multiple of 8 at operand 1 -- `movt zt0\[1\],x0'
+[^ :]+:[0-9]+: Error: byte index must be a multiple of 8 at operand 1 -- `movt zt0\[2\],x0'
+[^ :]+:[0-9]+: Error: byte index must be a multiple of 8 at operand 1 -- `movt zt0\[4\],x0'
+[^ :]+:[0-9]+: Error: byte index must be a multiple of 8 at operand 1 -- `movt zt0\[7\],x0'
+[^ :]+:[0-9]+: Error: byte index must be a multiple of 8 at operand 1 -- `movt zt0\[49\],x0'
+[^ :]+:[0-9]+: Error: byte index must be a multiple of 8 at operand 1 -- `movt zt0\[50\],x0'
+[^ :]+:[0-9]+: Error: byte index must be a multiple of 8 at operand 1 -- `movt zt0\[52\],x0'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 56 at operand 1 -- `movt zt0\[57\],x0'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 56 at operand 1 -- `movt zt0\[64\],x0'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 56 at operand 1 -- `movt zt0\[1<<32\],x0'
+[^ :]+:[0-9]+: Error: missing register index at operand 1 -- `movt zt0\.b\[0\],x0'
+[^ :]+:[0-9]+: Error: missing register index at operand 1 -- `movt zt0/z\[0\],x0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `movt zt0\[0\],sp'
+[^ :]+:[0-9]+: Error: operand mismatch -- `movt zt0\[0\],w0'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: movt zt0\[0\], x0
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `movt zt0\[0\],wsp'
+[^ :]+:[0-9]+: Error: operand mismatch -- `movt zt0\[0\],wzr'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: movt zt0\[0\], xzr
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `movt zt0\[0\],0'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `ldr 0,\[x0\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 2 -- `ldr zt0,0'
+[^ :]+:[0-9]+: Error: operand 2 must be an address with base register \(no offset\) -- `ldr zt0,\[x0,#0\]'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `ldr Zt0,\[x0\]'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `ldr zT0,\[x0\]'
+[^ :]+:[0-9]+: Error: '\]' expected at operand 2 -- `ldr zt0,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 2 -- `ldr zt0,\[w0\]'
+[^ :]+:[0-9]+: Error: missing offset in the pre-indexed address at operand 2 -- `ldr zt0,\[x0\]!'
+[^ :]+:[0-9]+: Error: invalid base register at operand 2 -- `ldr zt0,\[xzr\]'
+[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 2 -- `ldr zt0,\[wsp\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 2 -- `ldr zt0,\[x0,xzr\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 2 -- `ldr zt0,\[x1,x2\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 15 at operand 3 -- `luti2 z0\.b,zt0,z0\[-1\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 15 at operand 3 -- `luti2 z0\.b,zt0,z0\[16\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 z0\.b,zt0,z0\.b\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: luti2 z0\.b, zt0, z0\[0\]
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: luti2 z0\.h, zt0, z0\[0\]
+[^ :]+:[0-9]+: Info: luti2 z0\.s, zt0, z0\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 z0,zt0,z0\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: luti2 z0\.b, zt0, z0\[0\]
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: luti2 z0\.h, zt0, z0\[0\]
+[^ :]+:[0-9]+: Info: luti2 z0\.s, zt0, z0\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 z0\.d,zt0,z0\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: luti2 z0\.b, zt0, z0\[0\]
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: luti2 z0\.h, zt0, z0\[0\]
+[^ :]+:[0-9]+: Info: luti2 z0\.s, zt0, z0\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 z0\.q,zt0,z0\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: luti2 z0\.b, zt0, z0\[0\]
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: luti2 z0\.h, zt0, z0\[0\]
+[^ :]+:[0-9]+: Info: luti2 z0\.s, zt0, z0\[0\]
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `luti2 z0\.b,zt0,zt0'
+[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `luti2 0,zt0,z0\[0\]'
+[^ :]+:[0-9]+: Error: expected a register at operand 2 -- `luti2 z0\.b,0,z0\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `luti2 z0\.b,zt0,0'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `luti2 {z1\.b-z2\.b},zt0,z0\[0\]'
+[^ :]+:[0-9]+: Error: unexpected register type at operand 2 -- `luti2 {z0\.b-z1\.b},z0,z0\[0\]'
+[^ :]+:[0-9]+: Error: unexpected register type at operand 2 -- `luti2 {z0\.b-z1\.b},za,z0\[0\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 {z0\.h-z1\.h},zt0,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: luti2 {z0\.h-z1\.h}, zt0, z0\[0\]
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: luti2 {z0\.b-z1\.b}, zt0, z0\[0\]
+[^ :]+:[0-9]+: Info: luti2 {z0\.s-z1\.s}, zt0, z0\[0\]
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `luti2 {z0\.h-z1\.h},zt0,z0\[-1\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `luti2 {z0\.h-z1\.h},zt0,z0\[8\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 {z0\.d-z1\.d},zt0,z0\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: luti2 {z0\.b-z1\.b}, zt0, z0\[0\]
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: luti2 {z0\.h-z1\.h}, zt0, z0\[0\]
+[^ :]+:[0-9]+: Info: luti2 {z0\.s-z1\.s}, zt0, z0\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 {z0\.q-z1\.q},zt0,z0\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: luti2 {z0\.b-z1\.b}, zt0, z0\[0\]
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: luti2 {z0\.h-z1\.h}, zt0, z0\[0\]
+[^ :]+:[0-9]+: Info: luti2 {z0\.s-z1\.s}, zt0, z0\[0\]
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `luti2 {z1\.s-z4\.s},zt0,z0\[0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `luti2 {z2\.s-z5\.s},zt0,z0\[0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `luti2 {z3\.s-z6\.s},zt0,z0\[0\]'
+[^ :]+:[0-9]+: Error: unexpected register type at operand 2 -- `luti2 {z0\.s-z3\.s},z0,z0\[0\]'
+[^ :]+:[0-9]+: Error: unexpected register type at operand 2 -- `luti2 {z0\.b-z3\.b},za,z0\[0\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 {z0\.b-z3\.b},zt0,z0\.b\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: luti2 {z0\.b-z3\.b}, zt0, z0\[0\]
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: luti2 {z0\.h-z3\.h}, zt0, z0\[0\]
+[^ :]+:[0-9]+: Info: luti2 {z0\.s-z3\.s}, zt0, z0\[0\]
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `luti2 {z0\.b-z3\.b},zt0,z0\[-1\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `luti2 {z0\.b-z3\.b},zt0,z0\[4\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 {z0\.d-z3\.d},zt0,z0\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: luti2 {z0\.b-z3\.b}, zt0, z0\[0\]
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: luti2 {z0\.h-z3\.h}, zt0, z0\[0\]
+[^ :]+:[0-9]+: Info: luti2 {z0\.s-z3\.s}, zt0, z0\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 {z0\.q-z3\.q},zt0,z0\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: luti2 {z0\.b-z3\.b}, zt0, z0\[0\]
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: luti2 {z0\.h-z3\.h}, zt0, z0\[0\]
+[^ :]+:[0-9]+: Info: luti2 {z0\.s-z3\.s}, zt0, z0\[0\]
+[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `luti4 0,zt0,z0\[0\]'
+[^ :]+:[0-9]+: Error: expected a register at operand 2 -- `luti4 z0\.b,0,z0\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `luti4 z0\.b,zt0,0'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `luti4 z0\.h,zt0,z0\[-1\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `luti4 z0\.h,zt0,z0\[8\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 z0\.h,zt0,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: luti4 z0\.h, zt0, z0\[0\]
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: luti4 z0\.b, zt0, z0\[0\]
+[^ :]+:[0-9]+: Info: luti4 z0\.s, zt0, z0\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 z0,zt0,z0\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: luti4 z0\.b, zt0, z0\[0\]
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: luti4 z0\.h, zt0, z0\[0\]
+[^ :]+:[0-9]+: Info: luti4 z0\.s, zt0, z0\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 z0\.d,zt0,z0\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: luti4 z0\.b, zt0, z0\[0\]
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: luti4 z0\.h, zt0, z0\[0\]
+[^ :]+:[0-9]+: Info: luti4 z0\.s, zt0, z0\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 z0\.q,zt0,z0\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: luti4 z0\.b, zt0, z0\[0\]
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: luti4 z0\.h, zt0, z0\[0\]
+[^ :]+:[0-9]+: Info: luti4 z0\.s, zt0, z0\[0\]
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `luti4 z0\.h,zt0,zt0'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `luti4 {z1\.h-z2\.h},zt0,z0\[0\]'
+[^ :]+:[0-9]+: Error: unexpected register type at operand 2 -- `luti4 {z0\.h-z1\.h},z0,z0\[0\]'
+[^ :]+:[0-9]+: Error: unexpected register type at operand 2 -- `luti4 {z0\.h-z1\.h},za,z0\[0\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 {z0\.h-z1\.h},zt0,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: luti4 {z0\.h-z1\.h}, zt0, z0\[0\]
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: luti4 {z0\.b-z1\.b}, zt0, z0\[0\]
+[^ :]+:[0-9]+: Info: luti4 {z0\.s-z1\.s}, zt0, z0\[0\]
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `luti4 {z0\.h-z1\.h},zt0,z0\[-1\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `luti4 {z0\.h-z1\.h},zt0,z0\[4\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 {z0\.d-z1\.d},zt0,z0\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: luti4 {z0\.b-z1\.b}, zt0, z0\[0\]
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: luti4 {z0\.h-z1\.h}, zt0, z0\[0\]
+[^ :]+:[0-9]+: Info: luti4 {z0\.s-z1\.s}, zt0, z0\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 {z0\.q-z1\.q},zt0,z0\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: luti4 {z0\.b-z1\.b}, zt0, z0\[0\]
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: luti4 {z0\.h-z1\.h}, zt0, z0\[0\]
+[^ :]+:[0-9]+: Info: luti4 {z0\.s-z1\.s}, zt0, z0\[0\]
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `luti4 {z1\.s-z4\.s},zt0,z0\[0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `luti4 {z2\.s-z5\.s},zt0,z0\[0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `luti4 {z3\.s-z6\.s},zt0,z0\[0\]'
+[^ :]+:[0-9]+: Error: unexpected register type at operand 2 -- `luti4 {z0\.s-z3\.s},z0,z0\[0\]'
+[^ :]+:[0-9]+: Error: unexpected register type at operand 2 -- `luti4 {z0\.s-z3\.s},za,z0\[0\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 {z0\.s-z3\.s},zt0,z0\.s\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: luti4 {z0\.s-z3\.s}, zt0, z0\[0\]
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: luti4 {z0\.b-z3\.b}, zt0, z0\[0\]
+[^ :]+:[0-9]+: Info: luti4 {z0\.h-z3\.h}, zt0, z0\[0\]
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `luti4 {z0\.s-z3\.s},zt0,z0\[-1\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `luti4 {z0\.s-z3\.s},zt0,z0\[2\]'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `luti4 {z0\.b-z3\.b},zt0,z0\[0\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 {z0\.d-z3\.d},zt0,z0\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: luti4 {z0\.b-z3\.b}, zt0, z0\[0\]
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: luti4 {z0\.h-z3\.h}, zt0, z0\[0\]
+[^ :]+:[0-9]+: Info: luti4 {z0\.s-z3\.s}, zt0, z0\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 {z0\.q-z3\.q},zt0,z0\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: luti4 {z0\.b-z3\.b}, zt0, z0\[0\]
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: luti4 {z0\.h-z3\.h}, zt0, z0\[0\]
+[^ :]+:[0-9]+: Info: luti4 {z0\.s-z3\.s}, zt0, z0\[0\]
diff --git a/gas/testsuite/gas/aarch64/sme2-8-invalid.s b/gas/testsuite/gas/aarch64/sme2-8-invalid.s
new file mode 100644
index 00000000000..a9712c7aa13
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-8-invalid.s
@@ -0,0 +1,116 @@
+ zero 0
+
+ zero zt0
+ zero {
+ zero { foo }
+ zero { zt }
+ zero { x0 }
+ zero { z0 }
+ zero { zt0
+ zero { zt0.b }
+ zero { zt0, zt0 }
+
+ movt 0, zt0[0]
+ movt x0, 0
+
+ movt zt0, x0
+ movt za[0], x0
+ movt za0[0], x0
+ movt zt0[#0], x0
+ movt zt0[-1], x0
+ movt zt0[1],x0
+ movt zt0[2],x0
+ movt zt0[4],x0
+ movt zt0[7],x0
+ movt zt0[49],x0
+ movt zt0[50],x0
+ movt zt0[52],x0
+ movt zt0[57],x0
+ movt zt0[64], x0
+ movt zt0[1<<32], x0
+ movt zt0.b[0], x0
+ movt zt0/z[0], x0
+ movt zt0[0], sp
+ movt zt0[0], w0
+ movt zt0[0], wsp
+ movt zt0[0], wzr
+ movt zt0[0], 0
+
+ ldr 0, [x0]
+ ldr zt0, 0
+
+ ldr zt0, [x0, #0]
+ ldr Zt0, [x0]
+ ldr zT0, [x0]
+ ldr zt0, [x0, #0, mul vl]
+ ldr zt0, [w0]
+ ldr zt0, [x0]!
+ ldr zt0, [xzr]
+ ldr zt0, [wsp]
+ ldr zt0, [x0, xzr]
+ ldr zt0, [x1, x2]
+
+ luti2 z0.b, zt0, z0[-1]
+ luti2 z0.b, zt0, z0[16]
+ luti2 z0.b, zt0, z0.b[0]
+ luti2 z0, zt0, z0[0]
+ luti2 z0.d, zt0, z0[0]
+ luti2 z0.q, zt0, z0[0]
+ luti2 z0.b, zt0, zt0
+
+ luti2 0, zt0, z0[0]
+ luti2 z0.b, 0, z0[0]
+ luti2 z0.b, zt0, 0
+
+ luti2 { z1.b - z2.b }, zt0, z0[0]
+ luti2 { z0.b - z1.b }, z0, z0[0]
+ luti2 { z0.b - z1.b }, za, z0[0]
+ luti2 { z0.h - z1.h }, zt0, z0.h[0]
+ luti2 { z0.h - z1.h }, zt0, z0[-1]
+ luti2 { z0.h - z1.h }, zt0, z0[8]
+ luti2 { z0.d - z1.d }, zt0, z0[0]
+ luti2 { z0.q - z1.q }, zt0, z0[0]
+
+ luti2 { z1.s - z4.s }, zt0, z0[0]
+ luti2 { z2.s - z5.s }, zt0, z0[0]
+ luti2 { z3.s - z6.s }, zt0, z0[0]
+ luti2 { z0.s - z3.s }, z0, z0[0]
+ luti2 { z0.b - z3.b }, za, z0[0]
+ luti2 { z0.b - z3.b }, zt0, z0.b[0]
+ luti2 { z0.b - z3.b }, zt0, z0[-1]
+ luti2 { z0.b - z3.b }, zt0, z0[4]
+ luti2 { z0.d - z3.d }, zt0, z0[0]
+ luti2 { z0.q - z3.q }, zt0, z0[0]
+
+ luti4 0, zt0, z0[0]
+ luti4 z0.b, 0, z0[0]
+ luti4 z0.b, zt0, 0
+
+ luti4 z0.h, zt0, z0[-1]
+ luti4 z0.h, zt0, z0[8]
+ luti4 z0.h, zt0, z0.h[0]
+ luti4 z0, zt0, z0[0]
+ luti4 z0.d, zt0, z0[0]
+ luti4 z0.q, zt0, z0[0]
+ luti4 z0.h, zt0, zt0
+
+ luti4 { z1.h - z2.h }, zt0, z0[0]
+ luti4 { z0.h - z1.h }, z0, z0[0]
+ luti4 { z0.h - z1.h }, za, z0[0]
+ luti4 { z0.h - z1.h }, zt0, z0.h[0]
+ luti4 { z0.h - z1.h }, zt0, z0[-1]
+ luti4 { z0.h - z1.h }, zt0, z0[4]
+ luti4 { z0.d - z1.d }, zt0, z0[0]
+ luti4 { z0.q - z1.q }, zt0, z0[0]
+
+ luti4 { z1.s - z4.s }, zt0, z0[0]
+ luti4 { z2.s - z5.s }, zt0, z0[0]
+ luti4 { z3.s - z6.s }, zt0, z0[0]
+ luti4 { z0.s - z3.s }, z0, z0[0]
+ luti4 { z0.s - z3.s }, za, z0[0]
+ luti4 { z0.s - z3.s }, zt0, z0.s[0]
+ luti4 { z0.s - z3.s }, zt0, z0[-1]
+ luti4 { z0.s - z3.s }, zt0, z0[2]
+ luti4 { z0.b - z3.b }, zt0, z0[0]
+ luti4 { z0.d - z3.d }, zt0, z0[0]
+ luti4 { z0.q - z3.q }, zt0, z0[0]
diff --git a/gas/testsuite/gas/aarch64/sme2-8-noarch.d b/gas/testsuite/gas/aarch64/sme2-8-noarch.d
new file mode 100644
index 00000000000..116e9d67b66
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-8-noarch.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a+sme
+#source: sme2-8.s
+#error_output: sme2-8-noarch.l
diff --git a/gas/testsuite/gas/aarch64/sme2-8-noarch.l b/gas/testsuite/gas/aarch64/sme2-8-noarch.l
new file mode 100644
index 00000000000..994b359532d
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-8-noarch.l
@@ -0,0 +1,104 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: selected processor does not support `zero {zt0}'
+[^ :]+:[0-9]+: Error: selected processor does not support `zero {ZT0}'
+[^ :]+:[0-9]+: Error: selected processor does not support `movt x0,zt0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `movt X0,ZT0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `movt x30,zt0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `movt xzr,zt0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `movt x0,zt0\[56\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `movt x9,zt0\[24\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `movt x15,zt0\[40\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `movt x22,zt0\[48\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `movt zt0\[0\],x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `movt ZT0\[0\],X0'
+[^ :]+:[0-9]+: Error: selected processor does not support `movt zt0\[56\],x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `movt zt0\[0\],x30'
+[^ :]+:[0-9]+: Error: selected processor does not support `movt zt0\[0\],xzr'
+[^ :]+:[0-9]+: Error: selected processor does not support `movt zt0\[8\],x20'
+[^ :]+:[0-9]+: Error: selected processor does not support `movt zt0\[16\],x25'
+[^ :]+:[0-9]+: Error: selected processor does not support `movt zt0\[32\],x27'
+[^ :]+:[0-9]+: Error: selected processor does not support `movt zt0\[24\],x29'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldr zt0,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldr ZT0,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldr zt0,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldr zt0,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `str zt0,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `str ZT0,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `str zt0,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `str zt0,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z0\.b,zt0,z0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti2 Z0\.B,ZT0,Z0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z31\.b,zt0,z0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z0\.b,zt0,z31\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z0\.b,zt0,z0\[15\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z0\.h,zt0,z0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z31\.h,zt0,z0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z0\.h,zt0,z31\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z0\.h,zt0,z0\[15\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z0\.s,zt0,z0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z31\.s,zt0,z0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z0\.s,zt0,z31\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z0\.s,zt0,z0\[15\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.b-z1\.b},zt0,z0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {Z0\.B-Z1\.B},ZT0,Z0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z30\.b-z31\.b},zt0,z0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.b-z1\.b},zt0,z31\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.b-z1\.b},zt0,z0\[7\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.h-z1\.h},zt0,z0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z30\.h-z31\.h},zt0,z0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.h-z1\.h},zt0,z31\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.h-z1\.h},zt0,z0\[7\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.s-z1\.s},zt0,z0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z30\.s-z31\.s},zt0,z0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.s-z1\.s},zt0,z31\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.s-z1\.s},zt0,z0\[7\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.b-z3\.b},zt0,z0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {Z0\.B-Z3\.B},ZT0,Z0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z28\.b-z31\.b},zt0,z0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.b-z3\.b},zt0,z31\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.b-z3\.b},zt0,z0\[3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.h-z3\.h},zt0,z0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z28\.h-z31\.h},zt0,z0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.h-z3\.h},zt0,z31\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.h-z3\.h},zt0,z0\[3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.s-z3\.s},zt0,z0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z28\.s-z31\.s},zt0,z0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.s-z3\.s},zt0,z31\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.s-z3\.s},zt0,z0\[3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z0\.b,zt0,z0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti4 Z0\.b,ZT0,Z0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z31\.b,zt0,z0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z0\.b,zt0,z31\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z0\.b,zt0,z0\[7\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z0\.h,zt0,z0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti4 Z0\.H,ZT0,Z0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z31\.h,zt0,z0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z0\.h,zt0,z31\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z0\.h,zt0,z0\[7\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z0\.s,zt0,z0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z31\.s,zt0,z0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z0\.s,zt0,z31\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z0\.s,zt0,z0\[7\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.b-z1\.b},zt0,z0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {Z0\.b-Z1\.b},ZT0,Z0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z30\.b-z31\.b},zt0,z0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.b-z1\.b},zt0,z31\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.b-z1\.b},zt0,z0\[3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.h-z1\.h},zt0,z0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {Z0\.H-Z1\.H},ZT0,Z0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z30\.h-z31\.h},zt0,z0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.h-z1\.h},zt0,z31\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.h-z1\.h},zt0,z0\[3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.s-z1\.s},zt0,z0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z30\.s-z31\.s},zt0,z0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.s-z1\.s},zt0,z31\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.s-z1\.s},zt0,z0\[3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.h-z3\.h},zt0,z0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {Z0\.H-Z3\.H},ZT0,Z0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z28\.h-z31\.h},zt0,z0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.h-z3\.h},zt0,z31\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.h-z3\.h},zt0,z0\[1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.s-z3\.s},zt0,z0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z28\.s-z31\.s},zt0,z0\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.s-z3\.s},zt0,z31\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.s-z3\.s},zt0,z0\[1\]'
diff --git a/gas/testsuite/gas/aarch64/sme2-8.d b/gas/testsuite/gas/aarch64/sme2-8.d
new file mode 100644
index 00000000000..a129dff4d70
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-8.d
@@ -0,0 +1,112 @@
+#as: -march=armv8-a+sme2
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+[^:]+: c0480001 zero {zt0}
+[^:]+: c0480001 zero {zt0}
+[^:]+: c04c03e0 movt x0, zt0\[0\]
+[^:]+: c04c03e0 movt x0, zt0\[0\]
+[^:]+: c04c03fe movt x30, zt0\[0\]
+[^:]+: c04c03ff movt xzr, zt0\[0\]
+[^:]+: c04c73e0 movt x0, zt0\[56\]
+[^:]+: c04c33e9 movt x9, zt0\[24\]
+[^:]+: c04c53ef movt x15, zt0\[40\]
+[^:]+: c04c63f6 movt x22, zt0\[48\]
+[^:]+: c04e03e0 movt zt0\[0\], x0
+[^:]+: c04e03e0 movt zt0\[0\], x0
+[^:]+: c04e73e0 movt zt0\[56\], x0
+[^:]+: c04e03fe movt zt0\[0\], x30
+[^:]+: c04e03ff movt zt0\[0\], xzr
+[^:]+: c04e13f4 movt zt0\[8\], x20
+[^:]+: c04e23f9 movt zt0\[16\], x25
+[^:]+: c04e43fb movt zt0\[32\], x27
+[^:]+: c04e33fd movt zt0\[24\], x29
+[^:]+: e11f8000 ldr zt0, \[x0\]
+[^:]+: e11f8000 ldr zt0, \[x0\]
+[^:]+: e11f83c0 ldr zt0, \[x30\]
+[^:]+: e11f83e0 ldr zt0, \[sp\]
+[^:]+: e13f8000 str zt0, \[x0\]
+[^:]+: e13f8000 str zt0, \[x0\]
+[^:]+: e13f83c0 str zt0, \[x30\]
+[^:]+: e13f83e0 str zt0, \[sp\]
+[^:]+: c0cc0000 luti2 z0\.b, zt0, z0\[0\]
+[^:]+: c0cc0000 luti2 z0\.b, zt0, z0\[0\]
+[^:]+: c0cc001f luti2 z31\.b, zt0, z0\[0\]
+[^:]+: c0cc03e0 luti2 z0\.b, zt0, z31\[0\]
+[^:]+: c0cfc000 luti2 z0\.b, zt0, z0\[15\]
+[^:]+: c0cc1000 luti2 z0\.h, zt0, z0\[0\]
+[^:]+: c0cc101f luti2 z31\.h, zt0, z0\[0\]
+[^:]+: c0cc13e0 luti2 z0\.h, zt0, z31\[0\]
+[^:]+: c0cfd000 luti2 z0\.h, zt0, z0\[15\]
+[^:]+: c0cc2000 luti2 z0\.s, zt0, z0\[0\]
+[^:]+: c0cc201f luti2 z31\.s, zt0, z0\[0\]
+[^:]+: c0cc23e0 luti2 z0\.s, zt0, z31\[0\]
+[^:]+: c0cfe000 luti2 z0\.s, zt0, z0\[15\]
+[^:]+: c08c4000 luti2 {z0\.b-z1\.b}, zt0, z0\[0\]
+[^:]+: c08c4000 luti2 {z0\.b-z1\.b}, zt0, z0\[0\]
+[^:]+: c08c401e luti2 {z30\.b-z31\.b}, zt0, z0\[0\]
+[^:]+: c08c43e0 luti2 {z0\.b-z1\.b}, zt0, z31\[0\]
+[^:]+: c08fc000 luti2 {z0\.b-z1\.b}, zt0, z0\[7\]
+[^:]+: c08c5000 luti2 {z0\.h-z1\.h}, zt0, z0\[0\]
+[^:]+: c08c501e luti2 {z30\.h-z31\.h}, zt0, z0\[0\]
+[^:]+: c08c53e0 luti2 {z0\.h-z1\.h}, zt0, z31\[0\]
+[^:]+: c08fd000 luti2 {z0\.h-z1\.h}, zt0, z0\[7\]
+[^:]+: c08c6000 luti2 {z0\.s-z1\.s}, zt0, z0\[0\]
+[^:]+: c08c601e luti2 {z30\.s-z31\.s}, zt0, z0\[0\]
+[^:]+: c08c63e0 luti2 {z0\.s-z1\.s}, zt0, z31\[0\]
+[^:]+: c08fe000 luti2 {z0\.s-z1\.s}, zt0, z0\[7\]
+[^:]+: c08c8000 luti2 {z0\.b-z3\.b}, zt0, z0\[0\]
+[^:]+: c08c8000 luti2 {z0\.b-z3\.b}, zt0, z0\[0\]
+[^:]+: c08c801c luti2 {z28\.b-z31\.b}, zt0, z0\[0\]
+[^:]+: c08c83e0 luti2 {z0\.b-z3\.b}, zt0, z31\[0\]
+[^:]+: c08f8000 luti2 {z0\.b-z3\.b}, zt0, z0\[3\]
+[^:]+: c08c9000 luti2 {z0\.h-z3\.h}, zt0, z0\[0\]
+[^:]+: c08c901c luti2 {z28\.h-z31\.h}, zt0, z0\[0\]
+[^:]+: c08c93e0 luti2 {z0\.h-z3\.h}, zt0, z31\[0\]
+[^:]+: c08f9000 luti2 {z0\.h-z3\.h}, zt0, z0\[3\]
+[^:]+: c08ca000 luti2 {z0\.s-z3\.s}, zt0, z0\[0\]
+[^:]+: c08ca01c luti2 {z28\.s-z31\.s}, zt0, z0\[0\]
+[^:]+: c08ca3e0 luti2 {z0\.s-z3\.s}, zt0, z31\[0\]
+[^:]+: c08fa000 luti2 {z0\.s-z3\.s}, zt0, z0\[3\]
+[^:]+: c0ca0000 luti4 z0\.b, zt0, z0\[0\]
+[^:]+: c0ca0000 luti4 z0\.b, zt0, z0\[0\]
+[^:]+: c0ca001f luti4 z31\.b, zt0, z0\[0\]
+[^:]+: c0ca03e0 luti4 z0\.b, zt0, z31\[0\]
+[^:]+: c0cbc000 luti4 z0\.b, zt0, z0\[7\]
+[^:]+: c0ca1000 luti4 z0\.h, zt0, z0\[0\]
+[^:]+: c0ca1000 luti4 z0\.h, zt0, z0\[0\]
+[^:]+: c0ca101f luti4 z31\.h, zt0, z0\[0\]
+[^:]+: c0ca13e0 luti4 z0\.h, zt0, z31\[0\]
+[^:]+: c0cbd000 luti4 z0\.h, zt0, z0\[7\]
+[^:]+: c0ca2000 luti4 z0\.s, zt0, z0\[0\]
+[^:]+: c0ca201f luti4 z31\.s, zt0, z0\[0\]
+[^:]+: c0ca23e0 luti4 z0\.s, zt0, z31\[0\]
+[^:]+: c0cbe000 luti4 z0\.s, zt0, z0\[7\]
+[^:]+: c08a4000 luti4 {z0\.b-z1\.b}, zt0, z0\[0\]
+[^:]+: c08a4000 luti4 {z0\.b-z1\.b}, zt0, z0\[0\]
+[^:]+: c08a401e luti4 {z30\.b-z31\.b}, zt0, z0\[0\]
+[^:]+: c08a43e0 luti4 {z0\.b-z1\.b}, zt0, z31\[0\]
+[^:]+: c08bc000 luti4 {z0\.b-z1\.b}, zt0, z0\[3\]
+[^:]+: c08a5000 luti4 {z0\.h-z1\.h}, zt0, z0\[0\]
+[^:]+: c08a5000 luti4 {z0\.h-z1\.h}, zt0, z0\[0\]
+[^:]+: c08a501e luti4 {z30\.h-z31\.h}, zt0, z0\[0\]
+[^:]+: c08a53e0 luti4 {z0\.h-z1\.h}, zt0, z31\[0\]
+[^:]+: c08bd000 luti4 {z0\.h-z1\.h}, zt0, z0\[3\]
+[^:]+: c08a6000 luti4 {z0\.s-z1\.s}, zt0, z0\[0\]
+[^:]+: c08a601e luti4 {z30\.s-z31\.s}, zt0, z0\[0\]
+[^:]+: c08a63e0 luti4 {z0\.s-z1\.s}, zt0, z31\[0\]
+[^:]+: c08be000 luti4 {z0\.s-z1\.s}, zt0, z0\[3\]
+[^:]+: c08a9000 luti4 {z0\.h-z3\.h}, zt0, z0\[0\]
+[^:]+: c08a9000 luti4 {z0\.h-z3\.h}, zt0, z0\[0\]
+[^:]+: c08a901c luti4 {z28\.h-z31\.h}, zt0, z0\[0\]
+[^:]+: c08a93e0 luti4 {z0\.h-z3\.h}, zt0, z31\[0\]
+[^:]+: c08b9000 luti4 {z0\.h-z3\.h}, zt0, z0\[1\]
+[^:]+: c08aa000 luti4 {z0\.s-z3\.s}, zt0, z0\[0\]
+[^:]+: c08aa01c luti4 {z28\.s-z31\.s}, zt0, z0\[0\]
+[^:]+: c08aa3e0 luti4 {z0\.s-z3\.s}, zt0, z31\[0\]
+[^:]+: c08ba000 luti4 {z0\.s-z3\.s}, zt0, z0\[1\]
diff --git a/gas/testsuite/gas/aarch64/sme2-8.s b/gas/testsuite/gas/aarch64/sme2-8.s
new file mode 100644
index 00000000000..2bd5449c214
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-8.s
@@ -0,0 +1,124 @@
+ zero { zt0 }
+ ZERO { ZT0 }
+
+ movt x0, zt0[0]
+ MOVT X0, ZT0[0]
+ movt x30, zt0[0]
+ movt xzr, zt0[0]
+ movt x0, zt0[56]
+ movt x9, zt0[24]
+ movt x15, zt0[40]
+ movt x22, zt0[48]
+
+ movt zt0[0], x0
+ MOVT ZT0[0], X0
+ movt zt0[56], x0
+ movt zt0[0], x30
+ movt zt0[0], xzr
+ movt zt0[8], x20
+ movt zt0[16], x25
+ movt zt0[32], x27
+ movt zt0[24], x29
+
+ ldr zt0, [x0]
+ LDR ZT0, [X0]
+ ldr zt0, [x30]
+ ldr zt0, [sp]
+
+ str zt0, [x0]
+ STR ZT0, [X0]
+ str zt0, [x30]
+ str zt0, [sp]
+
+ luti2 z0.b, zt0, z0[0]
+ LUTI2 Z0.B, ZT0, Z0[0]
+ luti2 z31.b, zt0, z0[0]
+ luti2 z0.b, zt0, z31[0]
+ luti2 z0.b, zt0, z0[15]
+
+ luti2 z0.h, zt0, z0[0]
+ luti2 z31.h, zt0, z0[0]
+ luti2 z0.h, zt0, z31[0]
+ luti2 z0.h, zt0, z0[15]
+
+ luti2 z0.s, zt0, z0[0]
+ luti2 z31.s, zt0, z0[0]
+ luti2 z0.s, zt0, z31[0]
+ luti2 z0.s, zt0, z0[15]
+
+ luti2 { z0.b - z1.b }, zt0, z0[0]
+ LUTI2 { Z0.B - Z1.B }, ZT0, Z0[0]
+ luti2 { z30.b - z31.b }, zt0, z0[0]
+ luti2 { z0.b - z1.b }, zt0, z31[0]
+ luti2 { z0.b - z1.b }, zt0, z0[7]
+
+ luti2 { z0.h - z1.h }, zt0, z0[0]
+ luti2 { z30.h - z31.h }, zt0, z0[0]
+ luti2 { z0.h - z1.h }, zt0, z31[0]
+ luti2 { z0.h - z1.h }, zt0, z0[7]
+
+ luti2 { z0.s - z1.s }, zt0, z0[0]
+ luti2 { z30.s - z31.s }, zt0, z0[0]
+ luti2 { z0.s - z1.s }, zt0, z31[0]
+ luti2 { z0.s - z1.s }, zt0, z0[7]
+
+ luti2 { z0.b - z3.b }, zt0, z0[0]
+ LUTI2 { Z0.B - Z3.B }, ZT0, Z0[0]
+ luti2 { z28.b - z31.b }, zt0, z0[0]
+ luti2 { z0.b - z3.b }, zt0, z31[0]
+ luti2 { z0.b - z3.b }, zt0, z0[3]
+
+ luti2 { z0.h - z3.h }, zt0, z0[0]
+ luti2 { z28.h - z31.h }, zt0, z0[0]
+ luti2 { z0.h - z3.h }, zt0, z31[0]
+ luti2 { z0.h - z3.h }, zt0, z0[3]
+
+ luti2 { z0.s - z3.s }, zt0, z0[0]
+ luti2 { z28.s - z31.s }, zt0, z0[0]
+ luti2 { z0.s - z3.s }, zt0, z31[0]
+ luti2 { z0.s - z3.s }, zt0, z0[3]
+
+ luti4 z0.b, zt0, z0[0]
+ LUTI4 Z0.b, ZT0, Z0[0]
+ luti4 z31.b, zt0, z0[0]
+ luti4 z0.b, zt0, z31[0]
+ luti4 z0.b, zt0, z0[7]
+
+ luti4 z0.h, zt0, z0[0]
+ LUTI4 Z0.H, ZT0, Z0[0]
+ luti4 z31.h, zt0, z0[0]
+ luti4 z0.h, zt0, z31[0]
+ luti4 z0.h, zt0, z0[7]
+
+ luti4 z0.s, zt0, z0[0]
+ luti4 z31.s, zt0, z0[0]
+ luti4 z0.s, zt0, z31[0]
+ luti4 z0.s, zt0, z0[7]
+
+ luti4 { z0.b - z1.b }, zt0, z0[0]
+ LUTI4 { Z0.b - Z1.b }, ZT0, Z0[0]
+ luti4 { z30.b - z31.b }, zt0, z0[0]
+ luti4 { z0.b - z1.b }, zt0, z31[0]
+ luti4 { z0.b - z1.b }, zt0, z0[3]
+
+ luti4 { z0.h - z1.h }, zt0, z0[0]
+ LUTI4 { Z0.H - Z1.H }, ZT0, Z0[0]
+ luti4 { z30.h - z31.h }, zt0, z0[0]
+ luti4 { z0.h - z1.h }, zt0, z31[0]
+ luti4 { z0.h - z1.h }, zt0, z0[3]
+
+ luti4 { z0.s - z1.s }, zt0, z0[0]
+ luti4 { z30.s - z31.s }, zt0, z0[0]
+ luti4 { z0.s - z1.s }, zt0, z31[0]
+ luti4 { z0.s - z1.s }, zt0, z0[3]
+
+ luti4 { z0.h - z3.h }, zt0, z0[0]
+ LUTI4 { Z0.H - Z3.H }, ZT0, Z0[0]
+ luti4 { z28.h - z31.h }, zt0, z0[0]
+ luti4 { z0.h - z3.h }, zt0, z31[0]
+ luti4 { z0.h - z3.h }, zt0, z0[1]
+
+ luti4 { z0.s - z3.s }, zt0, z0[0]
+ luti4 { z28.s - z31.s }, zt0, z0[0]
+ luti4 { z0.s - z3.s }, zt0, z31[0]
+ luti4 { z0.s - z3.s }, zt0, z0[1]
diff --git a/gas/testsuite/gas/aarch64/sve-invalid.l b/gas/testsuite/gas/aarch64/sve-invalid.l
index 00352f88f52..a02fbfe28ef 100644
--- a/gas/testsuite/gas/aarch64/sve-invalid.l
+++ b/gas/testsuite/gas/aarch64/sve-invalid.l
@@ -932,6 +932,14 @@
.*: Error: register element index out of range 0 to 63 at operand 2 -- `dup z0\.b,z1\.b\[-1\]'
.*: Error: register element index out of range 0 to 63 at operand 2 -- `dup z0\.b,z1\.b\[64\]'
.*: Error: constant expression required at operand 2 -- `dup z0\.b,z1\.b\[x0\]'
+.*: Error: operand mismatch -- `dup z0\.b,z1\[0\]'
+.*: Info: did you mean this\?
+.*: Info: dup z0\.b, z1\.b\[0\]
+.*: Info: other valid variant\(s\):
+.*: Info: dup z0\.h, z1\.h\[0\]
+.*: Info: dup z0\.s, z1\.s\[0\]
+.*: Info: dup z0\.d, z1\.d\[0\]
+.*: Info: dup z0\.q, z1\.q\[0\]
.*: Error: register element index out of range 0 to 31 at operand 2 -- `dup z0\.h,z1\.h\[-1\]'
.*: Error: register element index out of range 0 to 31 at operand 2 -- `dup z0\.h,z1\.h\[32\]'
.*: Error: constant expression required at operand 2 -- `dup z0\.h,z1\.h\[x0\]'
diff --git a/gas/testsuite/gas/aarch64/sve-invalid.s b/gas/testsuite/gas/aarch64/sve-invalid.s
index b56a08dc15c..c374396ebb3 100644
--- a/gas/testsuite/gas/aarch64/sve-invalid.s
+++ b/gas/testsuite/gas/aarch64/sve-invalid.s
@@ -1143,6 +1143,7 @@
dup z0.b, z1.b[63] // OK
dup z0.b, z1.b[64]
dup z0.b, z1.b[x0]
+ dup z0.b, z1[0]
dup z0.h, z1.h[-1]
dup z0.h, z1.h[0] // OK
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index ee0a3b65ab0..69e0f833170 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -515,8 +515,17 @@ enum aarch64_opnd
AARCH64_OPND_SME_ADDR_RI_U4xVL, /* SME [<Xn|SP>{, #<imm>, MUL VL}]. */
AARCH64_OPND_SME_SM_ZA, /* SME {SM | ZA}. */
AARCH64_OPND_SME_PnT_Wm_imm, /* SME <Pn>.<T>[<Wm>, #<imm>]. */
+ AARCH64_OPND_SME_Zn_INDEX1_16, /* Zn[index], bits [9:5] and [16:16]. */
+ AARCH64_OPND_SME_Zn_INDEX2_15, /* Zn[index], bits [9:5] and [16:15]. */
+ AARCH64_OPND_SME_Zn_INDEX2_16, /* Zn[index], bits [9:5] and [17:16]. */
+ AARCH64_OPND_SME_Zn_INDEX3_14, /* Zn[index], bits [9:5] and [16:14]. */
+ AARCH64_OPND_SME_Zn_INDEX3_15, /* Zn[index], bits [9:5] and [17:15]. */
+ AARCH64_OPND_SME_Zn_INDEX4_14, /* Zn[index], bits [9:5] and [17:14]. */
AARCH64_OPND_SME_VLxN_10, /* VLx2 or VLx4, in bit 10. */
AARCH64_OPND_SME_VLxN_13, /* VLx2 or VLx4, in bit 13. */
+ AARCH64_OPND_SME_ZT0, /* The fixed token zt0/ZT0 (not encoded). */
+ AARCH64_OPND_SME_ZT0_INDEX, /* ZT0[<imm>], bits [14:12]. */
+ AARCH64_OPND_SME_ZT0_LIST, /* { zt0/ZT0 } (not encoded). */
AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */
AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */
AARCH64_OPND_MOPS_ADDR_Rd, /* [Rd]!, in bits [0, 4]. */
@@ -690,6 +699,8 @@ enum aarch64_insn_class
sme_mov,
sme_ldr,
sme_psel,
+ sme_size_12_bhs,
+ sme_size_12_hs,
sme_size_22,
sme_str,
sme_start,
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index 9302253db59..cdc9e465d13 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -684,7 +684,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 33:
case 34:
case 35:
- case 247:
+ case 256:
return aarch64_ins_reglane (self, info, code, inst, errors);
case 36:
return aarch64_ins_reglist (self, info, code, inst, errors);
@@ -730,11 +730,12 @@ aarch64_insert_operand (const aarch64_operand *self,
case 193:
case 194:
case 236:
- case 244:
- case 245:
- case 246:
+ case 250:
case 251:
- case 252:
+ case 253:
+ case 255:
+ case 260:
+ case 261:
return aarch64_ins_imm (self, info, code, inst, errors);
case 44:
case 45:
@@ -803,6 +804,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 107:
return aarch64_ins_prfop (self, info, code, inst, errors);
case 108:
+ case 252:
+ case 254:
return aarch64_ins_none (self, info, code, inst, errors);
case 109:
return aarch64_ins_hint (self, info, code, inst, errors);
@@ -915,6 +918,12 @@ aarch64_insert_operand (const aarch64_operand *self,
return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors);
case 234:
case 235:
+ case 244:
+ case 245:
+ case 246:
+ case 247:
+ case 248:
+ case 249:
return aarch64_ins_simple_index (self, info, code, inst, errors);
case 238:
case 239:
@@ -926,9 +935,9 @@ aarch64_insert_operand (const aarch64_operand *self,
return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
case 243:
return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
- case 248:
- case 249:
- case 250:
+ case 257:
+ case 258:
+ case 259:
return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
default: assert (0); abort ();
}
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index acfec3773dc..bd03f4116cc 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -404,6 +404,8 @@ aarch64_ins_imm (const aarch64_operand *self, const aarch64_opnd_info *info,
imm = info->imm.value;
if (operand_need_shift_by_two (self))
imm >>= 2;
+ if (operand_need_shift_by_three (self))
+ imm >>= 3;
if (operand_need_shift_by_four (self))
imm >>= 4;
insert_all_fields (self, code, imm);
@@ -1946,11 +1948,21 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
/* The variant is encoded as part of the immediate. */
break;
+ case sme_size_12_bhs:
+ insert_field (FLD_SME_size_12, &inst->value,
+ aarch64_get_variant (inst), 0);
+ break;
+
case sme_size_22:
insert_field (FLD_SME_size_22, &inst->value,
aarch64_get_variant (inst), 0);
break;
+ case sme_size_12_hs:
+ insert_field (FLD_SME_size_12, &inst->value,
+ aarch64_get_variant (inst) + 1, 0);
+ break;
+
case sve_cpy:
insert_fields (&inst->value, aarch64_get_variant (inst),
0, 2, FLD_SVE_M_14, FLD_size);
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 5210db3b008..f69f30f8884 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -94,9 +94,9 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- if (((word >> 17) & 0x1) == 0)
+ if (((word >> 18) & 0x1) == 0)
{
- if (((word >> 18) & 0x1) == 0)
+ if (((word >> 17) & 0x1) == 0)
{
if (((word >> 19) & 0x1) == 0)
{
@@ -152,95 +152,194 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000000xx0x100xxxxxxxxxxxxxxxxx
- zero. */
- return 2392;
+ if (((word >> 22) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000x00x100xxxxxxxxxxxxxxxxx
+ zero. */
+ return 2392;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000x10x100xxxxxxxxxxxxxxxxx
+ zero. */
+ return 2596;
+ }
}
}
else
{
- if (((word >> 10) & 0x1) == 0)
+ if (((word >> 19) & 0x1) == 0)
{
- if (((word >> 11) & 0x1) == 0)
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000xx0x001xxxxxxxxxxxxxxxxx
+ mov. */
+ return 2388;
+ }
+ else
+ {
+ if (((word >> 22) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000000xx0xx10xxxxx00xxxxxxxxxx
- mov. */
- return 2499;
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000x00x101xx0xxxxxxxxxxxxxx
+ luti4. */
+ return 2499;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000x00x101xx1xxxxxxxxxxxxxx
+ luti4. */
+ return 2498;
+ }
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1000000xx0xx10xxxxx10xxxxxxxxxx
- mov. */
+ x1000000x10x101xxxxxxxxxxxxxxxxx
+ luti4. */
return 2497;
}
}
+ }
+ }
+ else
+ {
+ if (((word >> 10) & 0x1) == 0)
+ {
+ if (((word >> 11) & 0x1) == 0)
+ {
+ if (((word >> 19) & 0x1) == 0)
+ {
+ if (((word >> 17) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000xx0x010xxxxx00xxxxxxxxxx
+ mov. */
+ return 2506;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000xx0x011xxxxx00xxxxxxxxxx
+ mov. */
+ return 2502;
+ }
+ }
+ else
+ {
+ if (((word >> 22) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000x00x11xxx0xx00xxxxxxxxxx
+ luti2. */
+ return 2496;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000x00x11xxx1xx00xxxxxxxxxx
+ luti2. */
+ return 2495;
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 17) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000010x110xxxxx00xxxxxxxxxx
+ movt. */
+ return 2517;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000010x111xxxxx00xxxxxxxxxx
+ movt. */
+ return 2516;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000110x11xxxxxx00xxxxxxxxxx
+ luti2. */
+ return 2494;
+ }
+ }
+ }
+ }
else
{
- if (((word >> 11) & 0x1) == 0)
+ if (((word >> 17) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1000000xx0xx10xxxxx01xxxxxxxxxx
+ x1000000xx0xx10xxxxx10xxxxxxxxxx
mov. */
- return 2500;
+ return 2504;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1000000xx0xx10xxxxx11xxxxxxxxxx
+ x1000000xx0xx11xxxxx10xxxxxxxxxx
mov. */
- return 2498;
+ return 2500;
}
}
}
- }
- else
- {
- if (((word >> 18) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000000xx0xx01xxxxxxxxxxxxxxxxx
- mov. */
- return 2388;
- }
else
{
- if (((word >> 10) & 0x1) == 0)
+ if (((word >> 11) & 0x1) == 0)
{
- if (((word >> 11) & 0x1) == 0)
+ if (((word >> 17) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1000000xx0xx11xxxxx00xxxxxxxxxx
+ x1000000xx0xx10xxxxx01xxxxxxxxxx
mov. */
- return 2495;
+ return 2507;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1000000xx0xx11xxxxx10xxxxxxxxxx
+ x1000000xx0xx11xxxxx01xxxxxxxxxx
mov. */
- return 2493;
+ return 2503;
}
}
else
{
- if (((word >> 11) & 0x1) == 0)
+ if (((word >> 17) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1000000xx0xx11xxxxx01xxxxxxxxxx
+ x1000000xx0xx10xxxxx11xxxxxxxxxx
mov. */
- return 2496;
+ return 2505;
}
else
{
@@ -248,7 +347,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx0xx11xxxxx11xxxxxxxxxx
mov. */
- return 2494;
+ return 2501;
}
}
}
@@ -713,7 +812,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx000xxxxxxxxxxxx0
st1b. */
- return 2518;
+ return 2527;
}
else
{
@@ -721,7 +820,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx100xxxxxxxxxxxx0
st1b. */
- return 2519;
+ return 2528;
}
}
else
@@ -732,7 +831,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx010xxxxxxxxxxxx0
st1w. */
- return 2542;
+ return 2551;
}
else
{
@@ -740,7 +839,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx110xxxxxxxxxxxx0
st1w. */
- return 2543;
+ return 2552;
}
}
}
@@ -754,7 +853,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx001xxxxxxxxxxxx0
st1h. */
- return 2534;
+ return 2543;
}
else
{
@@ -762,7 +861,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx101xxxxxxxxxxxx0
st1h. */
- return 2535;
+ return 2544;
}
}
else
@@ -773,7 +872,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx011xxxxxxxxxxxx0
st1d. */
- return 2526;
+ return 2535;
}
else
{
@@ -781,7 +880,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx111xxxxxxxxxxxx0
st1d. */
- return 2527;
+ return 2536;
}
}
}
@@ -798,7 +897,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx000xxxxxxxxxxxx1
stnt1b. */
- return 2550;
+ return 2559;
}
else
{
@@ -806,7 +905,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx100xxxxxxxxxxxx1
stnt1b. */
- return 2551;
+ return 2560;
}
}
else
@@ -817,7 +916,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx010xxxxxxxxxxxx1
stnt1w. */
- return 2574;
+ return 2583;
}
else
{
@@ -825,7 +924,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx110xxxxxxxxxxxx1
stnt1w. */
- return 2575;
+ return 2584;
}
}
}
@@ -839,7 +938,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx001xxxxxxxxxxxx1
stnt1h. */
- return 2566;
+ return 2575;
}
else
{
@@ -847,7 +946,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx101xxxxxxxxxxxx1
stnt1h. */
- return 2567;
+ return 2576;
}
}
else
@@ -858,7 +957,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx011xxxxxxxxxxxx1
stnt1d. */
- return 2558;
+ return 2567;
}
else
{
@@ -866,7 +965,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx111xxxxxxxxxxxx1
stnt1d. */
- return 2559;
+ return 2568;
}
}
}
@@ -930,7 +1029,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx000xxxxxxxxxxxx0
st1b. */
- return 2514;
+ return 2523;
}
else
{
@@ -938,7 +1037,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx100xxxxxxxxxxxx0
st1b. */
- return 2515;
+ return 2524;
}
}
else
@@ -949,7 +1048,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx010xxxxxxxxxxxx0
st1w. */
- return 2538;
+ return 2547;
}
else
{
@@ -957,7 +1056,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx110xxxxxxxxxxxx0
st1w. */
- return 2539;
+ return 2548;
}
}
}
@@ -971,7 +1070,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx001xxxxxxxxxxxx0
st1h. */
- return 2530;
+ return 2539;
}
else
{
@@ -979,7 +1078,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx101xxxxxxxxxxxx0
st1h. */
- return 2531;
+ return 2540;
}
}
else
@@ -990,7 +1089,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx011xxxxxxxxxxxx0
st1d. */
- return 2522;
+ return 2531;
}
else
{
@@ -998,7 +1097,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx111xxxxxxxxxxxx0
st1d. */
- return 2523;
+ return 2532;
}
}
}
@@ -1015,7 +1114,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx000xxxxxxxxxxxx1
stnt1b. */
- return 2546;
+ return 2555;
}
else
{
@@ -1023,7 +1122,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx100xxxxxxxxxxxx1
stnt1b. */
- return 2547;
+ return 2556;
}
}
else
@@ -1034,7 +1133,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx010xxxxxxxxxxxx1
stnt1w. */
- return 2570;
+ return 2579;
}
else
{
@@ -1042,7 +1141,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx110xxxxxxxxxxxx1
stnt1w. */
- return 2571;
+ return 2580;
}
}
}
@@ -1056,7 +1155,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx001xxxxxxxxxxxx1
stnt1h. */
- return 2562;
+ return 2571;
}
else
{
@@ -1064,7 +1163,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx101xxxxxxxxxxxx1
stnt1h. */
- return 2563;
+ return 2572;
}
}
else
@@ -1075,7 +1174,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx011xxxxxxxxxxxx1
stnt1d. */
- return 2554;
+ return 2563;
}
else
{
@@ -1083,7 +1182,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx111xxxxxxxxxxxx1
stnt1d. */
- return 2555;
+ return 2564;
}
}
}
@@ -1265,11 +1364,22 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 14) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00001000xxxxx100xxxxxxxxx0xxx
- ld1b. */
- return 2436;
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00001000xxxxx100xxxxxxxxx0xxx
+ ld1b. */
+ return 2436;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1x00001000xxxxx100xxxxxxxxx0xxx
+ ldr. */
+ return 2493;
+ }
}
else
{
@@ -1623,7 +1733,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxx0xxxxxxxxxxxxxxxx
sel. */
- return 2512;
+ return 2521;
}
else
{
@@ -1631,7 +1741,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxx1xxxxxxxxxxxxxxxx
sel. */
- return 2513;
+ return 2522;
}
}
}
@@ -1655,7 +1765,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100001001xxxxx000xxxxxxxxx0xxx
st1b. */
- return 2520;
+ return 2529;
}
else
{
@@ -1663,7 +1773,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100001001xxxxx010xxxxxxxxx0xxx
st1w. */
- return 2544;
+ return 2553;
}
}
else
@@ -1674,7 +1784,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100001001xxxxx001xxxxxxxxx0xxx
st1h. */
- return 2536;
+ return 2545;
}
else
{
@@ -1682,7 +1792,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100001001xxxxx011xxxxxxxxx0xxx
st1d. */
- return 2528;
+ return 2537;
}
}
}
@@ -1696,7 +1806,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100001001xxxxx000xxxxxxxxx1xxx
stnt1b. */
- return 2552;
+ return 2561;
}
else
{
@@ -1704,7 +1814,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100001001xxxxx010xxxxxxxxx1xxx
stnt1w. */
- return 2576;
+ return 2585;
}
}
else
@@ -1715,7 +1825,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100001001xxxxx001xxxxxxxxx1xxx
stnt1h. */
- return 2568;
+ return 2577;
}
else
{
@@ -1723,7 +1833,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100001001xxxxx011xxxxxxxxx1xxx
stnt1d. */
- return 2560;
+ return 2569;
}
}
}
@@ -1745,11 +1855,22 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 14) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx100001001xxxxx100xxxxxxxxx0xxx
- st1b. */
- return 2521;
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100001001xxxxx100xxxxxxxxx0xxx
+ st1b. */
+ return 2530;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1100001001xxxxx100xxxxxxxxx0xxx
+ str. */
+ return 2587;
+ }
}
else
{
@@ -1757,7 +1878,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx100001001xxxxx110xxxxxxxxx0xxx
st1w. */
- return 2545;
+ return 2554;
}
}
else
@@ -1768,7 +1889,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx100001001xxxxx101xxxxxxxxx0xxx
st1h. */
- return 2537;
+ return 2546;
}
else
{
@@ -1776,7 +1897,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx100001001xxxxx111xxxxxxxxx0xxx
st1d. */
- return 2529;
+ return 2538;
}
}
}
@@ -1790,7 +1911,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx100001001xxxxx100xxxxxxxxx1xxx
stnt1b. */
- return 2553;
+ return 2562;
}
else
{
@@ -1798,7 +1919,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx100001001xxxxx110xxxxxxxxx1xxx
stnt1w. */
- return 2577;
+ return 2586;
}
}
else
@@ -1809,7 +1930,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx100001001xxxxx101xxxxxxxxx1xxx
stnt1h. */
- return 2569;
+ return 2578;
}
else
{
@@ -1817,7 +1938,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
[...]
[diff truncated at 100000 bytes]
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2023-03-30 10:15 [binutils-gdb] aarch64: Add the SME2 ZT0 instructions Richard Sandiford
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