* [binutils-gdb] aarch64: Add the SME2 vertical dot-product instructions
@ 2023-03-30 10:15 Richard Sandiford
0 siblings, 0 replies; only message in thread
From: Richard Sandiford @ 2023-03-30 10:15 UTC (permalink / raw)
To: bfd-cvs
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=a42de2296a069aa3037594585994b2d376b0baff
commit a42de2296a069aa3037594585994b2d376b0baff
Author: Richard Sandiford <richard.sandiford@arm.com>
Date: Thu Mar 30 11:09:14 2023 +0100
aarch64: Add the SME2 vertical dot-product instructions
There are three instruction formats here:
- BFVDOT + FVDOT
- SVDOT + UVDOT
- SUVDOT + USVDOT
There are also 64-bit forms of SVDOT and UVDOT.
Diff:
---
gas/testsuite/gas/aarch64/sme2-18-invalid.d | 3 +
gas/testsuite/gas/aarch64/sme2-18-invalid.l | 21 +
gas/testsuite/gas/aarch64/sme2-18-invalid.s | 20 +
gas/testsuite/gas/aarch64/sme2-18-noarch.d | 3 +
gas/testsuite/gas/aarch64/sme2-18-noarch.l | 21 +
gas/testsuite/gas/aarch64/sme2-18.d | 29 +
gas/testsuite/gas/aarch64/sme2-18.s | 21 +
gas/testsuite/gas/aarch64/sme2-19-invalid.d | 3 +
gas/testsuite/gas/aarch64/sme2-19-invalid.l | 36 +
gas/testsuite/gas/aarch64/sme2-19-invalid.s | 36 +
gas/testsuite/gas/aarch64/sme2-19-noarch.d | 3 +
gas/testsuite/gas/aarch64/sme2-19-noarch.l | 41 +
gas/testsuite/gas/aarch64/sme2-19.d | 49 +
gas/testsuite/gas/aarch64/sme2-19.s | 43 +
gas/testsuite/gas/aarch64/sme2-20-invalid.d | 3 +
gas/testsuite/gas/aarch64/sme2-20-invalid.l | 27 +
gas/testsuite/gas/aarch64/sme2-20-invalid.s | 23 +
gas/testsuite/gas/aarch64/sme2-20-noarch.d | 3 +
gas/testsuite/gas/aarch64/sme2-20-noarch.l | 21 +
gas/testsuite/gas/aarch64/sme2-20.d | 29 +
gas/testsuite/gas/aarch64/sme2-20.s | 21 +
gas/testsuite/gas/aarch64/sme2-i16i64-4-invalid.d | 3 +
gas/testsuite/gas/aarch64/sme2-i16i64-4-invalid.l | 11 +
gas/testsuite/gas/aarch64/sme2-i16i64-4-invalid.s | 12 +
gas/testsuite/gas/aarch64/sme2-i16i64-4-noarch.d | 3 +
gas/testsuite/gas/aarch64/sme2-i16i64-4-noarch.l | 21 +
gas/testsuite/gas/aarch64/sme2-i16i64-4.d | 29 +
gas/testsuite/gas/aarch64/sme2-i16i64-4.s | 21 +
opcodes/aarch64-dis-2.c | 1448 +++++++++++----------
opcodes/aarch64-tbl.h | 10 +
30 files changed, 1345 insertions(+), 669 deletions(-)
diff --git a/gas/testsuite/gas/aarch64/sme2-18-invalid.d b/gas/testsuite/gas/aarch64/sme2-18-invalid.d
new file mode 100644
index 00000000000..d049bda4368
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-18-invalid.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a
+#source: sme2-18-invalid.s
+#error_output: sme2-18-invalid.l
diff --git a/gas/testsuite/gas/aarch64/sme2-18-invalid.l b/gas/testsuite/gas/aarch64/sme2-18-invalid.l
new file mode 100644
index 00000000000..6a1b77a1494
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-18-invalid.l
@@ -0,0 +1,21 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: expected a ZA array vector at operand 1 -- `bfvdot 0,{z0\.h-z1\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected '{' at operand 2 -- `bfvdot za\.s\[w8,0\],0,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `bfvdot za\.s\[w8,0\],{z0\.h-z1\.h},0'
+[^ :]+:[0-9]+: Error: missing braces at operand 2 -- `fvdot za\.h\[w8,0\],z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `fvdot za\.h\[w8,0\],{z0\.h-z1\.h},z0\.h'
+[^ :]+:[0-9]+: Error: operand mismatch -- `fvdot za\.s\[w8,0\],{z0\.b-z1\.h},z0\.b\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: fvdot za\.s\[w8, 0\], {z0\.h-z1\.h}, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: expected a single offset rather than a range at operand 1 -- `fvdot za\.s\[w8,0:1\],{z0\.h-z1\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: operand 1 must have a vector group size of 2 -- `fvdot za\.s\[w8,0,vgx4\],{z0\.h-z1\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fvdot za\.s\[w7,0\],{z0\.h-z1\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fvdot za\.s\[w12,0\],{z0\.h-z1\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fvdot za\.s\[w8,-1\],{z0\.h-z1\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fvdot za\.s\[w8,8\],{z0\.h-z1\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `fvdot za\.s\[w8,0\],{z0\.h-z2\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `fvdot za\.s\[w8,0\],{z0\.h-z3\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fvdot za\.s\[w8,0\],{z1\.h-z2\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `fvdot za\.s\[w8,0\],{z0\.h-z1\.h},z0\.h\[-1\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `fvdot za\.s\[w8,0\],{z0\.h-z1\.h},z0\.h\[4\]'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fvdot za\.s\[w8,0\],{z0\.h-z1\.h},z16\.h\[0\]'
diff --git a/gas/testsuite/gas/aarch64/sme2-18-invalid.s b/gas/testsuite/gas/aarch64/sme2-18-invalid.s
new file mode 100644
index 00000000000..efe3235eed2
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-18-invalid.s
@@ -0,0 +1,20 @@
+ bfvdot 0, { z0.h - z1.h }, z0.h[0]
+ bfvdot za.s[w8, 0], 0, z0.h[0]
+ bfvdot za.s[w8, 0], { z0.h - z1.h }, 0
+
+ fvdot za.h[w8, 0], z0.h, z0.h
+ fvdot za.h[w8, 0], { z0.h - z1.h }, z0.h
+ fvdot za.s[w8, 0], { z0.b - z1.h }, z0.b[0]
+ fvdot za.s[w8, 0:1], { z0.h - z1.h }, z0.h[0]
+ fvdot za.s[w8, 0, vgx4], { z0.h - z1.h }, z0.h[0]
+
+ fvdot za.s[w7, 0], { z0.h - z1.h }, z0.h[0]
+ fvdot za.s[w12, 0], { z0.h - z1.h }, z0.h[0]
+ fvdot za.s[w8, -1], { z0.h - z1.h }, z0.h[0]
+ fvdot za.s[w8, 8], { z0.h - z1.h }, z0.h[0]
+ fvdot za.s[w8, 0], { z0.h - z2.h }, z0.h[0]
+ fvdot za.s[w8, 0], { z0.h - z3.h }, z0.h[0]
+ fvdot za.s[w8, 0], { z1.h - z2.h }, z0.h[0]
+ fvdot za.s[w8, 0], { z0.h - z1.h }, z0.h[-1]
+ fvdot za.s[w8, 0], { z0.h - z1.h }, z0.h[4]
+ fvdot za.s[w8, 0], { z0.h - z1.h }, z16.h[0]
diff --git a/gas/testsuite/gas/aarch64/sme2-18-noarch.d b/gas/testsuite/gas/aarch64/sme2-18-noarch.d
new file mode 100644
index 00000000000..1f9fbc9b58e
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-18-noarch.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a+sme
+#source: sme2-18.s
+#error_output: sme2-18-noarch.l
diff --git a/gas/testsuite/gas/aarch64/sme2-18-noarch.l b/gas/testsuite/gas/aarch64/sme2-18-noarch.l
new file mode 100644
index 00000000000..525e3950c9c
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-18-noarch.l
@@ -0,0 +1,21 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: selected processor does not support `bfvdot za\.s\[w8,0\],{z0\.h-z1\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfvdot za\.s\[w8,0,vgx2\],{z0\.h-z1\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfvdot ZA\.s\[W8,0,VGx2\],{Z0\.h-Z1\.h},Z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfvdot ZA\.S\[W8,0,VGX2\],{Z0\.H-Z1\.H},Z0\.H\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfvdot za\.s\[w11,0\],{z0\.h-z1\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfvdot za\.s\[w8,7\],{z0\.h-z1\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfvdot za\.s\[w8,0\],{z30\.h-z31\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfvdot za\.s\[w8,0\],{z0\.h-z1\.h},z15\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfvdot za\.s\[w8,0\],{z0\.h-z1\.h},z0\.h\[3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfvdot za\.s\[w10,2\],{z14\.h-z15\.h},z13\.h\[1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fvdot za\.s\[w8,0\],{z0\.h-z1\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fvdot za\.s\[w8,0,vgx2\],{z0\.h-z1\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fvdot ZA\.s\[W8,0,VGx2\],{Z0\.h-Z1\.h},Z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fvdot ZA\.S\[W8,0,VGX2\],{Z0\.H-Z1\.H},Z0\.H\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fvdot za\.s\[w11,0\],{z0\.h-z1\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fvdot za\.s\[w8,7\],{z0\.h-z1\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fvdot za\.s\[w8,0\],{z30\.h-z31\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fvdot za\.s\[w8,0\],{z0\.h-z1\.h},z15\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fvdot za\.s\[w8,0\],{z0\.h-z1\.h},z0\.h\[3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fvdot za\.s\[w10,2\],{z14\.h-z15\.h},z13\.h\[1\]'
diff --git a/gas/testsuite/gas/aarch64/sme2-18.d b/gas/testsuite/gas/aarch64/sme2-18.d
new file mode 100644
index 00000000000..017f275fa6d
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-18.d
@@ -0,0 +1,29 @@
+#as: -march=armv8-a+sme2
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+[^:]+: c1500018 bfvdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
+[^:]+: c1500018 bfvdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
+[^:]+: c1500018 bfvdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
+[^:]+: c1500018 bfvdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
+[^:]+: c1506018 bfvdot za\.s\[w11, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
+[^:]+: c150001f bfvdot za\.s\[w8, 7, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
+[^:]+: c15003d8 bfvdot za\.s\[w8, 0, vgx2\], {z30\.h-z31\.h}, z0\.h\[0\]
+[^:]+: c15f0018 bfvdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z15\.h\[0\]
+[^:]+: c1500c18 bfvdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[3\]
+[^:]+: c15d45da bfvdot za\.s\[w10, 2, vgx2\], {z14\.h-z15\.h}, z13\.h\[1\]
+[^:]+: c1500008 fvdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
+[^:]+: c1500008 fvdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
+[^:]+: c1500008 fvdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
+[^:]+: c1500008 fvdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
+[^:]+: c1506008 fvdot za\.s\[w11, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
+[^:]+: c150000f fvdot za\.s\[w8, 7, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
+[^:]+: c15003c8 fvdot za\.s\[w8, 0, vgx2\], {z30\.h-z31\.h}, z0\.h\[0\]
+[^:]+: c15f0008 fvdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z15\.h\[0\]
+[^:]+: c1500c08 fvdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[3\]
+[^:]+: c15d45ca fvdot za\.s\[w10, 2, vgx2\], {z14\.h-z15\.h}, z13\.h\[1\]
diff --git a/gas/testsuite/gas/aarch64/sme2-18.s b/gas/testsuite/gas/aarch64/sme2-18.s
new file mode 100644
index 00000000000..b553b41cd95
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-18.s
@@ -0,0 +1,21 @@
+ bfvdot za.s[w8, 0], { z0.h - z1.h }, z0.h[0]
+ bfvdot za.s[w8, 0, vgx2], { z0.h - z1.h }, z0.h[0]
+ BFVDOT ZA.s[W8, 0, VGx2], { Z0.h - Z1.h }, Z0.h[0]
+ BFVDOT ZA.S[W8, 0, VGX2], { Z0.H - Z1.H }, Z0.H[0]
+ bfvdot za.s[w11, 0], { z0.h - z1.h }, z0.h[0]
+ bfvdot za.s[w8, 7], { z0.h - z1.h }, z0.h[0]
+ bfvdot za.s[w8, 0], { z30.h - z31.h }, z0.h[0]
+ bfvdot za.s[w8, 0], { z0.h - z1.h }, z15.h[0]
+ bfvdot za.s[w8, 0], { z0.h - z1.h }, z0.h[3]
+ bfvdot za.s[w10, 2], { z14.h - z15.h }, z13.h[1]
+
+ fvdot za.s[w8, 0], { z0.h - z1.h }, z0.h[0]
+ fvdot za.s[w8, 0, vgx2], { z0.h - z1.h }, z0.h[0]
+ FVDOT ZA.s[W8, 0, VGx2], { Z0.h - Z1.h }, Z0.h[0]
+ FVDOT ZA.S[W8, 0, VGX2], { Z0.H - Z1.H }, Z0.H[0]
+ fvdot za.s[w11, 0], { z0.h - z1.h }, z0.h[0]
+ fvdot za.s[w8, 7], { z0.h - z1.h }, z0.h[0]
+ fvdot za.s[w8, 0], { z30.h - z31.h }, z0.h[0]
+ fvdot za.s[w8, 0], { z0.h - z1.h }, z15.h[0]
+ fvdot za.s[w8, 0], { z0.h - z1.h }, z0.h[3]
+ fvdot za.s[w10, 2], { z14.h - z15.h }, z13.h[1]
diff --git a/gas/testsuite/gas/aarch64/sme2-19-invalid.d b/gas/testsuite/gas/aarch64/sme2-19-invalid.d
new file mode 100644
index 00000000000..ecc08442c6e
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-19-invalid.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a
+#source: sme2-19-invalid.s
+#error_output: sme2-19-invalid.l
diff --git a/gas/testsuite/gas/aarch64/sme2-19-invalid.l b/gas/testsuite/gas/aarch64/sme2-19-invalid.l
new file mode 100644
index 00000000000..936e6f50ca4
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-19-invalid.l
@@ -0,0 +1,36 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: expected a ZA array vector at operand 1 -- `svdot 0,{z0\.h-z1\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected '{' at operand 2 -- `svdot za\.s\[w8,0\],0,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `svdot za\.s\[w8,0\],{z0\.h-z1\.h},0'
+[^ :]+:[0-9]+: Error: missing braces at operand 2 -- `svdot za\.h\[w8,0\],z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `svdot za\.h\[w8,0\],{z0\.h-z1\.h},z0\.h'
+[^ :]+:[0-9]+: Error: expected a single offset rather than a range at operand 1 -- `svdot za\.s\[w8,0:1\],{z0\.h-z1\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: operand 1 must have a vector group size of 2 -- `svdot za\.s\[w8,0,vgx4\],{z0\.h-z1\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `svdot za\.s\[w7,0\],{z0\.h-z1\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `svdot za\.s\[w12,0\],{z0\.h-z1\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `svdot za\.s\[w8,-1\],{z0\.h-z1\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `svdot za\.s\[w8,8\],{z0\.h-z1\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `svdot za\.s\[w8,0\],{z0\.h-z2\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `svdot za\.s\[w8,0\],{z0\.h-z3\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `svdot za\.s\[w8,0\],{z1\.h-z2\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `svdot za\.s\[w8,0\],{z0\.h-z1\.h},z0\.h\[-1\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `svdot za\.s\[w8,0\],{z0\.h-z1\.h},z0\.h\[4\]'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `svdot za\.s\[w8,0\],{z0\.h-z1\.h},z16\.h\[0\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `svdot za\.s\[w8,0:1\],{z0\.b-z3\.b},z0\.h\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: svdot za\.s\[w8, 0:1\], {z0\.b-z3\.b}, z0\.b\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `svdot za\.s\[w8,0,vgx4\],{z0\.b-z3\.b},z0\.h\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: svdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `svdot za\.s\[w7,0\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `svdot za\.s\[w12,0\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `svdot za\.s\[w8,-1\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `svdot za\.s\[w8,8\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `svdot za\.s\[w8,0\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `svdot za\.s\[w8,0\],{z0\.b-z2\.b},z0\.b\[0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `svdot za\.s\[w8,0\],{z1\.b-z4\.b},z0\.b\[0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `svdot za\.s\[w8,0\],{z2\.b-z5\.b},z0\.b\[0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `svdot za\.s\[w8,0\],{z3\.b-z6\.b},z0\.b\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `svdot za\.s\[w8,0\],{z0\.b-z3\.b},z0\.b\[-1\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `svdot za\.s\[w8,0\],{z0\.b-z3\.b},z0\.b\[4\]'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `svdot za\.s\[w8,0\],{z0\.b-z3\.b},z16\.b\[0\]'
diff --git a/gas/testsuite/gas/aarch64/sme2-19-invalid.s b/gas/testsuite/gas/aarch64/sme2-19-invalid.s
new file mode 100644
index 00000000000..3c97857c442
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-19-invalid.s
@@ -0,0 +1,36 @@
+ svdot 0, { z0.h - z1.h }, z0.h[0]
+ svdot za.s[w8, 0], 0, z0.h[0]
+ svdot za.s[w8, 0], { z0.h - z1.h }, 0
+
+ svdot za.h[w8, 0], z0.h, z0.h
+ svdot za.h[w8, 0], { z0.h - z1.h }, z0.h
+
+ svdot za.s[w8, 0:1], { z0.h - z1.h }, z0.h[0]
+ svdot za.s[w8, 0, vgx4], { z0.h - z1.h }, z0.h[0]
+
+ svdot za.s[w7, 0], { z0.h - z1.h }, z0.h[0]
+ svdot za.s[w12, 0], { z0.h - z1.h }, z0.h[0]
+ svdot za.s[w8, -1], { z0.h - z1.h }, z0.h[0]
+ svdot za.s[w8, 8], { z0.h - z1.h }, z0.h[0]
+ svdot za.s[w8, 0], { z0.h - z2.h }, z0.h[0]
+ svdot za.s[w8, 0], { z0.h - z3.h }, z0.h[0]
+ svdot za.s[w8, 0], { z1.h - z2.h }, z0.h[0]
+ svdot za.s[w8, 0], { z0.h - z1.h }, z0.h[-1]
+ svdot za.s[w8, 0], { z0.h - z1.h }, z0.h[4]
+ svdot za.s[w8, 0], { z0.h - z1.h }, z16.h[0]
+
+ svdot za.s[w8, 0:1], { z0.b - z3.b }, z0.h[0]
+ svdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.h[0]
+
+ svdot za.s[w7, 0], { z0.b - z3.b }, z0.b[0]
+ svdot za.s[w12, 0], { z0.b - z3.b }, z0.b[0]
+ svdot za.s[w8, -1], { z0.b - z3.b }, z0.b[0]
+ svdot za.s[w8, 8], { z0.b - z3.b }, z0.b[0]
+ svdot za.s[w8, 0], { z0.b - z1.b }, z0.b[0]
+ svdot za.s[w8, 0], { z0.b - z2.b }, z0.b[0]
+ svdot za.s[w8, 0], { z1.b - z4.b }, z0.b[0]
+ svdot za.s[w8, 0], { z2.b - z5.b }, z0.b[0]
+ svdot za.s[w8, 0], { z3.b - z6.b }, z0.b[0]
+ svdot za.s[w8, 0], { z0.b - z3.b }, z0.b[-1]
+ svdot za.s[w8, 0], { z0.b - z3.b }, z0.b[4]
+ svdot za.s[w8, 0], { z0.b - z3.b }, z16.b[0]
diff --git a/gas/testsuite/gas/aarch64/sme2-19-noarch.d b/gas/testsuite/gas/aarch64/sme2-19-noarch.d
new file mode 100644
index 00000000000..9006a30a52a
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-19-noarch.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a+sme
+#source: sme2-19.s
+#error_output: sme2-19-noarch.l
diff --git a/gas/testsuite/gas/aarch64/sme2-19-noarch.l b/gas/testsuite/gas/aarch64/sme2-19-noarch.l
new file mode 100644
index 00000000000..c4d760e17a0
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-19-noarch.l
@@ -0,0 +1,41 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: selected processor does not support `svdot za\.s\[w8,0\],{z0\.h-z1\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `svdot za\.s\[w8,0,vgx2\],{z0\.h-z1\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `svdot ZA\.s\[W8,0,VGx2\],{Z0\.h-Z1\.h},Z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `svdot ZA\.S\[W8,0,VGX2\],{Z0\.H-Z1\.H},Z0\.H\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `svdot za\.s\[w11,0\],{z0\.h-z1\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `svdot za\.s\[w8,7\],{z0\.h-z1\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `svdot za\.s\[w8,0\],{z30\.h-z31\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `svdot za\.s\[w8,0\],{z0\.h-z1\.h},z15\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `svdot za\.s\[w8,0\],{z0\.h-z1\.h},z0\.h\[3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `svdot za\.s\[w10,2\],{z14\.h-z15\.h},z13\.h\[1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `svdot za\.s\[w8,0\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `svdot za\.s\[w8,0,vgx4\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `svdot ZA\.s\[W8,0,VGx4\],{Z0\.b-Z3\.b},Z0\.b\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `svdot ZA\.S\[W8,0,VGX4\],{Z0\.B-Z3\.B},Z0\.B\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `svdot za\.s\[w11,0\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `svdot za\.s\[w8,7\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `svdot za\.s\[w8,0\],{z28\.b-z31\.b},z0\.b\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `svdot za\.s\[w8,0\],{z0\.b-z3\.b},z15\.b\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `svdot za\.s\[w8,0\],{z0\.b-z3\.b},z0\.b\[3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `svdot za\.s\[w9,1\],{z4\.b-z7\.b},z10\.b\[2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `uvdot za\.s\[w8,0\],{z0\.h-z1\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `uvdot za\.s\[w8,0,vgx2\],{z0\.h-z1\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `uvdot ZA\.s\[W8,0,VGx2\],{Z0\.h-Z1\.h},Z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `uvdot ZA\.S\[W8,0,VGX2\],{Z0\.H-Z1\.H},Z0\.H\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `uvdot za\.s\[w11,0\],{z0\.h-z1\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `uvdot za\.s\[w8,7\],{z0\.h-z1\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `uvdot za\.s\[w8,0\],{z30\.h-z31\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `uvdot za\.s\[w8,0\],{z0\.h-z1\.h},z15\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `uvdot za\.s\[w8,0\],{z0\.h-z1\.h},z0\.h\[3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `uvdot za\.s\[w10,2\],{z14\.h-z15\.h},z13\.h\[1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `uvdot za\.s\[w8,0\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `uvdot za\.s\[w8,0,vgx4\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `uvdot ZA\.s\[W8,0,VGx4\],{Z0\.b-Z3\.b},Z0\.b\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `uvdot ZA\.S\[W8,0,VGX4\],{Z0\.B-Z3\.B},Z0\.B\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `uvdot za\.s\[w11,0\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `uvdot za\.s\[w8,7\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `uvdot za\.s\[w8,0\],{z28\.b-z31\.b},z0\.b\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `uvdot za\.s\[w8,0\],{z0\.b-z3\.b},z15\.b\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `uvdot za\.s\[w8,0\],{z0\.b-z3\.b},z0\.b\[3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `uvdot za\.s\[w9,1\],{z4\.b-z7\.b},z10\.b\[2\]'
diff --git a/gas/testsuite/gas/aarch64/sme2-19.d b/gas/testsuite/gas/aarch64/sme2-19.d
new file mode 100644
index 00000000000..5af3a2acd2a
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-19.d
@@ -0,0 +1,49 @@
+#as: -march=armv8-a+sme2
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+[^:]+: c1500020 svdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
+[^:]+: c1500020 svdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
+[^:]+: c1500020 svdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
+[^:]+: c1500020 svdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
+[^:]+: c1506020 svdot za\.s\[w11, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
+[^:]+: c1500027 svdot za\.s\[w8, 7, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
+[^:]+: c15003e0 svdot za\.s\[w8, 0, vgx2\], {z30\.h-z31\.h}, z0\.h\[0\]
+[^:]+: c15f0020 svdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z15\.h\[0\]
+[^:]+: c1500c20 svdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[3\]
+[^:]+: c15d45e2 svdot za\.s\[w10, 2, vgx2\], {z14\.h-z15\.h}, z13\.h\[1\]
+[^:]+: c1508020 svdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+[^:]+: c1508020 svdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+[^:]+: c1508020 svdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+[^:]+: c1508020 svdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+[^:]+: c150e020 svdot za\.s\[w11, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+[^:]+: c1508027 svdot za\.s\[w8, 7, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+[^:]+: c15083a0 svdot za\.s\[w8, 0, vgx4\], {z28\.b-z31\.b}, z0\.b\[0\]
+[^:]+: c15f8020 svdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z15\.b\[0\]
+[^:]+: c1508c20 svdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[3\]
+[^:]+: c15aa8a1 svdot za\.s\[w9, 1, vgx4\], {z4\.b-z7\.b}, z10\.b\[2\]
+[^:]+: c1500030 uvdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
+[^:]+: c1500030 uvdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
+[^:]+: c1500030 uvdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
+[^:]+: c1500030 uvdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
+[^:]+: c1506030 uvdot za\.s\[w11, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
+[^:]+: c1500037 uvdot za\.s\[w8, 7, vgx2\], {z0\.h-z1\.h}, z0\.h\[0\]
+[^:]+: c15003f0 uvdot za\.s\[w8, 0, vgx2\], {z30\.h-z31\.h}, z0\.h\[0\]
+[^:]+: c15f0030 uvdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z15\.h\[0\]
+[^:]+: c1500c30 uvdot za\.s\[w8, 0, vgx2\], {z0\.h-z1\.h}, z0\.h\[3\]
+[^:]+: c15d45f2 uvdot za\.s\[w10, 2, vgx2\], {z14\.h-z15\.h}, z13\.h\[1\]
+[^:]+: c1508030 uvdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+[^:]+: c1508030 uvdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+[^:]+: c1508030 uvdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+[^:]+: c1508030 uvdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+[^:]+: c150e030 uvdot za\.s\[w11, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+[^:]+: c1508037 uvdot za\.s\[w8, 7, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+[^:]+: c15083b0 uvdot za\.s\[w8, 0, vgx4\], {z28\.b-z31\.b}, z0\.b\[0\]
+[^:]+: c15f8030 uvdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z15\.b\[0\]
+[^:]+: c1508c30 uvdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[3\]
+[^:]+: c15aa8b1 uvdot za\.s\[w9, 1, vgx4\], {z4\.b-z7\.b}, z10\.b\[2\]
diff --git a/gas/testsuite/gas/aarch64/sme2-19.s b/gas/testsuite/gas/aarch64/sme2-19.s
new file mode 100644
index 00000000000..d95296f5fa1
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-19.s
@@ -0,0 +1,43 @@
+ svdot za.s[w8, 0], { z0.h - z1.h }, z0.h[0]
+ svdot za.s[w8, 0, vgx2], { z0.h - z1.h }, z0.h[0]
+ SVDOT ZA.s[W8, 0, VGx2], { Z0.h - Z1.h }, Z0.h[0]
+ SVDOT ZA.S[W8, 0, VGX2], { Z0.H - Z1.H }, Z0.H[0]
+ svdot za.s[w11, 0], { z0.h - z1.h }, z0.h[0]
+ svdot za.s[w8, 7], { z0.h - z1.h }, z0.h[0]
+ svdot za.s[w8, 0], { z30.h - z31.h }, z0.h[0]
+ svdot za.s[w8, 0], { z0.h - z1.h }, z15.h[0]
+ svdot za.s[w8, 0], { z0.h - z1.h }, z0.h[3]
+ svdot za.s[w10, 2], { z14.h - z15.h }, z13.h[1]
+
+ svdot za.s[w8, 0], { z0.b - z3.b }, z0.b[0]
+ svdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]
+ SVDOT ZA.s[W8, 0, VGx4], { Z0.b - Z3.b }, Z0.b[0]
+ SVDOT ZA.S[W8, 0, VGX4], { Z0.B - Z3.B }, Z0.B[0]
+ svdot za.s[w11, 0], { z0.b - z3.b }, z0.b[0]
+ svdot za.s[w8, 7], { z0.b - z3.b }, z0.b[0]
+ svdot za.s[w8, 0], { z28.b - z31.b }, z0.b[0]
+ svdot za.s[w8, 0], { z0.b - z3.b }, z15.b[0]
+ svdot za.s[w8, 0], { z0.b - z3.b }, z0.b[3]
+ svdot za.s[w9, 1], { z4.b - z7.b }, z10.b[2]
+
+ uvdot za.s[w8, 0], { z0.h - z1.h }, z0.h[0]
+ uvdot za.s[w8, 0, vgx2], { z0.h - z1.h }, z0.h[0]
+ UVDOT ZA.s[W8, 0, VGx2], { Z0.h - Z1.h }, Z0.h[0]
+ UVDOT ZA.S[W8, 0, VGX2], { Z0.H - Z1.H }, Z0.H[0]
+ uvdot za.s[w11, 0], { z0.h - z1.h }, z0.h[0]
+ uvdot za.s[w8, 7], { z0.h - z1.h }, z0.h[0]
+ uvdot za.s[w8, 0], { z30.h - z31.h }, z0.h[0]
+ uvdot za.s[w8, 0], { z0.h - z1.h }, z15.h[0]
+ uvdot za.s[w8, 0], { z0.h - z1.h }, z0.h[3]
+ uvdot za.s[w10, 2], { z14.h - z15.h }, z13.h[1]
+
+ uvdot za.s[w8, 0], { z0.b - z3.b }, z0.b[0]
+ uvdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]
+ UVDOT ZA.s[W8, 0, VGx4], { Z0.b - Z3.b }, Z0.b[0]
+ UVDOT ZA.S[W8, 0, VGX4], { Z0.B - Z3.B }, Z0.B[0]
+ uvdot za.s[w11, 0], { z0.b - z3.b }, z0.b[0]
+ uvdot za.s[w8, 7], { z0.b - z3.b }, z0.b[0]
+ uvdot za.s[w8, 0], { z28.b - z31.b }, z0.b[0]
+ uvdot za.s[w8, 0], { z0.b - z3.b }, z15.b[0]
+ uvdot za.s[w8, 0], { z0.b - z3.b }, z0.b[3]
+ uvdot za.s[w9, 1], { z4.b - z7.b }, z10.b[2]
diff --git a/gas/testsuite/gas/aarch64/sme2-20-invalid.d b/gas/testsuite/gas/aarch64/sme2-20-invalid.d
new file mode 100644
index 00000000000..e7691162f13
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-20-invalid.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a
+#source: sme2-20-invalid.s
+#error_output: sme2-20-invalid.l
diff --git a/gas/testsuite/gas/aarch64/sme2-20-invalid.l b/gas/testsuite/gas/aarch64/sme2-20-invalid.l
new file mode 100644
index 00000000000..cea44765bbb
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-20-invalid.l
@@ -0,0 +1,27 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: expected a ZA array vector at operand 1 -- `suvdot 0,{z0\.b-z3\.b},z0\.b\[0\]'
+[^ :]+:[0-9]+: Error: expected '{' at operand 2 -- `suvdot za\.s\[w8,0\],0,z0\.b\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `suvdot za\.s\[w8,0\],{z0\.b-z3\.b},0'
+[^ :]+:[0-9]+: Error: missing braces at operand 2 -- `suvdot za\.h\[w8,0\],z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `suvdot za\.h\[w8,0\],{z0\.h-z1\.h},z0\.h'
+[^ :]+:[0-9]+: Error: operand mismatch -- `suvdot za\.s\[w8,0\],{z0\.h-z1\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: suvdot za\.s\[w8, 0\], {z0\.b-z1\.b}, z0\.b\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `suvdot za\.s\[w8,0:1\],{z0\.b-z3\.b},z0\.h\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: suvdot za\.s\[w8, 0:1\], {z0\.b-z3\.b}, z0\.b\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `suvdot za\.s\[w8,0,vgx4\],{z0\.b-z3\.b},z0\.h\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: suvdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `suvdot za\.s\[w7,0\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `suvdot za\.s\[w12,0\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `suvdot za\.s\[w8,-1\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `suvdot za\.s\[w8,8\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `suvdot za\.s\[w8,0\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `suvdot za\.s\[w8,0\],{z0\.b-z2\.b},z0\.b\[0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `suvdot za\.s\[w8,0\],{z1\.b-z4\.b},z0\.b\[0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `suvdot za\.s\[w8,0\],{z2\.b-z5\.b},z0\.b\[0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `suvdot za\.s\[w8,0\],{z3\.b-z6\.b},z0\.b\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `suvdot za\.s\[w8,0\],{z0\.b-z3\.b},z0\.b\[-1\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `suvdot za\.s\[w8,0\],{z0\.b-z3\.b},z0\.b\[4\]'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `suvdot za\.s\[w8,0\],{z0\.b-z3\.b},z16\.b\[0\]'
diff --git a/gas/testsuite/gas/aarch64/sme2-20-invalid.s b/gas/testsuite/gas/aarch64/sme2-20-invalid.s
new file mode 100644
index 00000000000..9669e28733a
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-20-invalid.s
@@ -0,0 +1,23 @@
+ suvdot 0, { z0.b - z3.b }, z0.b[0]
+ suvdot za.s[w8, 0], 0, z0.b[0]
+ suvdot za.s[w8, 0], { z0.b - z3.b }, 0
+
+ suvdot za.h[w8, 0], z0.h, z0.h
+ suvdot za.h[w8, 0], { z0.h - z1.h }, z0.h
+ suvdot za.s[w8, 0], { z0.h - z1.h }, z0.h[0]
+
+ suvdot za.s[w8, 0:1], { z0.b - z3.b }, z0.h[0]
+ suvdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.h[0]
+
+ suvdot za.s[w7, 0], { z0.b - z3.b }, z0.b[0]
+ suvdot za.s[w12, 0], { z0.b - z3.b }, z0.b[0]
+ suvdot za.s[w8, -1], { z0.b - z3.b }, z0.b[0]
+ suvdot za.s[w8, 8], { z0.b - z3.b }, z0.b[0]
+ suvdot za.s[w8, 0], { z0.b - z1.b }, z0.b[0]
+ suvdot za.s[w8, 0], { z0.b - z2.b }, z0.b[0]
+ suvdot za.s[w8, 0], { z1.b - z4.b }, z0.b[0]
+ suvdot za.s[w8, 0], { z2.b - z5.b }, z0.b[0]
+ suvdot za.s[w8, 0], { z3.b - z6.b }, z0.b[0]
+ suvdot za.s[w8, 0], { z0.b - z3.b }, z0.b[-1]
+ suvdot za.s[w8, 0], { z0.b - z3.b }, z0.b[4]
+ suvdot za.s[w8, 0], { z0.b - z3.b }, z16.b[0]
diff --git a/gas/testsuite/gas/aarch64/sme2-20-noarch.d b/gas/testsuite/gas/aarch64/sme2-20-noarch.d
new file mode 100644
index 00000000000..f73e2610161
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-20-noarch.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a+sme
+#source: sme2-20.s
+#error_output: sme2-20-noarch.l
diff --git a/gas/testsuite/gas/aarch64/sme2-20-noarch.l b/gas/testsuite/gas/aarch64/sme2-20-noarch.l
new file mode 100644
index 00000000000..8b268d3aaa6
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-20-noarch.l
@@ -0,0 +1,21 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: selected processor does not support `suvdot za\.s\[w8,0\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `suvdot za\.s\[w8,0,vgx4\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `suvdot ZA\.s\[W8,0,VGx4\],{Z0\.b-Z3\.b},Z0\.b\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `suvdot ZA\.S\[W8,0,VGX4\],{Z0\.B-Z3\.B},Z0\.B\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `suvdot za\.s\[w11,0\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `suvdot za\.s\[w8,7\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `suvdot za\.s\[w8,0\],{z28\.b-z31\.b},z0\.b\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `suvdot za\.s\[w8,0\],{z0\.b-z3\.b},z15\.b\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `suvdot za\.s\[w8,0\],{z0\.b-z3\.b},z0\.b\[3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `suvdot za\.s\[w9,1\],{z4\.b-z7\.b},z10\.b\[2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `usvdot za\.s\[w8,0\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `usvdot za\.s\[w8,0,vgx4\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `usvdot ZA\.s\[W8,0,VGx4\],{Z0\.b-Z3\.b},Z0\.b\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `usvdot ZA\.S\[W8,0,VGX4\],{Z0\.B-Z3\.B},Z0\.B\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `usvdot za\.s\[w11,0\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `usvdot za\.s\[w8,7\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `usvdot za\.s\[w8,0\],{z28\.b-z31\.b},z0\.b\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `usvdot za\.s\[w8,0\],{z0\.b-z3\.b},z15\.b\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `usvdot za\.s\[w8,0\],{z0\.b-z3\.b},z0\.b\[3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `usvdot za\.s\[w9,1\],{z4\.b-z7\.b},z10\.b\[2\]'
diff --git a/gas/testsuite/gas/aarch64/sme2-20.d b/gas/testsuite/gas/aarch64/sme2-20.d
new file mode 100644
index 00000000000..860152a0bd4
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-20.d
@@ -0,0 +1,29 @@
+#as: -march=armv8-a+sme2
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+[^:]+: c1508038 suvdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+[^:]+: c1508038 suvdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+[^:]+: c1508038 suvdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+[^:]+: c1508038 suvdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+[^:]+: c150e038 suvdot za\.s\[w11, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+[^:]+: c150803f suvdot za\.s\[w8, 7, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+[^:]+: c15083b8 suvdot za\.s\[w8, 0, vgx4\], {z28\.b-z31\.b}, z0\.b\[0\]
+[^:]+: c15f8038 suvdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z15\.b\[0\]
+[^:]+: c1508c38 suvdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[3\]
+[^:]+: c15aa8b9 suvdot za\.s\[w9, 1, vgx4\], {z4\.b-z7\.b}, z10\.b\[2\]
+[^:]+: c1508028 usvdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+[^:]+: c1508028 usvdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+[^:]+: c1508028 usvdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+[^:]+: c1508028 usvdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+[^:]+: c150e028 usvdot za\.s\[w11, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+[^:]+: c150802f usvdot za\.s\[w8, 7, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+[^:]+: c15083a8 usvdot za\.s\[w8, 0, vgx4\], {z28\.b-z31\.b}, z0\.b\[0\]
+[^:]+: c15f8028 usvdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z15\.b\[0\]
+[^:]+: c1508c28 usvdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[3\]
+[^:]+: c15aa8a9 usvdot za\.s\[w9, 1, vgx4\], {z4\.b-z7\.b}, z10\.b\[2\]
diff --git a/gas/testsuite/gas/aarch64/sme2-20.s b/gas/testsuite/gas/aarch64/sme2-20.s
new file mode 100644
index 00000000000..bcec166ca1d
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-20.s
@@ -0,0 +1,21 @@
+ suvdot za.s[w8, 0], { z0.b - z3.b }, z0.b[0]
+ suvdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]
+ SUVDOT ZA.s[W8, 0, VGx4], { Z0.b - Z3.b }, Z0.b[0]
+ SUVDOT ZA.S[W8, 0, VGX4], { Z0.B - Z3.B }, Z0.B[0]
+ suvdot za.s[w11, 0], { z0.b - z3.b }, z0.b[0]
+ suvdot za.s[w8, 7], { z0.b - z3.b }, z0.b[0]
+ suvdot za.s[w8, 0], { z28.b - z31.b }, z0.b[0]
+ suvdot za.s[w8, 0], { z0.b - z3.b }, z15.b[0]
+ suvdot za.s[w8, 0], { z0.b - z3.b }, z0.b[3]
+ suvdot za.s[w9, 1], { z4.b - z7.b }, z10.b[2]
+
+ usvdot za.s[w8, 0], { z0.b - z3.b }, z0.b[0]
+ usvdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]
+ USVDOT ZA.s[W8, 0, VGx4], { Z0.b - Z3.b }, Z0.b[0]
+ USVDOT ZA.S[W8, 0, VGX4], { Z0.B - Z3.B }, Z0.B[0]
+ usvdot za.s[w11, 0], { z0.b - z3.b }, z0.b[0]
+ usvdot za.s[w8, 7], { z0.b - z3.b }, z0.b[0]
+ usvdot za.s[w8, 0], { z28.b - z31.b }, z0.b[0]
+ usvdot za.s[w8, 0], { z0.b - z3.b }, z15.b[0]
+ usvdot za.s[w8, 0], { z0.b - z3.b }, z0.b[3]
+ usvdot za.s[w9, 1], { z4.b - z7.b }, z10.b[2]
diff --git a/gas/testsuite/gas/aarch64/sme2-i16i64-4-invalid.d b/gas/testsuite/gas/aarch64/sme2-i16i64-4-invalid.d
new file mode 100644
index 00000000000..6352d4bb328
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-i16i64-4-invalid.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a
+#source: sme2-i16i64-4-invalid.s
+#error_output: sme2-i16i64-4-invalid.l
diff --git a/gas/testsuite/gas/aarch64/sme2-i16i64-4-invalid.l b/gas/testsuite/gas/aarch64/sme2-i16i64-4-invalid.l
new file mode 100644
index 00000000000..c33f15ec46f
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-i16i64-4-invalid.l
@@ -0,0 +1,11 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `svdot za\.d\[w8,0\],{z0\.h-z1\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `svdot za\.d\[w8,0\],{z0\.h-z3\.h},z0\.h\[-1\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `svdot za\.d\[w8,0\],{z0\.h-z3\.h},z0\.h\[2\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `svdot za\.d\[w8,0\],{z1\.h-z4\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `svdot za\.d\[w8,0\],{z2\.h-z5\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `svdot za\.d\[w8,0\],{z3\.h-z6\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `svdot za\.d\[w8,0\],{z0\.h-z1\.h},z0\.h'
+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `svdot za\.d\[w8,0\],{z0\.h-z3\.h},z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `svdot za\.d\[w8,0\],{z0\.h-z1\.h},{z0\.h-z1\.h}'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `svdot za\.d\[w8,0\],{z0\.h-z3\.h},{z0\.h-z3\.h}'
diff --git a/gas/testsuite/gas/aarch64/sme2-i16i64-4-invalid.s b/gas/testsuite/gas/aarch64/sme2-i16i64-4-invalid.s
new file mode 100644
index 00000000000..ef9862831fe
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-i16i64-4-invalid.s
@@ -0,0 +1,12 @@
+ svdot za.d[w8, 0], { z0.h - z1.h }, z0.h[0]
+
+ svdot za.d[w8, 0], { z0.h - z3.h }, z0.h[-1]
+ svdot za.d[w8, 0], { z0.h - z3.h }, z0.h[2]
+ svdot za.d[w8, 0], { z1.h - z4.h }, z0.h[0]
+ svdot za.d[w8, 0], { z2.h - z5.h }, z0.h[0]
+ svdot za.d[w8, 0], { z3.h - z6.h }, z0.h[0]
+
+ svdot za.d[w8, 0], { z0.h - z1.h }, z0.h
+ svdot za.d[w8, 0], { z0.h - z3.h }, z0.h
+ svdot za.d[w8, 0], { z0.h - z1.h }, { z0.h - z1.h }
+ svdot za.d[w8, 0], { z0.h - z3.h }, { z0.h - z3.h }
diff --git a/gas/testsuite/gas/aarch64/sme2-i16i64-4-noarch.d b/gas/testsuite/gas/aarch64/sme2-i16i64-4-noarch.d
new file mode 100644
index 00000000000..6d48f4e0ff8
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-i16i64-4-noarch.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a+sme2
+#source: sme2-i16i64-4.s
+#error_output: sme2-i16i64-4-noarch.l
diff --git a/gas/testsuite/gas/aarch64/sme2-i16i64-4-noarch.l b/gas/testsuite/gas/aarch64/sme2-i16i64-4-noarch.l
new file mode 100644
index 00000000000..4b27662fee8
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-i16i64-4-noarch.l
@@ -0,0 +1,21 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: selected processor does not support `svdot za\.d\[w8,0\],{z0\.h-z3\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `svdot za\.d\[w8,0,vgx4\],{z0\.h-z3\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `svdot ZA\.d\[W8,0,VGx4\],{Z0\.h-Z3\.h},Z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `svdot ZA\.D\[W8,0,VGX4\],{Z0\.H-Z3\.H},Z0\.H\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `svdot za\.d\[w11,0\],{z0\.h-z3\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `svdot za\.d\[w8,7\],{z0\.h-z3\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `svdot za\.d\[w8,0\],{z28\.h-z31\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `svdot za\.d\[w8,0\],{z0\.h-z3\.h},z15\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `svdot za\.d\[w8,0\],{z0\.h-z3\.h},z0\.h\[1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `svdot za\.d\[w9,1\],{z4\.h-z7\.h},z10\.h\[1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `uvdot za\.d\[w8,0\],{z0\.h-z3\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `uvdot za\.d\[w8,0,vgx4\],{z0\.h-z3\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `uvdot ZA\.d\[W8,0,VGx4\],{Z0\.h-Z3\.h},Z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `uvdot ZA\.D\[W8,0,VGX4\],{Z0\.H-Z3\.H},Z0\.H\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `uvdot za\.d\[w11,0\],{z0\.h-z3\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `uvdot za\.d\[w8,7\],{z0\.h-z3\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `uvdot za\.d\[w8,0\],{z28\.h-z31\.h},z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `uvdot za\.d\[w8,0\],{z0\.h-z3\.h},z15\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `uvdot za\.d\[w8,0\],{z0\.h-z3\.h},z0\.h\[1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `uvdot za\.d\[w9,1\],{z4\.h-z7\.h},z10\.h\[1\]'
diff --git a/gas/testsuite/gas/aarch64/sme2-i16i64-4.d b/gas/testsuite/gas/aarch64/sme2-i16i64-4.d
new file mode 100644
index 00000000000..441baebe89e
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-i16i64-4.d
@@ -0,0 +1,29 @@
+#as: -march=armv8-a+sme2+sme-i16i64
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+[^:]+: c1d08808 svdot za\.d\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
+[^:]+: c1d08808 svdot za\.d\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
+[^:]+: c1d08808 svdot za\.d\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
+[^:]+: c1d08808 svdot za\.d\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
+[^:]+: c1d0e808 svdot za\.d\[w11, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
+[^:]+: c1d0880f svdot za\.d\[w8, 7, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
+[^:]+: c1d08b88 svdot za\.d\[w8, 0, vgx4\], {z28\.h-z31\.h}, z0\.h\[0\]
+[^:]+: c1df8808 svdot za\.d\[w8, 0, vgx4\], {z0\.h-z3\.h}, z15\.h\[0\]
+[^:]+: c1d08c08 svdot za\.d\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[1\]
+[^:]+: c1daac89 svdot za\.d\[w9, 1, vgx4\], {z4\.h-z7\.h}, z10\.h\[1\]
+[^:]+: c1d08818 uvdot za\.d\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
+[^:]+: c1d08818 uvdot za\.d\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
+[^:]+: c1d08818 uvdot za\.d\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
+[^:]+: c1d08818 uvdot za\.d\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
+[^:]+: c1d0e818 uvdot za\.d\[w11, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
+[^:]+: c1d0881f uvdot za\.d\[w8, 7, vgx4\], {z0\.h-z3\.h}, z0\.h\[0\]
+[^:]+: c1d08b98 uvdot za\.d\[w8, 0, vgx4\], {z28\.h-z31\.h}, z0\.h\[0\]
+[^:]+: c1df8818 uvdot za\.d\[w8, 0, vgx4\], {z0\.h-z3\.h}, z15\.h\[0\]
+[^:]+: c1d08c18 uvdot za\.d\[w8, 0, vgx4\], {z0\.h-z3\.h}, z0\.h\[1\]
+[^:]+: c1daac99 uvdot za\.d\[w9, 1, vgx4\], {z4\.h-z7\.h}, z10\.h\[1\]
diff --git a/gas/testsuite/gas/aarch64/sme2-i16i64-4.s b/gas/testsuite/gas/aarch64/sme2-i16i64-4.s
new file mode 100644
index 00000000000..fbddfa6e3a3
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-i16i64-4.s
@@ -0,0 +1,21 @@
+ svdot za.d[w8, 0], { z0.h - z3.h }, z0.h[0]
+ svdot za.d[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]
+ SVDOT ZA.d[W8, 0, VGx4], { Z0.h - Z3.h }, Z0.h[0]
+ SVDOT ZA.D[W8, 0, VGX4], { Z0.H - Z3.H }, Z0.H[0]
+ svdot za.d[w11, 0], { z0.h - z3.h }, z0.h[0]
+ svdot za.d[w8, 7], { z0.h - z3.h }, z0.h[0]
+ svdot za.d[w8, 0], { z28.h - z31.h }, z0.h[0]
+ svdot za.d[w8, 0], { z0.h - z3.h }, z15.h[0]
+ svdot za.d[w8, 0], { z0.h - z3.h }, z0.h[1]
+ svdot za.d[w9, 1], { z4.h - z7.h }, z10.h[1]
+
+ uvdot za.d[w8, 0], { z0.h - z3.h }, z0.h[0]
+ uvdot za.d[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]
+ UVDOT ZA.d[W8, 0, VGx4], { Z0.h - Z3.h }, Z0.h[0]
+ UVDOT ZA.D[W8, 0, VGX4], { Z0.H - Z3.H }, Z0.H[0]
+ uvdot za.d[w11, 0], { z0.h - z3.h }, z0.h[0]
+ uvdot za.d[w8, 7], { z0.h - z3.h }, z0.h[0]
+ uvdot za.d[w8, 0], { z28.h - z31.h }, z0.h[0]
+ uvdot za.d[w8, 0], { z0.h - z3.h }, z15.h[0]
+ uvdot za.d[w8, 0], { z0.h - z3.h }, z0.h[1]
+ uvdot za.d[w9, 1], { z4.h - z7.h }, z10.h[1]
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index c631e1cd59b..ddd0a68970a 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -166,7 +166,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000x10x100xxxxxxxxxxxxxxxxx
zero. */
- return 2825;
+ return 2833;
}
}
}
@@ -190,7 +190,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000x00x101xx0xxxxxxxxxxxxxx
luti4. */
- return 2583;
+ return 2585;
}
else
{
@@ -198,7 +198,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000x00x101xx1xxxxxxxxxxxxxx
luti4. */
- return 2582;
+ return 2584;
}
}
else
@@ -207,7 +207,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000x10x101xxxxxxxxxxxxxxxxx
luti4. */
- return 2581;
+ return 2583;
}
}
}
@@ -226,7 +226,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx0x010xxxxx00xxxxxxxxxx
mov. */
- return 2590;
+ return 2592;
}
else
{
@@ -234,7 +234,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx0x011xxxxx00xxxxxxxxxx
mov. */
- return 2586;
+ return 2588;
}
}
else
@@ -247,7 +247,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000x00x11xxx0xx00xxxxxxxxxx
luti2. */
- return 2580;
+ return 2582;
}
else
{
@@ -255,7 +255,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000x00x11xxx1xx00xxxxxxxxxx
luti2. */
- return 2579;
+ return 2581;
}
}
else
@@ -268,7 +268,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000010x110xxxxx00xxxxxxxxxx
movt. */
- return 2601;
+ return 2603;
}
else
{
@@ -276,7 +276,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000010x111xxxxx00xxxxxxxxxx
movt. */
- return 2600;
+ return 2602;
}
}
else
@@ -285,7 +285,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000110x11xxxxxx00xxxxxxxxxx
luti2. */
- return 2578;
+ return 2580;
}
}
}
@@ -298,7 +298,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx0xx10xxxxx10xxxxxxxxxx
mov. */
- return 2588;
+ return 2590;
}
else
{
@@ -306,7 +306,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx0xx11xxxxx10xxxxxxxxxx
mov. */
- return 2584;
+ return 2586;
}
}
}
@@ -320,7 +320,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx0xx10xxxxx01xxxxxxxxxx
mov. */
- return 2591;
+ return 2593;
}
else
{
@@ -328,7 +328,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx0xx11xxxxx01xxxxxxxxxx
mov. */
- return 2587;
+ return 2589;
}
}
else
@@ -339,7 +339,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx0xx10xxxxx11xxxxxxxxxx
mov. */
- return 2589;
+ return 2591;
}
else
{
@@ -347,7 +347,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx0xx11xxxxx11xxxxxxxxxx
mov. */
- return 2585;
+ return 2587;
}
}
}
@@ -374,7 +374,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000000xxxxx000xxxxxxxxxxxx0
ld1b. */
- return 2517;
+ return 2519;
}
else
{
@@ -382,7 +382,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000000xxxxx100xxxxxxxxxxxx0
ld1b. */
- return 2518;
+ return 2520;
}
}
else
@@ -393,7 +393,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000000xxxxx010xxxxxxxxxxxx0
ld1w. */
- return 2541;
+ return 2543;
}
else
{
@@ -401,7 +401,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000000xxxxx110xxxxxxxxxxxx0
ld1w. */
- return 2542;
+ return 2544;
}
}
}
@@ -415,7 +415,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000000xxxxx001xxxxxxxxxxxx0
ld1h. */
- return 2533;
+ return 2535;
}
else
{
@@ -423,7 +423,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000000xxxxx101xxxxxxxxxxxx0
ld1h. */
- return 2534;
+ return 2536;
}
}
else
@@ -434,7 +434,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000000xxxxx011xxxxxxxxxxxx0
ld1d. */
- return 2525;
+ return 2527;
}
else
{
@@ -442,7 +442,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000000xxxxx111xxxxxxxxxxxx0
ld1d. */
- return 2526;
+ return 2528;
}
}
}
@@ -459,7 +459,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000000xxxxx000xxxxxxxxxxxx1
ldnt1b. */
- return 2549;
+ return 2551;
}
else
{
@@ -467,7 +467,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000000xxxxx100xxxxxxxxxxxx1
ldnt1b. */
- return 2550;
+ return 2552;
}
}
else
@@ -478,7 +478,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000000xxxxx010xxxxxxxxxxxx1
ldnt1w. */
- return 2573;
+ return 2575;
}
else
{
@@ -486,7 +486,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000000xxxxx110xxxxxxxxxxxx1
ldnt1w. */
- return 2574;
+ return 2576;
}
}
}
@@ -500,7 +500,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000000xxxxx001xxxxxxxxxxxx1
ldnt1h. */
- return 2565;
+ return 2567;
}
else
{
@@ -508,7 +508,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000000xxxxx101xxxxxxxxxxxx1
ldnt1h. */
- return 2566;
+ return 2568;
}
}
else
@@ -519,7 +519,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000000xxxxx011xxxxxxxxxxxx1
ldnt1d. */
- return 2557;
+ return 2559;
}
else
{
@@ -527,7 +527,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000000xxxxx111xxxxxxxxxxxx1
ldnt1d. */
- return 2558;
+ return 2560;
}
}
}
@@ -591,7 +591,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000010xxxxx000xxxxxxxxxxxx0
ld1b. */
- return 2513;
+ return 2515;
}
else
{
@@ -599,7 +599,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000010xxxxx100xxxxxxxxxxxx0
ld1b. */
- return 2514;
+ return 2516;
}
}
else
@@ -610,7 +610,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000010xxxxx010xxxxxxxxxxxx0
ld1w. */
- return 2537;
+ return 2539;
}
else
{
@@ -618,7 +618,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000010xxxxx110xxxxxxxxxxxx0
ld1w. */
- return 2538;
+ return 2540;
}
}
}
@@ -632,7 +632,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000010xxxxx001xxxxxxxxxxxx0
ld1h. */
- return 2529;
+ return 2531;
}
else
{
@@ -640,7 +640,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000010xxxxx101xxxxxxxxxxxx0
ld1h. */
- return 2530;
+ return 2532;
}
}
else
@@ -651,7 +651,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000010xxxxx011xxxxxxxxxxxx0
ld1d. */
- return 2521;
+ return 2523;
}
else
{
@@ -659,7 +659,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000010xxxxx111xxxxxxxxxxxx0
ld1d. */
- return 2522;
+ return 2524;
}
}
}
@@ -676,7 +676,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000010xxxxx000xxxxxxxxxxxx1
ldnt1b. */
- return 2545;
+ return 2547;
}
else
{
@@ -684,7 +684,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000010xxxxx100xxxxxxxxxxxx1
ldnt1b. */
- return 2546;
+ return 2548;
}
}
else
@@ -695,7 +695,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000010xxxxx010xxxxxxxxxxxx1
ldnt1w. */
- return 2569;
+ return 2571;
}
else
{
@@ -703,7 +703,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000010xxxxx110xxxxxxxxxxxx1
ldnt1w. */
- return 2570;
+ return 2572;
}
}
}
@@ -717,7 +717,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000010xxxxx001xxxxxxxxxxxx1
ldnt1h. */
- return 2561;
+ return 2563;
}
else
{
@@ -725,7 +725,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000010xxxxx101xxxxxxxxxxxx1
ldnt1h. */
- return 2562;
+ return 2564;
}
}
else
@@ -736,7 +736,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000010xxxxx011xxxxxxxxxxxx1
ldnt1d. */
- return 2553;
+ return 2555;
}
else
{
@@ -744,7 +744,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000010xxxxx111xxxxxxxxxxxx1
ldnt1d. */
- return 2554;
+ return 2556;
}
}
}
@@ -812,7 +812,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx000xxxxxxxxxxxx0
st1b. */
- return 2671;
+ return 2673;
}
else
{
@@ -820,7 +820,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx100xxxxxxxxxxxx0
st1b. */
- return 2672;
+ return 2674;
}
}
else
@@ -831,7 +831,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx010xxxxxxxxxxxx0
st1w. */
- return 2695;
+ return 2697;
}
else
{
@@ -839,7 +839,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx110xxxxxxxxxxxx0
st1w. */
- return 2696;
+ return 2698;
}
}
}
@@ -853,7 +853,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx001xxxxxxxxxxxx0
st1h. */
- return 2687;
+ return 2689;
}
else
{
@@ -861,7 +861,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx101xxxxxxxxxxxx0
st1h. */
- return 2688;
+ return 2690;
}
}
else
@@ -872,7 +872,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx011xxxxxxxxxxxx0
st1d. */
- return 2679;
+ return 2681;
}
else
{
@@ -880,7 +880,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx111xxxxxxxxxxxx0
st1d. */
- return 2680;
+ return 2682;
}
}
}
@@ -897,7 +897,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx000xxxxxxxxxxxx1
stnt1b. */
- return 2703;
+ return 2705;
}
else
{
@@ -905,7 +905,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx100xxxxxxxxxxxx1
stnt1b. */
- return 2704;
+ return 2706;
}
}
else
@@ -916,7 +916,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx010xxxxxxxxxxxx1
stnt1w. */
- return 2727;
+ return 2729;
}
else
{
@@ -924,7 +924,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx110xxxxxxxxxxxx1
stnt1w. */
- return 2728;
+ return 2730;
}
}
}
@@ -938,7 +938,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx001xxxxxxxxxxxx1
stnt1h. */
- return 2719;
+ return 2721;
}
else
{
@@ -946,7 +946,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx101xxxxxxxxxxxx1
stnt1h. */
- return 2720;
+ return 2722;
}
}
else
@@ -957,7 +957,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx011xxxxxxxxxxxx1
stnt1d. */
- return 2711;
+ return 2713;
}
else
{
@@ -965,7 +965,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx111xxxxxxxxxxxx1
stnt1d. */
- return 2712;
+ return 2714;
}
}
}
@@ -1029,7 +1029,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx000xxxxxxxxxxxx0
st1b. */
- return 2667;
+ return 2669;
}
else
{
@@ -1037,7 +1037,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx100xxxxxxxxxxxx0
st1b. */
- return 2668;
+ return 2670;
}
}
else
@@ -1048,7 +1048,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx010xxxxxxxxxxxx0
st1w. */
- return 2691;
+ return 2693;
}
else
{
@@ -1056,7 +1056,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx110xxxxxxxxxxxx0
st1w. */
- return 2692;
+ return 2694;
}
}
}
@@ -1070,7 +1070,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx001xxxxxxxxxxxx0
st1h. */
- return 2683;
+ return 2685;
}
else
{
@@ -1078,7 +1078,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx101xxxxxxxxxxxx0
st1h. */
- return 2684;
+ return 2686;
}
}
else
@@ -1089,7 +1089,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx011xxxxxxxxxxxx0
st1d. */
- return 2675;
+ return 2677;
}
else
{
@@ -1097,7 +1097,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx111xxxxxxxxxxxx0
st1d. */
- return 2676;
+ return 2678;
}
}
}
@@ -1114,7 +1114,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx000xxxxxxxxxxxx1
stnt1b. */
- return 2699;
+ return 2701;
}
else
{
@@ -1122,7 +1122,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx100xxxxxxxxxxxx1
stnt1b. */
- return 2700;
+ return 2702;
}
}
else
@@ -1133,7 +1133,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx010xxxxxxxxxxxx1
stnt1w. */
- return 2723;
+ return 2725;
}
else
{
@@ -1141,7 +1141,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx110xxxxxxxxxxxx1
stnt1w. */
- return 2724;
+ return 2726;
}
}
}
@@ -1155,7 +1155,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx001xxxxxxxxxxxx1
stnt1h. */
- return 2715;
+ return 2717;
}
else
{
@@ -1163,7 +1163,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx101xxxxxxxxxxxx1
stnt1h. */
- return 2716;
+ return 2718;
}
}
else
@@ -1174,7 +1174,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx011xxxxxxxxxxxx1
stnt1d. */
- return 2707;
+ return 2709;
}
else
{
@@ -1182,7 +1182,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx111xxxxxxxxxxxx1
stnt1d. */
- return 2708;
+ return 2710;
}
}
}
@@ -1274,7 +1274,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010000xxxxxxxxxxxxxxx000xx
smlall. */
- return 2635;
+ return 2637;
}
else
{
@@ -1282,7 +1282,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010000xxxxxxxxxxxxxxx001xx
usmlall. */
- return 2809;
+ return 2814;
}
}
else
@@ -1295,7 +1295,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx0xxxxxxxxx000xxx
smlall. */
- return 2636;
+ return 2638;
}
else
{
@@ -1303,7 +1303,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx1xxxxxxxxx000xxx
smlall. */
- return 2637;
+ return 2639;
}
}
else
@@ -1314,7 +1314,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx0xxxxxxxxx100xxx
usmlall. */
- return 2810;
+ return 2815;
}
else
{
@@ -1322,7 +1322,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx1xxxxxxxxx100xxx
[...]
[diff truncated at 100000 bytes]
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2023-03-30 10:15 [binutils-gdb] aarch64: Add the SME2 vertical dot-product instructions Richard Sandiford
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