* [binutils-gdb] aarch64: Add the SME2 shift instructions
@ 2023-03-30 10:16 Richard Sandiford
0 siblings, 0 replies; only message in thread
From: Richard Sandiford @ 2023-03-30 10:16 UTC (permalink / raw)
To: bfd-cvs
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=6efa660124f481a5ba415cedd195764ea6ac09fd
commit 6efa660124f481a5ba415cedd195764ea6ac09fd
Author: Richard Sandiford <richard.sandiford@arm.com>
Date: Thu Mar 30 11:09:16 2023 +0100
aarch64: Add the SME2 shift instructions
There are two instruction formats here:
- SQRSHR, SQRSHRU and UQRSHR, which operate on lists of two
or four registers.
- SQRSHRN, SQRSHRUN and UQRSHRN, which operate on lists of
four registers.
These are the first SME2 instructions to have immediate operands.
The patch makes sure that, when parsing SME2 instructions with
immediate operands, the new predicate-as-counter registers are
parsed as registers rather than as #-less immediates.
Diff:
---
gas/config/tc-aarch64.c | 17 +-
gas/testsuite/gas/aarch64/sme2-27-invalid.d | 3 +
gas/testsuite/gas/aarch64/sme2-27-invalid.l | 31 +
gas/testsuite/gas/aarch64/sme2-27-invalid.s | 25 +
gas/testsuite/gas/aarch64/sme2-27-noarch.d | 3 +
gas/testsuite/gas/aarch64/sme2-27-noarch.l | 50 ++
gas/testsuite/gas/aarch64/sme2-27.d | 62 ++
gas/testsuite/gas/aarch64/sme2-27.s | 71 ++
gas/testsuite/gas/aarch64/sme2-28-invalid.d | 3 +
gas/testsuite/gas/aarch64/sme2-28-invalid.l | 19 +
gas/testsuite/gas/aarch64/sme2-28-invalid.s | 11 +
gas/testsuite/gas/aarch64/sme2-28-noarch.d | 3 +
gas/testsuite/gas/aarch64/sme2-28-noarch.l | 26 +
gas/testsuite/gas/aarch64/sme2-28.d | 34 +
gas/testsuite/gas/aarch64/sme2-28.s | 29 +
include/opcode/aarch64.h | 3 +
opcodes/aarch64-asm-2.c | 23 +-
opcodes/aarch64-asm.c | 14 +
opcodes/aarch64-asm.h | 1 +
opcodes/aarch64-dis-2.c | 1092 +++++++++++++++------------
opcodes/aarch64-dis.c | 17 +
opcodes/aarch64-dis.h | 1 +
opcodes/aarch64-opc-2.c | 2 +
opcodes/aarch64-opc.c | 12 +
opcodes/aarch64-tbl.h | 22 +
25 files changed, 1066 insertions(+), 508 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 2c8d5916182..781c87bbc41 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -349,6 +349,13 @@ struct reloc_entry
| REG_TYPE(FP_B) | REG_TYPE(FP_H) \
| REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \
| REG_TYPE(Z) | REG_TYPE(P)) \
+ /* Likewise, but with predicate-as-counter registers added. */ \
+ MULTI_REG_TYPE(R_ZR_SP_BHSDQ_VZP_PN, REG_TYPE(R_32) | REG_TYPE(R_64) \
+ | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
+ | REG_TYPE(ZR_32) | REG_TYPE(ZR_64) | REG_TYPE(V) \
+ | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
+ | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \
+ | REG_TYPE(Z) | REG_TYPE(P) | REG_TYPE(PN)) \
/* Any integer register; used for error messages only. */ \
MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
| REG_TYPE(SP_32) | REG_TYPE(SP_64) \
@@ -6527,9 +6534,11 @@ parse_operands (char *str, const aarch64_opcode *opcode)
clear_error ();
skip_whitespace (str);
- if (AARCH64_CPU_HAS_ANY_FEATURES (*opcode->avariant,
- AARCH64_FEATURE_SVE
- | AARCH64_FEATURE_SVE2))
+ if (AARCH64_CPU_HAS_FEATURE (*opcode->avariant, AARCH64_FEATURE_SME2))
+ imm_reg_type = REG_TYPE_R_ZR_SP_BHSDQ_VZP_PN;
+ else if (AARCH64_CPU_HAS_ANY_FEATURES (*opcode->avariant,
+ AARCH64_FEATURE_SVE
+ | AARCH64_FEATURE_SVE2))
imm_reg_type = REG_TYPE_R_ZR_SP_BHSDQ_VZP;
else
imm_reg_type = REG_TYPE_R_ZR_BHSDQ_V;
@@ -6892,6 +6901,8 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_SVE_SHLIMM_PRED:
case AARCH64_OPND_SVE_SHLIMM_UNPRED:
case AARCH64_OPND_SVE_SHLIMM_UNPRED_22:
+ case AARCH64_OPND_SME_SHRIMM4:
+ case AARCH64_OPND_SME_SHRIMM5:
case AARCH64_OPND_SVE_SHRIMM_PRED:
case AARCH64_OPND_SVE_SHRIMM_UNPRED:
case AARCH64_OPND_SVE_SHRIMM_UNPRED_22:
diff --git a/gas/testsuite/gas/aarch64/sme2-27-invalid.d b/gas/testsuite/gas/aarch64/sme2-27-invalid.d
new file mode 100644
index 00000000000..7b34ec4ce67
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-27-invalid.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a
+#source: sme2-27-invalid.s
+#error_output: sme2-27-invalid.l
diff --git a/gas/testsuite/gas/aarch64/sme2-27-invalid.l b/gas/testsuite/gas/aarch64/sme2-27-invalid.l
new file mode 100644
index 00000000000..9efaa04ca90
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-27-invalid.l
@@ -0,0 +1,31 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqrshr 0,{z0\.s-z1\.s},#1'
+[^ :]+:[0-9]+: Error: expected '{' at operand 2 -- `sqrshr z0\.h,0,#1'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqrshr z0\.h,{z1\.s-z2\.s},#1'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqrshr z0\.h,{z0\.s-z1\.s},#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqrshr z0\.h,{z0\.s-z1\.s},#17'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqrshr z0\.s,{z0\.d-z1\.d},#1'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: sqrshr z0\.h, {z0\.d-z1\.d}, #1
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: sqrshr z0\.b, {z0\.s-z1\.s}, #1
+[^ :]+:[0-9]+: Error: immediate operand required at operand 3 -- `sqrshr z0\.h,{z0\.s-z1\.s},x0'
+[^ :]+:[0-9]+: Error: immediate operand required at operand 3 -- `sqrshr z0\.h,{z0\.s-z1\.s},z0\.s'
+[^ :]+:[0-9]+: Error: immediate operand required at operand 3 -- `sqrshr z0\.h,{z0\.s-z1\.s},p0'
+[^ :]+:[0-9]+: Error: immediate operand required at operand 3 -- `sqrshr z0\.h,{z0\.s-z1\.s},pn0'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqrshr z0\.b,{z1\.s-z4\.s},#1'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqrshr z0\.b,{z2\.s-z5\.s},#1'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqrshr z0\.b,{z3\.s-z6\.s},#1'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshr z0\.b,{z0\.s-z3\.s},#-1'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshr z0\.b,{z0\.s-z3\.s},#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshr z0\.b,{z0\.s-z3\.s},#33'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqrshr z0\.b,{z0\.d-z3\.d},#1'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: sqrshr z0\.b, {z0\.s-z3\.s}, #1
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: sqrshr z0\.h, {z0\.d-z3\.d}, #1
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqrshr z0\.b,{z0\.d-z3\.d},#65'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: sqrshr z0\.b, {z0\.s-z3\.s}, #65
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: sqrshr z0\.h, {z0\.d-z3\.d}, #65
diff --git a/gas/testsuite/gas/aarch64/sme2-27-invalid.s b/gas/testsuite/gas/aarch64/sme2-27-invalid.s
new file mode 100644
index 00000000000..3a613af9a8d
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-27-invalid.s
@@ -0,0 +1,25 @@
+ .equ x0, 1
+ .equ z0.s, 2
+ .equ p0, 3
+ .equ pn0, 4
+
+ sqrshr 0, { z0.s - z1.s }, #1
+ sqrshr z0.h, 0, #1
+
+ sqrshr z0.h, { z1.s - z2.s }, #1
+ sqrshr z0.h, { z0.s - z1.s }, #0
+ sqrshr z0.h, { z0.s - z1.s }, #17
+ sqrshr z0.s, { z0.d - z1.d }, #1
+ sqrshr z0.h, { z0.s - z1.s }, x0
+ sqrshr z0.h, { z0.s - z1.s }, z0.s
+ sqrshr z0.h, { z0.s - z1.s }, p0
+ sqrshr z0.h, { z0.s - z1.s }, pn0
+
+ sqrshr z0.b, { z1.s - z4.s }, #1
+ sqrshr z0.b, { z2.s - z5.s }, #1
+ sqrshr z0.b, { z3.s - z6.s }, #1
+ sqrshr z0.b, { z0.s - z3.s }, #-1
+ sqrshr z0.b, { z0.s - z3.s }, #0
+ sqrshr z0.b, { z0.s - z3.s }, #33
+ sqrshr z0.b, { z0.d - z3.d }, #1
+ sqrshr z0.b, { z0.d - z3.d }, #65 // Double error
diff --git a/gas/testsuite/gas/aarch64/sme2-27-noarch.d b/gas/testsuite/gas/aarch64/sme2-27-noarch.d
new file mode 100644
index 00000000000..f0e735db033
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-27-noarch.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a+sme
+#source: sme2-27.s
+#error_output: sme2-27-noarch.l
diff --git a/gas/testsuite/gas/aarch64/sme2-27-noarch.l b/gas/testsuite/gas/aarch64/sme2-27-noarch.l
new file mode 100644
index 00000000000..72213e0c281
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-27-noarch.l
@@ -0,0 +1,50 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z0\.h,{z0\.s-z1\.s},#1'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z31\.h,{z0\.s-z1\.s},#1'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z0\.h,{z30\.s-z31\.s},#1'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z0\.h,{z0\.s-z1\.s},#16'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z14\.h,{z22\.s-z23\.s},#7'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z0\.h,{z0\.s-z1\.s},#x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z0\.h,{z0\.s-z1\.s},#z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z0\.h,{z0\.s-z1\.s},#p0'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z0\.h,{z0\.s-z1\.s},#pn0'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z0\.b,{z0\.s-z3\.s},#1'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z31\.b,{z0\.s-z3\.s},#1'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z0\.b,{z28\.s-z31\.s},#1'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z0\.b,{z0\.s-z3\.s},#32'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z6\.b,{z12\.s-z15\.s},#25'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z0\.h,{z0\.d-z3\.d},#1'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z31\.h,{z0\.d-z3\.d},#1'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z0\.h,{z28\.d-z31\.d},#1'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z0\.h,{z0\.d-z3\.d},#64'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z25\.h,{z20\.d-z23\.d},#50'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshru z0\.h,{z0\.s-z1\.s},#1'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshru z31\.h,{z0\.s-z1\.s},#1'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshru z0\.h,{z30\.s-z31\.s},#1'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshru z0\.h,{z0\.s-z1\.s},#16'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshru z14\.h,{z22\.s-z23\.s},#7'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshru z0\.b,{z0\.s-z3\.s},#1'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshru z31\.b,{z0\.s-z3\.s},#1'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshru z0\.b,{z28\.s-z31\.s},#1'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshru z0\.b,{z0\.s-z3\.s},#32'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshru z6\.b,{z12\.s-z15\.s},#25'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshru z0\.h,{z0\.d-z3\.d},#1'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshru z31\.h,{z0\.d-z3\.d},#1'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshru z0\.h,{z28\.d-z31\.d},#1'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshru z0\.h,{z0\.d-z3\.d},#64'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshru z25\.h,{z20\.d-z23\.d},#50'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqrshr z0\.h,{z0\.s-z1\.s},#1'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqrshr z31\.h,{z0\.s-z1\.s},#1'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqrshr z0\.h,{z30\.s-z31\.s},#1'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqrshr z0\.h,{z0\.s-z1\.s},#16'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqrshr z14\.h,{z22\.s-z23\.s},#7'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqrshr z0\.b,{z0\.s-z3\.s},#1'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqrshr z31\.b,{z0\.s-z3\.s},#1'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqrshr z0\.b,{z28\.s-z31\.s},#1'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqrshr z0\.b,{z0\.s-z3\.s},#32'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqrshr z6\.b,{z12\.s-z15\.s},#25'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqrshr z0\.h,{z0\.d-z3\.d},#1'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqrshr z31\.h,{z0\.d-z3\.d},#1'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqrshr z0\.h,{z28\.d-z31\.d},#1'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqrshr z0\.h,{z0\.d-z3\.d},#64'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqrshr z25\.h,{z20\.d-z23\.d},#50'
diff --git a/gas/testsuite/gas/aarch64/sme2-27.d b/gas/testsuite/gas/aarch64/sme2-27.d
new file mode 100644
index 00000000000..e217715489e
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-27.d
@@ -0,0 +1,62 @@
+#as: -march=armv8-a+sme2
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+[^:]+: c1efd400 sqrshr z0\.h, {z0\.s-z1\.s}, #1
+[^:]+: c1efd41f sqrshr z31\.h, {z0\.s-z1\.s}, #1
+[^:]+: c1efd7c0 sqrshr z0\.h, {z30\.s-z31\.s}, #1
+[^:]+: c1e0d400 sqrshr z0\.h, {z0\.s-z1\.s}, #16
+[^:]+: c1e9d6ce sqrshr z14\.h, {z22\.s-z23\.s}, #7
+[^:]+: c1efd400 sqrshr z0\.h, {z0\.s-z1\.s}, #1
+[^:]+: c1eed400 sqrshr z0\.h, {z0\.s-z1\.s}, #2
+[^:]+: c1edd400 sqrshr z0\.h, {z0\.s-z1\.s}, #3
+[^:]+: c1ecd400 sqrshr z0\.h, {z0\.s-z1\.s}, #4
+[^:]+: c17fd800 sqrshr z0\.b, {z0\.s-z3\.s}, #1
+[^:]+: c17fd81f sqrshr z31\.b, {z0\.s-z3\.s}, #1
+[^:]+: c17fdb80 sqrshr z0\.b, {z28\.s-z31\.s}, #1
+[^:]+: c160d800 sqrshr z0\.b, {z0\.s-z3\.s}, #32
+[^:]+: c167d986 sqrshr z6\.b, {z12\.s-z15\.s}, #25
+[^:]+: c1ffd800 sqrshr z0\.h, {z0\.d-z3\.d}, #1
+[^:]+: c1ffd81f sqrshr z31\.h, {z0\.d-z3\.d}, #1
+[^:]+: c1ffdb80 sqrshr z0\.h, {z28\.d-z31\.d}, #1
+[^:]+: c1a0d800 sqrshr z0\.h, {z0\.d-z3\.d}, #64
+[^:]+: c1aeda99 sqrshr z25\.h, {z20\.d-z23\.d}, #50
+[^:]+: c13fd800 \.inst 0xc13fd800 ; undefined
+[^:]+: c120d800 \.inst 0xc120d800 ; undefined
+[^:]+: c1ffd400 sqrshru z0\.h, {z0\.s-z1\.s}, #1
+[^:]+: c1ffd41f sqrshru z31\.h, {z0\.s-z1\.s}, #1
+[^:]+: c1ffd7c0 sqrshru z0\.h, {z30\.s-z31\.s}, #1
+[^:]+: c1f0d400 sqrshru z0\.h, {z0\.s-z1\.s}, #16
+[^:]+: c1f9d6ce sqrshru z14\.h, {z22\.s-z23\.s}, #7
+[^:]+: c17fd840 sqrshru z0\.b, {z0\.s-z3\.s}, #1
+[^:]+: c17fd85f sqrshru z31\.b, {z0\.s-z3\.s}, #1
+[^:]+: c17fdbc0 sqrshru z0\.b, {z28\.s-z31\.s}, #1
+[^:]+: c160d840 sqrshru z0\.b, {z0\.s-z3\.s}, #32
+[^:]+: c167d9c6 sqrshru z6\.b, {z12\.s-z15\.s}, #25
+[^:]+: c1ffd840 sqrshru z0\.h, {z0\.d-z3\.d}, #1
+[^:]+: c1ffd85f sqrshru z31\.h, {z0\.d-z3\.d}, #1
+[^:]+: c1ffdbc0 sqrshru z0\.h, {z28\.d-z31\.d}, #1
+[^:]+: c1a0d840 sqrshru z0\.h, {z0\.d-z3\.d}, #64
+[^:]+: c1aedad9 sqrshru z25\.h, {z20\.d-z23\.d}, #50
+[^:]+: c1efd420 uqrshr z0\.h, {z0\.s-z1\.s}, #1
+[^:]+: c1efd43f uqrshr z31\.h, {z0\.s-z1\.s}, #1
+[^:]+: c1efd7e0 uqrshr z0\.h, {z30\.s-z31\.s}, #1
+[^:]+: c1e0d420 uqrshr z0\.h, {z0\.s-z1\.s}, #16
+[^:]+: c1e9d6ee uqrshr z14\.h, {z22\.s-z23\.s}, #7
+[^:]+: c17fd820 uqrshr z0\.b, {z0\.s-z3\.s}, #1
+[^:]+: c17fd83f uqrshr z31\.b, {z0\.s-z3\.s}, #1
+[^:]+: c17fdba0 uqrshr z0\.b, {z28\.s-z31\.s}, #1
+[^:]+: c160d820 uqrshr z0\.b, {z0\.s-z3\.s}, #32
+[^:]+: c167d9a6 uqrshr z6\.b, {z12\.s-z15\.s}, #25
+[^:]+: c1ffd820 uqrshr z0\.h, {z0\.d-z3\.d}, #1
+[^:]+: c1ffd83f uqrshr z31\.h, {z0\.d-z3\.d}, #1
+[^:]+: c1ffdba0 uqrshr z0\.h, {z28\.d-z31\.d}, #1
+[^:]+: c1a0d820 uqrshr z0\.h, {z0\.d-z3\.d}, #64
+[^:]+: c1aedab9 uqrshr z25\.h, {z20\.d-z23\.d}, #50
+[^:]+: c13fd820 \.inst 0xc13fd820 ; undefined
+[^:]+: c120d820 \.inst 0xc120d820 ; undefined
diff --git a/gas/testsuite/gas/aarch64/sme2-27.s b/gas/testsuite/gas/aarch64/sme2-27.s
new file mode 100644
index 00000000000..e7e04ba68c9
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-27.s
@@ -0,0 +1,71 @@
+ .equ x0, 1
+ .equ z0.s, 2
+ .equ p0, 3
+ .equ pn0, 4
+
+ sqrshr z0.h, { z0.s - z1.s }, #1
+ sqrshr z31.h, { z0.s - z1.s }, #1
+ sqrshr z0.h, { z30.s - z31.s }, #1
+ sqrshr z0.h, { z0.s - z1.s }, #16
+ sqrshr z14.h, { z22.s - z23.s }, #7
+
+ sqrshr z0.h, { z0.s - z1.s }, #x0
+ sqrshr z0.h, { z0.s - z1.s }, #z0.s
+ sqrshr z0.h, { z0.s - z1.s }, #p0
+ sqrshr z0.h, { z0.s - z1.s }, #pn0
+
+ sqrshr z0.b, { z0.s - z3.s }, #1
+ sqrshr z31.b, { z0.s - z3.s }, #1
+ sqrshr z0.b, { z28.s - z31.s }, #1
+ sqrshr z0.b, { z0.s - z3.s }, #32
+ sqrshr z6.b, { z12.s - z15.s }, #25
+
+ sqrshr z0.h, { z0.d - z3.d }, #1
+ sqrshr z31.h, { z0.d - z3.d }, #1
+ sqrshr z0.h, { z28.d - z31.d }, #1
+ sqrshr z0.h, { z0.d - z3.d }, #64
+ sqrshr z25.h, { z20.d - z23.d }, #50
+
+ // Invalid SQRSHR
+ .inst 0xc13fd800
+ .inst 0xc120d800
+
+ sqrshru z0.h, { z0.s - z1.s }, #1
+ sqrshru z31.h, { z0.s - z1.s }, #1
+ sqrshru z0.h, { z30.s - z31.s }, #1
+ sqrshru z0.h, { z0.s - z1.s }, #16
+ sqrshru z14.h, { z22.s - z23.s }, #7
+
+ sqrshru z0.b, { z0.s - z3.s }, #1
+ sqrshru z31.b, { z0.s - z3.s }, #1
+ sqrshru z0.b, { z28.s - z31.s }, #1
+ sqrshru z0.b, { z0.s - z3.s }, #32
+ sqrshru z6.b, { z12.s - z15.s }, #25
+
+ sqrshru z0.h, { z0.d - z3.d }, #1
+ sqrshru z31.h, { z0.d - z3.d }, #1
+ sqrshru z0.h, { z28.d - z31.d }, #1
+ sqrshru z0.h, { z0.d - z3.d }, #64
+ sqrshru z25.h, { z20.d - z23.d }, #50
+
+ uqrshr z0.h, { z0.s - z1.s }, #1
+ uqrshr z31.h, { z0.s - z1.s }, #1
+ uqrshr z0.h, { z30.s - z31.s }, #1
+ uqrshr z0.h, { z0.s - z1.s }, #16
+ uqrshr z14.h, { z22.s - z23.s }, #7
+
+ uqrshr z0.b, { z0.s - z3.s }, #1
+ uqrshr z31.b, { z0.s - z3.s }, #1
+ uqrshr z0.b, { z28.s - z31.s }, #1
+ uqrshr z0.b, { z0.s - z3.s }, #32
+ uqrshr z6.b, { z12.s - z15.s }, #25
+
+ uqrshr z0.h, { z0.d - z3.d }, #1
+ uqrshr z31.h, { z0.d - z3.d }, #1
+ uqrshr z0.h, { z28.d - z31.d }, #1
+ uqrshr z0.h, { z0.d - z3.d }, #64
+ uqrshr z25.h, { z20.d - z23.d }, #50
+
+ // Invalid UQRSHR
+ .inst 0xc13fd820
+ .inst 0xc120d820
diff --git a/gas/testsuite/gas/aarch64/sme2-28-invalid.d b/gas/testsuite/gas/aarch64/sme2-28-invalid.d
new file mode 100644
index 00000000000..dbe03ce0a7c
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-28-invalid.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a
+#source: sme2-28-invalid.s
+#error_output: sme2-28-invalid.l
diff --git a/gas/testsuite/gas/aarch64/sme2-28-invalid.l b/gas/testsuite/gas/aarch64/sme2-28-invalid.l
new file mode 100644
index 00000000000..615f8c35039
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-28-invalid.l
@@ -0,0 +1,19 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqrshrn 0,{z0\.s-z3\.s},#1'
+[^ :]+:[0-9]+: Error: expected '{' at operand 2 -- `sqrshrn z0\.b,0,#1'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqrshrn z0\.b,{z1\.s-z4\.s},#1'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqrshrn z0\.b,{z2\.s-z5\.s},#1'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqrshrn z0\.b,{z3\.s-z6\.s},#1'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshrn z0\.b,{z0\.s-z3\.s},#-1'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshrn z0\.b,{z0\.s-z3\.s},#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshrn z0\.b,{z0\.s-z3\.s},#33'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqrshrn z0\.b,{z0\.d-z3\.d},#1'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: sqrshrn z0\.b, {z0\.s-z3\.s}, #1
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: sqrshrn z0\.h, {z0\.d-z3\.d}, #1
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqrshrn z0\.b,{z0\.d-z3\.d},#65'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: sqrshrn z0\.b, {z0\.s-z3\.s}, #65
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: sqrshrn z0\.h, {z0\.d-z3\.d}, #65
diff --git a/gas/testsuite/gas/aarch64/sme2-28-invalid.s b/gas/testsuite/gas/aarch64/sme2-28-invalid.s
new file mode 100644
index 00000000000..f587049967e
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-28-invalid.s
@@ -0,0 +1,11 @@
+ sqrshrn 0, { z0.s - z3.s }, #1
+ sqrshrn z0.b, 0, #1
+
+ sqrshrn z0.b, { z1.s - z4.s }, #1
+ sqrshrn z0.b, { z2.s - z5.s }, #1
+ sqrshrn z0.b, { z3.s - z6.s }, #1
+ sqrshrn z0.b, { z0.s - z3.s }, #-1
+ sqrshrn z0.b, { z0.s - z3.s }, #0
+ sqrshrn z0.b, { z0.s - z3.s }, #33
+ sqrshrn z0.b, { z0.d - z3.d }, #1
+ sqrshrn z0.b, { z0.d - z3.d }, #65 // Double error
diff --git a/gas/testsuite/gas/aarch64/sme2-28-noarch.d b/gas/testsuite/gas/aarch64/sme2-28-noarch.d
new file mode 100644
index 00000000000..de378eb1998
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-28-noarch.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a+sme
+#source: sme2-28.s
+#error_output: sme2-28-noarch.l
diff --git a/gas/testsuite/gas/aarch64/sme2-28-noarch.l b/gas/testsuite/gas/aarch64/sme2-28-noarch.l
new file mode 100644
index 00000000000..a3762f1b9a9
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-28-noarch.l
@@ -0,0 +1,26 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrn z0\.b,{z0\.s-z3\.s},#1'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrn z31\.b,{z0\.s-z3\.s},#1'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrn z0\.b,{z28\.s-z31\.s},#1'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrn z0\.b,{z0\.s-z3\.s},#32'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrn z6\.b,{z12\.s-z15\.s},#25'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrn z0\.h,{z0\.d-z3\.d},#1'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrn z31\.h,{z0\.d-z3\.d},#1'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrn z0\.h,{z28\.d-z31\.d},#1'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrn z0\.h,{z0\.d-z3\.d},#64'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrn z25\.h,{z20\.d-z23\.d},#50'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrun z0\.b,{z0\.s-z3\.s},#1'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrun z31\.b,{z0\.s-z3\.s},#1'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrun z0\.b,{z28\.s-z31\.s},#1'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrun z0\.b,{z0\.s-z3\.s},#32'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrun z6\.b,{z12\.s-z15\.s},#25'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqrshrn z0\.b,{z0\.s-z3\.s},#1'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqrshrn z31\.b,{z0\.s-z3\.s},#1'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqrshrn z0\.b,{z28\.s-z31\.s},#1'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqrshrn z0\.b,{z0\.s-z3\.s},#32'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqrshrn z6\.b,{z12\.s-z15\.s},#25'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqrshrn z0\.h,{z0\.d-z3\.d},#1'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqrshrn z31\.h,{z0\.d-z3\.d},#1'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqrshrn z0\.h,{z28\.d-z31\.d},#1'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqrshrn z0\.h,{z0\.d-z3\.d},#64'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqrshrn z25\.h,{z20\.d-z23\.d},#50'
diff --git a/gas/testsuite/gas/aarch64/sme2-28.d b/gas/testsuite/gas/aarch64/sme2-28.d
new file mode 100644
index 00000000000..b72273dd548
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-28.d
@@ -0,0 +1,34 @@
+#as: -march=armv8-a+sme2
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+[^:]+: c17fdc00 sqrshrn z0\.b, {z0\.s-z3\.s}, #1
+[^:]+: c17fdc1f sqrshrn z31\.b, {z0\.s-z3\.s}, #1
+[^:]+: c17fdf80 sqrshrn z0\.b, {z28\.s-z31\.s}, #1
+[^:]+: c160dc00 sqrshrn z0\.b, {z0\.s-z3\.s}, #32
+[^:]+: c167dd86 sqrshrn z6\.b, {z12\.s-z15\.s}, #25
+[^:]+: c1ffdc00 sqrshrn z0\.h, {z0\.d-z3\.d}, #1
+[^:]+: c1ffdc1f sqrshrn z31\.h, {z0\.d-z3\.d}, #1
+[^:]+: c1ffdf80 sqrshrn z0\.h, {z28\.d-z31\.d}, #1
+[^:]+: c1a0dc00 sqrshrn z0\.h, {z0\.d-z3\.d}, #64
+[^:]+: c1aede99 sqrshrn z25\.h, {z20\.d-z23\.d}, #50
+[^:]+: c17fdc40 sqrshrun z0\.b, {z0\.s-z3\.s}, #1
+[^:]+: c17fdc5f sqrshrun z31\.b, {z0\.s-z3\.s}, #1
+[^:]+: c17fdfc0 sqrshrun z0\.b, {z28\.s-z31\.s}, #1
+[^:]+: c160dc40 sqrshrun z0\.b, {z0\.s-z3\.s}, #32
+[^:]+: c167ddc6 sqrshrun z6\.b, {z12\.s-z15\.s}, #25
+[^:]+: c17fdc20 uqrshrn z0\.b, {z0\.s-z3\.s}, #1
+[^:]+: c17fdc3f uqrshrn z31\.b, {z0\.s-z3\.s}, #1
+[^:]+: c17fdfa0 uqrshrn z0\.b, {z28\.s-z31\.s}, #1
+[^:]+: c160dc20 uqrshrn z0\.b, {z0\.s-z3\.s}, #32
+[^:]+: c167dda6 uqrshrn z6\.b, {z12\.s-z15\.s}, #25
+[^:]+: c1ffdc20 uqrshrn z0\.h, {z0\.d-z3\.d}, #1
+[^:]+: c1ffdc3f uqrshrn z31\.h, {z0\.d-z3\.d}, #1
+[^:]+: c1ffdfa0 uqrshrn z0\.h, {z28\.d-z31\.d}, #1
+[^:]+: c1a0dc20 uqrshrn z0\.h, {z0\.d-z3\.d}, #64
+[^:]+: c1aedeb9 uqrshrn z25\.h, {z20\.d-z23\.d}, #50
diff --git a/gas/testsuite/gas/aarch64/sme2-28.s b/gas/testsuite/gas/aarch64/sme2-28.s
new file mode 100644
index 00000000000..3b51448288e
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-28.s
@@ -0,0 +1,29 @@
+ sqrshrn z0.b, { z0.s - z3.s }, #1
+ sqrshrn z31.b, { z0.s - z3.s }, #1
+ sqrshrn z0.b, { z28.s - z31.s }, #1
+ sqrshrn z0.b, { z0.s - z3.s }, #32
+ sqrshrn z6.b, { z12.s - z15.s }, #25
+
+ sqrshrn z0.h, { z0.d - z3.d }, #1
+ sqrshrn z31.h, { z0.d - z3.d }, #1
+ sqrshrn z0.h, { z28.d - z31.d }, #1
+ sqrshrn z0.h, { z0.d - z3.d }, #64
+ sqrshrn z25.h, { z20.d - z23.d }, #50
+
+ sqrshrun z0.b, { z0.s - z3.s }, #1
+ sqrshrun z31.b, { z0.s - z3.s }, #1
+ sqrshrun z0.b, { z28.s - z31.s }, #1
+ sqrshrun z0.b, { z0.s - z3.s }, #32
+ sqrshrun z6.b, { z12.s - z15.s }, #25
+
+ uqrshrn z0.b, { z0.s - z3.s }, #1
+ uqrshrn z31.b, { z0.s - z3.s }, #1
+ uqrshrn z0.b, { z28.s - z31.s }, #1
+ uqrshrn z0.b, { z0.s - z3.s }, #32
+ uqrshrn z6.b, { z12.s - z15.s }, #25
+
+ uqrshrn z0.h, { z0.d - z3.d }, #1
+ uqrshrn z31.h, { z0.d - z3.d }, #1
+ uqrshrn z0.h, { z28.d - z31.d }, #1
+ uqrshrn z0.h, { z0.d - z3.d }, #64
+ uqrshrn z25.h, { z20.d - z23.d }, #50
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index b445bf758fc..a4f1623d4ca 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -520,6 +520,8 @@ enum aarch64_opnd
AARCH64_OPND_SME_ADDR_RI_U4xVL, /* SME [<Xn|SP>{, #<imm>, MUL VL}]. */
AARCH64_OPND_SME_SM_ZA, /* SME {SM | ZA}. */
AARCH64_OPND_SME_PnT_Wm_imm, /* SME <Pn>.<T>[<Wm>, #<imm>]. */
+ AARCH64_OPND_SME_SHRIMM4, /* 4-bit right shift, bits [19:16]. */
+ AARCH64_OPND_SME_SHRIMM5, /* size + 5-bit right shift, bits [23:22,20:16]. */
AARCH64_OPND_SME_Zm_INDEX1, /* Zn.T[index], bits [19:16,10]. */
AARCH64_OPND_SME_Zm_INDEX2, /* Zn.T[index], bits [19:16,11:10]. */
AARCH64_OPND_SME_Zm_INDEX3_1, /* Zn.T[index], bits [19:16,10,2:1]. */
@@ -713,6 +715,7 @@ enum aarch64_insn_class
sme_mov,
sme_ldr,
sme_psel,
+ sme_shift,
sme_size_12_bhs,
sme_size_12_hs,
sme_size_22,
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index 3d439d4e688..03d1c0e1221 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -685,7 +685,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 33:
case 34:
case 35:
- case 268:
+ case 270:
return aarch64_ins_reglane (self, info, code, inst, errors);
case 36:
return aarch64_ins_reglist (self, info, code, inst, errors);
@@ -731,12 +731,12 @@ aarch64_insert_operand (const aarch64_operand *self,
case 193:
case 194:
case 237:
- case 262:
- case 263:
+ case 264:
case 265:
case 267:
- case 272:
- case 273:
+ case 269:
+ case 274:
+ case 275:
return aarch64_ins_imm (self, info, code, inst, errors);
case 44:
case 45:
@@ -805,8 +805,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 107:
return aarch64_ins_prfop (self, info, code, inst, errors);
case 108:
- case 264:
case 266:
+ case 268:
return aarch64_ins_none (self, info, code, inst, errors);
case 109:
return aarch64_ins_hint (self, info, code, inst, errors);
@@ -886,6 +886,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 184:
case 185:
case 186:
+ case 250:
return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
case 204:
case 205:
@@ -919,8 +920,6 @@ aarch64_insert_operand (const aarch64_operand *self,
return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors);
case 235:
case 236:
- case 249:
- case 250:
case 251:
case 252:
case 253:
@@ -932,6 +931,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 259:
case 260:
case 261:
+ case 262:
+ case 263:
return aarch64_ins_simple_index (self, info, code, inst, errors);
case 239:
case 240:
@@ -947,9 +948,11 @@ aarch64_insert_operand (const aarch64_operand *self,
return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
case 248:
return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
- case 269:
- case 270:
+ case 249:
+ return aarch64_ins_plain_shrimm (self, info, code, inst, errors);
case 271:
+ case 272:
+ case 273:
return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
default: assert (0); abort ();
}
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index 5f2e51044ce..0025cb6f80c 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -1624,6 +1624,19 @@ aarch64_ins_simple_index (const aarch64_operand *self,
return true;
}
+/* Insert a plain shift-right immediate, when there is only a single
+ element size. */
+bool
+aarch64_ins_plain_shrimm (const aarch64_operand *self,
+ const aarch64_opnd_info *info, aarch64_insn *code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
+{
+ unsigned int base = 1 << get_operand_field_width (self, 0);
+ insert_field (self->fields[0], code, base - info->imm.value, 0);
+ return true;
+}
+
/* Miscellaneous encoding functions. */
/* Encode size[0], i.e. bit 22, for
@@ -1980,6 +1993,7 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
0, 2, FLD_SVE_M_14, FLD_size);
break;
+ case sme_shift:
case sve_index:
case sve_shift_pred:
case sve_shift_unpred:
diff --git a/opcodes/aarch64-asm.h b/opcodes/aarch64-asm.h
index 4cc48dfdcb6..0028e8bbaed 100644
--- a/opcodes/aarch64-asm.h
+++ b/opcodes/aarch64-asm.h
@@ -111,6 +111,7 @@ AARCH64_DECL_OPD_INSERTER (ins_imm_rotate1);
AARCH64_DECL_OPD_INSERTER (ins_imm_rotate2);
AARCH64_DECL_OPD_INSERTER (ins_x0_to_x30);
AARCH64_DECL_OPD_INSERTER (ins_simple_index);
+AARCH64_DECL_OPD_INSERTER (ins_plain_shrimm);
#undef AARCH64_DECL_OPD_INSERTER
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 55a01e6e593..d82c37498e7 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -188,7 +188,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000x10x100xxxxxxxxxxxxxxxxx
zero. */
- return 2874;
+ return 2883;
}
}
}
@@ -856,7 +856,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx000xxxxxxxxxxxx0
st1b. */
- return 2705;
+ return 2711;
}
else
{
@@ -864,7 +864,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx100xxxxxxxxxxxx0
st1b. */
- return 2706;
+ return 2712;
}
}
else
@@ -875,7 +875,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx010xxxxxxxxxxxx0
st1w. */
- return 2729;
+ return 2735;
}
else
{
@@ -883,7 +883,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx110xxxxxxxxxxxx0
st1w. */
- return 2730;
+ return 2736;
}
}
}
@@ -897,7 +897,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx001xxxxxxxxxxxx0
st1h. */
- return 2721;
+ return 2727;
}
else
{
@@ -905,7 +905,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx101xxxxxxxxxxxx0
st1h. */
- return 2722;
+ return 2728;
}
}
else
@@ -916,7 +916,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx011xxxxxxxxxxxx0
st1d. */
- return 2713;
+ return 2719;
}
else
{
@@ -924,7 +924,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx111xxxxxxxxxxxx0
st1d. */
- return 2714;
+ return 2720;
}
}
}
@@ -941,7 +941,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx000xxxxxxxxxxxx1
stnt1b. */
- return 2737;
+ return 2743;
}
else
{
@@ -949,7 +949,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx100xxxxxxxxxxxx1
stnt1b. */
- return 2738;
+ return 2744;
}
}
else
@@ -960,7 +960,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx010xxxxxxxxxxxx1
stnt1w. */
- return 2761;
+ return 2767;
}
else
{
@@ -968,7 +968,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx110xxxxxxxxxxxx1
stnt1w. */
- return 2762;
+ return 2768;
}
}
}
@@ -982,7 +982,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx001xxxxxxxxxxxx1
stnt1h. */
- return 2753;
+ return 2759;
}
else
{
@@ -990,7 +990,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx101xxxxxxxxxxxx1
stnt1h. */
- return 2754;
+ return 2760;
}
}
else
@@ -1001,7 +1001,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx011xxxxxxxxxxxx1
stnt1d. */
- return 2745;
+ return 2751;
}
else
{
@@ -1009,7 +1009,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000001xxxxx111xxxxxxxxxxxx1
stnt1d. */
- return 2746;
+ return 2752;
}
}
}
@@ -1073,7 +1073,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx000xxxxxxxxxxxx0
st1b. */
- return 2701;
+ return 2707;
}
else
{
@@ -1081,7 +1081,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx100xxxxxxxxxxxx0
st1b. */
- return 2702;
+ return 2708;
}
}
else
@@ -1092,7 +1092,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx010xxxxxxxxxxxx0
st1w. */
- return 2725;
+ return 2731;
}
else
{
@@ -1100,7 +1100,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx110xxxxxxxxxxxx0
st1w. */
- return 2726;
+ return 2732;
}
}
}
@@ -1114,7 +1114,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx001xxxxxxxxxxxx0
st1h. */
- return 2717;
+ return 2723;
}
else
{
@@ -1122,7 +1122,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx101xxxxxxxxxxxx0
st1h. */
- return 2718;
+ return 2724;
}
}
else
@@ -1133,7 +1133,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx011xxxxxxxxxxxx0
st1d. */
- return 2709;
+ return 2715;
}
else
{
@@ -1141,7 +1141,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx111xxxxxxxxxxxx0
st1d. */
- return 2710;
+ return 2716;
}
}
}
@@ -1158,7 +1158,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx000xxxxxxxxxxxx1
stnt1b. */
- return 2733;
+ return 2739;
}
else
{
@@ -1166,7 +1166,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx100xxxxxxxxxxxx1
stnt1b. */
- return 2734;
+ return 2740;
}
}
else
@@ -1177,7 +1177,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx010xxxxxxxxxxxx1
stnt1w. */
- return 2757;
+ return 2763;
}
else
{
@@ -1185,7 +1185,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx110xxxxxxxxxxxx1
stnt1w. */
- return 2758;
+ return 2764;
}
}
}
@@ -1199,7 +1199,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx001xxxxxxxxxxxx1
stnt1h. */
- return 2749;
+ return 2755;
}
else
{
@@ -1207,7 +1207,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx101xxxxxxxxxxxx1
stnt1h. */
- return 2750;
+ return 2756;
}
}
else
@@ -1218,7 +1218,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx011xxxxxxxxxxxx1
stnt1d. */
- return 2741;
+ return 2747;
}
else
{
@@ -1226,7 +1226,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x00000011xxxxx111xxxxxxxxxxxx1
stnt1d. */
- return 2742;
+ return 2748;
}
}
}
@@ -1326,7 +1326,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010000xxxxxxxxxxxxxxx001xx
usmlall. */
- return 2855;
+ return 2864;
}
}
else
@@ -1358,7 +1358,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx0xxxxxxxxx100xxx
usmlall. */
- return 2856;
+ return 2865;
}
else
{
@@ -1366,7 +1366,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx1xxxxxxxxx100xxx
usmlall. */
- return 2857;
+ return 2866;
}
}
}
@@ -1381,7 +1381,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010000xxxxxxxxxxxxxxx100xx
umlall. */
- return 2816;
+ return 2822;
}
else
{
@@ -1389,7 +1389,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010000xxxxxxxxxxxxxxx101xx
sumlall. */
- return 2776;
+ return 2782;
}
}
else
@@ -1402,7 +1402,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx0xxxxxxxxx010xxx
umlall. */
- return 2817;
+ return 2823;
}
else
{
@@ -1410,7 +1410,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx1xxxxxxxxx010xxx
umlall. */
- return 2818;
+ return 2824;
}
}
else
@@ -1421,7 +1421,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx0xxxxxxxxx110xxx
sumlall. */
- return 2777;
+ return 2783;
}
else
{
@@ -1429,7 +1429,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx1xxxxxxxxx110xxx
sumlall. */
- return 2778;
+ return 2784;
}
}
}
@@ -1475,7 +1475,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010000xxxxxxxxxxxxxxx11xxx
umlsll. */
- return 2832;
+ return 2838;
}
else
{
@@ -1485,7 +1485,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx0xxxxxxxxxx11xxx
umlsll. */
- return 2833;
+ return 2839;
}
else
{
@@ -1493,7 +1493,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx1xxxxxxxxxx11xxx
umlsll. */
- return 2834;
+ return 2840;
}
}
}
@@ -1721,7 +1721,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011000xxxxxxx0xxxxxxx00xxx
smlall. */
- return 2877;
+ return 2886;
}
else
{
@@ -1731,7 +1731,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxx0xx0xxxxxxx00xxx
smlall. */
- return 2878;
+ return 2887;
}
else
{
@@ -1739,7 +1739,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxx1xx0xxxxxxx00xxx
smlall. */
- return 2879;
+ return 2888;
}
}
}
@@ -1806,7 +1806,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011000xxxxxxx0xxxxxxx10xxx
umlall. */
- return 2886;
+ return 2895;
}
else
{
@@ -1816,7 +1816,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxx0xx0xxxxxxx10xxx
umlall. */
- return 2887;
+ return 2896;
}
else
{
@@ -1824,7 +1824,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxx1xx0xxxxxxx10xxx
umlall. */
- return 2888;
+ return 2897;
}
}
}
@@ -1884,7 +1884,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011000xxxxxxx0xxxxxxx01xxx
smlsll. */
- return 2880;
+ return 2889;
}
else
{
@@ -1894,7 +1894,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011001xxxx0xx0xxxxxxx01xxx
smlsll. */
- return 2881;
+ return 2890;
}
else
{
@@ -1902,7 +1902,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011001xxxx1xx0xxxxxxx01xxx
smlsll. */
- return 2882;
+ return 2891;
}
}
}
@@ -1943,7 +1943,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx100001100xxxxxxxxxxxxxxxx01xxx
umopa. */
- return 2840;
+ return 2846;
}
}
else
@@ -1958,7 +1958,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011000xxxxxxx0xxxxxxx11xxx
umlsll. */
- return 2889;
+ return 2898;
}
else
{
@@ -1968,7 +1968,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011001xxxx0xx0xxxxxxx11xxx
umlsll. */
- return 2890;
+ return 2899;
}
else
{
@@ -1976,7 +1976,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011001xxxx1xx0xxxxxxx11xxx
umlsll. */
- return 2891;
+ return 2900;
}
}
}
@@ -2017,7 +2017,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx100001100xxxxxxxxxxxxxxxx11xxx
umops. */
- return 2841;
+ return 2847;
}
}
}
@@ -2103,7 +2103,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx0xx0xxxxxx100xxx
svdot. */
- return 2782;
+ return 2788;
}
else
{
@@ -2133,7 +2133,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx0xx1xxxxxx010xxx
udot. */
- return 2788;
+ return 2794;
}
}
else
@@ -2144,7 +2144,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx0xx0xxxxxx110xxx
uvdot. */
- return 2864;
+ return 2873;
}
else
{
@@ -2152,7 +2152,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx0xx1xxxxxx110xxx
udot. */
- return 2794;
+ return 2800;
}
}
}
@@ -2232,7 +2232,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx1xx0xxxxxx100xxx
svdot. */
- return 2783;
+ return 2789;
}
else
{
@@ -2262,7 +2262,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx1xx1xxxxxx010xxx
udot. */
- return 2789;
+ return 2795;
}
}
else
@@ -2273,7 +2273,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx1xx0xxxxxx110xxx
uvdot. */
- return 2865;
+ return 2874;
}
else
{
@@ -2281,7 +2281,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx1xx1xxxxxx110xxx
udot. */
- return 2795;
+ return 2801;
}
}
}
@@ -2362,7 +2362,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx0xxxxxxxxx101xxx
usdot. */
- return 2849;
+ return 2858;
}
}
else
@@ -2392,7 +2392,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx0xxxxxxxxx111xxx
sudot. */
- return 2772;
+ return 2778;
}
}
}
@@ -2460,7 +2460,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx1xx0xxxxxx101xxx
usvdot. */
- return 2863;
+ return 2872;
}
else
{
@@ -2468,7 +2468,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx1xx1xxxxxx101xxx
usdot. */
- return 2850;
+ return 2859;
}
}
}
@@ -2490,7 +2490,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx1xx0xxxxxx111xxx
suvdot. */
- return 2781;
+ return 2787;
}
else
{
@@ -2498,7 +2498,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx1xx1xxxxxx111xxx
sudot. */
- return 2773;
+ return 2779;
}
}
}
@@ -2522,7 +2522,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000001110xxxxx0xx0xxxxxxx00xxx
fmla. */
- return 2893;
+ return 2902;
}
else
{
@@ -2530,7 +2530,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000001110xxxxx1xx0xxxxxxx00xxx
fmla. */
- return 2894;
+ return 2903;
}
}
else
@@ -2576,7 +2576,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000001110xxxxx0xx00xxxxxx01xxx
sdot. */
- return 2875;
+ return 2884;
}
else
{
@@ -2584,7 +2584,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000001110xxxxx1xx00xxxxxx01xxx
sdot. */
- return 2876;
+ return 2885;
}
}
else
@@ -2593,7 +2593,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000001110xxxxxxxx01xxxxxx01xxx
svdot. */
- return 2883;
+ return 2892;
}
}
else
@@ -2662,7 +2662,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000001110xxxxx0xx0xxxxxxx10xxx
fmls. */
- return 2895;
+ return 2904;
}
else
{
@@ -2670,7 +2670,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000001110xxxxx1xx0xxxxxxx10xxx
fmls. */
- return 2896;
+ return 2905;
}
}
else
@@ -2681,7 +2681,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011100xxxxxxx1xxxxxxx10xxx
umlal. */
- return 2808;
+ return 2814;
}
else
{
@@ -2691,7 +2691,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxx0xx1xxxxxxx10xxx
umlal. */
- return 2809;
+ return 2815;
}
else
{
@@ -2699,7 +2699,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxx1xx1xxxxxxx10xxx
umlal. */
- return 2810;
+ return 2816;
}
}
}
@@ -2725,7 +2725,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx00001110xxxxx0xx00xxxxxx11xxx
udot. */
- return 2884;
+ return 2893;
}
else
{
@@ -2733,7 +2733,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx00001110xxxxx1xx00xxxxxx11xxx
udot. */
- return 2885;
+ return 2894;
}
}
else
@@ -2742,7 +2742,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx00001110xxxxxxxx01xxxxxx11xxx
uvdot. */
- return 2892;
+ return 2901;
}
}
else
@@ -2753,7 +2753,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000011100xxxxxxx1xxxxxxx11xxx
umlsl. */
- return 2824;
+ return 2830;
}
else
{
@@ -2763,7 +2763,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000011101xxxx0xx1xxxxxxx11xxx
umlsl. */
- return 2825;
+ return 2831;
}
else
{
@@ -2771,7 +2771,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000011101xxxx1xx1xxxxxxx11xxx
umlsl. */
- return 2826;
+ return 2832;
}
}
}
@@ -2868,7 +2868,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010x10xxxx0xx000xxxxx001xx
usmlall. */
- return 2859;
+ return 2868;
}
else
{
@@ -2876,7 +2876,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010x11xxxx0xx000xxxxx001xx
usmlall. */
- return 2860;
+ return 2869;
}
}
else
@@ -2887,7 +2887,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx000xxxxx001xx
usmlall. */
- return 2861;
+ return 2870;
}
else
{
@@ -2895,7 +2895,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx000xxxxx001xx
usmlall. */
- return 2862;
+ return 2871;
}
}
}
@@ -3092,7 +3092,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx0xx001xxxxx001xx
usmlall. */
- return 2858;
+ return 2867;
}
}
else
@@ -3198,7 +3198,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010x10xxxx0xx000xxxxx100xx
umlall. */
- return 2820;
+ return 2826;
}
else
{
@@ -3206,7 +3206,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010x11xxxx0xx000xxxxx100xx
umlall. */
- return 2821;
+ return 2827;
}
}
else
@@ -3217,7 +3217,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx000xxxxx100xx
umlall. */
- return 2822;
+ return 2828;
}
else
{
@@ -3225,7 +3225,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx000xxxxx100xx
umlall. */
- return 2823;
+ return 2829;
}
}
}
@@ -3237,7 +3237,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx000xxxxx101xx
sumlall. */
- return 2779;
+ return 2785;
}
else
{
@@ -3245,7 +3245,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx000xxxxx101xx
sumlall. */
- return 2780;
+ return 2786;
}
}
}
@@ -3346,7 +3346,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010110xxxx0xx010xxxxx10xxx
umlal. */
- return 2812;
+ return 2818;
}
else
{
@@ -3354,7 +3354,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010111xxxx0xx010xxxxx10xxx
umlal. */
- return 2813;
+ return 2819;
}
}
else
@@ -3365,7 +3365,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001111xxxx00xx010xxxxx10xxx
umlal. */
- return 2814;
+ return 2820;
}
else
{
@@ -3373,7 +3373,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001111xxxx10xx010xxxxx10xxx
umlal. */
- return 2815;
+ return 2821;
}
}
}
@@ -3431,7 +3431,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx0xx001xxxxx10xxx
umlall. */
- return 2819;
+ return 2825;
}
else
{
@@ -3443,7 +3443,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010x10xxxx0xx101xxxxx10xxx
udot. */
- return 2796;
+ return 2802;
}
else
{
@@ -3451,7 +3451,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010x11xxxx0xx101xxxxx10xxx
udot. */
- return 2797;
+ return 2803;
}
}
else
@@ -3462,7 +3462,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx101xxxxx10xxx
udot. */
- return 2798;
+ return 2804;
}
else
{
@@ -3470,7 +3470,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx101xxxxx10xxx
[...]
[diff truncated at 100000 bytes]
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