[binutils-gdb] RISC-V: test for expected / no unexpected symbols

[binutils-gdb] RISC-V: test for expected / no unexpected symbols

[Jan Beulich]

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=42dabba6578e4b19037512d052fdc711c1349d6f

commit 42dabba6578e4b19037512d052fdc711c1349d6f
Author: Jan Beulich <jbeulich@suse.com>
Date:   Tue Apr 25 11:18:49 2023 +0200

    RISC-V: test for expected / no unexpected symbols
    
    Both the temporary workaround for PR/gas 29940 and the existing special
    casing of GPRs in my_getSmallExpression() aren't really tested anywhere
    (i.e. with the workarounds remove testing would still succeed). Nor is
    there any test for uses of symbols with names matching GPRs, where such
    is permitted. Before altering how this is to be dealt with, install two
    testcases covering the expected behavior. (For now this includes only
    known affected insns; re-ordering of entries in riscv_opcodes[] could,
    however, yield more of them.)

Diff:
---
 gas/testsuite/gas/riscv/reg-syms-C.d |  4 ++++
 gas/testsuite/gas/riscv/reg-syms.d   |  8 ++++++++
 gas/testsuite/gas/riscv/reg-syms.s   | 10 ++++++++++
 3 files changed, 22 insertions(+)

diff --git a/gas/testsuite/gas/riscv/reg-syms-C.d b/gas/testsuite/gas/riscv/reg-syms-C.d
new file mode 100644
index 00000000000..3cc8400ced9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/reg-syms-C.d
@@ -0,0 +1,4 @@
+#as: -march=rv32ic
+#source: reg-syms.s
+#nm: --
+#dump: reg-syms.d
diff --git a/gas/testsuite/gas/riscv/reg-syms.d b/gas/testsuite/gas/riscv/reg-syms.d
new file mode 100644
index 00000000000..c7f8ad88521
--- /dev/null
+++ b/gas/testsuite/gas/riscv/reg-syms.d
@@ -0,0 +1,8 @@
+#as: -march=rv32i
+#nm: --
+
+0+ t start
+ +U x2
+ +U x4
+ +U x6
+ +U x8
diff --git a/gas/testsuite/gas/riscv/reg-syms.s b/gas/testsuite/gas/riscv/reg-syms.s
new file mode 100644
index 00000000000..4748fbf49ec
--- /dev/null
+++ b/gas/testsuite/gas/riscv/reg-syms.s
@@ -0,0 +1,10 @@
+	.text
+start:
+	and	x8, x8, x1
+	j	x2
+	jal	x3, x4
+	lui	x5, %hi(x6)
+	lw	x7, %lo(x8)(x9)
+	sll	x1, x1, x10
+	sra	x8, x8, x11
+	srl	x8, x8, x12