* [binutils-gdb] LoongArch: ld: Add support for linker relaxation.
@ 2023-05-30 12:04 liu & zhensong
0 siblings, 0 replies; only message in thread
From: liu & zhensong @ 2023-05-30 12:04 UTC (permalink / raw)
To: bfd-cvs
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=2bd766d6245bf9db77c42da3537c949ffb814bfc
commit 2bd766d6245bf9db77c42da3537c949ffb814bfc
Author: mengqinggang <mengqinggang@loongson.cn>
Date: Thu Dec 1 17:17:09 2022 +0800
LoongArch: ld: Add support for linker relaxation.
Add ld relax support and testsuits.
ld/ChangeLog:
* emultempl/loongarchelf.em: Regenerated.
* testsuite/ld-elf/compressed1d.d: Xfail loongarch*-*.
* testsuite/ld-elf/pr26936.d: Likewise.
* testsuite/ld-loongarch-elf/disas-jirl.d: Regenerated.
* testsuite/ld-loongarch-elf/disas-jirl-32.d: Regenerated.
* testsuite/ld-loongarch-elf/jmp_op.d: Likewise.
* testsuite/ld-loongarch-elf/macro_op.d: Likewise.
* testsuite/ld-loongarch-elf/macro_op_32.d: Likewise.
* testsuite/ld-loongarch-elf/relax-align.dd: New test.
* testsuite/ld-loongarch-elf/relax-align.s: New test.
* testsuite/ld-loongarch-elf/relax.exp: New test.
* testsuite/ld-loongarch-elf/relax.s: New test.
* testsuite/ld-loongarch-elf/uleb128.dd: New test.
* testsuite/ld-loongarch-elf/uleb128.s: New test.
Diff:
---
ld/emultempl/loongarchelf.em | 3 +
ld/testsuite/ld-elf/compressed1d.d | 3 +
ld/testsuite/ld-elf/pr26936.d | 4 +-
ld/testsuite/ld-loongarch-elf/disas-jirl-32.d | 2 +
ld/testsuite/ld-loongarch-elf/disas-jirl.d | 4 +-
ld/testsuite/ld-loongarch-elf/jmp_op.d | 65 +++++++++++++--------
ld/testsuite/ld-loongarch-elf/macro_op.d | 84 +++++++++++++++++++--------
ld/testsuite/ld-loongarch-elf/macro_op_32.d | 24 ++++++--
ld/testsuite/ld-loongarch-elf/relax-align.dd | 7 +++
ld/testsuite/ld-loongarch-elf/relax-align.s | 9 +++
ld/testsuite/ld-loongarch-elf/relax.exp | 77 ++++++++++++++++++++++++
ld/testsuite/ld-loongarch-elf/relax.s | 16 +++++
ld/testsuite/ld-loongarch-elf/uleb128.dd | 10 ++++
ld/testsuite/ld-loongarch-elf/uleb128.s | 21 +++++++
14 files changed, 273 insertions(+), 56 deletions(-)
diff --git a/ld/emultempl/loongarchelf.em b/ld/emultempl/loongarchelf.em
index b790f645c9b..4850feb8767 100644
--- a/ld/emultempl/loongarchelf.em
+++ b/ld/emultempl/loongarchelf.em
@@ -23,6 +23,7 @@ fragment <<EOF
#include "ldmain.h"
#include "ldctor.h"
#include "elf/loongarch.h"
+#include "elfxx-loongarch.h"
static void
larch_elf_before_allocation (void)
@@ -61,6 +62,8 @@ gld${EMULATION_NAME}_after_allocation (void)
}
}
+ enum phase_enum *phase = &(expld.dataseg.phase);
+ bfd_elf${ELFSIZE}_loongarch_set_data_segment_info (&link_info, (int *) phase);
/* gld${EMULATION_NAME}_map_segments (need_layout); */
ldelf_map_segments (need_layout);
}
diff --git a/ld/testsuite/ld-elf/compressed1d.d b/ld/testsuite/ld-elf/compressed1d.d
index 9d891c1933f..b178695e23f 100644
--- a/ld/testsuite/ld-elf/compressed1d.d
+++ b/ld/testsuite/ld-elf/compressed1d.d
@@ -4,10 +4,13 @@
#readelf: -SW
#xfail: [uses_genelf]
#xfail: [riscv_little_endian]
+#xfail: loongarch*-*-*
# Not all ELF targets use the elf.em emulation...
# RISC-V has linker relaxations that delete code, so text label subtractions
# do not get resolved at assembly time, which results in a compressed section
# for little endian targets; but it is uncompressed for big endian targets.
+# LoongArch has linker relaxations that delete code, so text label subtractions
+# do not get resolved at assembly time, which results in a compressed section.
#failif
#...
diff --git a/ld/testsuite/ld-elf/pr26936.d b/ld/testsuite/ld-elf/pr26936.d
index c479f475829..26c80ab90dc 100644
--- a/ld/testsuite/ld-elf/pr26936.d
+++ b/ld/testsuite/ld-elf/pr26936.d
@@ -6,10 +6,10 @@
#readelf: -wL -W
#target: [check_shared_lib_support]
# Assembly source file for the HPPA assembler is renamed and modifed by
-# sed. mn10300 and riscv put different numbers of local symbols in
+# sed. loongarch and mn10300 and riscv put different numbers of local symbols in
# linkonce section and comdat sections. xtensa has more than one member
# in comdat groups.
-#xfail: am33_2.0-*-* hppa*-*-hpux* mn10300-*-* riscv*-*-* xtensa*-*-*
+#xfail: am33_2.0-*-* hppa*-*-hpux* loongarch*-*-* mn10300-*-* riscv*-*-* xtensa*-*-*
#...
CU: .*/pr26936c.s:
diff --git a/ld/testsuite/ld-loongarch-elf/disas-jirl-32.d b/ld/testsuite/ld-loongarch-elf/disas-jirl-32.d
index 2f2a41afe75..cab7a5d4c99 100644
--- a/ld/testsuite/ld-loongarch-elf/disas-jirl-32.d
+++ b/ld/testsuite/ld-loongarch-elf/disas-jirl-32.d
@@ -10,6 +10,8 @@ Disassembly of section .text:
00000000.* <_start>:
[ ]+0:[ ]+1a000014[ ]+pcalau12i[ ]+\$t8,[ ]+0
[ ]+0:[ ]+R_LARCH_PCALA_HI20[ ]+_start
+[ ]+0:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+4:[ ]+02800294[ ]+addi.w[ ]+\$t8,[ ]+\$t8,[ ]+0
[ ]+4:[ ]+R_LARCH_PCALA_LO12[ ]+_start
+[ ]+4:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+8:[ ]+4c000281[ ]+jirl[ ]+\$ra,[ ]+\$t8,[ ]+0
diff --git a/ld/testsuite/ld-loongarch-elf/disas-jirl.d b/ld/testsuite/ld-loongarch-elf/disas-jirl.d
index 595c30c7361..eeb8dd05092 100644
--- a/ld/testsuite/ld-loongarch-elf/disas-jirl.d
+++ b/ld/testsuite/ld-loongarch-elf/disas-jirl.d
@@ -6,9 +6,11 @@
Disassembly of section .text:
-00000000.*:
+00000000.* <_start>:
[ ]+0:[ ]+1a000014[ ]+pcalau12i[ ]+\$t8,[ ]+0
[ ]+0:[ ]+R_LARCH_PCALA_HI20[ ]+_start
+[ ]+0:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+4:[ ]+02c00294[ ]+addi.d[ ]+\$t8,[ ]+\$t8,[ ]+0
[ ]+4:[ ]+R_LARCH_PCALA_LO12[ ]+_start
+[ ]+4:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+8:[ ]+4c000281[ ]+jirl[ ]+\$ra,[ ]+\$t8,[ ]+0
diff --git a/ld/testsuite/ld-loongarch-elf/jmp_op.d b/ld/testsuite/ld-loongarch-elf/jmp_op.d
index 218c13f9398..09f89100195 100644
--- a/ld/testsuite/ld-loongarch-elf/jmp_op.d
+++ b/ld/testsuite/ld-loongarch-elf/jmp_op.d
@@ -6,26 +6,45 @@
Disassembly of section .text:
-00000000.* <.text>:
-[ ]+0:[ ]+03400000[ ]+[ ]+andi[ ]+\$zero, \$zero, 0x0
-[ ]+4:[ ]+63fffc04[ ]+[ ]+blt[ ]+\$zero, \$a0, -4\(0x3fffc\)[ ]+# 0x0
-[ ]+8:[ ]+67fff880[ ]+[ ]+bge[ ]+\$a0, \$zero, -8\(0x3fff8\)[ ]+# 0x0
-[ ]+c:[ ]+67fff404[ ]+[ ]+bge[ ]+\$zero, \$a0, -12\(0x3fff4\)[ ]+# 0x0
-[ ]+10:[ ]+43fff09f[ ]+[ ]+beqz[ ]+\$a0, -16\(0x7ffff0\)[ ]+# 0x0
-[ ]+14:[ ]+47ffec9f[ ]+[ ]+bnez[ ]+\$a0, -20\(0x7fffec\)[ ]+# 0x0
-[ ]+18:[ ]+4bffe81f[ ]+[ ]+bceqz[ ]+\$fcc0, -24\(0x7fffe8\)[ ]+# 0x0
-[ ]+1c:[ ]+4bffe51f[ ]+[ ]+bcnez[ ]+\$fcc0, -28\(0x7fffe4\)[ ]+# 0x0
-[ ]+20:[ ]+4c000080[ ]+[ ]+jirl[ ]+\$zero, \$a0, 0
-[ ]+24:[ ]+53ffdfff[ ]+[ ]+b[ ]+-36\(0xfffffdc\)[ ]+# 0x0
-[ ]+28:[ ]+57ffdbff[ ]+[ ]+bl[ ]+-40\(0xfffffd8\)[ ]+# 0x0
-[ ]+2c:[ ]+5bffd485[ ]+[ ]+beq[ ]+\$a0, \$a1, -44\(0x3ffd4\)[ ]+# 0x0
-[ ]+30:[ ]+5fffd085[ ]+[ ]+bne[ ]+\$a0, \$a1, -48\(0x3ffd0\)[ ]+# 0x0
-[ ]+34:[ ]+63ffcc85[ ]+[ ]+blt[ ]+\$a0, \$a1, -52\(0x3ffcc\)[ ]+# 0x0
-[ ]+38:[ ]+63ffc8a4[ ]+[ ]+blt[ ]+\$a1, \$a0, -56\(0x3ffc8\)[ ]+# 0x0
-[ ]+3c:[ ]+67ffc485[ ]+[ ]+bge[ ]+\$a0, \$a1, -60\(0x3ffc4\)[ ]+# 0x0
-[ ]+40:[ ]+67ffc0a4[ ]+[ ]+bge[ ]+\$a1, \$a0, -64\(0x3ffc0\)[ ]+# 0x0
-[ ]+44:[ ]+6bffbc85[ ]+[ ]+bltu[ ]+\$a0, \$a1, -68\(0x3ffbc\)[ ]+# 0x0
-[ ]+48:[ ]+6bffb8a4[ ]+[ ]+bltu[ ]+\$a1, \$a0, -72\(0x3ffb8\)[ ]+# 0x0
-[ ]+4c:[ ]+6fffb485[ ]+[ ]+bgeu[ ]+\$a0, \$a1, -76\(0x3ffb4\)[ ]+# 0x0
-[ ]+50:[ ]+6fffb0a4[ ]+[ ]+bgeu[ ]+\$a1, \$a0, -80\(0x3ffb0\)[ ]+# 0x0
-[ ]+54:[ ]+4c000020[ ]+[ ]+jirl[ ]+\$zero, \$ra, 0
+00000000.* <.L1>:
+[ ]+0:[ ]+03400000[ ]+andi[ ]+\$zero,[ ]+\$zero,[ ]+0x0
+[ ]+4:[ ]+63fffc04[ ]+blt[ ]+\$zero,[ ]+\$a0,[ ]+-4\(0x3fffc\)[ ]+#[ ]+0[ ]+<.L1>
+[ ]+4:[ ]+R_LARCH_B16[ ]+.L1
+[ ]+8:[ ]+67fff880[ ]+bge[ ]+\$a0,[ ]+\$zero,[ ]+-8\(0x3fff8\)[ ]+#[ ]+0[ ]+<.L1>
+[ ]+8:[ ]+R_LARCH_B16[ ]+.L1
+[ ]+c:[ ]+67fff404[ ]+bge[ ]+\$zero,[ ]+\$a0,[ ]+-12\(0x3fff4\)[ ]+#[ ]+0[ ]+<.L1>
+[ ]+c:[ ]+R_LARCH_B16[ ]+.L1
+[ ]+10:[ ]+43fff09f[ ]+beqz[ ]+\$a0,[ ]+-16\(0x7ffff0\)[ ]+#[ ]+0[ ]+<.L1>
+[ ]+10:[ ]+R_LARCH_B21[ ]+.L1
+[ ]+14:[ ]+47ffec9f[ ]+bnez[ ]+\$a0,[ ]+-20\(0x7fffec\)[ ]+#[ ]+0[ ]+<.L1>
+[ ]+14:[ ]+R_LARCH_B21[ ]+.L1
+[ ]+18:[ ]+4bffe81f[ ]+bceqz[ ]+\$fcc0,[ ]+-24\(0x7fffe8\)[ ]+#[ ]+0[ ]+<.L1>
+[ ]+18:[ ]+R_LARCH_B21[ ]+.L1
+[ ]+1c:[ ]+4bffe51f[ ]+bcnez[ ]+\$fcc0,[ ]+-28\(0x7fffe4\)[ ]+#[ ]+0[ ]+<.L1>
+[ ]+1c:[ ]+R_LARCH_B21[ ]+.L1
+[ ]+20:[ ]+4c000080[ ]+jirl[ ]+\$zero,[ ]+\$a0,[ ]+0
+[ ]+24:[ ]+53ffdfff[ ]+b[ ]+-36\(0xfffffdc\)[ ]+#[ ]+0[ ]+<.L1>
+[ ]+24:[ ]+R_LARCH_B26[ ]+.L1
+[ ]+28:[ ]+57ffdbff[ ]+bl[ ]+-40\(0xfffffd8\)[ ]+#[ ]+0[ ]+<.L1>
+[ ]+28:[ ]+R_LARCH_B26[ ]+.L1
+[ ]+2c:[ ]+5bffd485[ ]+beq[ ]+\$a0,[ ]+\$a1,[ ]+-44\(0x3ffd4\)[ ]+#[ ]+0[ ]+<.L1>
+[ ]+2c:[ ]+R_LARCH_B16[ ]+.L1
+[ ]+30:[ ]+5fffd085[ ]+bne[ ]+\$a0,[ ]+\$a1,[ ]+-48\(0x3ffd0\)[ ]+#[ ]+0[ ]+<.L1>
+[ ]+30:[ ]+R_LARCH_B16[ ]+.L1
+[ ]+34:[ ]+63ffcc85[ ]+blt[ ]+\$a0,[ ]+\$a1,[ ]+-52\(0x3ffcc\)[ ]+#[ ]+0[ ]+<.L1>
+[ ]+34:[ ]+R_LARCH_B16[ ]+.L1
+[ ]+38:[ ]+63ffc8a4[ ]+blt[ ]+\$a1,[ ]+\$a0,[ ]+-56\(0x3ffc8\)[ ]+#[ ]+0[ ]+<.L1>
+[ ]+38:[ ]+R_LARCH_B16[ ]+.L1
+[ ]+3c:[ ]+67ffc485[ ]+bge[ ]+\$a0,[ ]+\$a1,[ ]+-60\(0x3ffc4\)[ ]+#[ ]+0[ ]+<.L1>
+[ ]+3c:[ ]+R_LARCH_B16[ ]+.L1
+[ ]+40:[ ]+67ffc0a4[ ]+bge[ ]+\$a1,[ ]+\$a0,[ ]+-64\(0x3ffc0\)[ ]+#[ ]+0[ ]+<.L1>
+[ ]+40:[ ]+R_LARCH_B16[ ]+.L1
+[ ]+44:[ ]+6bffbc85[ ]+bltu[ ]+\$a0,[ ]+\$a1,[ ]+-68\(0x3ffbc\)[ ]+#[ ]+0[ ]+<.L1>
+[ ]+44:[ ]+R_LARCH_B16[ ]+.L1
+[ ]+48:[ ]+6bffb8a4[ ]+bltu[ ]+\$a1,[ ]+\$a0,[ ]+-72\(0x3ffb8\)[ ]+#[ ]+0[ ]+<.L1>
+[ ]+48:[ ]+R_LARCH_B16[ ]+.L1
+[ ]+4c:[ ]+6fffb485[ ]+bgeu[ ]+\$a0,[ ]+\$a1,[ ]+-76\(0x3ffb4\)[ ]+#[ ]+0[ ]+<.L1>
+[ ]+4c:[ ]+R_LARCH_B16[ ]+.L1
+[ ]+50:[ ]+6fffb0a4[ ]+bgeu[ ]+\$a1,[ ]+\$a0,[ ]+-80\(0x3ffb0\)[ ]+#[ ]+0[ ]+<.L1>
+[ ]+50:[ ]+R_LARCH_B16[ ]+.L1
+[ ]+54:[ ]+4c000020[ ]+jirl[ ]+\$zero,[ ]+\$ra,[ ]+0
diff --git a/ld/testsuite/ld-loongarch-elf/macro_op.d b/ld/testsuite/ld-loongarch-elf/macro_op.d
index 39aa1fb929f..2649f63e566 100644
--- a/ld/testsuite/ld-loongarch-elf/macro_op.d
+++ b/ld/testsuite/ld-loongarch-elf/macro_op.d
@@ -13,16 +13,22 @@ Disassembly of section .text:
[ ]+c:[ ]+02bffc04[ ]+addi.w[ ]+\$a0,[ ]+\$zero,[ ]+-1\(0xfff\)
[ ]+10:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+10:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1
+[ ]+10:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+14:[ ]+28c00084[ ]+ld.d[ ]+\$a0,[ ]+\$a0,[ ]+0
[ ]+14:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1
+[ ]+14:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+18:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+18:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1
+[ ]+18:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+1c:[ ]+28c00084[ ]+ld.d[ ]+\$a0,[ ]+\$a0,[ ]+0
[ ]+1c:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1
+[ ]+1c:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+20:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+20:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1
+[ ]+20:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+24:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
[ ]+24:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1
+[ ]+24:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+28:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
[ ]+28:[ ]+R_LARCH_GOT64_PC_LO20[ ]+.L1
[ ]+2c:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0
@@ -30,12 +36,16 @@ Disassembly of section .text:
[ ]+30:[ ]+380c1484[ ]+ldx.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1
[ ]+34:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+34:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1
+[ ]+34:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+38:[ ]+28c00084[ ]+ld.d[ ]+\$a0,[ ]+\$a0,[ ]+0
[ ]+38:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1
+[ ]+38:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+3c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+3c:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1
+[ ]+3c:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+40:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
[ ]+40:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1
+[ ]+40:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+44:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
[ ]+44:[ ]+R_LARCH_GOT64_PC_LO20[ ]+.L1
[ ]+48:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0
@@ -43,77 +53,99 @@ Disassembly of section .text:
[ ]+4c:[ ]+380c1484[ ]+ldx.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1
[ ]+50:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+50:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1
+[ ]+50:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+54:[ ]+28c00084[ ]+ld.d[ ]+\$a0,[ ]+\$a0,[ ]+0
[ ]+54:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1
+[ ]+54:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+58:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+58:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1
+[ ]+58:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+5c:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
[ ]+5c:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1
+[ ]+5c:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+60:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
[ ]+60:[ ]+R_LARCH_GOT64_PC_LO20[ ]+.L1
[ ]+64:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0
[ ]+64:[ ]+R_LARCH_GOT64_PC_HI12[ ]+.L1
[ ]+68:[ ]+380c1484[ ]+ldx.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1
[ ]+6c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
-[ ]+6c:[ ]+R_LARCH_PCALA_HI20[ ]+.text
+[ ]+6c:[ ]+R_LARCH_PCALA_HI20[ ]+.L1
+[ ]+6c:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+70:[ ]+02c00084[ ]+addi.d[ ]+\$a0,[ ]+\$a0,[ ]+0
-[ ]+70:[ ]+R_LARCH_PCALA_LO12[ ]+.text
+[ ]+70:[ ]+R_LARCH_PCALA_LO12[ ]+.L1
+[ ]+70:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+74:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
-[ ]+74:[ ]+R_LARCH_PCALA_HI20[ ]+.text
+[ ]+74:[ ]+R_LARCH_PCALA_HI20[ ]+.L1
+[ ]+74:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+78:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
-[ ]+78:[ ]+R_LARCH_PCALA_LO12[ ]+.text
+[ ]+78:[ ]+R_LARCH_PCALA_LO12[ ]+.L1
+[ ]+78:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+7c:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
-[ ]+7c:[ ]+R_LARCH_PCALA64_LO20[ ]+.text
+[ ]+7c:[ ]+R_LARCH_PCALA64_LO20[ ]+.L1
[ ]+80:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0
-[ ]+80:[ ]+R_LARCH_PCALA64_HI12[ ]+.text
+[ ]+80:[ ]+R_LARCH_PCALA64_HI12[ ]+.L1
[ ]+84:[ ]+00109484[ ]+add.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1
[ ]+88:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
-[ ]+88:[ ]+R_LARCH_PCALA_HI20[ ]+.text
+[ ]+88:[ ]+R_LARCH_PCALA_HI20[ ]+.L1
+[ ]+88:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+8c:[ ]+02c00084[ ]+addi.d[ ]+\$a0,[ ]+\$a0,[ ]+0
-[ ]+8c:[ ]+R_LARCH_PCALA_LO12[ ]+.text
+[ ]+8c:[ ]+R_LARCH_PCALA_LO12[ ]+.L1
+[ ]+8c:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+90:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
-[ ]+90:[ ]+R_LARCH_PCALA_HI20[ ]+.text
+[ ]+90:[ ]+R_LARCH_PCALA_HI20[ ]+.L1
+[ ]+90:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+94:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
-[ ]+94:[ ]+R_LARCH_PCALA_LO12[ ]+.text
+[ ]+94:[ ]+R_LARCH_PCALA_LO12[ ]+.L1
+[ ]+94:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+98:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
-[ ]+98:[ ]+R_LARCH_PCALA64_LO20[ ]+.text
+[ ]+98:[ ]+R_LARCH_PCALA64_LO20[ ]+.L1
[ ]+9c:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0
-[ ]+9c:[ ]+R_LARCH_PCALA64_HI12[ ]+.text
+[ ]+9c:[ ]+R_LARCH_PCALA64_HI12[ ]+.L1
[ ]+a0:[ ]+00109484[ ]+add.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1
[ ]+a4:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0
[ ]+a4:[ ]+R_LARCH_MARK_LA[ ]+\*ABS\*
-[ ]+a4:[ ]+R_LARCH_ABS_HI20[ ]+.text
+[ ]+a4:[ ]+R_LARCH_ABS_HI20[ ]+.L1
[ ]+a8:[ ]+03800084[ ]+ori[ ]+\$a0,[ ]+\$a0,[ ]+0x0
-[ ]+a8:[ ]+R_LARCH_ABS_LO12[ ]+.text
+[ ]+a8:[ ]+R_LARCH_ABS_LO12[ ]+.L1
[ ]+ac:[ ]+16000004[ ]+lu32i.d[ ]+\$a0,[ ]+0
-[ ]+ac:[ ]+R_LARCH_ABS64_LO20[ ]+.text
+[ ]+ac:[ ]+R_LARCH_ABS64_LO20[ ]+.L1
[ ]+b0:[ ]+03000084[ ]+lu52i.d[ ]+\$a0,[ ]+\$a0,[ ]+0
-[ ]+b0:[ ]+R_LARCH_ABS64_HI12[ ]+.text
+[ ]+b0:[ ]+R_LARCH_ABS64_HI12[ ]+.L1
[ ]+b4:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
-[ ]+b4:[ ]+R_LARCH_PCALA_HI20[ ]+.text
+[ ]+b4:[ ]+R_LARCH_PCALA_HI20[ ]+.L1
+[ ]+b4:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+b8:[ ]+02c00084[ ]+addi.d[ ]+\$a0,[ ]+\$a0,[ ]+0
-[ ]+b8:[ ]+R_LARCH_PCALA_LO12[ ]+.text
+[ ]+b8:[ ]+R_LARCH_PCALA_LO12[ ]+.L1
+[ ]+b8:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+bc:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
-[ ]+bc:[ ]+R_LARCH_PCALA_HI20[ ]+.text
+[ ]+bc:[ ]+R_LARCH_PCALA_HI20[ ]+.L1
+[ ]+bc:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+c0:[ ]+02c00084[ ]+addi.d[ ]+\$a0,[ ]+\$a0,[ ]+0
-[ ]+c0:[ ]+R_LARCH_PCALA_LO12[ ]+.text
+[ ]+c0:[ ]+R_LARCH_PCALA_LO12[ ]+.L1
+[ ]+c0:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+c4:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
-[ ]+c4:[ ]+R_LARCH_PCALA_HI20[ ]+.text
+[ ]+c4:[ ]+R_LARCH_PCALA_HI20[ ]+.L1
+[ ]+c4:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+c8:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
-[ ]+c8:[ ]+R_LARCH_PCALA_LO12[ ]+.text
+[ ]+c8:[ ]+R_LARCH_PCALA_LO12[ ]+.L1
+[ ]+c8:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+cc:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
-[ ]+cc:[ ]+R_LARCH_PCALA64_LO20[ ]+.text
+[ ]+cc:[ ]+R_LARCH_PCALA64_LO20[ ]+.L1
[ ]+d0:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0
-[ ]+d0:[ ]+R_LARCH_PCALA64_HI12[ ]+.text
+[ ]+d0:[ ]+R_LARCH_PCALA64_HI12[ ]+.L1
[ ]+d4:[ ]+00109484[ ]+add.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1
[ ]+d8:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+d8:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1
+[ ]+d8:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+dc:[ ]+28c00084[ ]+ld.d[ ]+\$a0,[ ]+\$a0,[ ]+0
[ ]+dc:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1
+[ ]+dc:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+e0:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+e0:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1
+[ ]+e0:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+e4:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
[ ]+e4:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1
+[ ]+e4:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+e8:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
[ ]+e8:[ ]+R_LARCH_GOT64_PC_LO20[ ]+.L1
[ ]+ec:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0
@@ -140,10 +172,12 @@ Disassembly of section .text:
[ ]+118:[ ]+R_LARCH_TLS_LD_PC_HI20[ ]+TLS1
[ ]+11c:[ ]+02c00084[ ]+addi.d[ ]+\$a0,[ ]+\$a0,[ ]+0
[ ]+11c:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1
+[ ]+11c:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+120:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+120:[ ]+R_LARCH_TLS_LD_PC_HI20[ ]+TLS1
[ ]+124:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
[ ]+124:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1
+[ ]+124:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+128:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
[ ]+128:[ ]+R_LARCH_GOT64_PC_LO20[ ]+TLS1
[ ]+12c:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0
@@ -153,10 +187,12 @@ Disassembly of section .text:
[ ]+134:[ ]+R_LARCH_TLS_GD_PC_HI20[ ]+TLS1
[ ]+138:[ ]+02c00084[ ]+addi.d[ ]+\$a0,[ ]+\$a0,[ ]+0
[ ]+138:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1
+[ ]+138:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+13c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+13c:[ ]+R_LARCH_TLS_GD_PC_HI20[ ]+TLS1
[ ]+140:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
[ ]+140:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1
+[ ]+140:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+144:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
[ ]+144:[ ]+R_LARCH_GOT64_PC_LO20[ ]+TLS1
[ ]+148:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0
diff --git a/ld/testsuite/ld-loongarch-elf/macro_op_32.d b/ld/testsuite/ld-loongarch-elf/macro_op_32.d
index a78c4579ee9..f5a2b54dd9b 100644
--- a/ld/testsuite/ld-loongarch-elf/macro_op_32.d
+++ b/ld/testsuite/ld-loongarch-elf/macro_op_32.d
@@ -14,29 +14,39 @@ Disassembly of section .text:
[ ]+c:[ ]+02bffc04[ ]+addi.w[ ]+\$a0,[ ]+\$zero,[ ]+-1\(0xfff\)
[ ]+10:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+10:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1
+[ ]+10:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+14:[ ]+28800084[ ]+ld.w[ ]+\$a0,[ ]+\$a0,[ ]+0
[ ]+14:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1
+[ ]+14:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+18:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+18:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1
+[ ]+18:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+1c:[ ]+28800084[ ]+ld.w[ ]+\$a0,[ ]+\$a0,[ ]+0
[ ]+1c:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1
+[ ]+1c:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+20:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
-[ ]+20:[ ]+R_LARCH_PCALA_HI20[ ]+.text
+[ ]+20:[ ]+R_LARCH_PCALA_HI20[ ]+.L1
+[ ]+20:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+24:[ ]+02800084[ ]+addi.w[ ]+\$a0,[ ]+\$a0,[ ]+0
-[ ]+24:[ ]+R_LARCH_PCALA_LO12[ ]+.text
+[ ]+24:[ ]+R_LARCH_PCALA_LO12[ ]+.L1
+[ ]+24:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+28:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0
[ ]+28:[ ]+R_LARCH_MARK_LA[ ]+\*ABS\*
-[ ]+28:[ ]+R_LARCH_ABS_HI20[ ]+.text
+[ ]+28:[ ]+R_LARCH_ABS_HI20[ ]+.L1
[ ]+2c:[ ]+03800084[ ]+ori[ ]+\$a0,[ ]+\$a0,[ ]+0x0
-[ ]+2c:[ ]+R_LARCH_ABS_LO12[ ]+.text
+[ ]+2c:[ ]+R_LARCH_ABS_LO12[ ]+.L1
[ ]+30:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
-[ ]+30:[ ]+R_LARCH_PCALA_HI20[ ]+.text
+[ ]+30:[ ]+R_LARCH_PCALA_HI20[ ]+.L1
+[ ]+30:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+34:[ ]+02800084[ ]+addi.w[ ]+\$a0,[ ]+\$a0,[ ]+0
-[ ]+34:[ ]+R_LARCH_PCALA_LO12[ ]+.text
+[ ]+34:[ ]+R_LARCH_PCALA_LO12[ ]+.L1
+[ ]+34:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+38:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+38:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1
+[ ]+38:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+3c:[ ]+28800084[ ]+ld.w[ ]+\$a0,[ ]+\$a0,[ ]+0
[ ]+3c:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1
+[ ]+3c:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+40:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0
[ ]+40:[ ]+R_LARCH_TLS_LE_HI20[ ]+TLS1
[ ]+44:[ ]+03800084[ ]+ori[ ]+\$a0,[ ]+\$a0,[ ]+0x0
@@ -49,7 +59,9 @@ Disassembly of section .text:
[ ]+50:[ ]+R_LARCH_TLS_LD_PC_HI20[ ]+TLS1
[ ]+54:[ ]+02800084[ ]+addi.w[ ]+\$a0,[ ]+\$a0,[ ]+0
[ ]+54:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1
+[ ]+54:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+58:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+58:[ ]+R_LARCH_TLS_GD_PC_HI20[ ]+TLS1
[ ]+5c:[ ]+02800084[ ]+addi.w[ ]+\$a0,[ ]+\$a0,[ ]+0
[ ]+5c:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1
+[ ]+5c:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
diff --git a/ld/testsuite/ld-loongarch-elf/relax-align.dd b/ld/testsuite/ld-loongarch-elf/relax-align.dd
new file mode 100644
index 00000000000..3149738ff71
--- /dev/null
+++ b/ld/testsuite/ld-loongarch-elf/relax-align.dd
@@ -0,0 +1,7 @@
+#...
+.*pcaddi.*
+.*pcaddi.*
+.*andi.*
+.*andi.*
+.*0:.*pcaddi.*
+#pass
diff --git a/ld/testsuite/ld-loongarch-elf/relax-align.s b/ld/testsuite/ld-loongarch-elf/relax-align.s
new file mode 100644
index 00000000000..9617c02d8e5
--- /dev/null
+++ b/ld/testsuite/ld-loongarch-elf/relax-align.s
@@ -0,0 +1,9 @@
+# relax-align.o has 3 andi(nop) insns.
+# relax-align has 2 andi insns, ld relax delete andi insns.
+# the last pcaddi 16 bytes align.
+ .text
+L1:
+ la.local $a0, L1
+ la.local $a0, L1
+ .align 4
+ la.local $a0, L1
diff --git a/ld/testsuite/ld-loongarch-elf/relax.exp b/ld/testsuite/ld-loongarch-elf/relax.exp
new file mode 100644
index 00000000000..7ff876d7914
--- /dev/null
+++ b/ld/testsuite/ld-loongarch-elf/relax.exp
@@ -0,0 +1,77 @@
+# Expect script for LoongArch ELF linker tests
+# Copyright (C) 2022 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+
+if [istarget loongarch64-*-*] {
+
+ if [isbuild loongarch64-*-*] {
+ set testname "loongarch relax build"
+ set pre_builds [list \
+ [list \
+ "$testname" \
+ "" \
+ "" \
+ {relax.s} \
+ {} \
+ "relax" \
+ ] \
+ ]
+
+ run_cc_link_tests $pre_builds
+
+ if [file exist "tmpdir/relax"] {
+ set objdump_output [run_host_cmd "objdump" "-d tmpdir/relax"]
+ if { [ regexp ".*pcaddi.*pcaddi.*" $objdump_output] } {
+ pass "loongarch relax"
+ } {
+ fail "loongarch relax"
+ }
+ }
+ }
+
+ run_ld_link_tests \
+ [list \
+ [list \
+ "relax-align" \
+ "-e 0x0 -z relro" "" \
+ "" \
+ {relax-align.s} \
+ [list \
+ [list objdump -d relax-align.dd] \
+ ] \
+ "relax-align" \
+ ] \
+ ]
+
+ set objdump_flags "-s -j .data"
+ run_ld_link_tests \
+ [list \
+ [list \
+ "uleb128" \
+ "-e 0x0" "" \
+ "" \
+ {uleb128.s} \
+ [list \
+ [list objdump $objdump_flags uleb128.dd] \
+ ] \
+ "uleb128" \
+ ] \
+ ]
+}
diff --git a/ld/testsuite/ld-loongarch-elf/relax.s b/ld/testsuite/ld-loongarch-elf/relax.s
new file mode 100644
index 00000000000..2979ffa3714
--- /dev/null
+++ b/ld/testsuite/ld-loongarch-elf/relax.s
@@ -0,0 +1,16 @@
+ .data
+ .global a
+ .type a, @object
+a:
+ .word 123
+
+ .text
+ .global main
+ .type main, @function
+main:
+ la.local $a0, a
+ ld.w $a1, $a0, 0
+ la.global $a0, a
+ ld.w $a0, $a0, 0
+ sub.d $a0, $a0, $a1
+ jr $ra
diff --git a/ld/testsuite/ld-loongarch-elf/uleb128.dd b/ld/testsuite/ld-loongarch-elf/uleb128.dd
new file mode 100644
index 00000000000..c4ad3070ee1
--- /dev/null
+++ b/ld/testsuite/ld-loongarch-elf/uleb128.dd
@@ -0,0 +1,10 @@
+.*: .*
+
+Contents of section .*
+ [0-9a-f]+ 01020381 01000000 00000000 00000000.*
+#...
+ [0-9a-f]+ 00000004 ffff0500 06078380 01000000.*
+#...
+ [0-9a-f]+ 00000000 00000000 00000008 ffffffff.*
+ [0-9a-f]+ 09090909 09090909 09090909 09090909.*
+#pass
diff --git a/ld/testsuite/ld-loongarch-elf/uleb128.s b/ld/testsuite/ld-loongarch-elf/uleb128.s
new file mode 100644
index 00000000000..7299fb91a25
--- /dev/null
+++ b/ld/testsuite/ld-loongarch-elf/uleb128.s
@@ -0,0 +1,21 @@
+# From gas/all/relax.s, test ld process add_uleb128/sub_uleb128 reloc pair.
+ .data
+ .byte 1, 2, 3
+ .uleb128 L2 - L1
+L1:
+ .space 128 - 2
+ .byte 4
+ .p2align 1, 0xff
+L2:
+ .byte 5
+
+ .p2align 2
+ .byte 6, 7
+ .uleb128 L4 - L3
+L3:
+ .space 128*128 - 2
+ .byte 8
+ .p2align 2, 0xff
+L4:
+ .byte 9
+ .p2align 4, 9
^ permalink raw reply [flat|nested] only message in thread
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2023-05-30 12:04 [binutils-gdb] LoongArch: ld: Add support for linker relaxation liu & zhensong
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