* [binutils-gdb] LoongArch: gas: Add LVZ and LBT instructions support
@ 2023-06-30 9:35 liu & zhensong
0 siblings, 0 replies; only message in thread
From: liu & zhensong @ 2023-06-30 9:35 UTC (permalink / raw)
To: bfd-cvs
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=071726dee7881692c442c029ef876306b7cc7832
commit 071726dee7881692c442c029ef876306b7cc7832
Author: mengqinggang <mengqinggang@loongson.cn>
Date: Fri Jun 30 17:04:15 2023 +0800
LoongArch: gas: Add LVZ and LBT instructions support
gas/ChangeLog:
* config/tc-loongarch.c (md_parse_option): Add LARCH_opts.ase_lvz and
LARCH_opts.ase_lbt.
* testsuite/gas/loongarch/uleb128.d: Regenerated.
* testsuite/gas/loongarch/lvz-lbt.d: New test.
* testsuite/gas/loongarch/lvz-lbt.s: New test.
include/ChangeLog:
* opcode/loongarch.h (ase_lvz): New.
(ase_lbt): New.
opcodes/ChangeLog:
* loongarch-dis.c (set_default_loongarch_dis_options): Add
LARCH_opts.ase_lvz and LARCH_opts.ase_lbt.
* loongarch-opc.c (struct loongarch_ase): Add LVZ and LBT instructions.
Diff:
---
gas/config/tc-loongarch.c | 4 +
gas/testsuite/gas/loongarch/lvz-lbt.d | 191 ++++++++++++++++++++++++++++++++
gas/testsuite/gas/loongarch/lvz-lbt.s | 181 ++++++++++++++++++++++++++++++
gas/testsuite/gas/loongarch/uleb128.d | 52 ++++-----
include/opcode/loongarch.h | 6 +
opcodes/loongarch-dis.c | 2 +
opcodes/loongarch-opc.c | 200 +++++++++++++++++++++++++++++++++-
7 files changed, 608 insertions(+), 28 deletions(-)
diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c
index d23506cd023..439bde18b7d 100644
--- a/gas/config/tc-loongarch.c
+++ b/gas/config/tc-loongarch.c
@@ -168,6 +168,8 @@ md_parse_option (int c, const char *arg)
LARCH_opts.ase_lp64 = 1;
LARCH_opts.ase_lsx = 1;
LARCH_opts.ase_lasx = 1;
+ LARCH_opts.ase_lvz = 1;
+ LARCH_opts.ase_lbt = 1;
LARCH_opts.ase_abi = lp64[suf[4]];
}
else if (strncasecmp (arg, "ilp32", 5) == 0 && ilp32[suf[5]] != 0)
@@ -249,6 +251,8 @@ loongarch_after_parse_args ()
LARCH_opts.ase_lp64 = 1;
LARCH_opts.ase_lsx = 1;
LARCH_opts.ase_lasx = 1;
+ LARCH_opts.ase_lvz = 1;
+ LARCH_opts.ase_lbt = 1;
}
else if (strcmp (default_arch, "loongarch32") == 0)
{
diff --git a/gas/testsuite/gas/loongarch/lvz-lbt.d b/gas/testsuite/gas/loongarch/lvz-lbt.d
new file mode 100644
index 00000000000..f89707762dc
--- /dev/null
+++ b/gas/testsuite/gas/loongarch/lvz-lbt.d
@@ -0,0 +1,191 @@
+#as:
+#objdump: -dr
+#skip: loongarch32-*-*
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+00000000.* <.text>:
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+[ ]*2b8:[ ]*003fc41f[ ]*armrrx\.w[ ]*\$zero,[ ]*0x1[ ]*
+[ ]*2bc:[ ]*00364420[ ]*armmove[ ]*\$zero,[ ]*\$ra,[ ]*0x1[ ]*
+[ ]*2c0:[ ]*003fc41d[ ]*armmov\.w[ ]*\$zero,[ ]*0x1[ ]*
+[ ]*2c4:[ ]*003fc41e[ ]*armmov\.d[ ]*\$zero,[ ]*0x1[ ]*
+[ ]*2c8:[ ]*005c0440[ ]*armmfflag[ ]*\$zero,[ ]*0x1[ ]*
+[ ]*2cc:[ ]*005c0460[ ]*armmtflag[ ]*\$zero,[ ]*0x1[ ]*
+[ ]*2d0:[ ]*0036c400[ ]*setarmj[ ]*\$zero,[ ]*0x1[ ]*
diff --git a/gas/testsuite/gas/loongarch/lvz-lbt.s b/gas/testsuite/gas/loongarch/lvz-lbt.s
new file mode 100644
index 00000000000..64469a4362d
--- /dev/null
+++ b/gas/testsuite/gas/loongarch/lvz-lbt.s
@@ -0,0 +1,181 @@
+gcsrrd $r0, 1
+gcsrwr $r0, 1
+gcsrxchg $r0, $r1, 1
+gtlbflush
+hvcl 1
+movgr2scr $scr0, $r1
+movscr2gr $r0, $scr1
+jiscr0 100
+jiscr1 100
+addu12i.w $r0, $r1, 1
+addu12i.d $r0, $r1, 1
+adc.b $r0, $r1, $r2
+adc.h $r0, $r1, $r2
+adc.w $r0, $r1, $r2
+adc.d $r0, $r1, $r2
+sbc.b $r0, $r1, $r2
+sbc.h $r0, $r1, $r2
+sbc.w $r0, $r1, $r2
+sbc.d $r0, $r1, $r2
+rotr.b $r0, $r1, $r2
+rotr.h $r0, $r1, $r2
+rotri.b $r0, $r1, 1
+rotri.h $r0, $r1, 1
+rcr.b $r0, $r1, $r2
+rcr.h $r0, $r1, $r2
+rcr.w $r0, $r1, $r2
+rcr.d $r0, $r1, $r2
+rcri.b $r0, $r1, 1
+rcri.h $r0, $r1, 1
+rcri.w $r0, $r1, 1
+rcri.d $r0, $r1, 1
+fcvt.ud.d $f0, $f1
+fcvt.ld.d $f0, $f1
+fcvt.d.ld $f0, $f1, $f2
+ldl.d $r0, $r1, 1
+ldl.w $r0, $r1, 1
+ldr.w $r0, $r1, 1
+ldr.d $r0, $r1, 1
+stl.w $r0, $r1, 1
+stl.d $r0, $r1, 1
+str.w $r0, $r1, 1
+str.d $r0, $r1, 1
+x86adc.b $r0, $r1
+x86adc.h $r0, $r1
+x86adc.w $r0, $r1
+x86adc.d $r0, $r1
+x86add.b $r0, $r1
+x86add.h $r0, $r1
+x86add.w $r0, $r1
+x86add.d $r0, $r1
+x86add.wu $r0, $r1
+x86add.du $r0, $r1
+x86inc.b $r0
+x86inc.h $r0
+x86inc.w $r0
+x86inc.d $r0
+x86sbc.b $r0, $r1
+x86sbc.h $r0, $r1
+x86sbc.w $r0, $r1
+x86sbc.d $r0, $r1
+x86sub.b $r0, $r1
+x86sub.h $r0, $r1
+x86sub.w $r0, $r1
+x86sub.d $r0, $r1
+x86sub.wu $r0, $r1
+x86sub.du $r0, $r1
+x86dec.b $r0
+x86dec.h $r0
+x86dec.w $r0
+x86dec.d $r0
+x86and.b $r0, $r1
+x86and.h $r0, $r1
+x86and.w $r0, $r1
+x86and.d $r0, $r1
+x86or.b $r0, $r1
+x86or.h $r0, $r1
+x86or.w $r0, $r1
+x86or.d $r0, $r1
+x86xor.b $r0, $r1
+x86xor.h $r0, $r1
+x86xor.w $r0, $r1
+x86xor.d $r0, $r1
+x86mul.b $r0, $r1
+x86mul.h $r0, $r1
+x86mul.w $r0, $r1
+x86mul.d $r0, $r1
+x86mul.bu $r0, $r1
+x86mul.hu $r0, $r1
+x86mul.wu $r0, $r1
+x86mul.du $r0, $r1
+x86rcl.b $r0, $r1
+x86rcl.h $r0, $r1
+x86rcl.w $r0, $r1
+x86rcl.d $r0, $r1
+x86rcli.b $r0, 1
+x86rcli.h $r0, 1
+x86rcli.w $r0, 1
+x86rcli.d $r0, 1
+x86rcr.b $r0, $r1
+x86rcr.h $r0, $r1
+x86rcr.w $r0, $r1
+x86rcr.d $r0, $r1
+x86rcri.b $r0, 1
+x86rcri.h $r0, 1
+x86rcri.w $r0, 1
+x86rcri.d $r0, 1
+x86rotl.b $r0, $r1
+x86rotl.h $r0, $r1
+x86rotl.w $r0, $r1
+x86rotl.d $r0, $r1
+x86rotli.b $r0, 1
+x86rotli.h $r0, 1
+x86rotli.w $r0, 1
+x86rotli.d $r0, 1
+x86rotr.b $r0, $r1
+x86rotr.h $r0, $r1
+x86rotr.d $r0, $r1
+x86rotr.w $r0, $r1
+x86rotri.b $r0, 1
+x86rotri.h $r0, 1
+x86rotri.w $r0, 1
+x86rotri.d $r0, 1
+x86sll.b $r0, $r1
+x86sll.h $r0, $r1
+x86sll.w $r0, $r1
+x86sll.d $r0, $r1
+x86slli.b $r0, 1
+x86slli.h $r0, 1
+x86slli.w $r0, 1
+x86slli.d $r0, 1
+x86srl.b $r0, $r1
+x86srl.h $r0, $r1
+x86srl.w $r0, $r1
+x86srl.d $r0, $r1
+x86srli.b $r0, 1
+x86srli.h $r0, 1
+x86srli.w $r0, 1
+x86srli.d $r0, 1
+x86sra.b $r0, $r1
+x86sra.h $r0, $r1
+x86sra.w $r0, $r1
+x86sra.d $r0, $r1
+x86srai.b $r0, 1
+x86srai.h $r0, 1
+x86srai.w $r0, 1
+x86srai.d $r0, 1
+setx86j $r0, 1
+setx86loope $r0, $r1
+setx86loopne $r0, $r1
+x86mfflag $r0, 1
+x86mtflag $r0, 1
+x86mftop $r0
+x86mttop 1
+x86inctop
+x86dectop
+x86settm
+x86clrtm
+x86settag $r0, 1, 1
+armadd.w $r0, $r1, 1
+armsub.w $r0, $r1, 1
+armadc.w $r0, $r1, 1
+armsbc.w $r0, $r1, 1
+armand.w $r0, $r1, 1
+armor.w $r0, $r1, 1
+armxor.w $r0, $r1, 1
+armnot.w $r0, 1
+armsll.w $r0, $r1, 1
+armsrl.w $r0, $r1, 1
+armsra.w $r0, $r1, 1
+armrotr.w $r0, $r1, 1
+armslli.w $r0, 1, 1
+armsrli.w $r0, 1, 1
+armsrai.w $r0, 1, 1
+armrotri.w $r0, 1, 1
+armrrx.w $r0, 1
+armmove $r0, $r1, 1
+armmov.w $r0, 1
+armmov.d $r0, 1
+armmfflag $r0, 1
+armmtflag $r0, 1
+setarmj $r0, 1
diff --git a/gas/testsuite/gas/loongarch/uleb128.d b/gas/testsuite/gas/loongarch/uleb128.d
index ad67ded9e7d..1a6730f3aab 100644
--- a/gas/testsuite/gas/loongarch/uleb128.d
+++ b/gas/testsuite/gas/loongarch/uleb128.d
@@ -8,29 +8,29 @@
Disassembly of section .data:
00000000.* <L1-0x5>:
-[ ]+0:[ ]+80030201[ ]+\.word[ ]+0x80030201
-[ ]+3:[ ]+R_LARCH_ADD_ULEB128[ ]+L2
-[ ]+3:[ ]+R_LARCH_SUB_ULEB128[ ]+L1
-[ ]+\.\.\.
-
-0000000000000005[ ]+<L1>:
-[ ]+\.\.\.
-[ ]+81:[ ]+ff040000[ ]+\.word[ ]+0xff040000
-[ ]+85:[ ]+cacop[ ]+0x1f,[ ]+\$t3,[ ]+1
-
-0000000000000086[ ]+<L2>:
-[ ]+86:[ ]+07060005[ ]+\.word[ ]+0x07060005
-[ ]+8a:[ ]+\.word[ ]+0x00008080
-[ ]+8a:[ ]+R_LARCH_ADD_ULEB128[ ]+L4
-[ ]+8a:[ ]+R_LARCH_SUB_ULEB128[ ]+L3
-
-000000000000008d[ ]+<L3>:
-[ ]+\.\.\.
-[ ]+4089:[ ]+ff080000[ ]+\.word[ ]+0xff080000
-[ ]+408d:[ ]+\.word[ ]+0x09ffffff
-
-0000000000004090[ ]+<L4>:
-[ ]+4090:[ ]+09090909[ ]+\.word[ ]+0x09090909
-[ ]+4094:[ ]+09090909[ ]+\.word[ ]+0x09090909
-[ ]+4098:[ ]+09090909[ ]+\.word[ ]+0x09090909
-[ ]+409c:[ ]+09090909[ ]+\.word[ ]+0x09090909
+[ ]*0:[ ]*80030201[ ]*\.word[ ]*0x80030201
+[ ]*3:[ ]*R_LARCH_ADD_ULEB128[ ]*L2
+[ ]*3:[ ]*R_LARCH_SUB_ULEB128[ ]*L1
+[ ]*\.\.\.
+
+[ ]*0000000000000005[ ]*<L1>:
+[ ]*\.\.\.
+[ ]*81:[ ]*ff040000[ ]*\.word[ ]*0xff040000
+[ ]*85:[ ]*cacop[ ]*0x1f,[ ]*\$t3,[ ]*1
+
+[ ]*0000000000000086[ ]*<L2>:
+[ ]*86:[ ]*07060005[ ]*\.word[ ]*0x07060005
+[ ]*8a:[ ]*x86inc\.b[ ]*\$a0
+[ ]*8a:[ ]*R_LARCH_ADD_ULEB128[ ]*L4
+[ ]*8a:[ ]*R_LARCH_SUB_ULEB128[ ]*L3
+
+[ ]*000000000000008d[ ]*<L3>:
+[ ]*\.\.\.
+[ ]*4089:[ ]*ff080000[ ]*\.word[ ]*0xff080000
+[ ]*408d:[ ]*\.word[ ]*0x09ffffff
+
+[ ]*0000000000004090[ ]*<L4>:
+[ ]*4090:[ ]*09090909[ ]*\.word[ ]*0x09090909
+[ ]*4094:[ ]*09090909[ ]*\.word[ ]*0x09090909
+[ ]*4098:[ ]*09090909[ ]*\.word[ ]*0x09090909
+[ ]*409c:[ ]*09090909[ ]*\.word[ ]*0x09090909
diff --git a/include/opcode/loongarch.h b/include/opcode/loongarch.h
index 6d399f70a98..e145db5e8a6 100644
--- a/include/opcode/loongarch.h
+++ b/include/opcode/loongarch.h
@@ -211,6 +211,9 @@ dec2 : [1-9][0-9]?
int use_lsx;
int use_lasx;
+ int use_lvz;
+ int use_lbt;
+
int use_la_local_with_abs;
int use_la_global_with_pcrel;
int use_la_global_with_abs;
@@ -225,6 +228,9 @@ dec2 : [1-9][0-9]?
#define ase_lsx isa.use_lsx
#define ase_lasx isa.use_lasx
+#define ase_lvz isa.use_lvz
+#define ase_lbt isa.use_lbt
+
#define ase_labs isa.use_la_local_with_abs
#define ase_gpcr isa.use_la_global_with_pcrel
#define ase_gabs isa.use_la_global_with_abs
diff --git a/opcodes/loongarch-dis.c b/opcodes/loongarch-dis.c
index 8d72519be9f..1e711f27415 100644
--- a/opcodes/loongarch-dis.c
+++ b/opcodes/loongarch-dis.c
@@ -79,6 +79,8 @@ set_default_loongarch_dis_options (void)
LARCH_opts.ase_df = 1;
LARCH_opts.ase_lsx = 1;
LARCH_opts.ase_lasx = 1;
+ LARCH_opts.ase_lvz = 1;
+ LARCH_opts.ase_lbt = 1;
loongarch_r_disname = loongarch_r_lp64_name;
loongarch_f_disname = loongarch_f_lp64_name;
diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c
index 05cf4eb463c..e2259177445 100644
--- a/opcodes/loongarch-opc.c
+++ b/opcodes/loongarch-opc.c
@@ -1664,6 +1664,7 @@ static struct loongarch_opcode loongarch_lsx_opcodes[] =
{ 0x73e40000, 0xfffc0000, "vpermi.w", "v0:5,v5:5,u10:8", 0, 0, 0, 0},
{ 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */
};
+
static struct loongarch_opcode loongarch_lasx_opcodes[] =
{
/* match, mask, name, format, macro, include, exclude, pinfo. */
@@ -2339,6 +2340,199 @@ static struct loongarch_opcode loongarch_lasx_opcodes[] =
{ 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */
};
+static struct loongarch_opcode loongarch_lvz_opcodes[] =
+{
+ /* match, mask, name, format, macro, include, exclude, pinfo. */
+ {0x05000000, 0xff0003e0, "gcsrrd", "r0:5,u10:14", 0, 0, 0, 0},
+ {0x05000020, 0xff0003e0, "gcsrwr", "r0:5,u10:14", 0, 0, 0, 0},
+ {0x05000000, 0xff000000, "gcsrxchg", "r0:5,r5:5,u10:14", 0, 0, 0, 0},
+ {0x06482401, 0xffffffff, "gtlbflush", "", 0, 0, 0, 0},
+ {0x002b8000, 0xffff8000, "hvcl", "u0:15", 0, 0, 0, 0},
+ { 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */
+};
+
+static struct loongarch_opcode loongarch_lbt_opcodes[] =
+{
+ /* match, mask, name, format, macro, include, exclude, pinfo. */
+ {0x00000800, 0xfffffc1c, "movgr2scr", "cr0:2,r5:5", 0, 0, 0, 0},
+ {0x00000c00, 0xffffff80, "movscr2gr", "r0:5,cr5:2", 0, 0, 0, 0},
+ {0x48000200, 0xfc0003e0, "jiscr0", "s0:5|10:16<<2", 0, 0, 0, 0},
+ {0x48000300, 0xfc0003e0, "jiscr1", "s0:5|10:16<<2", 0, 0, 0, 0},
+ {0x00290000, 0xffff8000, "addu12i.w", "r0:5,r5:5,s10:5", 0, 0, 0, 0},
+ {0x00298000, 0xffff8000, "addu12i.d", "r0:5,r5:5,s10:5", 0, 0, 0, 0},
+ {0x00300000, 0xffff8000, "adc.b", "r0:5,r5:5,r10:5", 0, 0, 0, 0},
+ {0x00308000, 0xffff8000, "adc.h", "r0:5,r5:5,r10:5", 0, 0, 0, 0},
+ {0x00310000, 0xffff8000, "adc.w", "r0:5,r5:5,r10:5", 0, 0, 0, 0},
+ {0x00318000, 0xffff8000, "adc.d", "r0:5,r5:5,r10:5", 0, 0, 0, 0},
+ {0x00320000, 0xffff8000, "sbc.b", "r0:5,r5:5,r10:5", 0, 0, 0, 0},
+ {0x00328000, 0xffff8000, "sbc.h", "r0:5,r5:5,r10:5", 0, 0, 0, 0},
+ {0x00330000, 0xffff8000, "sbc.w", "r0:5,r5:5,r10:5", 0, 0, 0, 0},
+ {0x00338000, 0xffff8000, "sbc.d", "r0:5,r5:5,r10:5", 0, 0, 0, 0},
+ {0x001a0000, 0xffff8000, "rotr.b", "r0:5,r5:5,r10:5", 0, 0, 0, 0},
+ {0x001a8000, 0xffff8000, "rotr.h", "r0:5,r5:5,r10:5", 0, 0, 0, 0},
+ {0x004c2000, 0xffffe000, "rotri.b", "r0:5,r5:5,u10:3", 0, 0, 0, 0},
+ {0x004c4000, 0xffffc000, "rotri.h", "r0:5,r5:5,u10:4", 0, 0, 0, 0},
+ {0x00340000, 0xffff8000, "rcr.b", "r0:5,r5:5,r10:5", 0, 0, 0, 0},
+ {0x00348000, 0xffff8000, "rcr.h", "r0:5,r5:5,r10:5", 0, 0, 0, 0},
+ {0x00350000, 0xffff8000, "rcr.w", "r0:5,r5:5,r10:5", 0, 0, 0, 0},
+ {0x00358000, 0xffff8000, "rcr.d", "r0:5,r5:5,r10:5", 0, 0, 0, 0},
+ {0x00502000, 0xffffe000, "rcri.b", "r0:5,r5:5,u10:3", 0, 0, 0, 0},
+ {0x00504000, 0xffffc000, "rcri.h", "r0:5,r5:5,u10:4", 0, 0, 0, 0},
+ {0x00508000, 0xffff8000, "rcri.w", "r0:5,r5:5,u10:5", 0, 0, 0, 0},
+ {0x00510000, 0xffff0000, "rcri.d", "r0:5,r5:5,u10:6", 0, 0, 0, 0},
+ {0x0114e400, 0xfffffc00, "fcvt.ud.d", "f0:5,f5:5", 0, 0, 0, 0},
+ {0x0114e000, 0xfffffc00, "fcvt.ld.d", "f0:5,f5:5", 0, 0, 0, 0},
+ {0x01150000, 0xffff8000, "fcvt.d.ld", "f0:5,f5:5,f10:5", 0, 0, 0, 0},
+ {0x2e800000, 0xffc00000, "ldl.d", "r0:5,r5:5,s10:12", 0, 0, 0, 0},
+ {0x2e000000, 0xffc00000, "ldl.w", "r0:5,r5:5,s10:12", 0, 0, 0, 0},
+ {0x2e400000, 0xffc00000, "ldr.w", "r0:5,r5:5,s10:12", 0, 0, 0, 0},
+ {0x2ec00000, 0xffc00000, "ldr.d", "r0:5,r5:5,s10:12", 0, 0, 0, 0},
+ {0x2f000000, 0xffc00000, "stl.w", "r0:5,r5:5,s10:12", 0, 0, 0, 0},
+ {0x2f800000, 0xffc00000, "stl.d", "r0:5,r5:5,s10:12", 0, 0, 0, 0},
+ {0x2f400000, 0xffc00000, "str.w", "r0:5,r5:5,s10:12", 0, 0, 0, 0},
+ {0x2fc00000, 0xffc00000, "str.d", "r0:5,r5:5,s10:12", 0, 0, 0, 0},
+ {0x003f000c, 0xffff801f, "x86adc.b", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f000d, 0xffff801f, "x86adc.h", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f000e, 0xffff801f, "x86adc.w", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f000f, 0xffff801f, "x86adc.d", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f0004, 0xffff801f, "x86add.b", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f0005, 0xffff801f, "x86add.h", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f0006, 0xffff801f, "x86add.w", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f0007, 0xffff801f, "x86add.d", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f0000, 0xffff801f, "x86add.wu", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f0001, 0xffff801f, "x86add.du", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x00008000, 0xfffffc1f, "x86inc.b", "r5:5", 0, 0, 0, 0},
+ {0x00008001, 0xfffffc1f, "x86inc.h", "r5:5", 0, 0, 0, 0},
+ {0x00008002, 0xfffffc1f, "x86inc.w", "r5:5", 0, 0, 0, 0},
+ {0x00008003, 0xfffffc1f, "x86inc.d", "r5:5", 0, 0, 0, 0},
+ {0x003f0010, 0xffff801f, "x86sbc.b", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f0011, 0xffff801f, "x86sbc.h", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f0012, 0xffff801f, "x86sbc.w", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f0013, 0xffff801f, "x86sbc.d", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f0008, 0xffff801f, "x86sub.b", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f0009, 0xffff801f, "x86sub.h", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f000a, 0xffff801f, "x86sub.w", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f000b, 0xffff801f, "x86sub.d", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f0002, 0xffff801f, "x86sub.wu", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f0003, 0xffff801f, "x86sub.du", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x00008004, 0xfffffc1f, "x86dec.b", "r5:5", 0, 0, 0, 0},
+ {0x00008005, 0xfffffc1f, "x86dec.h", "r5:5", 0, 0, 0, 0},
+ {0x00008006, 0xfffffc1f, "x86dec.w", "r5:5", 0, 0, 0, 0},
+ {0x00008007, 0xfffffc1f, "x86dec.d", "r5:5", 0, 0, 0, 0},
+ {0x003f8010, 0xffff801f, "x86and.b", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f8011, 0xffff801f, "x86and.h", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f8012, 0xffff801f, "x86and.w", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f8013, 0xffff801f, "x86and.d", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f8014, 0xffff801f, "x86or.b", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f8015, 0xffff801f, "x86or.h", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f8016, 0xffff801f, "x86or.w", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f8017, 0xffff801f, "x86or.d", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f8018, 0xffff801f, "x86xor.b", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f8019, 0xffff801f, "x86xor.h", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f801a, 0xffff801f, "x86xor.w", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f801b, 0xffff801f, "x86xor.d", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003e8000, 0xffff801f, "x86mul.b", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003e8001, 0xffff801f, "x86mul.h", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003e8002, 0xffff801f, "x86mul.w", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003e8003, 0xffff801f, "x86mul.d", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003e8004, 0xffff801f, "x86mul.bu", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003e8005, 0xffff801f, "x86mul.hu", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003e8006, 0xffff801f, "x86mul.wu", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003e8007, 0xffff801f, "x86mul.du", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f800c, 0xffff801f, "x86rcl.b", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f800d, 0xffff801f, "x86rcl.h", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f800e, 0xffff801f, "x86rcl.w", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f800f, 0xffff801f, "x86rcl.d", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x00542018, 0xffffe01f, "x86rcli.b", "r5:5,u10:3", 0, 0, 0, 0},
+ {0x00544019, 0xffffc01f, "x86rcli.h", "r5:5,u10:4", 0, 0, 0, 0},
+ {0x0054801a, 0xffff801f, "x86rcli.w", "r5:5,u10:5", 0, 0, 0, 0},
+ {0x0055001b, 0xffff001f, "x86rcli.d", "r5:5,u10:6", 0, 0, 0, 0},
+ {0x003f8008, 0xffff801f, "x86rcr.b", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f8009, 0xffff801f, "x86rcr.h", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f800a, 0xffff801f, "x86rcr.w", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f800b, 0xffff801f, "x86rcr.d", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x00542010, 0xffffe01f, "x86rcri.b", "r5:5,u10:3", 0, 0, 0, 0},
+ {0x00544011, 0xffffc01f, "x86rcri.h", "r5:5,u10:4", 0, 0, 0, 0},
+ {0x00548012, 0xffff801f, "x86rcri.w", "r5:5,u10:5", 0, 0, 0, 0},
+ {0x00550013, 0xffff001f, "x86rcri.d", "r5:5,u10:6", 0, 0, 0, 0},
+ {0x003f8004, 0xffff801f, "x86rotl.b", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f8005, 0xffff801f, "x86rotl.h", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f8006, 0xffff801f, "x86rotl.w", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f8007, 0xffff801f, "x86rotl.d", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x00542014, 0xffffe01f, "x86rotli.b", "r5:5,u10:3", 0, 0, 0, 0},
+ {0x00544015, 0xffffc01f, "x86rotli.h", "r5:5,u10:4", 0, 0, 0, 0},
+ {0x00548016, 0xffff801f, "x86rotli.w", "r5:5,u10:5", 0, 0, 0, 0},
+ {0x00550017, 0xffff001f, "x86rotli.d", "r5:5,u10:6", 0, 0, 0, 0},
+ {0x003f8000, 0xffff801f, "x86rotr.b", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f8001, 0xffff801f, "x86rotr.h", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f8002, 0xffff801f, "x86rotr.d", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f8003, 0xffff801f, "x86rotr.w", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x0054200c, 0xffffe01f, "x86rotri.b", "r5:5,u10:3", 0, 0, 0, 0},
+ {0x0054400d, 0xffffc01f, "x86rotri.h", "r5:5,u10:4", 0, 0, 0, 0},
+ {0x0054800e, 0xffff801f, "x86rotri.w", "r5:5,u10:5", 0, 0, 0, 0},
+ {0x0055000f, 0xffff001f, "x86rotri.d", "r5:5,u10:6", 0, 0, 0, 0},
+ {0x003f0014, 0xffff801f, "x86sll.b", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f0015, 0xffff801f, "x86sll.h", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f0016, 0xffff801f, "x86sll.w", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f0017, 0xffff801f, "x86sll.d", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x00542000, 0xffffe01f, "x86slli.b", "r5:5,u10:3", 0, 0, 0, 0},
+ {0x00544001, 0xffffc01f, "x86slli.h", "r5:5,u10:4", 0, 0, 0, 0},
+ {0x00548002, 0xffff801f, "x86slli.w", "r5:5,u10:5", 0, 0, 0, 0},
+ {0x00550003, 0xffff001f, "x86slli.d", "r5:5,u10:6", 0, 0, 0, 0},
+ {0x003f0018, 0xffff801f, "x86srl.b", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f0019, 0xffff801f, "x86srl.h", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f001a, 0xffff801f, "x86srl.w", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f001b, 0xffff801f, "x86srl.d", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x00542004, 0xffffe01f, "x86srli.b", "r5:5,u10:3", 0, 0, 0, 0},
+ {0x00544005, 0xffffc01f, "x86srli.h", "r5:5,u10:4", 0, 0, 0, 0},
+ {0x00548006, 0xffff801f, "x86srli.w", "r5:5,u10:5", 0, 0, 0, 0},
+ {0x00550007, 0xffff001f, "x86srli.d", "r5:5,u10:6", 0, 0, 0, 0},
+ {0x003f001c, 0xffff801f, "x86sra.b", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f001d, 0xffff801f, "x86sra.h", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f001e, 0xffff801f, "x86sra.w", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x003f001f, 0xffff801f, "x86sra.d", "r5:5,r10:5", 0, 0, 0, 0},
+ {0x00542008, 0xffffe01f, "x86srai.b", "r5:5,u10:3", 0, 0, 0, 0},
+ {0x00544009, 0xffffc01f, "x86srai.h", "r5:5,u10:4", 0, 0, 0, 0},
+ {0x0054800a, 0xffff801f, "x86srai.w", "r5:5,u10:5", 0, 0, 0, 0},
+ {0x0055000b, 0xffff001f, "x86srai.d", "r5:5,u10:6", 0, 0, 0, 0},
+ {0x00368000, 0xffffc3e0, "setx86j", "r0:5,u10:4", 0, 0, 0, 0},
+ {0x00007800, 0xfffffc00, "setx86loope", "r0:5,r5:5", 0, 0, 0, 0},
+ {0x00007c00, 0xfffffc00, "setx86loopne", "r0:5,r5:5", 0, 0, 0, 0},
+ {0x005c0000, 0xfffc03e0, "x86mfflag", "r0:5,u10:8", 0, 0, 0, 0},
+ {0x005c0020, 0xfffc03e0, "x86mtflag", "r0:5,u10:8", 0, 0, 0, 0},
+ {0x00007400, 0xffffffe0, "x86mftop", "r0:5", 0, 0, 0, 0},
+ {0x00007000, 0xffffff1f, "x86mttop", "u5:3", 0, 0, 0, 0},
+ {0x00008009, 0xffffffff, "x86inctop", "", 0, 0, 0, 0},
+ {0x00008029, 0xffffffff, "x86dectop", "", 0, 0, 0, 0},
+ {0x00008008, 0xffffffff, "x86settm", "", 0, 0, 0, 0},
+ {0x00008028, 0xffffffff, "x86clrtm", "", 0, 0, 0, 0},
+ {0x00580000, 0xfffc0000, "x86settag", "r0:5,u5:5,u10:8", 0, 0, 0, 0},
+ {0x00370010, 0xffff8010, "armadd.w", "r5:5,r10:5,u0:4", 0, 0, 0, 0},
+ {0x00378010, 0xffff8010, "armsub.w", "r5:5,r10:5,u0:4", 0, 0, 0, 0},
+ {0x00380010, 0xffff8010, "armadc.w", "r5:5,r10:5,u0:4", 0, 0, 0, 0},
+ {0x00388010, 0xffff8010, "armsbc.w", "r5:5,r10:5,u0:4", 0, 0, 0, 0},
+ {0x00390010, 0xffff8010, "armand.w", "r5:5,r10:5,u0:4", 0, 0, 0, 0},
+ {0x00398010, 0xffff8010, "armor.w", "r5:5,r10:5,u0:4", 0, 0, 0, 0},
+ {0x003a0010, 0xffff8010, "armxor.w", "r5:5,r10:5,u0:4", 0, 0, 0, 0},
+ {0x003fc01c, 0xffffc01f, "armnot.w", "r5:5,u10:4", 0, 0, 0, 0},
+ {0x003a8010, 0xffff8010, "armsll.w", "r5:5,r10:5,u0:4", 0, 0, 0, 0},
+ {0x003b0010, 0xffff8010, "armsrl.w", "r5:5,r10:5,u0:4", 0, 0, 0, 0},
+ {0x003b8010, 0xffff8010, "armsra.w", "r5:5,r10:5,u0:4", 0, 0, 0, 0},
+ {0x003c0010, 0xffff8010, "armrotr.w", "r5:5,r10:5,u0:4", 0, 0, 0, 0},
+ {0x003c8010, 0xffff8010, "armslli.w", "r5:5,u10:5,u0:4", 0, 0, 0, 0},
+ {0x003d0010, 0xffff8010, "armsrli.w", "r5:5,u10:5,u0:4", 0, 0, 0, 0},
+ {0x003d8010, 0xffff8010, "armsrai.w", "r5:5,u10:5,u0:4", 0, 0, 0, 0},
+ {0x003e0010, 0xffff8010, "armrotri.w", "r5:5,u10:5,u0:4", 0, 0, 0, 0},
+ {0x003fc01f, 0xffffc01f, "armrrx.w", "r5:5,u10:4", 0, 0, 0, 0},
+ {0x00364000, 0xffffc000, "armmove", "r0:5,r5:5,u10:4", 0, 0, 0, 0},
+ {0x003fc01d, 0xffffc01f, "armmov.w", "r5:5,u10:4", 0, 0, 0, 0},
+ {0x003fc01e, 0xffffc01f, "armmov.d", "r5:5,u10:4", 0, 0, 0, 0},
+ {0x005c0040, 0xfffc03e0, "armmfflag", "r0:5,u10:8", 0, 0, 0, 0},
+ {0x005c0060, 0xfffc03e0, "armmtflag", "r0:5,u10:8", 0, 0, 0, 0},
+ {0x0036c000, 0xffffc3e0, "setarmj", "r0:5,u10:4", 0, 0, 0, 0},
+ { 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */
+};
+
struct loongarch_ase loongarch_ASEs[] =
{
{ &LARCH_opts.ase_ilp32, loongarch_macro_opcodes, 0, 0, { 0 }, 0, 0 },
@@ -2355,7 +2549,9 @@ struct loongarch_ase loongarch_ASEs[] =
{ &LARCH_opts.ase_df, loongarch_4opt_double_float_opcodes, 0, 0, { 0 }, 0, 0 },
{ &LARCH_opts.ase_sf, loongarch_single_float_load_store_opcodes, 0, 0, { 0 }, 0, 0 },
{ &LARCH_opts.ase_df, loongarch_double_float_load_store_opcodes, 0, 0, { 0 }, 0, 0 },
- { &LARCH_opts.ase_lsx, loongarch_lsx_opcodes, 0, 0, { 0}, 0, 0 },
- { &LARCH_opts.ase_lasx, loongarch_lasx_opcodes, 0, 0, { 0}, 0, 0 },
+ { &LARCH_opts.ase_lsx, loongarch_lsx_opcodes, 0, 0, { 0 }, 0, 0 },
+ { &LARCH_opts.ase_lasx, loongarch_lasx_opcodes, 0, 0, { 0 }, 0, 0 },
+ { &LARCH_opts.ase_lvz, loongarch_lvz_opcodes, 0, 0, { 0 }, 0, 0 },
+ { &LARCH_opts.ase_lbt, loongarch_lbt_opcodes, 0, 0, { 0 }, 0, 0 },
{ 0, 0, 0, 0, { 0 }, 0, 0 },
};
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2023-06-30 9:35 [binutils-gdb] LoongArch: gas: Add LVZ and LBT instructions support liu & zhensong
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