* [binutils-gdb] x86: optimize pre-AVX512 {, V}PCMPGT* with identical sources
@ 2023-07-04 15:07 Jan Beulich
0 siblings, 0 replies; only message in thread
From: Jan Beulich @ 2023-07-04 15:07 UTC (permalink / raw)
To: bfd-cvs
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=33889538969edd801bdaf5422c863fe2a0b7cf45
commit 33889538969edd801bdaf5422c863fe2a0b7cf45
Author: Jan Beulich <jbeulich@suse.com>
Date: Tue Jul 4 17:06:51 2023 +0200
x86: optimize pre-AVX512 {,V}PCMPGT* with identical sources
These are better expressed by the zeroing idiom {,V}PXOR. In some cases
this also results in a shorter encoding.
Diff:
---
gas/config/tc-i386.c | 40 +++++
gas/testsuite/gas/i386/optimize-1.d | 15 ++
gas/testsuite/gas/i386/optimize-1.s | 19 +++
gas/testsuite/gas/i386/optimize-1a.d | 15 ++
gas/testsuite/gas/i386/optimize-4.d | 15 ++
gas/testsuite/gas/i386/optimize-5.d | 15 ++
gas/testsuite/gas/i386/x86-64-optimize-2.d | 19 +++
gas/testsuite/gas/i386/x86-64-optimize-2.s | 23 +++
gas/testsuite/gas/i386/x86-64-optimize-2a.d | 19 +++
gas/testsuite/gas/i386/x86-64-optimize-2b.d | 19 +++
gas/testsuite/gas/i386/x86-64-optimize-2c.d | 226 ++++++++++++++++++++++++++++
gas/testsuite/gas/i386/x86-64-optimize-5.d | 19 +++
gas/testsuite/gas/i386/x86-64-optimize-6.d | 19 +++
gas/testsuite/gas/i386/x86-64.exp | 1 +
opcodes/i386-opc.tbl | 12 +-
opcodes/i386-tbl.h | 30 ++--
16 files changed, 485 insertions(+), 21 deletions(-)
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index eb3f128e6ef..8ebeaf1ab84 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -4580,6 +4580,46 @@ optimize_encoding (void)
i.tm.opcode_space = SPACE_0F;
i.tm.base_opcode = 0x76;
}
+ else if (((i.tm.base_opcode >= 0x64
+ && i.tm.base_opcode <= 0x66
+ && i.tm.opcode_space == SPACE_0F)
+ || (i.tm.base_opcode == 0x37
+ && i.tm.opcode_space == SPACE_0F38))
+ && i.operands == i.reg_operands
+ && i.op[0].regs == i.op[1].regs
+ && !is_evex_encoding (&i.tm))
+ {
+ /* Optimize: -O:
+ pcmpgt[bwd] %mmN, %mmN -> pxor %mmN, %mmN
+ pcmpgt[bwdq] %xmmN, %xmmN -> pxor %xmmN, %xmmN
+ vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM -> vpxor %xmmN, %xmmN, %xmmM (N < 8)
+ vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM -> vpxor %xmm0, %xmm0, %xmmM (N > 7)
+ vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM -> vpxor %ymmN, %ymmN, %ymmM (N < 8)
+ vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM -> vpxor %ymm0, %ymm0, %ymmM (N > 7)
+ */
+ i.tm.opcode_space = SPACE_0F;
+ i.tm.base_opcode = 0xef;
+ if (i.tm.opcode_modifier.vex && (i.op[0].regs->reg_flags & RegRex))
+ {
+ if (i.operands == 2)
+ {
+ gas_assert (i.tm.opcode_modifier.sse2avx);
+
+ i.operands = 3;
+ i.reg_operands = 3;
+ i.tm.operands = 3;
+
+ i.op[2].regs = i.op[0].regs;
+ i.types[2] = i.types[0];
+ i.flags[2] = i.flags[0];
+ i.tm.operand_types[2] = i.tm.operand_types[0];
+
+ i.tm.opcode_modifier.sse2avx = 0;
+ }
+ i.op[0].regs -= i.op[0].regs->reg_num + 8;
+ i.op[1].regs = i.op[0].regs;
+ }
+ }
}
/* Return non-zero for load instruction. */
diff --git a/gas/testsuite/gas/i386/optimize-1.d b/gas/testsuite/gas/i386/optimize-1.d
index f6c54b7c4a5..23d715c27d5 100644
--- a/gas/testsuite/gas/i386/optimize-1.d
+++ b/gas/testsuite/gas/i386/optimize-1.d
@@ -147,6 +147,21 @@ Disassembly of section .text:
+[a-f0-9]+: 62 .* vporq 0x80\(%eax\),%ymm2,%ymm3
+[a-f0-9]+: 62 .* vpxord 0x80\(%eax\),%ymm2,%ymm3
+[a-f0-9]+: 62 .* vpxorq 0x80\(%eax\),%ymm2,%ymm3
+ +[a-f0-9]+: 0f .* pxor %mm2,%mm2
+ +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm0
+ +[a-f0-9]+: c5 .* vpxor %ymm2,%ymm2,%ymm0
+ +[a-f0-9]+: 0f .* pxor %mm2,%mm2
+ +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm0
+ +[a-f0-9]+: c5 .* vpxor %ymm2,%ymm2,%ymm0
+ +[a-f0-9]+: 0f .* pxor %mm2,%mm2
+ +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm0
+ +[a-f0-9]+: c5 .* vpxor %ymm2,%ymm2,%ymm0
+ +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm0
+ +[a-f0-9]+: c5 .* vpxor %ymm2,%ymm2,%ymm0
+[a-f0-9]+: 0f ba e0 0f bt \$0xf,%eax
+[a-f0-9]+: 66 0f ba e0 10 bt \$0x10,%ax
+[a-f0-9]+: 0f ba f8 0f btc \$0xf,%eax
diff --git a/gas/testsuite/gas/i386/optimize-1.s b/gas/testsuite/gas/i386/optimize-1.s
index 53a0dd7aec3..e253142db0c 100644
--- a/gas/testsuite/gas/i386/optimize-1.s
+++ b/gas/testsuite/gas/i386/optimize-1.s
@@ -171,6 +171,25 @@ _start:
vpxord 128(%eax), %ymm2, %ymm3
vpxorq 128(%eax), %ymm2, %ymm3
+ pcmpgtb %mm2, %mm2
+ pcmpgtb %xmm2, %xmm2
+ vpcmpgtb %xmm2, %xmm2, %xmm0
+ vpcmpgtb %ymm2, %ymm2, %ymm0
+
+ pcmpgtw %mm2, %mm2
+ pcmpgtw %xmm2, %xmm2
+ vpcmpgtw %xmm2, %xmm2, %xmm0
+ vpcmpgtw %ymm2, %ymm2, %ymm0
+
+ pcmpgtd %mm2, %mm2
+ pcmpgtd %xmm2, %xmm2
+ vpcmpgtd %xmm2, %xmm2, %xmm0
+ vpcmpgtd %ymm2, %ymm2, %ymm0
+
+ pcmpgtq %xmm2, %xmm2
+ vpcmpgtq %xmm2, %xmm2, %xmm0
+ vpcmpgtq %ymm2, %ymm2, %ymm0
+
bt $15, %ax
bt $16, %ax
btc $15, %ax
diff --git a/gas/testsuite/gas/i386/optimize-1a.d b/gas/testsuite/gas/i386/optimize-1a.d
index d0bf1b4c796..33c647bf5c6 100644
--- a/gas/testsuite/gas/i386/optimize-1a.d
+++ b/gas/testsuite/gas/i386/optimize-1a.d
@@ -148,6 +148,21 @@ Disassembly of section .text:
+[a-f0-9]+: 62 .* vporq 0x80\(%eax\),%ymm2,%ymm3
+[a-f0-9]+: 62 .* vpxord 0x80\(%eax\),%ymm2,%ymm3
+[a-f0-9]+: 62 .* vpxorq 0x80\(%eax\),%ymm2,%ymm3
+ +[a-f0-9]+: 0f .* pxor %mm2,%mm2
+ +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm0
+ +[a-f0-9]+: c5 .* vpxor %ymm2,%ymm2,%ymm0
+ +[a-f0-9]+: 0f .* pxor %mm2,%mm2
+ +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm0
+ +[a-f0-9]+: c5 .* vpxor %ymm2,%ymm2,%ymm0
+ +[a-f0-9]+: 0f .* pxor %mm2,%mm2
+ +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm0
+ +[a-f0-9]+: c5 .* vpxor %ymm2,%ymm2,%ymm0
+ +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm0
+ +[a-f0-9]+: c5 .* vpxor %ymm2,%ymm2,%ymm0
+[a-f0-9]+: 0f ba e0 0f bt \$0xf,%eax
+[a-f0-9]+: 66 0f ba e0 10 bt \$0x10,%ax
+[a-f0-9]+: 0f ba f8 0f btc \$0xf,%eax
diff --git a/gas/testsuite/gas/i386/optimize-4.d b/gas/testsuite/gas/i386/optimize-4.d
index 092d078706e..fa9b95fe8fe 100644
--- a/gas/testsuite/gas/i386/optimize-4.d
+++ b/gas/testsuite/gas/i386/optimize-4.d
@@ -147,6 +147,21 @@ Disassembly of section .text:
+[a-f0-9]+: 62 .* vporq 0x80\(%eax\),%ymm2,%ymm3
+[a-f0-9]+: 62 .* vpxord 0x80\(%eax\),%ymm2,%ymm3
+[a-f0-9]+: 62 .* vpxorq 0x80\(%eax\),%ymm2,%ymm3
+ +[a-f0-9]+: 0f .* pxor %mm2,%mm2
+ +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm0
+ +[a-f0-9]+: c5 .* vpxor %ymm2,%ymm2,%ymm0
+ +[a-f0-9]+: 0f .* pxor %mm2,%mm2
+ +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm0
+ +[a-f0-9]+: c5 .* vpxor %ymm2,%ymm2,%ymm0
+ +[a-f0-9]+: 0f .* pxor %mm2,%mm2
+ +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm0
+ +[a-f0-9]+: c5 .* vpxor %ymm2,%ymm2,%ymm0
+ +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm0
+ +[a-f0-9]+: c5 .* vpxor %ymm2,%ymm2,%ymm0
+[a-f0-9]+: 0f ba e0 0f bt \$0xf,%eax
+[a-f0-9]+: 66 0f ba e0 10 bt \$0x10,%ax
+[a-f0-9]+: 0f ba f8 0f btc \$0xf,%eax
diff --git a/gas/testsuite/gas/i386/optimize-5.d b/gas/testsuite/gas/i386/optimize-5.d
index 1d1397be9b2..36d0ba96e54 100644
--- a/gas/testsuite/gas/i386/optimize-5.d
+++ b/gas/testsuite/gas/i386/optimize-5.d
@@ -147,6 +147,21 @@ Disassembly of section .text:
+[a-f0-9]+: 62 .* vporq 0x80\(%eax\),%ymm2,%ymm3
+[a-f0-9]+: 62 .* vpxord 0x80\(%eax\),%ymm2,%ymm3
+[a-f0-9]+: 62 .* vpxorq 0x80\(%eax\),%ymm2,%ymm3
+ +[a-f0-9]+: 0f .* pxor %mm2,%mm2
+ +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm0
+ +[a-f0-9]+: c5 .* vpxor %ymm2,%ymm2,%ymm0
+ +[a-f0-9]+: 0f .* pxor %mm2,%mm2
+ +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm0
+ +[a-f0-9]+: c5 .* vpxor %ymm2,%ymm2,%ymm0
+ +[a-f0-9]+: 0f .* pxor %mm2,%mm2
+ +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm0
+ +[a-f0-9]+: c5 .* vpxor %ymm2,%ymm2,%ymm0
+ +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm0
+ +[a-f0-9]+: c5 .* vpxor %ymm2,%ymm2,%ymm0
+[a-f0-9]+: 0f ba e0 0f bt \$0xf,%eax
+[a-f0-9]+: 66 0f ba e0 10 bt \$0x10,%ax
+[a-f0-9]+: 0f ba f8 0f btc \$0xf,%eax
diff --git a/gas/testsuite/gas/i386/x86-64-optimize-2.d b/gas/testsuite/gas/i386/x86-64-optimize-2.d
index cb6b81537be..87bf3edfbaa 100644
--- a/gas/testsuite/gas/i386/x86-64-optimize-2.d
+++ b/gas/testsuite/gas/i386/x86-64-optimize-2.d
@@ -203,4 +203,23 @@ Disassembly of section .text:
+[a-f0-9]+: 62 .* vporq 0x80\(%rax\),%ymm2,%ymm3
+[a-f0-9]+: 62 .* vpxord 0x80\(%rax\),%ymm2,%ymm3
+[a-f0-9]+: 62 .* vpxorq 0x80\(%rax\),%ymm2,%ymm3
+ +[a-f0-9]+: 0f .* pxor %mm2,%mm2
+ +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2
+ +[a-f0-9]+: 66 .* pxor %xmm12,%xmm12
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm8
+ +[a-f0-9]+: c5 .* vpxor %ymm0,%ymm0,%ymm1
+ +[a-f0-9]+: 0f .* pxor %mm2,%mm2
+ +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2
+ +[a-f0-9]+: 66 .* pxor %xmm12,%xmm12
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm8
+ +[a-f0-9]+: c5 .* vpxor %ymm0,%ymm0,%ymm1
+ +[a-f0-9]+: 0f .* pxor %mm2,%mm2
+ +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2
+ +[a-f0-9]+: 66 .* pxor %xmm12,%xmm12
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm8
+ +[a-f0-9]+: c5 .* vpxor %ymm0,%ymm0,%ymm1
+ +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2
+ +[a-f0-9]+: 66 .* pxor %xmm12,%xmm12
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm8
+ +[a-f0-9]+: c5 .* vpxor %ymm0,%ymm0,%ymm1
#pass
diff --git a/gas/testsuite/gas/i386/x86-64-optimize-2.s b/gas/testsuite/gas/i386/x86-64-optimize-2.s
index 22dbd1ce469..3d16a7875a3 100644
--- a/gas/testsuite/gas/i386/x86-64-optimize-2.s
+++ b/gas/testsuite/gas/i386/x86-64-optimize-2.s
@@ -226,3 +226,26 @@ _start:
vporq 128(%rax), %ymm2, %ymm3
vpxord 128(%rax), %ymm2, %ymm3
vpxorq 128(%rax), %ymm2, %ymm3
+
+ pcmpgtb %mm2, %mm2
+ pcmpgtb %xmm2, %xmm2
+ pcmpgtb %xmm12, %xmm12
+ vpcmpgtb %xmm2, %xmm2, %xmm8
+ vpcmpgtb %ymm12, %ymm12, %ymm1
+
+ pcmpgtw %mm2, %mm2
+ pcmpgtw %xmm2, %xmm2
+ pcmpgtw %xmm12, %xmm12
+ vpcmpgtw %xmm2, %xmm2, %xmm8
+ vpcmpgtw %ymm12, %ymm12, %ymm1
+
+ pcmpgtd %mm2, %mm2
+ pcmpgtd %xmm2, %xmm2
+ pcmpgtd %xmm12, %xmm12
+ vpcmpgtd %xmm2, %xmm2, %xmm8
+ vpcmpgtd %ymm12, %ymm12, %ymm1
+
+ pcmpgtq %xmm2, %xmm2
+ pcmpgtq %xmm12, %xmm12
+ vpcmpgtq %xmm2, %xmm2, %xmm8
+ vpcmpgtq %ymm12, %ymm12, %ymm1
diff --git a/gas/testsuite/gas/i386/x86-64-optimize-2a.d b/gas/testsuite/gas/i386/x86-64-optimize-2a.d
index 70a8ff31475..f12507b8f55 100644
--- a/gas/testsuite/gas/i386/x86-64-optimize-2a.d
+++ b/gas/testsuite/gas/i386/x86-64-optimize-2a.d
@@ -204,4 +204,23 @@ Disassembly of section .text:
+[a-f0-9]+: 62 .* vporq 0x80\(%rax\),%ymm2,%ymm3
+[a-f0-9]+: 62 .* vpxord 0x80\(%rax\),%ymm2,%ymm3
+[a-f0-9]+: 62 .* vpxorq 0x80\(%rax\),%ymm2,%ymm3
+ +[a-f0-9]+: 0f .* pxor %mm2,%mm2
+ +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2
+ +[a-f0-9]+: 66 .* pxor %xmm12,%xmm12
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm8
+ +[a-f0-9]+: c5 .* vpxor %ymm0,%ymm0,%ymm1
+ +[a-f0-9]+: 0f .* pxor %mm2,%mm2
+ +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2
+ +[a-f0-9]+: 66 .* pxor %xmm12,%xmm12
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm8
+ +[a-f0-9]+: c5 .* vpxor %ymm0,%ymm0,%ymm1
+ +[a-f0-9]+: 0f .* pxor %mm2,%mm2
+ +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2
+ +[a-f0-9]+: 66 .* pxor %xmm12,%xmm12
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm8
+ +[a-f0-9]+: c5 .* vpxor %ymm0,%ymm0,%ymm1
+ +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2
+ +[a-f0-9]+: 66 .* pxor %xmm12,%xmm12
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm8
+ +[a-f0-9]+: c5 .* vpxor %ymm0,%ymm0,%ymm1
#pass
diff --git a/gas/testsuite/gas/i386/x86-64-optimize-2b.d b/gas/testsuite/gas/i386/x86-64-optimize-2b.d
index 1d815699afc..e572491a9da 100644
--- a/gas/testsuite/gas/i386/x86-64-optimize-2b.d
+++ b/gas/testsuite/gas/i386/x86-64-optimize-2b.d
@@ -203,4 +203,23 @@ Disassembly of section .text:
+[a-f0-9]+: 62 .* vporq 0x80\(%rax\),%ymm2,%ymm3
+[a-f0-9]+: 62 .* vpxord 0x80\(%rax\),%ymm2,%ymm3
+[a-f0-9]+: 62 .* vpxorq 0x80\(%rax\),%ymm2,%ymm3
+ +[a-f0-9]+: 0f .* pxor %mm2,%mm2
+ +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2
+ +[a-f0-9]+: 66 .* pxor %xmm12,%xmm12
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm8
+ +[a-f0-9]+: c5 .* vpxor %ymm0,%ymm0,%ymm1
+ +[a-f0-9]+: 0f .* pxor %mm2,%mm2
+ +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2
+ +[a-f0-9]+: 66 .* pxor %xmm12,%xmm12
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm8
+ +[a-f0-9]+: c5 .* vpxor %ymm0,%ymm0,%ymm1
+ +[a-f0-9]+: 0f .* pxor %mm2,%mm2
+ +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2
+ +[a-f0-9]+: 66 .* pxor %xmm12,%xmm12
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm8
+ +[a-f0-9]+: c5 .* vpxor %ymm0,%ymm0,%ymm1
+ +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2
+ +[a-f0-9]+: 66 .* pxor %xmm12,%xmm12
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm8
+ +[a-f0-9]+: c5 .* vpxor %ymm0,%ymm0,%ymm1
#pass
diff --git a/gas/testsuite/gas/i386/x86-64-optimize-2c.d b/gas/testsuite/gas/i386/x86-64-optimize-2c.d
new file mode 100644
index 00000000000..73a50a35b74
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-optimize-2c.d
@@ -0,0 +1,226 @@
+#source: x86-64-optimize-2.s
+#as: -O -msse2avx
+#objdump: -drw
+#name: x86-64 optimized encoding 2c with -O and SSE2AVX
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+: 62 71 f5 4f 55 f9 vandnpd %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+: c5 71 55 f9 vandnpd %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+: c5 71 55 f9 vandnpd %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+: c5 71 55 f9 vandnpd %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+: 62 e1 f5 48 55 c1 vandnpd %zmm1,%zmm1,%zmm16
+ +[a-f0-9]+: 62 e1 f5 28 55 c1 vandnpd %ymm1,%ymm1,%ymm16
+ +[a-f0-9]+: 62 b1 f5 40 55 c9 vandnpd %zmm17,%zmm17,%zmm1
+ +[a-f0-9]+: 62 b1 f5 20 55 c9 vandnpd %ymm17,%ymm17,%ymm1
+ +[a-f0-9]+: 62 71 74 4f 55 f9 vandnps %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+: c5 70 55 f9 vandnps %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+: c5 70 55 f9 vandnps %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+: c5 70 55 f9 vandnps %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+: 62 e1 74 48 55 c1 vandnps %zmm1,%zmm1,%zmm16
+ +[a-f0-9]+: 62 e1 74 28 55 c1 vandnps %ymm1,%ymm1,%ymm16
+ +[a-f0-9]+: 62 b1 74 40 55 c9 vandnps %zmm17,%zmm17,%zmm1
+ +[a-f0-9]+: 62 b1 74 20 55 c9 vandnps %ymm17,%ymm17,%ymm1
+ +[a-f0-9]+: c5 71 df f9 vpandn %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+: 62 71 75 4f df f9 vpandnd %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+: c5 71 df f9 vpandn %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+: c5 71 df f9 vpandn %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+: c5 71 df f9 vpandn %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+: 62 e1 75 48 df c1 vpandnd %zmm1,%zmm1,%zmm16
+ +[a-f0-9]+: 62 e1 75 28 df c1 vpandnd %ymm1,%ymm1,%ymm16
+ +[a-f0-9]+: 62 b1 75 40 df c9 vpandnd %zmm17,%zmm17,%zmm1
+ +[a-f0-9]+: 62 b1 75 20 df c9 vpandnd %ymm17,%ymm17,%ymm1
+ +[a-f0-9]+: 62 71 f5 4f df f9 vpandnq %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+: c5 71 df f9 vpandn %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+: c5 71 df f9 vpandn %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+: c5 71 df f9 vpandn %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+: 62 e1 f5 48 df c1 vpandnq %zmm1,%zmm1,%zmm16
+ +[a-f0-9]+: 62 e1 f5 28 df c1 vpandnq %ymm1,%ymm1,%ymm16
+ +[a-f0-9]+: 62 b1 f5 40 df c9 vpandnq %zmm17,%zmm17,%zmm1
+ +[a-f0-9]+: 62 b1 f5 20 df c9 vpandnq %ymm17,%ymm17,%ymm1
+ +[a-f0-9]+: 62 71 f5 4f 57 f9 vxorpd %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+: c5 71 57 f9 vxorpd %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+: c5 71 57 f9 vxorpd %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+: c5 71 57 f9 vxorpd %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+: 62 e1 f5 48 57 c1 vxorpd %zmm1,%zmm1,%zmm16
+ +[a-f0-9]+: 62 e1 f5 28 57 c1 vxorpd %ymm1,%ymm1,%ymm16
+ +[a-f0-9]+: 62 b1 f5 40 57 c9 vxorpd %zmm17,%zmm17,%zmm1
+ +[a-f0-9]+: 62 b1 f5 20 57 c9 vxorpd %ymm17,%ymm17,%ymm1
+ +[a-f0-9]+: 62 71 74 4f 57 f9 vxorps %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+: c5 70 57 f9 vxorps %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+: c5 70 57 f9 vxorps %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+: c5 70 57 f9 vxorps %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+: 62 e1 74 48 57 c1 vxorps %zmm1,%zmm1,%zmm16
+ +[a-f0-9]+: 62 e1 74 28 57 c1 vxorps %ymm1,%ymm1,%ymm16
+ +[a-f0-9]+: 62 b1 74 40 57 c9 vxorps %zmm17,%zmm17,%zmm1
+ +[a-f0-9]+: 62 b1 74 20 57 c9 vxorps %ymm17,%ymm17,%ymm1
+ +[a-f0-9]+: c5 71 ef f9 vpxor %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+: 62 71 75 4f ef f9 vpxord %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+: c5 71 ef f9 vpxor %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+: c5 71 ef f9 vpxor %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+: c5 71 ef f9 vpxor %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+: 62 e1 75 48 ef c1 vpxord %zmm1,%zmm1,%zmm16
+ +[a-f0-9]+: 62 e1 75 28 ef c1 vpxord %ymm1,%ymm1,%ymm16
+ +[a-f0-9]+: 62 b1 75 40 ef c9 vpxord %zmm17,%zmm17,%zmm1
+ +[a-f0-9]+: 62 b1 75 20 ef c9 vpxord %ymm17,%ymm17,%ymm1
+ +[a-f0-9]+: 62 71 f5 4f ef f9 vpxorq %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+: c5 71 ef f9 vpxor %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+: c5 71 ef f9 vpxor %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+: c5 71 ef f9 vpxor %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+: 62 e1 f5 48 ef c1 vpxorq %zmm1,%zmm1,%zmm16
+ +[a-f0-9]+: 62 e1 f5 28 ef c1 vpxorq %ymm1,%ymm1,%ymm16
+ +[a-f0-9]+: 62 b1 f5 40 ef c9 vpxorq %zmm17,%zmm17,%zmm1
+ +[a-f0-9]+: 62 b1 f5 20 ef c9 vpxorq %ymm17,%ymm17,%ymm1
+ +[a-f0-9]+: 62 71 75 4f f8 f9 vpsubb %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+: c5 71 f8 f9 vpsubb %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+: c5 71 f8 f9 vpsubb %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+: c5 71 f8 f9 vpsubb %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+: 62 e1 75 48 f8 c1 vpsubb %zmm1,%zmm1,%zmm16
+ +[a-f0-9]+: 62 e1 75 28 f8 c1 vpsubb %ymm1,%ymm1,%ymm16
+ +[a-f0-9]+: 62 b1 75 40 f8 c9 vpsubb %zmm17,%zmm17,%zmm1
+ +[a-f0-9]+: 62 b1 75 20 f8 c9 vpsubb %ymm17,%ymm17,%ymm1
+ +[a-f0-9]+: 62 71 75 4f f9 f9 vpsubw %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+: c5 71 f9 f9 vpsubw %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+: c5 71 f9 f9 vpsubw %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+: c5 71 f9 f9 vpsubw %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+: 62 e1 75 48 f9 c1 vpsubw %zmm1,%zmm1,%zmm16
+ +[a-f0-9]+: 62 e1 75 28 f9 c1 vpsubw %ymm1,%ymm1,%ymm16
+ +[a-f0-9]+: 62 b1 75 40 f9 c9 vpsubw %zmm17,%zmm17,%zmm1
+ +[a-f0-9]+: 62 b1 75 20 f9 c9 vpsubw %ymm17,%ymm17,%ymm1
+ +[a-f0-9]+: 62 71 75 4f fa f9 vpsubd %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+: c5 71 fa f9 vpsubd %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+: c5 71 fa f9 vpsubd %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+: c5 71 fa f9 vpsubd %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+: 62 e1 75 48 fa c1 vpsubd %zmm1,%zmm1,%zmm16
+ +[a-f0-9]+: 62 e1 75 28 fa c1 vpsubd %ymm1,%ymm1,%ymm16
+ +[a-f0-9]+: 62 b1 75 40 fa c9 vpsubd %zmm17,%zmm17,%zmm1
+ +[a-f0-9]+: 62 b1 75 20 fa c9 vpsubd %ymm17,%ymm17,%ymm1
+ +[a-f0-9]+: 62 71 f5 4f fb f9 vpsubq %zmm1,%zmm1,%zmm15\{%k7\}
+ +[a-f0-9]+: c5 71 fb f9 vpsubq %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+: c5 71 fb f9 vpsubq %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+: c5 71 fb f9 vpsubq %xmm1,%xmm1,%xmm15
+ +[a-f0-9]+: 62 e1 f5 48 fb c1 vpsubq %zmm1,%zmm1,%zmm16
+ +[a-f0-9]+: 62 e1 f5 28 fb c1 vpsubq %ymm1,%ymm1,%ymm16
+ +[a-f0-9]+: 62 b1 f5 40 fb c9 vpsubq %zmm17,%zmm17,%zmm1
+ +[a-f0-9]+: 62 b1 f5 20 fb c9 vpsubq %ymm17,%ymm17,%ymm1
+ +[a-f0-9]+: c5 f9 6f d1 vmovdqa %xmm1,%xmm2
+ +[a-f0-9]+: c5 f9 6f d1 vmovdqa %xmm1,%xmm2
+ +[a-f0-9]+: c5 fa 6f d1 vmovdqu %xmm1,%xmm2
+ +[a-f0-9]+: c5 fa 6f d1 vmovdqu %xmm1,%xmm2
+ +[a-f0-9]+: c5 fa 6f d1 vmovdqu %xmm1,%xmm2
+ +[a-f0-9]+: c5 fa 6f d1 vmovdqu %xmm1,%xmm2
+ +[a-f0-9]+: c4 41 79 6f e3 vmovdqa %xmm11,%xmm12
+ +[a-f0-9]+: c4 41 79 6f e3 vmovdqa %xmm11,%xmm12
+ +[a-f0-9]+: c4 41 7a 6f e3 vmovdqu %xmm11,%xmm12
+ +[a-f0-9]+: c4 41 7a 6f e3 vmovdqu %xmm11,%xmm12
+ +[a-f0-9]+: c4 41 7a 6f e3 vmovdqu %xmm11,%xmm12
+ +[a-f0-9]+: c4 41 7a 6f e3 vmovdqu %xmm11,%xmm12
+ +[a-f0-9]+: c5 f9 6f 50 7f vmovdqa 0x7f\(%rax\),%xmm2
+ +[a-f0-9]+: c5 f9 6f 50 7f vmovdqa 0x7f\(%rax\),%xmm2
+ +[a-f0-9]+: c5 fa 6f 50 7f vmovdqu 0x7f\(%rax\),%xmm2
+ +[a-f0-9]+: c5 fa 6f 50 7f vmovdqu 0x7f\(%rax\),%xmm2
+ +[a-f0-9]+: c5 fa 6f 50 7f vmovdqu 0x7f\(%rax\),%xmm2
+ +[a-f0-9]+: c5 fa 6f 50 7f vmovdqu 0x7f\(%rax\),%xmm2
+ +[a-f0-9]+: 62 f1 7d 08 7f 48 08 vmovdqa32 %xmm1,0x80\(%rax\)
+ +[a-f0-9]+: 62 f1 fd 08 7f 48 08 vmovdqa64 %xmm1,0x80\(%rax\)
+ +[a-f0-9]+: 62 f1 7f 08 7f 48 08 vmovdqu8 %xmm1,0x80\(%rax\)
+ +[a-f0-9]+: 62 f1 ff 08 7f 48 08 vmovdqu16 %xmm1,0x80\(%rax\)
+ +[a-f0-9]+: 62 f1 7e 08 7f 48 08 vmovdqu32 %xmm1,0x80\(%rax\)
+ +[a-f0-9]+: 62 f1 fe 08 7f 48 08 vmovdqu64 %xmm1,0x80\(%rax\)
+ +[a-f0-9]+: c5 fd 6f d1 vmovdqa %ymm1,%ymm2
+ +[a-f0-9]+: c5 fd 6f d1 vmovdqa %ymm1,%ymm2
+ +[a-f0-9]+: c5 fe 6f d1 vmovdqu %ymm1,%ymm2
+ +[a-f0-9]+: c5 fe 6f d1 vmovdqu %ymm1,%ymm2
+ +[a-f0-9]+: c5 fe 6f d1 vmovdqu %ymm1,%ymm2
+ +[a-f0-9]+: c5 fe 6f d1 vmovdqu %ymm1,%ymm2
+ +[a-f0-9]+: c4 41 7d 6f e3 vmovdqa %ymm11,%ymm12
+ +[a-f0-9]+: c4 41 7d 6f e3 vmovdqa %ymm11,%ymm12
+ +[a-f0-9]+: c4 41 7e 6f e3 vmovdqu %ymm11,%ymm12
+ +[a-f0-9]+: c4 41 7e 6f e3 vmovdqu %ymm11,%ymm12
+ +[a-f0-9]+: c4 41 7e 6f e3 vmovdqu %ymm11,%ymm12
+ +[a-f0-9]+: c4 41 7e 6f e3 vmovdqu %ymm11,%ymm12
+ +[a-f0-9]+: c5 fd 6f 50 7f vmovdqa 0x7f\(%rax\),%ymm2
+ +[a-f0-9]+: c5 fd 6f 50 7f vmovdqa 0x7f\(%rax\),%ymm2
+ +[a-f0-9]+: c5 fe 6f 50 7f vmovdqu 0x7f\(%rax\),%ymm2
+ +[a-f0-9]+: c5 fe 6f 50 7f vmovdqu 0x7f\(%rax\),%ymm2
+ +[a-f0-9]+: c5 fe 6f 50 7f vmovdqu 0x7f\(%rax\),%ymm2
+ +[a-f0-9]+: c5 fe 6f 50 7f vmovdqu 0x7f\(%rax\),%ymm2
+ +[a-f0-9]+: 62 f1 7d 28 7f 48 04 vmovdqa32 %ymm1,0x80\(%rax\)
+ +[a-f0-9]+: 62 f1 fd 28 7f 48 04 vmovdqa64 %ymm1,0x80\(%rax\)
+ +[a-f0-9]+: 62 f1 7f 28 7f 48 04 vmovdqu8 %ymm1,0x80\(%rax\)
+ +[a-f0-9]+: 62 f1 ff 28 7f 48 04 vmovdqu16 %ymm1,0x80\(%rax\)
+ +[a-f0-9]+: 62 f1 7e 28 7f 48 04 vmovdqu32 %ymm1,0x80\(%rax\)
+ +[a-f0-9]+: 62 f1 fe 28 7f 48 04 vmovdqu64 %ymm1,0x80\(%rax\)
+ +[a-f0-9]+: 62 f1 7d 48 6f 10 vmovdqa32 \(%rax\),%zmm2
+ +[a-f0-9]+: c5 .* vpand %xmm2,%xmm3,%xmm4
+ +[a-f0-9]+: c4 .* vpand %xmm12,%xmm3,%xmm4
+ +[a-f0-9]+: c5 .* vpandn %xmm2,%xmm13,%xmm4
+ +[a-f0-9]+: c5 .* vpandn %xmm2,%xmm3,%xmm14
+ +[a-f0-9]+: c5 .* vpor %xmm2,%xmm3,%xmm4
+ +[a-f0-9]+: c4 .* vpor %xmm12,%xmm3,%xmm4
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm13,%xmm4
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm3,%xmm14
+ +[a-f0-9]+: c5 .* vpand %ymm2,%ymm3,%ymm4
+ +[a-f0-9]+: c4 .* vpand %ymm12,%ymm3,%ymm4
+ +[a-f0-9]+: c5 .* vpandn %ymm2,%ymm13,%ymm4
+ +[a-f0-9]+: c5 .* vpandn %ymm2,%ymm3,%ymm14
+ +[a-f0-9]+: c5 .* vpor %ymm2,%ymm3,%ymm4
+ +[a-f0-9]+: c4 .* vpor %ymm12,%ymm3,%ymm4
+ +[a-f0-9]+: c5 .* vpxor %ymm2,%ymm13,%ymm4
+ +[a-f0-9]+: c5 .* vpxor %ymm2,%ymm3,%ymm14
+ +[a-f0-9]+: c5 .* vpand 0x70\(%rax\),%xmm2,%xmm3
+ +[a-f0-9]+: c5 .* vpand 0x70\(%rax\),%xmm2,%xmm3
+ +[a-f0-9]+: c5 .* vpandn 0x70\(%rax\),%xmm2,%xmm3
+ +[a-f0-9]+: c5 .* vpandn 0x70\(%rax\),%xmm2,%xmm3
+ +[a-f0-9]+: c5 .* vpor 0x70\(%rax\),%xmm2,%xmm3
+ +[a-f0-9]+: c5 .* vpor 0x70\(%rax\),%xmm2,%xmm3
+ +[a-f0-9]+: c5 .* vpxor 0x70\(%rax\),%xmm2,%xmm3
+ +[a-f0-9]+: c5 .* vpxor 0x70\(%rax\),%xmm2,%xmm3
+ +[a-f0-9]+: 62 .* vpandd 0x80\(%rax\),%xmm2,%xmm3
+ +[a-f0-9]+: 62 .* vpandq 0x80\(%rax\),%xmm2,%xmm3
+ +[a-f0-9]+: 62 .* vpandnd 0x80\(%rax\),%xmm2,%xmm3
+ +[a-f0-9]+: 62 .* vpandnq 0x80\(%rax\),%xmm2,%xmm3
+ +[a-f0-9]+: 62 .* vpord 0x80\(%rax\),%xmm2,%xmm3
+ +[a-f0-9]+: 62 .* vporq 0x80\(%rax\),%xmm2,%xmm3
+ +[a-f0-9]+: 62 .* vpxord 0x80\(%rax\),%xmm2,%xmm3
+ +[a-f0-9]+: 62 .* vpxorq 0x80\(%rax\),%xmm2,%xmm3
+ +[a-f0-9]+: c5 .* vpand 0x60\(%rax\),%ymm2,%ymm3
+ +[a-f0-9]+: c5 .* vpand 0x60\(%rax\),%ymm2,%ymm3
+ +[a-f0-9]+: c5 .* vpandn 0x60\(%rax\),%ymm2,%ymm3
+ +[a-f0-9]+: c5 .* vpandn 0x60\(%rax\),%ymm2,%ymm3
+ +[a-f0-9]+: c5 .* vpor 0x60\(%rax\),%ymm2,%ymm3
+ +[a-f0-9]+: c5 .* vpor 0x60\(%rax\),%ymm2,%ymm3
+ +[a-f0-9]+: c5 .* vpxor 0x60\(%rax\),%ymm2,%ymm3
+ +[a-f0-9]+: c5 .* vpxor 0x60\(%rax\),%ymm2,%ymm3
+ +[a-f0-9]+: 62 .* vpandd 0x80\(%rax\),%ymm2,%ymm3
+ +[a-f0-9]+: 62 .* vpandq 0x80\(%rax\),%ymm2,%ymm3
+ +[a-f0-9]+: 62 .* vpandnd 0x80\(%rax\),%ymm2,%ymm3
+ +[a-f0-9]+: 62 .* vpandnq 0x80\(%rax\),%ymm2,%ymm3
+ +[a-f0-9]+: 62 .* vpord 0x80\(%rax\),%ymm2,%ymm3
+ +[a-f0-9]+: 62 .* vporq 0x80\(%rax\),%ymm2,%ymm3
+ +[a-f0-9]+: 62 .* vpxord 0x80\(%rax\),%ymm2,%ymm3
+ +[a-f0-9]+: 62 .* vpxorq 0x80\(%rax\),%ymm2,%ymm3
+ +[a-f0-9]+: 0f .* pxor %mm2,%mm2
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm2
+ +[a-f0-9]+: c5 .* vpxor %xmm0,%xmm0,%xmm12
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm8
+ +[a-f0-9]+: c5 .* vpxor %ymm0,%ymm0,%ymm1
+ +[a-f0-9]+: 0f .* pxor %mm2,%mm2
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm2
+ +[a-f0-9]+: c5 .* vpxor %xmm0,%xmm0,%xmm12
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm8
+ +[a-f0-9]+: c5 .* vpxor %ymm0,%ymm0,%ymm1
+ +[a-f0-9]+: 0f .* pxor %mm2,%mm2
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm2
+ +[a-f0-9]+: c5 .* vpxor %xmm0,%xmm0,%xmm12
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm8
+ +[a-f0-9]+: c5 .* vpxor %ymm0,%ymm0,%ymm1
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm2
+ +[a-f0-9]+: c5 .* vpxor %xmm0,%xmm0,%xmm12
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm8
+ +[a-f0-9]+: c5 .* vpxor %ymm0,%ymm0,%ymm1
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-optimize-5.d b/gas/testsuite/gas/i386/x86-64-optimize-5.d
index 9fd0ec2aa37..5b272aa0945 100644
--- a/gas/testsuite/gas/i386/x86-64-optimize-5.d
+++ b/gas/testsuite/gas/i386/x86-64-optimize-5.d
@@ -203,6 +203,25 @@ Disassembly of section .text:
+[a-f0-9]+: 62 .* vporq 0x80\(%rax\),%ymm2,%ymm3
+[a-f0-9]+: 62 .* vpxord 0x80\(%rax\),%ymm2,%ymm3
+[a-f0-9]+: 62 .* vpxorq 0x80\(%rax\),%ymm2,%ymm3
+ +[a-f0-9]+: 0f .* pxor %mm2,%mm2
+ +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2
+ +[a-f0-9]+: 66 .* pxor %xmm12,%xmm12
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm8
+ +[a-f0-9]+: c5 .* vpxor %ymm0,%ymm0,%ymm1
+ +[a-f0-9]+: 0f .* pxor %mm2,%mm2
+ +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2
+ +[a-f0-9]+: 66 .* pxor %xmm12,%xmm12
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm8
+ +[a-f0-9]+: c5 .* vpxor %ymm0,%ymm0,%ymm1
+ +[a-f0-9]+: 0f .* pxor %mm2,%mm2
+ +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2
+ +[a-f0-9]+: 66 .* pxor %xmm12,%xmm12
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm8
+ +[a-f0-9]+: c5 .* vpxor %ymm0,%ymm0,%ymm1
+ +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2
+ +[a-f0-9]+: 66 .* pxor %xmm12,%xmm12
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm8
+ +[a-f0-9]+: c5 .* vpxor %ymm0,%ymm0,%ymm1
+[a-f0-9]+: 62 f1 f5 08 55 e9 \{evex\} vandnpd %xmm1,%xmm1,%xmm5
+[a-f0-9]+: 62 f1 f5 08 55 e9 \{evex\} vandnpd %xmm1,%xmm1,%xmm5
+[a-f0-9]+: 62 f1 7d 28 6f d1 vmovdqa32 %ymm1,%ymm2
diff --git a/gas/testsuite/gas/i386/x86-64-optimize-6.d b/gas/testsuite/gas/i386/x86-64-optimize-6.d
index 6cacaf9d783..48105c3063e 100644
--- a/gas/testsuite/gas/i386/x86-64-optimize-6.d
+++ b/gas/testsuite/gas/i386/x86-64-optimize-6.d
@@ -203,6 +203,25 @@ Disassembly of section .text:
+[a-f0-9]+: 62 .* vporq 0x80\(%rax\),%ymm2,%ymm3
+[a-f0-9]+: 62 .* vpxord 0x80\(%rax\),%ymm2,%ymm3
+[a-f0-9]+: 62 .* vpxorq 0x80\(%rax\),%ymm2,%ymm3
+ +[a-f0-9]+: 0f .* pxor %mm2,%mm2
+ +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2
+ +[a-f0-9]+: 66 .* pxor %xmm12,%xmm12
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm8
+ +[a-f0-9]+: c5 .* vpxor %ymm0,%ymm0,%ymm1
+ +[a-f0-9]+: 0f .* pxor %mm2,%mm2
+ +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2
+ +[a-f0-9]+: 66 .* pxor %xmm12,%xmm12
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm8
+ +[a-f0-9]+: c5 .* vpxor %ymm0,%ymm0,%ymm1
+ +[a-f0-9]+: 0f .* pxor %mm2,%mm2
+ +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2
+ +[a-f0-9]+: 66 .* pxor %xmm12,%xmm12
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm8
+ +[a-f0-9]+: c5 .* vpxor %ymm0,%ymm0,%ymm1
+ +[a-f0-9]+: 66 .* pxor %xmm2,%xmm2
+ +[a-f0-9]+: 66 .* pxor %xmm12,%xmm12
+ +[a-f0-9]+: c5 .* vpxor %xmm2,%xmm2,%xmm8
+ +[a-f0-9]+: c5 .* vpxor %ymm0,%ymm0,%ymm1
+[a-f0-9]+: 62 f1 f5 08 55 e9 \{evex\} vandnpd %xmm1,%xmm1,%xmm5
+[a-f0-9]+: 62 f1 f5 08 55 e9 \{evex\} vandnpd %xmm1,%xmm1,%xmm5
+[a-f0-9]+: 62 f1 7d 28 6f d1 vmovdqa32 %ymm1,%ymm2
diff --git a/gas/testsuite/gas/i386/x86-64.exp b/gas/testsuite/gas/i386/x86-64.exp
index 48ec9c21929..49205f9b996 100644
--- a/gas/testsuite/gas/i386/x86-64.exp
+++ b/gas/testsuite/gas/i386/x86-64.exp
@@ -520,6 +520,7 @@ run_dump_test "x86-64-optimize-1"
run_dump_test "x86-64-optimize-2"
run_dump_test "x86-64-optimize-2a"
run_dump_test "x86-64-optimize-2b"
+run_dump_test "x86-64-optimize-2c"
run_dump_test "x86-64-optimize-3"
run_dump_test "x86-64-optimize-3b"
run_dump_test "x86-64-optimize-4"
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 607a4382497..f9abffb4b9f 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -1025,8 +1025,8 @@ pand<mmx>, 0x<mmx:pfx>0fdb, <mmx:cpu>, Modrm|<mmx:attr>|C|NoSuf, { <mmx:reg>|<mm
pandn<mmx>, 0x<mmx:pfx>0fdf, <mmx:cpu>, Modrm|<mmx:attr>|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> }
pcmpeq<bw><mmx>, 0x<mmx:pfx>0f74 | <bw:opc>, <mmx:cpu>, Modrm|<mmx:attr>|C|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> }
pcmpeqd<mmx>, 0x<mmx:pfx>0f76, <mmx:cpu>, Modrm|<mmx:attr>|C|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> }
-pcmpgt<bw><mmx>, 0x<mmx:pfx>0f64 | <bw:opc>, <mmx:cpu>, Modrm|<mmx:attr>|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> }
-pcmpgtd<mmx>, 0x<mmx:pfx>0f66, <mmx:cpu>, Modrm|<mmx:attr>|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> }
+pcmpgt<bw><mmx>, 0x<mmx:pfx>0f64 | <bw:opc>, <mmx:cpu>, Modrm|<mmx:attr>|NoSuf|Optimize, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> }
+pcmpgtd<mmx>, 0x<mmx:pfx>0f66, <mmx:cpu>, Modrm|<mmx:attr>|NoSuf|Optimize, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> }
pmaddwd<mmx>, 0x<mmx:pfx>0ff5, <mmx:cpu>, Modrm|<mmx:attr>|C|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> }
pmulhw<mmx>, 0x<mmx:pfx>0fe5, <mmx:cpu>, Modrm|<mmx:attr>|C|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> }
pmullw<mmx>, 0x<mmx:pfx>0fd5, <mmx:cpu>, Modrm|<mmx:attr>|C|NoSuf, { <mmx:reg>|<mmx:mem>|Unspecified|BaseIndex, <mmx:reg> }
@@ -1405,7 +1405,7 @@ rounds<sd><sse41>, 0x660f3a0a | <sd:opc>, <sse41:cpu>, Modrm|<sse41:scal>|<sse41
<sse42:cpu:attr:vvvv, $avx:AVX:Vex128|VexW0|SSE2AVX:VexVVVV, $sse:SSE4_2::>
-pcmpgtq<sse42>, 0x660f3837, <sse42:cpu>, Modrm|<sse42:attr>|<sse42:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
+pcmpgtq<sse42>, 0x660f3837, <sse42:cpu>, Modrm|<sse42:attr>|<sse42:vvvv>|NoSuf|Optimize, { RegXMM|Unspecified|BaseIndex, RegXMM }
pcmpestri<sse42>, 0x660f3a61, <sse42:cpu>|No64, Modrm|<sse42:attr>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
pcmpestri, 0x6661, AVX|x64, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
pcmpestri, 0x660f3a61, SSE4_2|x64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
@@ -1597,9 +1597,9 @@ vpcmpestri, 0x6661, AVX|No64, Modrm|Vex|Space0F3A|NoSuf, { Imm8, Unspecified|Bas
vpcmpestri, 0x6661, AVX|x64, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
vpcmpestrm, 0x6660, AVX|No64, Modrm|Vex|Space0F3A|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM }
vpcmpestrm, 0x6660, AVX|x64, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
-vpcmpgt<bw>, 0x6664 | <bw:opc>, AVX|AVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vpcmpgtd, 0x6666, AVX|AVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vpcmpgtq, 0x6637, AVX|AVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
+vpcmpgt<bw>, 0x6664 | <bw:opc>, AVX|AVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
+vpcmpgtd, 0x6666, AVX|AVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
+vpcmpgtq, 0x6637, AVX|AVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckOperandSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vpcmpistri, 0x6663, AVX, Modrm|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM }
vpcmpistrm, 0x6662, AVX, Modrm|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM }
vperm2f128, 0x6606, AVX, Modrm|Vex256|Space0F3A|VexVVVV|VexW0|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index 4a6c92a29ff..4779cc958db 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -9746,7 +9746,7 @@ static const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0 } } } },
{ MN_pcmpgtb, 0x64 | 0, 2, SPACE_0F, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -9760,7 +9760,7 @@ static const insn_template i386_optab[] =
1, 0, 0, 0, 0, 0 } } } },
{ MN_pcmpgtb, 0x64 | 0, 2, SPACE_0F, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -9774,7 +9774,7 @@ static const insn_template i386_optab[] =
1, 0, 0, 0, 0, 0 } } } },
{ MN_pcmpgtb, 0x64 | 0, 2, SPACE_0F, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -9788,7 +9788,7 @@ static const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0 } } } },
{ MN_pcmpgtw, 0x64 | 1, 2, SPACE_0F, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -9802,7 +9802,7 @@ static const insn_template i386_optab[] =
1, 0, 0, 0, 0, 0 } } } },
{ MN_pcmpgtw, 0x64 | 1, 2, SPACE_0F, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -9816,7 +9816,7 @@ static const insn_template i386_optab[] =
1, 0, 0, 0, 0, 0 } } } },
{ MN_pcmpgtw, 0x64 | 1, 2, SPACE_0F, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -9830,7 +9830,7 @@ static const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0 } } } },
{ MN_pcmpgtd, 0x66, 2, SPACE_0F, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -9844,7 +9844,7 @@ static const insn_template i386_optab[] =
1, 0, 0, 0, 0, 0 } } } },
{ MN_pcmpgtd, 0x66, 2, SPACE_0F, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -9858,7 +9858,7 @@ static const insn_template i386_optab[] =
1, 0, 0, 0, 0, 0 } } } },
{ MN_pcmpgtd, 0x66, 2, SPACE_0F, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -19050,7 +19050,7 @@ static const insn_template i386_optab[] =
1, 0, 0, 0, 0, 0 } } } },
{ MN_pcmpgtq, 0x37, 2, SPACE_0F38, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -19064,7 +19064,7 @@ static const insn_template i386_optab[] =
1, 0, 0, 0, 0, 0 } } } },
{ MN_pcmpgtq, 0x37, 2, SPACE_0F38, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -30244,7 +30244,7 @@ static const insn_template i386_optab[] =
1, 0, 0, 0, 0, 0 } } } },
{ MN_vpcmpgtb, 0x64 | 0, 3, SPACE_0F, None,
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 1, 1, 3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ 0, 0, 0, 1, 1, 3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -30276,7 +30276,7 @@ static const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0 } } } },
{ MN_vpcmpgtw, 0x64 | 1, 3, SPACE_0F, None,
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 1, 1, 3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ 0, 0, 0, 1, 1, 3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -30308,7 +30308,7 @@ static const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0 } } } },
{ MN_vpcmpgtd, 0x66, 3, SPACE_0F, None,
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 1, 1, 3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ 0, 0, 0, 1, 1, 3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -30340,7 +30340,7 @@ static const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0 } } } },
{ MN_vpcmpgtq, 0x37, 3, SPACE_0F38, None,
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 1, 1, 3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ 0, 0, 0, 1, 1, 3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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2023-07-04 15:07 [binutils-gdb] x86: optimize pre-AVX512 {, V}PCMPGT* with identical sources Jan Beulich
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