[binutils-gdb] arm: Fix encoding of MVE vqshr[u]n

[Alex Coplan <acoplan@sourceware.org>]

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=b3a561abc3040264aa0c60a8082e2433b0ca38a1

commit b3a561abc3040264aa0c60a8082e2433b0ca38a1
Author: Alex Coplan <alex.coplan@arm.com>
Date:   Tue Apr 2 13:42:13 2024 +0100

    arm: Fix encoding of MVE vqshr[u]n
    
    As it stands, these insns are incorrectly encoded as vqrshr[u]n.
    Concretely, the problem can be seen as follows:
    
    $ cat t.s
    vqrshrnb.s16 q0,q0,#8
    vqshrnb.s16 q0,q0,#8
    $ gas/as-new t.s -march=armv8.1-m.main+mve -o t.o
    $ binutils/objdump -d t.o -m armv8.1-m.main
    
    t.o:     file format elf32-littlearm
    
    Disassembly of section .text:
    
    00000000 <.text>:
       0:   ee88 0f41       vqrshrnb.s16    q0, q0, #0
       4:   ee88 0f41       vqrshrnb.s16    q0, q0, #0
    
    Here we assemble these two instructions to the same opcode.  The
    encoding of the first is the correct, while the encoding of the second
    is incorrect, and the bottom bit should be clear, see the Armv8-M ARM:
    https://developer.arm.com/documentation/ddi0553/latest/
    
    There is an additional problem here in that the disassembly of the
    immediate is incorrect.  llvm-objdump shows the correct disassembly
    here:
    
    t.o:    file format elf32-littlearm
    
    Disassembly of section .text:
    
    00000000 <$t>:
           0: ee88 0f41     vqrshrnb.s16    q0, q0, #8
           4: ee88 0f41     vqrshrnb.s16    q0, q0, #8
    
    Note that we defer adding a test for the correct encoding of these insns
    until the next patch which fixes the disassembly issue.

Diff:
---
 gas/config/tc-arm.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 3bbb75c169a..89c85745adc 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -26621,10 +26621,10 @@ static const struct asm_opcode insns[] =
  mCEF(vshrnb,	  _vshrnb,	3, (RMQ, RMQ, I32z),	mve_vshrn),
  mCEF(vrshrnt,	  _vrshrnt,	3, (RMQ, RMQ, I32z),	mve_vshrn),
  mCEF(vrshrnb,	  _vrshrnb,	3, (RMQ, RMQ, I32z),	mve_vshrn),
- mCEF(vqshrnt,	  _vqrshrnt,	3, (RMQ, RMQ, I32z),	mve_vshrn),
- mCEF(vqshrnb,	  _vqrshrnb,	3, (RMQ, RMQ, I32z),	mve_vshrn),
- mCEF(vqshrunt,	  _vqrshrunt,	3, (RMQ, RMQ, I32z),	mve_vshrn),
- mCEF(vqshrunb,	  _vqrshrunb,	3, (RMQ, RMQ, I32z),	mve_vshrn),
+ mCEF(vqshrnt,	  _vqshrnt,	3, (RMQ, RMQ, I32z),	mve_vshrn),
+ mCEF(vqshrnb,	  _vqshrnb,	3, (RMQ, RMQ, I32z),	mve_vshrn),
+ mCEF(vqshrunt,	  _vqshrunt,	3, (RMQ, RMQ, I32z),	mve_vshrn),
+ mCEF(vqshrunb,	  _vqshrunb,	3, (RMQ, RMQ, I32z),	mve_vshrn),
  mCEF(vqrshrnt,	  _vqrshrnt,	3, (RMQ, RMQ, I32z),	mve_vshrn),
  mCEF(vqrshrnb,	  _vqrshrnb,	3, (RMQ, RMQ, I32z),	mve_vshrn),
  mCEF(vqrshrunt,  _vqrshrunt,	3, (RMQ, RMQ, I32z),	mve_vshrn),