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From: Jan Beulich <jbeulich@suse.com>
To: Binutils <binutils@sourceware.org>
Cc: "H.J. Lu" <hjl.tools@gmail.com>
Subject: [PATCH] x86: drop "regmask" static variable
Date: Wed, 5 Oct 2022 09:40:50 +0200	[thread overview]
Message-ID: <1266f001-4511-2662-dba9-14b4d0317c57@suse.com> (raw)

Replace its two uses by more direct checks, paralleling what's already
there for SIMD registers.

--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1907,7 +1907,6 @@ operand_type_xor (i386_operand_type x, i
 static const i386_operand_type anydisp = OPERAND_TYPE_ANYDISP;
 static const i386_operand_type anyimm = OPERAND_TYPE_ANYIMM;
 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
-static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
@@ -8190,7 +8189,7 @@ if(flag_debug) fprintf(stderr, "%s: imm=
 		  || ((op.bitfield.class != Reg
 		       || (!op.bitfield.dword && !op.bitfield.qword))
 		      && op.bitfield.class != RegSIMD
-		      && !operand_type_equal (&op, &regmask)))
+		      && op.bitfield.class != RegMask))
 		abort ();
 	      i.vex.register_specifier = i.op[vvvv].regs;
 	      dest++;
@@ -8601,7 +8600,7 @@ if(flag_debug) fprintf(stderr, "%s: imm=
 	      if ((type->bitfield.class != Reg
 		   || (!type->bitfield.dword && !type->bitfield.qword))
 		  && type->bitfield.class != RegSIMD
-		  && !operand_type_equal (type, &regmask))
+		  && type->bitfield.class != RegMask)
 		abort ();
 
 	      i.vex.register_specifier = i.op[vex_reg].regs;

             reply	other threads:[~2022-10-05  7:40 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-05  7:40 Jan Beulich [this message]
2022-10-11 17:50 ` H.J. Lu

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