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* [PATCH] x86: drop "regmask" static variable
@ 2022-10-05  7:40 Jan Beulich
  2022-10-11 17:50 ` H.J. Lu
  0 siblings, 1 reply; 2+ messages in thread
From: Jan Beulich @ 2022-10-05  7:40 UTC (permalink / raw)
  To: Binutils; +Cc: H.J. Lu

Replace its two uses by more direct checks, paralleling what's already
there for SIMD registers.

--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1907,7 +1907,6 @@ operand_type_xor (i386_operand_type x, i
 static const i386_operand_type anydisp = OPERAND_TYPE_ANYDISP;
 static const i386_operand_type anyimm = OPERAND_TYPE_ANYIMM;
 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
-static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
@@ -8190,7 +8189,7 @@ if(flag_debug) fprintf(stderr, "%s: imm=
 		  || ((op.bitfield.class != Reg
 		       || (!op.bitfield.dword && !op.bitfield.qword))
 		      && op.bitfield.class != RegSIMD
-		      && !operand_type_equal (&op, &regmask)))
+		      && op.bitfield.class != RegMask))
 		abort ();
 	      i.vex.register_specifier = i.op[vvvv].regs;
 	      dest++;
@@ -8601,7 +8600,7 @@ if(flag_debug) fprintf(stderr, "%s: imm=
 	      if ((type->bitfield.class != Reg
 		   || (!type->bitfield.dword && !type->bitfield.qword))
 		  && type->bitfield.class != RegSIMD
-		  && !operand_type_equal (type, &regmask))
+		  && type->bitfield.class != RegMask)
 		abort ();
 
 	      i.vex.register_specifier = i.op[vex_reg].regs;

^ permalink raw reply	[flat|nested] 2+ messages in thread
* Re: [PATCH] x86: drop "regmask" static variable
  2022-10-05  7:40 [PATCH] x86: drop "regmask" static variable Jan Beulich
@ 2022-10-11 17:50 ` H.J. Lu
  0 siblings, 0 replies; 2+ messages in thread
From: H.J. Lu @ 2022-10-11 17:50 UTC (permalink / raw)
  To: Jan Beulich; +Cc: Binutils

On Wed, Oct 5, 2022 at 12:40 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> Replace its two uses by more direct checks, paralleling what's already
> there for SIMD registers.
>
> --- a/gas/config/tc-i386.c
> +++ b/gas/config/tc-i386.c
> @@ -1907,7 +1907,6 @@ operand_type_xor (i386_operand_type x, i
>  static const i386_operand_type anydisp = OPERAND_TYPE_ANYDISP;
>  static const i386_operand_type anyimm = OPERAND_TYPE_ANYIMM;
>  static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
> -static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
>  static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
>  static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
>  static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
> @@ -8190,7 +8189,7 @@ if(flag_debug) fprintf(stderr, "%s: imm=
>                   || ((op.bitfield.class != Reg
>                        || (!op.bitfield.dword && !op.bitfield.qword))
>                       && op.bitfield.class != RegSIMD
> -                     && !operand_type_equal (&op, &regmask)))
> +                     && op.bitfield.class != RegMask))
>                 abort ();
>               i.vex.register_specifier = i.op[vvvv].regs;
>               dest++;
> @@ -8601,7 +8600,7 @@ if(flag_debug) fprintf(stderr, "%s: imm=
>               if ((type->bitfield.class != Reg
>                    || (!type->bitfield.dword && !type->bitfield.qword))
>                   && type->bitfield.class != RegSIMD
> -                 && !operand_type_equal (type, &regmask))
> +                 && type->bitfield.class != RegMask)
>                 abort ();
>
>               i.vex.register_specifier = i.op[vex_reg].regs;

OK.

Thanks.

-- 
H.J.

^ permalink raw reply	[flat|nested] 2+ messages in thread
end of thread, other threads:[~2022-10-11 17:51 UTC | newest]

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