From: Claudiu Zissulescu <claziss@gmail.com>
To: binutils@sourceware.org
Cc: claziss@synopsys.com, fbedard@synopsys.com
Subject: [PATCH] [ARC][committed] Update int_vector_base aux register.
Date: Tue, 25 Feb 2020 08:29:00 -0000 [thread overview]
Message-ID: <20200225082921.199701-1-claziss@gmail.com> (raw)
INT_VECTOR_BASE auxiliary register is available across all ARC
architectures.
xxxx-xx-xx Claudiu Zissulescu <claziss@gmail.com>
* arc-regs.h (int_vector_base): Make it available for all ARC
CPUs.
Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
---
opcodes/ChangeLog | 5 +++++
opcodes/arc-regs.h | 3 +--
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 73091b9e61..5d83578641 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
+
+ * arc-regs.h (int_vector_base): Make it available for all ARC
+ CPUs.
+
2020-02-20 Nelson Chu <nelson.chu@sifive.com>
* riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
diff --git a/opcodes/arc-regs.h b/opcodes/arc-regs.h
index a1d98bf179..4494a0630a 100644
--- a/opcodes/arc-regs.h
+++ b/opcodes/arc-regs.h
@@ -71,8 +71,7 @@ DEF (0x21, ARC_OPCODE_ARCALL, NONE, count0)
DEF (0x22, ARC_OPCODE_ARCALL, NONE, control0)
DEF (0x23, ARC_OPCODE_ARCALL, NONE, limit0)
DEF (0x24, ARC_OPCODE_ARCV1, NONE, pcport)
-DEF (0x25, ARC_OPCODE_ARC700, NONE, int_vector_base)
-DEF (0x25, ARC_OPCODE_ARCV2, NONE, int_vector_base)
+DEF (0x25, ARC_OPCODE_ARCALL, NONE, int_vector_base)
DEF (0x26, ARC_OPCODE_ARC600, NONE, aux_vbfdw_mode)
DEF (0x27, ARC_OPCODE_ARC600, NONE, aux_vbfdw_bm0)
DEF (0x28, ARC_OPCODE_ARC600, NONE, aux_vbfdw_bm1)
--
2.24.1
reply other threads:[~2020-02-25 8:29 UTC|newest]
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