[PATCH 2/4] aarch64: Add support for Armv8-R DFB alias

[PATCH 2/4] aarch64: Add support for Armv8-R DFB alias

[Alex Coplan]

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This patch adds support for the DFB alias introduced in Armv8-R AArch64.

N.B. this patch does not contain the changes to the regenerated files
opcodes/aarch64-*-2.c: please regenerate these when testing the patch.

Testing:
 * New test to check DFB alias is correctly assembled/disassembled.
 * Regression tested an x64 -> aarch64-none-elf cross, no regressions.

---

gas/ChangeLog:

2020-09-04  Alex Coplan  <alex.coplan@arm.com>

	* testsuite/gas/aarch64/dfb.d: New test.
	* testsuite/gas/aarch64/dfb.s: Input.

opcodes/ChangeLog:

2020-09-04  Alex Coplan  <alex.coplan@arm.com>

	* aarch64-tbl.h (aarch64_feature_v8_r): New.
	(ARMV8_R): New.
	(V8_R_INSN): New.
	(aarch64_opcode_table): Add dfb.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
---
 gas/testsuite/gas/aarch64/dfb.d | 8 ++++++++
 gas/testsuite/gas/aarch64/dfb.s | 2 ++
 opcodes/aarch64-tbl.h           | 6 ++++++
 3 files changed, 16 insertions(+)
 create mode 100644 gas/testsuite/gas/aarch64/dfb.d
 create mode 100644 gas/testsuite/gas/aarch64/dfb.s

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diff --git a/gas/testsuite/gas/aarch64/dfb.d b/gas/testsuite/gas/aarch64/dfb.d
new file mode 100644
index 00000000000..70aead952a5
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/dfb.d
@@ -0,0 +1,8 @@
+#objdump: -dr -m aarch64:armv8-r
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+.*:	d5033c9f 	dfb
diff --git a/gas/testsuite/gas/aarch64/dfb.s b/gas/testsuite/gas/aarch64/dfb.s
new file mode 100644
index 00000000000..df0ad5921a5
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/dfb.s
@@ -0,0 +1,2 @@
+.arch armv8-r
+dfb
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 5ad718014e0..1cecaead14d 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2406,6 +2406,8 @@ static const aarch64_feature_set aarch64_feature_f32mm_sve =
 static const aarch64_feature_set aarch64_feature_f64mm_sve =
   AARCH64_FEATURE (AARCH64_FEATURE_V8_2 | AARCH64_FEATURE_F64MM
        | AARCH64_FEATURE_SVE, 0);
+static const aarch64_feature_set aarch64_feature_v8_r =
+  AARCH64_FEATURE (AARCH64_FEATURE_V8_R, 0);
 
 
 #define CORE		&aarch64_feature_v8
@@ -2450,6 +2452,7 @@ static const aarch64_feature_set aarch64_feature_f64mm_sve =
 #define F32MM_SVE     &aarch64_feature_f32mm_sve
 #define F64MM_SVE     &aarch64_feature_f64mm_sve
 #define I8MM      &aarch64_feature_i8mm
+#define ARMV8_R	  &aarch64_feature_v8_r
 
 #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
@@ -2553,6 +2556,8 @@ static const aarch64_feature_set aarch64_feature_f64mm_sve =
   { NAME, OPCODE, MASK, CLASS, 0, F64MM_SVE, OPS, QUALS, FLAGS, CONSTRAINTS, TIED, NULL }
 #define F32MATMUL_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS, CONSTRAINTS, TIED) \
   { NAME, OPCODE, MASK, CLASS, 0, F32MM_SVE, OPS, QUALS, FLAGS, CONSTRAINTS, TIED, NULL }
+#define V8_R_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+  { NAME, OPCODE, MASK, CLASS, 0, ARMV8_R, OPS, QUALS, FLAGS, 0, 0, NULL }
 
 struct aarch64_opcode aarch64_opcode_table[] =
 {
@@ -3845,6 +3850,7 @@ struct aarch64_opcode aarch64_opcode_table[] =
   CORE_INSN ("tsb", 0xd503225f, 0xffffffff, ic_system, 0, OP1 (BARRIER_PSB), {}, F_ALIAS),
   CORE_INSN ("clrex", 0xd503305f, 0xfffff0ff, ic_system, 0, OP1 (UIMM4), {}, F_OPD0_OPT | F_DEFAULT (0xF)),
   CORE_INSN ("dsb", 0xd503309f, 0xfffff0ff, ic_system, 0, OP1 (BARRIER), {}, F_HAS_ALIAS),
+  V8_R_INSN ("dfb", 0xd5033c9f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
   CORE_INSN ("ssbb", 0xd503309f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
   CORE_INSN ("pssbb", 0xd503349f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
   CORE_INSN ("dmb", 0xd50330bf, 0xfffff0ff, ic_system, 0, OP1 (BARRIER), {}, 0),