* [PATCH 1/4] CSKY: Fix and add some instructions for VDSPV1.
@ 2020-10-12 14:29 Cooper Qu
2020-10-12 14:30 ` [PATCH 2/4] CSKY: Add version flag in eflag and fix bug in disassembling register Cooper Qu
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Cooper Qu @ 2020-10-12 14:29 UTC (permalink / raw)
To: binutils, lifang_xia; +Cc: Cooper Qu
gas/
* config/tc-csky.c (get_operand_value): Add handler for
OPRND_TYPE_IMM5b_VSH and OPRND_TYPE_VREG_WITH_INDEX.
* testsuite/gas/csky/csky_vdsp.d : Fix the disassembling
for vector register.
opcodes/
* csky-dis.c (csky_output_operand): Add handler for
OPRND_TYPE_IMM5b_VSH and OPRND_TYPE_VREG_WITH_INDEX.
* csky-opc.h (OPRND_TYPE_VREG_WITH_INDEX): New enum.
(OPRND_TYPE_IMM5b_VSH): New enum.
(csky_v2_opcodes): Fix and add some instructions for VDSPV1.
Change-Id: Ia5675d7b716fe5c331e6121ad8f83061ef6454bb
---
gas/config/tc-csky.c | 12 ++
gas/testsuite/gas/csky/csky_vdsp.d | 54 +++----
opcodes/csky-dis.c | 19 ++-
opcodes/csky-opc.h | 243 ++++++++++++++++++++++++-----
4 files changed, 262 insertions(+), 66 deletions(-)
diff --git a/gas/config/tc-csky.c b/gas/config/tc-csky.c
index 569fe2bc852..23481b838b1 100644
--- a/gas/config/tc-csky.c
+++ b/gas/config/tc-csky.c
@@ -3673,6 +3673,17 @@ get_operand_value (struct csky_opcode_info *op,
}
return TRUE;
+ case OPRND_TYPE_IMM5b_VSH:
+ /* For vshri.T and vshli.T. */
+ if (is_imm_within_range (oper, 0, 31))
+ {
+ int val = csky_insn.val[csky_insn.idx - 1];
+ val = (val << 1) | (val >> 4);
+ val &= 0x1f;
+ csky_insn.val[csky_insn.idx - 1] = val;
+ return TRUE;
+ }
+ return FALSE;
case OPRND_TYPE_IMM8b_BMASKI:
/* For csky v2 bmask, which will transfer to 16bits movi. */
if (is_imm_within_range (oper, 1, 8))
@@ -4240,6 +4251,7 @@ get_operand_value (struct csky_opcode_info *op,
case OPRND_TYPE_AREG_WITH_LSHIFT_FPU:
return is_reg_lshift_illegal (oper, 1);
case OPRND_TYPE_FREG_WITH_INDEX:
+ case OPRND_TYPE_VREG_WITH_INDEX:
if (parse_type_freg (oper, 0))
{
if (**oper == '[')
diff --git a/gas/testsuite/gas/csky/csky_vdsp.d b/gas/testsuite/gas/csky/csky_vdsp.d
index 3af441315b9..97330b01004 100644
--- a/gas/testsuite/gas/csky/csky_vdsp.d
+++ b/gas/testsuite/gas/csky/csky_vdsp.d
@@ -6,30 +6,30 @@
Disassembly of section \.text:
#...
-\s*[0-9a-f]*:\s*f8623c02\s*vstrq\.8\s*fr2,\s*\(r2,\s*r3\s*<<\s*0\)
-\s*[0-9a-f]*:\s*f8623d02\s*vstrq\.16\s*fr2,\s*\(r2,\s*r3\s*<<\s*0\)
-\s*[0-9a-f]*:\s*f8623e02\s*vstrq\.32\s*fr2,\s*\(r2,\s*r3\s*<<\s*0\)
-\s*[0-9a-f]*:\s*f8623402\s*vldrq\.8\s*fr2,\s*\(r2,\s*r3\s*<<\s*0\)
-\s*[0-9a-f]*:\s*f8623502\s*vldrq\.16\s*fr2,\s*\(r2,\s*r3\s*<<\s*0\)
-\s*[0-9a-f]*:\s*f8623602\s*vldrq\.32\s*fr2,\s*\(r2,\s*r3\s*<<\s*0\)
-\s*[0-9a-f]*:\s*f8623802\s*vstrd\.8\s*fr2,\s*\(r2,\s*r3\s*<<\s*0\)
-\s*[0-9a-f]*:\s*f8623902\s*vstrd\.16\s*fr2,\s*\(r2,\s*r3\s*<<\s*0\)
-\s*[0-9a-f]*:\s*f8623a02\s*vstrd\.32\s*fr2,\s*\(r2,\s*r3\s*<<\s*0\)
-\s*[0-9a-f]*:\s*f8623002\s*vldrd\.8\s*fr2,\s*\(r2,\s*r3\s*<<\s*0\)
-\s*[0-9a-f]*:\s*f8623102\s*vldrd\.16\s*fr2,\s*\(r2,\s*r3\s*<<\s*0\)
-\s*[0-9a-f]*:\s*f8623202\s*vldrd\.32\s*fr2,\s*\(r2,\s*r3\s*<<\s*0\)
-\s*[0-9a-f]*:\s*f8022412\s*vldq\.8\s*fr2,\s*\(r2,\s*0x10\)
-\s*[0-9a-f]*:\s*f8022512\s*vldq\.16\s*fr2,\s*\(r2,\s*0x10\)
-\s*[0-9a-f]*:\s*f8022612\s*vldq\.32\s*fr2,\s*\(r2,\s*0x10\)
-\s*[0-9a-f]*:\s*f8022c12\s*vstq\.8\s*fr2,\s*\(r2,\s*0x10\)
-\s*[0-9a-f]*:\s*f8022d12\s*vstq\.16\s*fr2,\s*\(r2,\s*0x10\)
-\s*[0-9a-f]*:\s*f8022e12\s*vstq\.32\s*fr2,\s*\(r2,\s*0x10\)
-\s*[0-9a-f]*:\s*f8022022\s*vldd\.8\s*fr2,\s*\(r2,\s*0x10\)
-\s*[0-9a-f]*:\s*f8022122\s*vldd\.16\s*fr2,\s*\(r2,\s*0x10\)
-\s*[0-9a-f]*:\s*f8022222\s*vldd\.32\s*fr2,\s*\(r2,\s*0x10\)
-\s*[0-9a-f]*:\s*f8022822\s*vstd\.8\s*fr2,\s*\(r2,\s*0x10\)
-\s*[0-9a-f]*:\s*f8022922\s*vstd\.16\s*fr2,\s*\(r2,\s*0x10\)
-\s*[0-9a-f]*:\s*f8022a22\s*vstd\.32\s*fr2,\s*\(r2,\s*0x10\)
+\s*[0-9a-f]*:\s*f8623c02\s*vstrq\.8\s*vr2,\s*\(r2,\s*r3\s*<<\s*0\)
+\s*[0-9a-f]*:\s*f8623d02\s*vstrq\.16\s*vr2,\s*\(r2,\s*r3\s*<<\s*0\)
+\s*[0-9a-f]*:\s*f8623e02\s*vstrq\.32\s*vr2,\s*\(r2,\s*r3\s*<<\s*0\)
+\s*[0-9a-f]*:\s*f8623402\s*vldrq\.8\s*vr2,\s*\(r2,\s*r3\s*<<\s*0\)
+\s*[0-9a-f]*:\s*f8623502\s*vldrq\.16\s*vr2,\s*\(r2,\s*r3\s*<<\s*0\)
+\s*[0-9a-f]*:\s*f8623602\s*vldrq\.32\s*vr2,\s*\(r2,\s*r3\s*<<\s*0\)
+\s*[0-9a-f]*:\s*f8623802\s*vstrd\.8\s*vr2,\s*\(r2,\s*r3\s*<<\s*0\)
+\s*[0-9a-f]*:\s*f8623902\s*vstrd\.16\s*vr2,\s*\(r2,\s*r3\s*<<\s*0\)
+\s*[0-9a-f]*:\s*f8623a02\s*vstrd\.32\s*vr2,\s*\(r2,\s*r3\s*<<\s*0\)
+\s*[0-9a-f]*:\s*f8623002\s*vldrd\.8\s*vr2,\s*\(r2,\s*r3\s*<<\s*0\)
+\s*[0-9a-f]*:\s*f8623102\s*vldrd\.16\s*vr2,\s*\(r2,\s*r3\s*<<\s*0\)
+\s*[0-9a-f]*:\s*f8623202\s*vldrd\.32\s*vr2,\s*\(r2,\s*r3\s*<<\s*0\)
+\s*[0-9a-f]*:\s*f8022412\s*vldq\.8\s*vr2,\s*\(r2,\s*0x10\)
+\s*[0-9a-f]*:\s*f8022512\s*vldq\.16\s*vr2,\s*\(r2,\s*0x10\)
+\s*[0-9a-f]*:\s*f8022612\s*vldq\.32\s*vr2,\s*\(r2,\s*0x10\)
+\s*[0-9a-f]*:\s*f8022c12\s*vstq\.8\s*vr2,\s*\(r2,\s*0x10\)
+\s*[0-9a-f]*:\s*f8022d12\s*vstq\.16\s*vr2,\s*\(r2,\s*0x10\)
+\s*[0-9a-f]*:\s*f8022e12\s*vstq\.32\s*vr2,\s*\(r2,\s*0x10\)
+\s*[0-9a-f]*:\s*f8022022\s*vldd\.8\s*vr2,\s*\(r2,\s*0x10\)
+\s*[0-9a-f]*:\s*f8022122\s*vldd\.16\s*vr2,\s*\(r2,\s*0x10\)
+\s*[0-9a-f]*:\s*f8022222\s*vldd\.32\s*vr2,\s*\(r2,\s*0x10\)
+\s*[0-9a-f]*:\s*f8022822\s*vstd\.8\s*vr2,\s*\(r2,\s*0x10\)
+\s*[0-9a-f]*:\s*f8022922\s*vstd\.16\s*vr2,\s*\(r2,\s*0x10\)
+\s*[0-9a-f]*:\s*f8022a22\s*vstd\.32\s*vr2,\s*\(r2,\s*0x10\)
\s*[0-9a-f]*:\s*c43eb020\s*vmulsh\s*r30,\s*r1
\s*[0-9a-f]*:\s*c7e0b040\s*vmulsha\s*r0,\s*r31
\s*[0-9a-f]*:\s*c58cb420\s*vmulsw\s*r12,\s*r12
@@ -43,9 +43,9 @@ Disassembly of section \.text:
\s*[0-9a-f]*:\s*f8101305\s*vmtvr.u8\s*vr5\[0\],\s*r16
\s*[0-9a-f]*:\s*f8ea1324\s*vmtvr.u16\s*vr4\[7\],\s*r10
\s*[0-9a-f]*:\s*f9ea134f\s*vmtvr.u32\s*vr15\[15\],\s*r10
-\s*[0-9a-f]*:\s*f94a0e81\s*vdup.8\s*fr1,\s*vr10\[10\]
-\s*[0-9a-f]*:\s*f83a0e8f\s*vdup.16\s*fr15,\s*vr10\[1\]
-\s*[0-9a-f]*:\s*faaa0e87\s*vdup.32\s*fr7,\s*vr10\[5\]
+\s*[0-9a-f]*:\s*f94a0e81\s*vdup.8\s*vr1,\s*vr10\[10\]
+\s*[0-9a-f]*:\s*f83a0e8f\s*vdup.16\s*vr15,\s*vr10\[1\]
+\s*[0-9a-f]*:\s*faaa0e87\s*vdup.32\s*vr7,\s*vr10\[5\]
\s*[0-9a-f]*:\s*f8030c02\s*vmov\s*vr2,\s*vr3
\s*[0-9a-f]*:\s*f8030062\s*vcadd\.eu8\s*vr2,\s*vr3
\s*[0-9a-f]*:\s*f8130062\s*vcadd\.eu16\s*vr2,\s*vr3
diff --git a/opcodes/csky-dis.c b/opcodes/csky-dis.c
index b31b685b905..4916bb6c37a 100644
--- a/opcodes/csky-dis.c
+++ b/opcodes/csky-dis.c
@@ -415,6 +415,15 @@ csky_output_operand (char *str, struct operand const *oprnd,
strcat (str, buf);
ret = 0;
break;
+ case OPRND_TYPE_IMM5b_VSH:
+ {
+ char num[128];
+ value = ((value & 0x1) << 4) | (value >> 1);
+ sprintf (num, "%d", (int)value);
+ strcat (str, num);
+ ret = 0;
+ break;
+ }
case OPRND_TYPE_MSB2SIZE:
case OPRND_TYPE_LSB2SIZE:
{
@@ -837,7 +846,7 @@ csky_output_operand (char *str, struct operand const *oprnd,
else if ((value & 0x3) == 0x3)
strcat (str, "3");
break;
- case OPRND_TYPE_FREG_WITH_INDEX:
+ case OPRND_TYPE_VREG_WITH_INDEX:
{
unsigned freg_val = value & 0xf;
unsigned index_val = (value >> 4) & 0xf;
@@ -845,6 +854,14 @@ csky_output_operand (char *str, struct operand const *oprnd,
strcat(str, buf);
break;
}
+ case OPRND_TYPE_FREG_WITH_INDEX:
+ {
+ unsigned freg_val = value & 0xf;
+ unsigned index_val = (value >> 4) & 0xf;
+ sprintf (buf, "fr%d[%d]", freg_val, index_val);
+ strcat(str, buf);
+ break;
+ }
case OPRND_TYPE_REGr4_r7:
if (IS_CSKY_V1 (mach_flag))
{
diff --git a/opcodes/csky-opc.h b/opcodes/csky-opc.h
index 199b8913717..e309253a18c 100644
--- a/opcodes/csky-opc.h
+++ b/opcodes/csky-opc.h
@@ -44,6 +44,7 @@ enum operand_type
OPRND_TYPE_AREG_WITH_LSHIFT_FPU,
OPRND_TYPE_FREG_WITH_INDEX,
+ OPRND_TYPE_VREG_WITH_INDEX,
/* r1 only, for xtrb0(1)(2)(3) in csky v1 ISA. */
OPRND_TYPE_REG_r1a,
/* r1 only, for divs/divu in csky v1 ISA. */
@@ -133,6 +134,7 @@ enum operand_type
OPRND_TYPE_IMM5b_LS,
/* Operand type for rori and rotri. */
OPRND_TYPE_IMM5b_RORI,
+ OPRND_TYPE_IMM5b_VSH,
OPRND_TYPE_IMM5b_POWER,
OPRND_TYPE_IMM5b_7_31_POWER,
OPRND_TYPE_IMM5b_BMASKI,
@@ -6416,200 +6418,215 @@ const struct csky_opcode csky_v2_opcodes[] =
/* The followings are vdsp instructions for ck810. */
OP32 ("vdup.8",
OPCODE_INFO2 (0xf8000e80,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
- (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
CSKY_ISA_VDSP),
OP32 ("vdup.16",
OPCODE_INFO2 (0xf8100e80,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
- (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
CSKY_ISA_VDSP),
OP32 ("vdup.32",
OPCODE_INFO2 (0xfa000e80,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
- (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
CSKY_ISA_VDSP),
OP32 ("vmfvr.u8",
OPCODE_INFO2 (0xf8001200,
(0_4, AREG, OPRND_SHIFT_0_BIT),
- (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
+ (16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
CSKY_ISA_VDSP),
OP32 ("vmfvr.u16",
OPCODE_INFO2 (0xf8001220,
(0_4, AREG, OPRND_SHIFT_0_BIT),
- (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
+ (16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
CSKY_ISA_VDSP),
OP32 ("vmfvr.u32",
OPCODE_INFO2 (0xf8001240,
(0_4, AREG, OPRND_SHIFT_0_BIT),
- (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
+ (16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
CSKY_ISA_VDSP),
OP32 ("vmfvr.s8",
OPCODE_INFO2 (0xf8001280,
(0_4, AREG, OPRND_SHIFT_0_BIT),
- (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
+ (16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
CSKY_ISA_VDSP),
OP32 ("vmfvr.s16",
OPCODE_INFO2 (0xf80012a0,
(0_4, AREG, OPRND_SHIFT_0_BIT),
- (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
+ (16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
CSKY_ISA_VDSP),
OP32 ("vmtvr.u8",
OPCODE_INFO2 (0xf8001300,
- (0_3or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT),
+ (0_3or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT),
(16_20, AREG, OPRND_SHIFT_0_BIT)),
CSKY_ISA_VDSP),
OP32 ("vmtvr.u16",
OPCODE_INFO2 (0xf8001320,
- (0_3or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT),
+ (0_3or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT),
(16_20, AREG, OPRND_SHIFT_0_BIT)),
CSKY_ISA_VDSP),
+ OP32 ("vins.8",
+ OPCODE_INFO2 (0xf8001400,
+ (0_3or5_8, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT),
+ (16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vins.16",
+ OPCODE_INFO2 (0xf8101400,
+ (0_3or5_8, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT),
+ (16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vins.32",
+ OPCODE_INFO2 (0xfa001400,
+ (0_3or5_8, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT),
+ (16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
OP32 ("vmtvr.u32",
OPCODE_INFO2 (0xf8001340,
- (0_3or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT),
+ (0_3or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT),
(16_20, AREG, OPRND_SHIFT_0_BIT)),
CSKY_ISA_VDSP),
OP32 ("vldd.8",
SOPCODE_INFO2 (0xf8002000,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))),
CSKY_ISA_VDSP),
OP32 ("vldd.16",
SOPCODE_INFO2 (0xf8002100,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))),
CSKY_ISA_VDSP),
OP32 ("vldd.32",
SOPCODE_INFO2 (0xf8002200,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))),
CSKY_ISA_VDSP),
OP32 ("vldq.8",
SOPCODE_INFO2 (0xf8002400,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))),
CSKY_ISA_VDSP),
OP32 ("vldq.16",
SOPCODE_INFO2 (0xf8002500,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))),
CSKY_ISA_VDSP),
OP32 ("vldq.32",
SOPCODE_INFO2 (0xf8002600,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))),
CSKY_ISA_VDSP),
OP32 ("vstd.8",
SOPCODE_INFO2 (0xf8002800,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))),
CSKY_ISA_VDSP),
OP32 ("vstd.16",
SOPCODE_INFO2 (0xf8002900,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))),
CSKY_ISA_VDSP),
OP32 ("vstd.32",
SOPCODE_INFO2 (0xf8002a00,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))),
CSKY_ISA_VDSP),
OP32 ("vstq.8",
SOPCODE_INFO2 (0xf8002c00,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))),
CSKY_ISA_VDSP),
OP32 ("vstq.16",
SOPCODE_INFO2 (0xf8002d00,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))),
CSKY_ISA_VDSP),
OP32 ("vstq.32",
SOPCODE_INFO2 (0xf8002e00,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))),
CSKY_ISA_VDSP),
OP32 ("vldrd.8",
SOPCODE_INFO2 (0xf8003000,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))),
CSKY_ISA_VDSP),
OP32 ("vldrd.16",
SOPCODE_INFO2 (0xf8003100,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))),
CSKY_ISA_VDSP),
OP32 ("vldrd.32",
SOPCODE_INFO2 (0xf8003200,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))),
CSKY_ISA_VDSP),
OP32 ("vldrq.8",
SOPCODE_INFO2 (0xf8003400,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))),
CSKY_ISA_VDSP),
OP32 ("vldrq.16",
SOPCODE_INFO2 (0xf8003500,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))),
CSKY_ISA_VDSP),
OP32 ("vldrq.32",
SOPCODE_INFO2 (0xf8003600,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))),
CSKY_ISA_VDSP),
OP32 ("vstrd.8",
SOPCODE_INFO2 (0xf8003800,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))),
CSKY_ISA_VDSP),
OP32 ("vstrd.16",
SOPCODE_INFO2 (0xf8003900,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))),
CSKY_ISA_VDSP),
OP32 ("vstrd.32",
SOPCODE_INFO2 (0xf8003a00,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))),
CSKY_ISA_VDSP),
OP32 ("vstrq.8",
SOPCODE_INFO2 (0xf8003c00,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))),
CSKY_ISA_VDSP),
OP32 ("vstrq.16",
SOPCODE_INFO2 (0xf8003d00,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))),
CSKY_ISA_VDSP),
OP32 ("vstrq.32",
SOPCODE_INFO2 (0xf8003e00,
- (0_3, FREG, OPRND_SHIFT_0_BIT),
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
(5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))),
CSKY_ISA_VDSP),
@@ -7888,6 +7905,84 @@ const struct csky_opcode csky_v2_opcodes[] =
(16_19, VREG, OPRND_SHIFT_0_BIT),
(21_24, VREG, OPRND_SHIFT_0_BIT)),
CSKY_ISA_VDSP),
+ OP32 ("vshri.u8",
+ OPCODE_INFO3 (0xf8000600,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vshri.u16",
+ OPCODE_INFO3 (0xf8100600,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vshri.u32",
+ OPCODE_INFO3 (0xfa000600,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vshri.s8",
+ OPCODE_INFO3 (0xf8000610,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vshri.s16",
+ OPCODE_INFO3 (0xf8100610,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vshri.s32",
+ OPCODE_INFO3 (0xfa000610,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vshri.u8.r",
+ OPCODE_INFO3 (0xf8000640,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vshri.u16.r",
+ OPCODE_INFO3 (0xf8100640,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vshri.u32.r",
+ OPCODE_INFO3 (0xfa000640,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vshri.s8.r",
+ OPCODE_INFO3 (0xf8000650,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vshri.s16.r",
+ OPCODE_INFO3 (0xf8100650,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vshri.s32.r",
+ OPCODE_INFO3 (0xfa000650,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vshr.s32.r",
+ OPCODE_INFO3 (0xfa0006d0,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (21_24, VREG, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
OP32 ("vshr.s32.r",
OPCODE_INFO3 (0xfa0006d0,
(0_3, VREG, OPRND_SHIFT_0_BIT),
@@ -7966,6 +8061,78 @@ const struct csky_opcode csky_v2_opcodes[] =
(16_19, VREG, OPRND_SHIFT_0_BIT),
(21_24, VREG, OPRND_SHIFT_0_BIT)),
CSKY_ISA_VDSP),
+ OP32 ("vshli.u8",
+ OPCODE_INFO3 (0xf8000700,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vshli.u16",
+ OPCODE_INFO3 (0xf8100700,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vshli.u32",
+ OPCODE_INFO3 (0xfa000700,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vshli.s8",
+ OPCODE_INFO3 (0xf8000710,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vshli.s16",
+ OPCODE_INFO3 (0xf8100710,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vshli.s32",
+ OPCODE_INFO3 (0xfa000710,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vshli.u8.s",
+ OPCODE_INFO3 (0xf8000740,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vshli.u16.s",
+ OPCODE_INFO3 (0xf8100740,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vshli.u32.s",
+ OPCODE_INFO3 (0xfa000740,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vshli.s8.s",
+ OPCODE_INFO3 (0xf8000750,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vshli.s16.s",
+ OPCODE_INFO3 (0xf8100750,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
+ OP32 ("vshli.s32.s",
+ OPCODE_INFO3 (0xfa000750,
+ (0_3, VREG, OPRND_SHIFT_0_BIT),
+ (16_19, VREG, OPRND_SHIFT_0_BIT),
+ (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+ CSKY_ISA_VDSP),
OP32 ("vcmphs.u8",
OPCODE_INFO3 (0xf8000800,
(0_3, VREG, OPRND_SHIFT_0_BIT),
--
2.26.2
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 2/4] CSKY: Add version flag in eflag and fix bug in disassembling register.
2020-10-12 14:29 [PATCH 1/4] CSKY: Fix and add some instructions for VDSPV1 Cooper Qu
@ 2020-10-12 14:30 ` Cooper Qu
2020-10-12 14:31 ` [PATCH 3/4] CSKY: Change plsl.u16 to plsl.16 Cooper Qu
2020-10-12 14:31 ` [PATCH 4/4] CSKY: Change default linker script for elf toolchain Cooper Qu
2 siblings, 0 replies; 5+ messages in thread
From: Cooper Qu @ 2020-10-12 14:30 UTC (permalink / raw)
To: binutils, lifang_xia; +Cc: Cooper Qu
gas/
* config/tc-csky.c (md_begin): Add version flag in eflag.
include/
* opcode/csky.h (CSKY_VERSION_V1): Define, currently used.
(CSKY_VERSION_V2): Define.
(CSKY_VERSION_V3): Define.
opcodes/
* csky-dis.c (get_gr_name): Fix bug in disassembling register.
(get_cr_name): Likewise.
Change-Id: Iafe3a9ce6fe544880a225b9fae439275a828bb34
---
gas/config/tc-csky.c | 2 +-
include/opcode/csky.h | 5 +++++
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/gas/config/tc-csky.c b/gas/config/tc-csky.c
index 23481b838b1..10272fede1c 100644
--- a/gas/config/tc-csky.c
+++ b/gas/config/tc-csky.c
@@ -1852,7 +1852,7 @@ md_begin (void)
str_hash_insert (csky_macros_hash,
v2_lrw_macro_opcode.name, &v2_lrw_macro_opcode, 0);
/* Set e_flag to ELF Head. */
- bfd_set_private_flags (stdoutput, mach_flag & ~(0xffff));
+ bfd_set_private_flags (stdoutput, mach_flag | CSKY_VERSION_V1);
/* Set bfd_mach to bfd backend data. */
bfd_set_arch_mach (stdoutput, bfd_arch_csky, bfd_mach_flag);
diff --git a/include/opcode/csky.h b/include/opcode/csky.h
index 1ff9dfa20f8..e368478b857 100644
--- a/include/opcode/csky.h
+++ b/include/opcode/csky.h
@@ -93,6 +93,11 @@
#define CSKY_ARCH_JAVA (1 << 8)
#define CSKY_ARCH_APS (1 << 7)
+/* eflag's Versions. */
+#define CSKY_VERSION_V1 (1 << 24)
+#define CSKY_VERSION_V2 (2 << 24)
+#define CSKY_VERSION_V3 (3 << 24)
+
#define IS_CSKY_V1(a) \
(((a) & CSKY_ABI_MASK) == CSKY_ABI_V1)
#define IS_CSKY_V2(a) \
--
2.26.2
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 3/4] CSKY: Change plsl.u16 to plsl.16.
2020-10-12 14:29 [PATCH 1/4] CSKY: Fix and add some instructions for VDSPV1 Cooper Qu
2020-10-12 14:30 ` [PATCH 2/4] CSKY: Add version flag in eflag and fix bug in disassembling register Cooper Qu
@ 2020-10-12 14:31 ` Cooper Qu
2020-10-12 14:31 ` [PATCH 4/4] CSKY: Change default linker script for elf toolchain Cooper Qu
2 siblings, 0 replies; 5+ messages in thread
From: Cooper Qu @ 2020-10-12 14:31 UTC (permalink / raw)
To: binutils, lifang_xia; +Cc: Cooper Qu
gas/
* testsuite/gas/csky/enhance_dsp.s : Change plsl.u16 to plsl.16.
* testsuite/gas/csky/enhance_dsp.d : Change plsl.u16 to plsl.16.
opcodes/
* csky-opc.h (csky_v2_opcodes): Change plsl.u16 to plsl.16.
Change-Id: Ifb43573192e215527355f6541365b9f6a8ec80a4
---
gas/testsuite/gas/csky/enhance_dsp.d | 2 +-
gas/testsuite/gas/csky/enhance_dsp.s | 2 +-
opcodes/csky-opc.h | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/gas/testsuite/gas/csky/enhance_dsp.d b/gas/testsuite/gas/csky/enhance_dsp.d
index 17b33eaecb0..5733fc6c197 100644
--- a/gas/testsuite/gas/csky/enhance_dsp.d
+++ b/gas/testsuite/gas/csky/enhance_dsp.d
@@ -110,7 +110,7 @@ Disassembly of section \.text:
\s*[0-9a-f]*:\s*f8e3d302\s*plsri\.u16\.r\s*r2,\s*r3,\s*8
\s*[0-9a-f]*:\s*f883d342\s*plsr\.u16\.r\s*r2,\s*r3,\s*r4
\s*[0-9a-f]*:\s*f8e3d402\s*plsli\.16\s*r2,\s*r3,\s*8
-\s*[0-9a-f]*:\s*fa03d442\s*plsl\.u16\s*r2,\s*r3,\s*r16
+\s*[0-9a-f]*:\s*fa03d442\s*plsl\.16\s*r2,\s*r3,\s*r16
\s*[0-9a-f]*:\s*f8e3d502\s*plsli\.u16\.s\s*r2,\s*r3,\s*8
\s*[0-9a-f]*:\s*f8e3d582\s*plsli\.s16\.s\s*r2,\s*r3,\s*8
\s*[0-9a-f]*:\s*f883d542\s*plsl\.u16\.s\s*r2,\s*r3,\s*r4
diff --git a/gas/testsuite/gas/csky/enhance_dsp.s b/gas/testsuite/gas/csky/enhance_dsp.s
index 32772e27097..4081a28869d 100644
--- a/gas/testsuite/gas/csky/enhance_dsp.s
+++ b/gas/testsuite/gas/csky/enhance_dsp.s
@@ -110,7 +110,7 @@ hello:
plsri.u16.r r2, r3, 8
plsr.u16.r r2, r3, r4
plsli.16 r2, r3, 8
- plsl.u16 r2, r3, r16
+ plsl.16 r2, r3, r16
plsli.u16.s r2, r3, 8
plsli.s16.s r2, r3, 8
plsl.u16.s r2, r3, r4
diff --git a/opcodes/csky-opc.h b/opcodes/csky-opc.h
index e309253a18c..fd84fd99e5a 100644
--- a/opcodes/csky-opc.h
+++ b/opcodes/csky-opc.h
@@ -5782,7 +5782,7 @@ const struct csky_opcode csky_v2_opcodes[] =
(16_20, AREG, OPRND_SHIFT_0_BIT),
(21_25, OIMM4b, OPRND_SHIFT_0_BIT)),
CSKY_ISA_DSP_ENHANCE),
- OP32 ("plsl.u16",
+ OP32 ("plsl.16",
OPCODE_INFO3 (0xf800d440,
(0_4, AREG, OPRND_SHIFT_0_BIT),
(16_20, AREG, OPRND_SHIFT_0_BIT),
--
2.26.2
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 4/4] CSKY: Change default linker script for elf toolchain.
2020-10-12 14:29 [PATCH 1/4] CSKY: Fix and add some instructions for VDSPV1 Cooper Qu
2020-10-12 14:30 ` [PATCH 2/4] CSKY: Add version flag in eflag and fix bug in disassembling register Cooper Qu
2020-10-12 14:31 ` [PATCH 3/4] CSKY: Change plsl.u16 to plsl.16 Cooper Qu
@ 2020-10-12 14:31 ` Cooper Qu
2020-10-26 9:16 ` Lifang Xia
2 siblings, 1 reply; 5+ messages in thread
From: Cooper Qu @ 2020-10-12 14:31 UTC (permalink / raw)
To: binutils, lifang_xia; +Cc: Cooper Qu
ld/
* emulparams/cskyelf.sh (TEXT_START_ADDR): Change to 0x60000000.
(DATA_ADDR) : Define.
(OTHER_SYMBOLS) : Define.
(OTHER_BSS_SYMBOLS) : Set symbol __sbss__.
(OTHER_BSS_END_SYMBOLS) : Set symbol __ebss__.
* ld/emulparams/cskyelf_linux.sh : Don't include cskyelf.sh.
* testsuite/ld-csky/data.d : Fix '/s*' to match spaces.
* testsuite/ld-csky/hilo16.d : Likewise.
Change-Id: Ia29b32eab4157ae5be0fc0b6125fb5b7d9dac939
---
ld/emulparams/cskyelf.sh | 15 +++++++++-----
ld/emulparams/cskyelf_linux.sh | 36 +++++++++++++++++++++++++++++++++-
ld/testsuite/ld-csky/data.d | 12 ++++++------
ld/testsuite/ld-csky/hilo16.d | 4 ++--
4 files changed, 53 insertions(+), 14 deletions(-)
diff --git a/ld/emulparams/cskyelf.sh b/ld/emulparams/cskyelf.sh
index b940c6c2978..58cab16844a 100644
--- a/ld/emulparams/cskyelf.sh
+++ b/ld/emulparams/cskyelf.sh
@@ -1,5 +1,3 @@
-# If you change this file, please also look at files which source this one:
-# cskyelf_linux.sh
SCRIPT_NAME=elf
OUTPUT_FORMAT="elf32-csky-little"
BIG_OUTPUT_FORMAT="elf32-csky-big"
@@ -7,7 +5,14 @@ LITTLE_OUTPUT_FORMAT="elf32-csky-little"
NO_REL_RELOCS=yes
TARGET_PAGE_SIZE=0x400
MAXPAGESIZE="CONSTANT (MAXPAGESIZE)"
-TEXT_START_ADDR=0x8000
+TEXT_START_ADDR=0x60000000
+DATA_ADDR=0x20000000
+OTHER_SYMBOLS='
+ PROVIDE (__stack = 0x01000000 - 0x8);
+ PROVIDE (__heap_start = 0x00000100);
+ PROVIDE (__heap_end = 0x00900000);
+ PROVIDE (__csky_exit = 0x10002000);
+'
CHECK_RELOCS_AFTER_OPEN_INPUT=yes
NONPAGED_TEXT_START_ADDR=0
ATTRS_SECTIONS='.csky.attributes 0 : { KEEP (*(.csky.attributes)) KEEP (*(.csky.attributes)) }'
@@ -27,8 +32,8 @@ EXTRA_EM_FILE=cskyelf
NOP=0
ENTRY=__start
-OTHER_BSS_SYMBOLS="__bss_start__ = . ;"
-OTHER_BSS_END_SYMBOLS="__bss_end__ = . ;"
+OTHER_BSS_SYMBOLS="__sbss__ = . ;"
+OTHER_BSS_END_SYMBOLS="__ebss__ = . ;"
# This sets the stack to the top of the simulator memory (2^19 bytes).
# STACK_ADDR=0x80000
diff --git a/ld/emulparams/cskyelf_linux.sh b/ld/emulparams/cskyelf_linux.sh
index 84fbbf8ef5c..d29233f9301 100644
--- a/ld/emulparams/cskyelf_linux.sh
+++ b/ld/emulparams/cskyelf_linux.sh
@@ -1,4 +1,38 @@
-source_sh ${srcdir}/emulparams/cskyelf.sh
+SCRIPT_NAME=elf
+OUTPUT_FORMAT="elf32-csky-little"
+BIG_OUTPUT_FORMAT="elf32-csky-big"
+LITTLE_OUTPUT_FORMAT="elf32-csky-little"
+NO_REL_RELOCS=yes
+TARGET_PAGE_SIZE=0x400
+MAXPAGESIZE="CONSTANT (MAXPAGESIZE)"
+TEXT_START_ADDR=0x8000
+CHECK_RELOCS_AFTER_OPEN_INPUT=yes
+NONPAGED_TEXT_START_ADDR=0
+ATTRS_SECTIONS='.csky.attributes 0 : { KEEP (*(.csky.attributes)) KEEP (*(.csky.attributes)) }'
+ARCH=csky
+EMBEDDED=yes
+EXTRA_EM_FILE=cskyelf
+
+# There is a problem with the NOP value - it must work for both
+# big endian and little endian systems. Unfortunately there is
+# no symmetrical mcore opcode that functions as a noop. The
+# chosen solution is to use "tst r0, r14". This is a symmetrical
+# value, and apart from the corruption of the C bit, it has no other
+# side effects. Since the carry bit is never tested without being
+# explicitly set first, and since the NOP code is only used as a
+# fill value between independently viable pieces of code, it should
+# not matter.
+NOP=0
+
+ENTRY=__start
+OTHER_BSS_SYMBOLS="__bss_start__ = . ;"
+OTHER_BSS_END_SYMBOLS="__bss_end__ = . ;"
+
+# This sets the stack to the top of the simulator memory (2^19 bytes).
+# STACK_ADDR=0x80000
+
+TEMPLATE_NAME=elf
+
unset EMBEDDED
unset ENTRY
diff --git a/ld/testsuite/ld-csky/data.d b/ld/testsuite/ld-csky/data.d
index 21b2f27f45b..f1dd470094e 100644
--- a/ld/testsuite/ld-csky/data.d
+++ b/ld/testsuite/ld-csky/data.d
@@ -10,9 +10,9 @@
Disassembly of section .text:
[0-9a-f]+ <__start>:
- [0-9a-f]+: cd400004 lrs.b r10, \[0x4\] // the offset is based on .data
- [0-9a-f]+: cd440002 lrs.h r10, \[0x2\] // the offset is based on .data
- [0-9a-f]+: cd480001 lrs.w r10, \[0x1\] // the offset is based on .data
- [0-9a-f]+: cd700004 srs.b r11, \[0x4\] // the offset is based on .data
- [0-9a-f]+: cd740002 srs.h r11, \[0x2\] // the offset is based on .data
- [0-9a-f]+: cd780001 srs.w r11, \[0x1\] // the offset is based on .data
+\s*[0-9a-f]+: cd400004 lrs.b r10, \[0x4\] // the offset is based on .data
+\s*[0-9a-f]+: cd440002 lrs.h r10, \[0x2\] // the offset is based on .data
+\s*[0-9a-f]+: cd480001 lrs.w r10, \[0x1\] // the offset is based on .data
+\s*[0-9a-f]+: cd700004 srs.b r11, \[0x4\] // the offset is based on .data
+\s*[0-9a-f]+: cd740002 srs.h r11, \[0x2\] // the offset is based on .data
+\s*[0-9a-f]+: cd780001 srs.w r11, \[0x1\] // the offset is based on .data
diff --git a/ld/testsuite/ld-csky/hilo16.d b/ld/testsuite/ld-csky/hilo16.d
index f2435c0ad08..d038a06cf70 100644
--- a/ld/testsuite/ld-csky/hilo16.d
+++ b/ld/testsuite/ld-csky/hilo16.d
@@ -10,5 +10,5 @@
Disassembly of section .text:
[0-9a-f]+ <__start>:
- [0-9a-f]+: ea21dead movih r1, 57005
- [0-9a-f]+: ec21beef ori r1, r1, 48879
+\s*[0-9a-f]+: ea21dead movih r1, 57005
+\s*[0-9a-f]+: ec21beef ori r1, r1, 48879
--
2.26.2
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 4/4] CSKY: Change default linker script for elf toolchain.
2020-10-12 14:31 ` [PATCH 4/4] CSKY: Change default linker script for elf toolchain Cooper Qu
@ 2020-10-26 9:16 ` Lifang Xia
0 siblings, 0 replies; 5+ messages in thread
From: Lifang Xia @ 2020-10-26 9:16 UTC (permalink / raw)
To: Cooper Qu, binutils
Hi Cooper,
All of the 4 patches are commited.
The 4/4 patch which modifies the default address spaces in the linker, I
add some comment in the source files which are descripted the default
adress spaces.
Best Regards,
Lifang Xia
On 2020/10/12 22:31, Cooper Qu wrote:
> ld/
> * emulparams/cskyelf.sh (TEXT_START_ADDR): Change to 0x60000000.
> (DATA_ADDR) : Define.
> (OTHER_SYMBOLS) : Define.
> (OTHER_BSS_SYMBOLS) : Set symbol __sbss__.
> (OTHER_BSS_END_SYMBOLS) : Set symbol __ebss__.
> * ld/emulparams/cskyelf_linux.sh : Don't include cskyelf.sh.
> * testsuite/ld-csky/data.d : Fix '/s*' to match spaces.
> * testsuite/ld-csky/hilo16.d : Likewise.
>
> Change-Id: Ia29b32eab4157ae5be0fc0b6125fb5b7d9dac939
> ---
> ld/emulparams/cskyelf.sh | 15 +++++++++-----
> ld/emulparams/cskyelf_linux.sh | 36 +++++++++++++++++++++++++++++++++-
> ld/testsuite/ld-csky/data.d | 12 ++++++------
> ld/testsuite/ld-csky/hilo16.d | 4 ++--
> 4 files changed, 53 insertions(+), 14 deletions(-)
>
> diff --git a/ld/emulparams/cskyelf.sh b/ld/emulparams/cskyelf.sh
> index b940c6c2978..58cab16844a 100644
> --- a/ld/emulparams/cskyelf.sh
> +++ b/ld/emulparams/cskyelf.sh
> @@ -1,5 +1,3 @@
> -# If you change this file, please also look at files which source this one:
> -# cskyelf_linux.sh
> SCRIPT_NAME=elf
> OUTPUT_FORMAT="elf32-csky-little"
> BIG_OUTPUT_FORMAT="elf32-csky-big"
> @@ -7,7 +5,14 @@ LITTLE_OUTPUT_FORMAT="elf32-csky-little"
> NO_REL_RELOCS=yes
> TARGET_PAGE_SIZE=0x400
> MAXPAGESIZE="CONSTANT (MAXPAGESIZE)"
> -TEXT_START_ADDR=0x8000
> +TEXT_START_ADDR=0x60000000
> +DATA_ADDR=0x20000000
> +OTHER_SYMBOLS='
> + PROVIDE (__stack = 0x01000000 - 0x8);
> + PROVIDE (__heap_start = 0x00000100);
> + PROVIDE (__heap_end = 0x00900000);
> + PROVIDE (__csky_exit = 0x10002000);
> +'
> CHECK_RELOCS_AFTER_OPEN_INPUT=yes
> NONPAGED_TEXT_START_ADDR=0
> ATTRS_SECTIONS='.csky.attributes 0 : { KEEP (*(.csky.attributes)) KEEP (*(.csky.attributes)) }'
> @@ -27,8 +32,8 @@ EXTRA_EM_FILE=cskyelf
> NOP=0
>
> ENTRY=__start
> -OTHER_BSS_SYMBOLS="__bss_start__ = . ;"
> -OTHER_BSS_END_SYMBOLS="__bss_end__ = . ;"
> +OTHER_BSS_SYMBOLS="__sbss__ = . ;"
> +OTHER_BSS_END_SYMBOLS="__ebss__ = . ;"
>
> # This sets the stack to the top of the simulator memory (2^19 bytes).
> # STACK_ADDR=0x80000
> diff --git a/ld/emulparams/cskyelf_linux.sh b/ld/emulparams/cskyelf_linux.sh
> index 84fbbf8ef5c..d29233f9301 100644
> --- a/ld/emulparams/cskyelf_linux.sh
> +++ b/ld/emulparams/cskyelf_linux.sh
> @@ -1,4 +1,38 @@
> -source_sh ${srcdir}/emulparams/cskyelf.sh
> +SCRIPT_NAME=elf
> +OUTPUT_FORMAT="elf32-csky-little"
> +BIG_OUTPUT_FORMAT="elf32-csky-big"
> +LITTLE_OUTPUT_FORMAT="elf32-csky-little"
> +NO_REL_RELOCS=yes
> +TARGET_PAGE_SIZE=0x400
> +MAXPAGESIZE="CONSTANT (MAXPAGESIZE)"
> +TEXT_START_ADDR=0x8000
> +CHECK_RELOCS_AFTER_OPEN_INPUT=yes
> +NONPAGED_TEXT_START_ADDR=0
> +ATTRS_SECTIONS='.csky.attributes 0 : { KEEP (*(.csky.attributes)) KEEP (*(.csky.attributes)) }'
> +ARCH=csky
> +EMBEDDED=yes
> +EXTRA_EM_FILE=cskyelf
> +
> +# There is a problem with the NOP value - it must work for both
> +# big endian and little endian systems. Unfortunately there is
> +# no symmetrical mcore opcode that functions as a noop. The
> +# chosen solution is to use "tst r0, r14". This is a symmetrical
> +# value, and apart from the corruption of the C bit, it has no other
> +# side effects. Since the carry bit is never tested without being
> +# explicitly set first, and since the NOP code is only used as a
> +# fill value between independently viable pieces of code, it should
> +# not matter.
> +NOP=0
> +
> +ENTRY=__start
> +OTHER_BSS_SYMBOLS="__bss_start__ = . ;"
> +OTHER_BSS_END_SYMBOLS="__bss_end__ = . ;"
> +
> +# This sets the stack to the top of the simulator memory (2^19 bytes).
> +# STACK_ADDR=0x80000
> +
> +TEMPLATE_NAME=elf
> +
>
> unset EMBEDDED
> unset ENTRY
> diff --git a/ld/testsuite/ld-csky/data.d b/ld/testsuite/ld-csky/data.d
> index 21b2f27f45b..f1dd470094e 100644
> --- a/ld/testsuite/ld-csky/data.d
> +++ b/ld/testsuite/ld-csky/data.d
> @@ -10,9 +10,9 @@
> Disassembly of section .text:
>
> [0-9a-f]+ <__start>:
> - [0-9a-f]+: cd400004 lrs.b r10, \[0x4\] // the offset is based on .data
> - [0-9a-f]+: cd440002 lrs.h r10, \[0x2\] // the offset is based on .data
> - [0-9a-f]+: cd480001 lrs.w r10, \[0x1\] // the offset is based on .data
> - [0-9a-f]+: cd700004 srs.b r11, \[0x4\] // the offset is based on .data
> - [0-9a-f]+: cd740002 srs.h r11, \[0x2\] // the offset is based on .data
> - [0-9a-f]+: cd780001 srs.w r11, \[0x1\] // the offset is based on .data
> +\s*[0-9a-f]+: cd400004 lrs.b r10, \[0x4\] // the offset is based on .data
> +\s*[0-9a-f]+: cd440002 lrs.h r10, \[0x2\] // the offset is based on .data
> +\s*[0-9a-f]+: cd480001 lrs.w r10, \[0x1\] // the offset is based on .data
> +\s*[0-9a-f]+: cd700004 srs.b r11, \[0x4\] // the offset is based on .data
> +\s*[0-9a-f]+: cd740002 srs.h r11, \[0x2\] // the offset is based on .data
> +\s*[0-9a-f]+: cd780001 srs.w r11, \[0x1\] // the offset is based on .data
> diff --git a/ld/testsuite/ld-csky/hilo16.d b/ld/testsuite/ld-csky/hilo16.d
> index f2435c0ad08..d038a06cf70 100644
> --- a/ld/testsuite/ld-csky/hilo16.d
> +++ b/ld/testsuite/ld-csky/hilo16.d
> @@ -10,5 +10,5 @@
> Disassembly of section .text:
>
> [0-9a-f]+ <__start>:
> - [0-9a-f]+: ea21dead movih r1, 57005
> - [0-9a-f]+: ec21beef ori r1, r1, 48879
> +\s*[0-9a-f]+: ea21dead movih r1, 57005
> +\s*[0-9a-f]+: ec21beef ori r1, r1, 48879
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-10-26 9:18 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-10-12 14:29 [PATCH 1/4] CSKY: Fix and add some instructions for VDSPV1 Cooper Qu
2020-10-12 14:30 ` [PATCH 2/4] CSKY: Add version flag in eflag and fix bug in disassembling register Cooper Qu
2020-10-12 14:31 ` [PATCH 3/4] CSKY: Change plsl.u16 to plsl.16 Cooper Qu
2020-10-12 14:31 ` [PATCH 4/4] CSKY: Change default linker script for elf toolchain Cooper Qu
2020-10-26 9:16 ` Lifang Xia
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