* [PATCH] ld:LoongArch: Add test cases to adapt to LoongArch32 and LoongArch64
@ 2022-03-14 2:47 liuzhensong
0 siblings, 0 replies; only message in thread
From: liuzhensong @ 2022-03-14 2:47 UTC (permalink / raw)
To: binutils; +Cc: liuzhensong
ld/testsuite/ld-loongarch-elf
* ld-loongarch-elf.exp: Test LoongArch32 and LoongArch64 testcases respectively.
* jmp_op.d: Fix bug in test LoongArch32.
* disas-jirl-32.d: New test case for LoongArch32.
* disas-jirl-32.s: New test case for LoongArch32.
* disas-jirl.d: Skip test case LoongArch32.
* macro_op_32.d: New test case for LoongArch32.
* macro_op_32.s: New test case for LoongArch32.
* macro_op.d: Skip test case LoongArch32.
---
ld/testsuite/ld-loongarch-elf/disas-jirl-32.d | 15 +
ld/testsuite/ld-loongarch-elf/disas-jirl-32.s | 5 +
ld/testsuite/ld-loongarch-elf/disas-jirl.d | 3 +-
ld/testsuite/ld-loongarch-elf/jmp_op.d | 2 +-
.../ld-loongarch-elf/ld-loongarch-elf.exp | 9 +-
ld/testsuite/ld-loongarch-elf/macro_op.d | 3 +-
ld/testsuite/ld-loongarch-elf/macro_op_32.d | 729 ++++++++++++++++++
ld/testsuite/ld-loongarch-elf/macro_op_32.s | 29 +
8 files changed, 791 insertions(+), 4 deletions(-)
create mode 100644 ld/testsuite/ld-loongarch-elf/disas-jirl-32.d
create mode 100644 ld/testsuite/ld-loongarch-elf/disas-jirl-32.s
create mode 100644 ld/testsuite/ld-loongarch-elf/macro_op_32.d
create mode 100644 ld/testsuite/ld-loongarch-elf/macro_op_32.s
diff --git a/ld/testsuite/ld-loongarch-elf/disas-jirl-32.d b/ld/testsuite/ld-loongarch-elf/disas-jirl-32.d
new file mode 100644
index 00000000000..6621c03e5bc
--- /dev/null
+++ b/ld/testsuite/ld-loongarch-elf/disas-jirl-32.d
@@ -0,0 +1,15 @@
+#name: jirl zero-offset symbols for LoongArch32
+#source: disas-jirl-32.s
+#ld: --no-relax
+#objdump: -d
+#skip: loongarch64-*-*
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+00010054 <_start>:
+[ ]+10054:[ ]+1c000014 [ ]+pcaddu12i[ ]+[ ]+\$t8, 0
+[ ]+10058:[ ]+02800294 [ ]+addi.w[ ]+[ ]+\$t8, \$t8, 0
+[ ]+1005c:[ ]+4c000281 [ ]+jirl[ ]+[ ]+\$ra, \$t8, 0
diff --git a/ld/testsuite/ld-loongarch-elf/disas-jirl-32.s b/ld/testsuite/ld-loongarch-elf/disas-jirl-32.s
new file mode 100644
index 00000000000..d6027c9cc9a
--- /dev/null
+++ b/ld/testsuite/ld-loongarch-elf/disas-jirl-32.s
@@ -0,0 +1,5 @@
+ .text
+ .globl _start
+_start:
+ la.local $r20,_start
+ jirl $r1, $r20, 0
diff --git a/ld/testsuite/ld-loongarch-elf/disas-jirl.d b/ld/testsuite/ld-loongarch-elf/disas-jirl.d
index 8c60f634156..f79111a5d8b 100644
--- a/ld/testsuite/ld-loongarch-elf/disas-jirl.d
+++ b/ld/testsuite/ld-loongarch-elf/disas-jirl.d
@@ -1,7 +1,8 @@
-#name: jirl zero-offset symbols
+#name: jirl zero-offset symbols for LoongArch64
#source: disas-jirl.s
#ld: --no-relax
#objdump: -d
+#skip: loongarch32-*-*
.*:[ ]+file format .*
diff --git a/ld/testsuite/ld-loongarch-elf/jmp_op.d b/ld/testsuite/ld-loongarch-elf/jmp_op.d
index e6c50e8e991..c68f7aa49ba 100644
--- a/ld/testsuite/ld-loongarch-elf/jmp_op.d
+++ b/ld/testsuite/ld-loongarch-elf/jmp_op.d
@@ -6,7 +6,7 @@
Disassembly of section .text:
-0000000000000000 <.text>:
+0+0 <.text>:
[ ]+0:[ ]+03400000 [ ]+andi[ ]+[ ]+\$zero, \$zero, 0x0
[ ]+4:[ ]+60000004 [ ]+bgtz[ ]+[ ]+\$a0, 0[ ]+# 0x4
[ ]+[ ]+[ ]+4: R_LARCH_SOP_PUSH_PCREL[ ]+L1
diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp
index c9480ab3323..dfa8ee18865 100644
--- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp
+++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp
@@ -26,9 +26,16 @@ proc loongarch_choose_lp64_emul {} {
return "elf64lloongarch"
}
-if [istarget "loongarch*-*-*"] {
+if [istarget "loongarch64-*-*"] {
run_dump_test "jmp_op"
run_dump_test "macro_op"
run_dump_test "syscall"
run_dump_test "disas-jirl"
}
+
+if [istarget "loongarch32-*-*"] {
+ run_dump_test "jmp_op"
+ run_dump_test "macro_op_32"
+ run_dump_test "syscall"
+ run_dump_test "disas-jirl-32"
+}
diff --git a/ld/testsuite/ld-loongarch-elf/macro_op.d b/ld/testsuite/ld-loongarch-elf/macro_op.d
index 548553eedbc..af100608824 100644
--- a/ld/testsuite/ld-loongarch-elf/macro_op.d
+++ b/ld/testsuite/ld-loongarch-elf/macro_op.d
@@ -1,12 +1,13 @@
#as:
#objdump: -dr
+#skip: loongarch32-*-*
.*:[ ]+file format .*
Disassembly of section .text:
-0000000000000000 <.text>:
+0+0 <.text>:
[ ]+0:[ ]+00150004 [ ]+move[ ]+[ ]+\$a0, \$zero
[ ]+4:[ ]+02bffc04 [ ]+addi.w[ ]+[ ]+\$a0, \$zero, -1\(0xfff\)
[ ]+8:[ ]+00150004 [ ]+move[ ]+[ ]+\$a0, \$zero
diff --git a/ld/testsuite/ld-loongarch-elf/macro_op_32.d b/ld/testsuite/ld-loongarch-elf/macro_op_32.d
new file mode 100644
index 00000000000..24906ecfd04
--- /dev/null
+++ b/ld/testsuite/ld-loongarch-elf/macro_op_32.d
@@ -0,0 +1,729 @@
+#as:
+#objdump: -dr
+#skip: loongarch64-*-*
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+0 <.text>:
+[ ]+0:[ ]+00150004 [ ]+move[ ]+[ ]+\$a0, \$zero
+[ ]+4:[ ]+02bffc04 [ ]+addi.w[ ]+[ ]+\$a0, \$zero, -1\(0xfff\)
+[ ]+8:[ ]+00150004 [ ]+move[ ]+[ ]+\$a0, \$zero
+[ ]+c:[ ]+02bffc04 [ ]+addi.w[ ]+[ ]+\$a0, \$zero, -1\(0xfff\)
+[ ]+10:[ ]+1c000004 [ ]+pcaddu12i[ ]+[ ]+\$a0, 0
+[ ]+[ ]+[ ]+10: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x800
+[ ]+[ ]+[ ]+10: R_LARCH_SOP_PUSH_GPREL[ ]+L1
+[ ]+[ ]+[ ]+10: R_LARCH_SOP_ADD[ ]+\*ABS\*
+[ ]+[ ]+[ ]+10: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x20
+[ ]+[ ]+[ ]+10: R_LARCH_SOP_SL[ ]+\*ABS\*
+[ ]+[ ]+[ ]+10: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x2c
+[ ]+[ ]+[ ]+10: R_LARCH_SOP_SR[ ]+\*ABS\*
+[ ]+[ ]+[ ]+10: R_LARCH_SOP_POP_32_S_5_20[ ]+\*ABS\*
+[ ]+14:[ ]+28800084 [ ]+ld.w[ ]+[ ]+\$a0, \$a0, 0
+[ ]+[ ]+[ ]+14: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x4
+[ ]+[ ]+[ ]+14: R_LARCH_SOP_PUSH_GPREL[ ]+L1
+[ ]+[ ]+[ ]+14: R_LARCH_SOP_ADD[ ]+\*ABS\*
+[ ]+[ ]+[ ]+14: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x804
+[ ]+[ ]+[ ]+14: R_LARCH_SOP_PUSH_GPREL[ ]+L1
+[ ]+[ ]+[ ]+14: R_LARCH_SOP_ADD[ ]+\*ABS\*
+[ ]+[ ]+[ ]+14: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0xc
+[ ]+[ ]+[ ]+14: R_LARCH_SOP_SR[ ]+\*ABS\*
+[ ]+[ ]+[ ]+14: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0xc
+[ ]+[ ]+[ ]+14: R_LARCH_SOP_SL[ ]+\*ABS\*
+[ ]+[ ]+[ ]+14: R_LARCH_SOP_SUB[ ]+\*ABS\*
+[ ]+[ ]+[ ]+14: R_LARCH_SOP_POP_32_S_10_12[ ]+\*ABS\*
+[ ]+18:[ ]+1c000004 [ ]+pcaddu12i[ ]+[ ]+\$a0, 0
+[ ]+[ ]+[ ]+18: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x800
+[ ]+[ ]+[ ]+18: R_LARCH_SOP_PUSH_GPREL[ ]+L1
+[ ]+[ ]+[ ]+18: R_LARCH_SOP_ADD[ ]+\*ABS\*
+[ ]+[ ]+[ ]+18: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x20
+[ ]+[ ]+[ ]+18: R_LARCH_SOP_SL[ ]+\*ABS\*
+[ ]+[ ]+[ ]+18: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x2c
+[ ]+[ ]+[ ]+18: R_LARCH_SOP_SR[ ]+\*ABS\*
+[ ]+[ ]+[ ]+18: R_LARCH_SOP_POP_32_S_5_20[ ]+\*ABS\*
+[ ]+1c:[ ]+28800084 [ ]+ld.w[ ]+[ ]+\$a0, \$a0, 0
+[ ]+[ ]+[ ]+1c: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x4
+[ ]+[ ]+[ ]+1c: R_LARCH_SOP_PUSH_GPREL[ ]+L1
+[ ]+[ ]+[ ]+1c: R_LARCH_SOP_ADD[ ]+\*ABS\*
+[ ]+[ ]+[ ]+1c: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x804
+[ ]+[ ]+[ ]+1c: R_LARCH_SOP_PUSH_GPREL[ ]+L1
+[ ]+[ ]+[ ]+1c: R_LARCH_SOP_ADD[ ]+\*ABS\*
+[ ]+[ ]+[ ]+1c: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0xc
+[ ]+[ ]+[ ]+1c: R_LARCH_SOP_SR[ ]+\*ABS\*
+[ ]+[ ]+[ ]+1c: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0xc
+[ ]+[ ]+[ ]+1c: R_LARCH_SOP_SL[ ]+\*ABS\*
+[ ]+[ ]+[ ]+1c: R_LARCH_SOP_SUB[ ]+\*ABS\*
+[ ]+[ ]+[ ]+1c: R_LARCH_SOP_POP_32_S_10_12[ ]+\*ABS\*
+[ ]+20:[ ]+1c000004 [ ]+pcaddu12i[ ]+[ ]+\$a0, 0
+[ ]+[ ]+[ ]+20: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_
+[ ]+[ ]+[ ]+20: R_LARCH_SOP_PUSH_GPREL[ ]+L1
+[ ]+[ ]+[ ]+20: R_LARCH_SOP_ADD[ ]+\*ABS\*
+[ ]+[ ]+[ ]+20: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\-0x80000000
+[ ]+[ ]+[ ]+20: R_LARCH_SOP_PUSH_GPREL[ ]+L1
+[ ]+[ ]+[ ]+20: R_LARCH_SOP_ADD[ ]+\*ABS\*
+[ ]+[ ]+[ ]+20: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x20
+[ ]+[ ]+[ ]+20: R_LARCH_SOP_SR[ ]+\*ABS\*
+[ ]+[ ]+[ ]+20: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x20
+[ ]+[ ]+[ ]+20: R_LARCH_SOP_SL[ ]+\*ABS\*
+[ ]+[ ]+[ ]+20: R_LARCH_SOP_SUB[ ]+\*ABS\*
+[ ]+[ ]+[ ]+20: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x20
+[ ]+[ ]+[ ]+20: R_LARCH_SOP_SL[ ]+\*ABS\*
+[ ]+[ ]+[ ]+20: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x2c
+[ ]+[ ]+[ ]+20: R_LARCH_SOP_SR[ ]+\*ABS\*
+[ ]+[ ]+[ ]+20: R_LARCH_SOP_POP_32_S_5_20[ ]+\*ABS\*
+[ ]+24:[ ]+03800005 [ ]+ori[ ]+[ ]+\$a1, \$zero, 0x0
+[ ]+[ ]+[ ]+24: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x4
+[ ]+[ ]+[ ]+24: R_LARCH_SOP_PUSH_GPREL[ ]+L1
+[ ]+[ ]+[ ]+24: R_LARCH_SOP_ADD[ ]+\*ABS\*
+[ ]+[ ]+[ ]+24: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\-0x7ffffffc
+[ ]+[ ]+[ ]+24: R_LARCH_SOP_PUSH_GPREL[ ]+L1
+[ ]+[ ]+[ ]+24: R_LARCH_SOP_ADD[ ]+\*ABS\*
+[ ]+[ ]+[ ]+24: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x20
+[ ]+[ ]+[ ]+24: R_LARCH_SOP_SR[ ]+\*ABS\*
+[ ]+[ ]+[ ]+24: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x20
+[ ]+[ ]+[ ]+24: R_LARCH_SOP_SL[ ]+\*ABS\*
+[ ]+[ ]+[ ]+24: R_LARCH_SOP_SUB[ ]+\*ABS\*
+[ ]+[ ]+[ ]+24: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0xfff
+[ ]+[ ]+[ ]+24: R_LARCH_SOP_AND[ ]+\*ABS\*
+[ ]+[ ]+[ ]+24: R_LARCH_SOP_POP_32_U_10_12[ ]+\*ABS\*
+[ ]+28:[ ]+16000005 [ ]+lu32i.d[ ]+[ ]+\$a1, 0
+[ ]+[ ]+[ ]+28: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\-0x7ffffff8
+[ ]+[ ]+[ ]+28: R_LARCH_SOP_PUSH_GPREL[ ]+L1
+[ ]+[ ]+[ ]+28: R_LARCH_SOP_ADD[ ]+\*ABS\*
+[ ]+[ ]+[ ]+28: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0xc
+[ ]+[ ]+[ ]+28: R_LARCH_SOP_SL[ ]+\*ABS\*
+[ ]+[ ]+[ ]+28: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x2c
+[ ]+[ ]+[ ]+28: R_LARCH_SOP_SR[ ]+\*ABS\*
+[ ]+[ ]+[ ]+28: R_LARCH_SOP_POP_32_S_5_20[ ]+\*ABS\*
+[ ]+2c:[ ]+030000a5 [ ]+lu52i.d[ ]+[ ]+\$a1, \$a1, 0
+[ ]+[ ]+[ ]+2c: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\-0x7ffffff4
+[ ]+[ ]+[ ]+2c: R_LARCH_SOP_PUSH_GPREL[ ]+L1
+[ ]+[ ]+[ ]+2c: R_LARCH_SOP_ADD[ ]+\*ABS\*
+[ ]+[ ]+[ ]+2c: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x34
+[ ]+[ ]+[ ]+2c: R_LARCH_SOP_SR[ ]+\*ABS\*
+[ ]+[ ]+[ ]+2c: R_LARCH_SOP_POP_32_S_10_12[ ]+\*ABS\*
+[ ]+30:[ ]+380c1484 [ ]+ldx.d[ ]+[ ]+\$a0, \$a0, \$a1
+[ ]+34:[ ]+1c000004 [ ]+pcaddu12i[ ]+[ ]+\$a0, 0
+[ ]+[ ]+[ ]+34: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x800
+[ ]+[ ]+[ ]+34: R_LARCH_SOP_PUSH_GPREL[ ]+L1
+[ ]+[ ]+[ ]+34: R_LARCH_SOP_ADD[ ]+\*ABS\*
+[ ]+[ ]+[ ]+34: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x20
+[ ]+[ ]+[ ]+34: R_LARCH_SOP_SL[ ]+\*ABS\*
+[ ]+[ ]+[ ]+34: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x2c
+[ ]+[ ]+[ ]+34: R_LARCH_SOP_SR[ ]+\*ABS\*
+[ ]+[ ]+[ ]+34: R_LARCH_SOP_POP_32_S_5_20[ ]+\*ABS\*
+[ ]+38:[ ]+28800084 [ ]+ld.w[ ]+[ ]+\$a0, \$a0, 0
+[ ]+[ ]+[ ]+38: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x4
+[ ]+[ ]+[ ]+38: R_LARCH_SOP_PUSH_GPREL[ ]+L1
+[ ]+[ ]+[ ]+38: R_LARCH_SOP_ADD[ ]+\*ABS\*
+[ ]+[ ]+[ ]+38: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x804
+[ ]+[ ]+[ ]+38: R_LARCH_SOP_PUSH_GPREL[ ]+L1
+[ ]+[ ]+[ ]+38: R_LARCH_SOP_ADD[ ]+\*ABS\*
+[ ]+[ ]+[ ]+38: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0xc
+[ ]+[ ]+[ ]+38: R_LARCH_SOP_SR[ ]+\*ABS\*
+[ ]+[ ]+[ ]+38: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0xc
+[ ]+[ ]+[ ]+38: R_LARCH_SOP_SL[ ]+\*ABS\*
+[ ]+[ ]+[ ]+38: R_LARCH_SOP_SUB[ ]+\*ABS\*
+[ ]+[ ]+[ ]+38: R_LARCH_SOP_POP_32_S_10_12[ ]+\*ABS\*
+[ ]+3c:[ ]+1c000004 [ ]+pcaddu12i[ ]+[ ]+\$a0, 0
+[ ]+[ ]+[ ]+3c: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_
+[ ]+[ ]+[ ]+3c: R_LARCH_SOP_PUSH_GPREL[ ]+L1
+[ ]+[ ]+[ ]+3c: R_LARCH_SOP_ADD[ ]+\*ABS\*
+[ ]+[ ]+[ ]+3c: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\-0x80000000
+[ ]+[ ]+[ ]+3c: R_LARCH_SOP_PUSH_GPREL[ ]+L1
+[ ]+[ ]+[ ]+3c: R_LARCH_SOP_ADD[ ]+\*ABS\*
+[ ]+[ ]+[ ]+3c: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x20
+[ ]+[ ]+[ ]+3c: R_LARCH_SOP_SR[ ]+\*ABS\*
+[ ]+[ ]+[ ]+3c: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x20
+[ ]+[ ]+[ ]+3c: R_LARCH_SOP_SL[ ]+\*ABS\*
+[ ]+[ ]+[ ]+3c: R_LARCH_SOP_SUB[ ]+\*ABS\*
+[ ]+[ ]+[ ]+3c: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x20
+[ ]+[ ]+[ ]+3c: R_LARCH_SOP_SL[ ]+\*ABS\*
+[ ]+[ ]+[ ]+3c: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x2c
+[ ]+[ ]+[ ]+3c: R_LARCH_SOP_SR[ ]+\*ABS\*
+[ ]+[ ]+[ ]+3c: R_LARCH_SOP_POP_32_S_5_20[ ]+\*ABS\*
+[ ]+40:[ ]+03800005 [ ]+ori[ ]+[ ]+\$a1, \$zero, 0x0
+[ ]+[ ]+[ ]+40: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x4
+[ ]+[ ]+[ ]+40: R_LARCH_SOP_PUSH_GPREL[ ]+L1
+[ ]+[ ]+[ ]+40: R_LARCH_SOP_ADD[ ]+\*ABS\*
+[ ]+[ ]+[ ]+40: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\-0x7ffffffc
+[ ]+[ ]+[ ]+40: R_LARCH_SOP_PUSH_GPREL[ ]+L1
+[ ]+[ ]+[ ]+40: R_LARCH_SOP_ADD[ ]+\*ABS\*
+[ ]+[ ]+[ ]+40: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x20
+[ ]+[ ]+[ ]+40: R_LARCH_SOP_SR[ ]+\*ABS\*
+[ ]+[ ]+[ ]+40: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x20
+[ ]+[ ]+[ ]+40: R_LARCH_SOP_SL[ ]+\*ABS\*
+[ ]+[ ]+[ ]+40: R_LARCH_SOP_SUB[ ]+\*ABS\*
+[ ]+[ ]+[ ]+40: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0xfff
+[ ]+[ ]+[ ]+40: R_LARCH_SOP_AND[ ]+\*ABS\*
+[ ]+[ ]+[ ]+40: R_LARCH_SOP_POP_32_U_10_12[ ]+\*ABS\*
+[ ]+44:[ ]+16000005 [ ]+lu32i.d[ ]+[ ]+\$a1, 0
+[ ]+[ ]+[ ]+44: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\-0x7ffffff8
+[ ]+[ ]+[ ]+44: R_LARCH_SOP_PUSH_GPREL[ ]+L1
+[ ]+[ ]+[ ]+44: R_LARCH_SOP_ADD[ ]+\*ABS\*
+[ ]+[ ]+[ ]+44: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0xc
+[ ]+[ ]+[ ]+44: R_LARCH_SOP_SL[ ]+\*ABS\*
+[ ]+[ ]+[ ]+44: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x2c
+[ ]+[ ]+[ ]+44: R_LARCH_SOP_SR[ ]+\*ABS\*
+[ ]+[ ]+[ ]+44: R_LARCH_SOP_POP_32_S_5_20[ ]+\*ABS\*
+[ ]+48:[ ]+030000a5 [ ]+lu52i.d[ ]+[ ]+\$a1, \$a1, 0
+[ ]+[ ]+[ ]+48: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\-0x7ffffff4
+[ ]+[ ]+[ ]+48: R_LARCH_SOP_PUSH_GPREL[ ]+L1
+[ ]+[ ]+[ ]+48: R_LARCH_SOP_ADD[ ]+\*ABS\*
+[ ]+[ ]+[ ]+48: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x34
+[ ]+[ ]+[ ]+48: R_LARCH_SOP_SR[ ]+\*ABS\*
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+[ ]+[ ]+[ ]+b8: R_LARCH_SOP_SUB[ ]+\*ABS\*
+[ ]+[ ]+[ ]+b8: R_LARCH_SOP_POP_32_S_10_12[ ]+\*ABS\*
+[ ]+bc:[ ]+1c000004 [ ]+pcaddu12i[ ]+[ ]+\$a0, 0
+[ ]+[ ]+[ ]+bc: R_LARCH_SOP_PUSH_PCREL[ ]+L1
+[ ]+[ ]+[ ]+bc: R_LARCH_SOP_PUSH_PCREL[ ]+L1\-0x80000000
+[ ]+[ ]+[ ]+bc: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x20
+[ ]+[ ]+[ ]+bc: R_LARCH_SOP_SR[ ]+\*ABS\*
+[ ]+[ ]+[ ]+bc: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x20
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+[ ]+[ ]+[ ]+11c: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\-0x7ffffffc
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+[ ]+[ ]+[ ]+11c: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x20
+[ ]+[ ]+[ ]+11c: R_LARCH_SOP_SR[ ]+\*ABS\*
+[ ]+[ ]+[ ]+11c: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x20
+[ ]+[ ]+[ ]+11c: R_LARCH_SOP_SL[ ]+\*ABS\*
+[ ]+[ ]+[ ]+11c: R_LARCH_SOP_SUB[ ]+\*ABS\*
+[ ]+[ ]+[ ]+11c: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0xfff
+[ ]+[ ]+[ ]+11c: R_LARCH_SOP_AND[ ]+\*ABS\*
+[ ]+[ ]+[ ]+11c: R_LARCH_SOP_POP_32_U_10_12[ ]+\*ABS\*
+[ ]+120:[ ]+16000005 [ ]+lu32i.d[ ]+[ ]+\$a1, 0
+[ ]+[ ]+[ ]+120: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\-0x7ffffff8
+[ ]+[ ]+[ ]+120: R_LARCH_SOP_PUSH_TLS_GD[ ]+L1
+[ ]+[ ]+[ ]+120: R_LARCH_SOP_ADD[ ]+\*ABS\*
+[ ]+[ ]+[ ]+120: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0xc
+[ ]+[ ]+[ ]+120: R_LARCH_SOP_SL[ ]+\*ABS\*
+[ ]+[ ]+[ ]+120: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x2c
+[ ]+[ ]+[ ]+120: R_LARCH_SOP_SR[ ]+\*ABS\*
+[ ]+[ ]+[ ]+120: R_LARCH_SOP_POP_32_S_5_20[ ]+\*ABS\*
+[ ]+124:[ ]+030000a5 [ ]+lu52i.d[ ]+[ ]+\$a1, \$a1, 0
+[ ]+[ ]+[ ]+124: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\-0x7ffffff4
+[ ]+[ ]+[ ]+124: R_LARCH_SOP_PUSH_TLS_GD[ ]+L1
+[ ]+[ ]+[ ]+124: R_LARCH_SOP_ADD[ ]+\*ABS\*
+[ ]+[ ]+[ ]+124: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x34
+[ ]+[ ]+[ ]+124: R_LARCH_SOP_SR[ ]+\*ABS\*
+[ ]+[ ]+[ ]+124: R_LARCH_SOP_POP_32_S_10_12[ ]+\*ABS\*
+[ ]+128:[ ]+00109484 [ ]+add.d[ ]+[ ]+\$a0, \$a0, \$a1
+[ ]+12c:[ ]+1c000004 [ ]+pcaddu12i[ ]+[ ]+\$a0, 0
+[ ]+[ ]+[ ]+12c: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x800
+[ ]+[ ]+[ ]+12c: R_LARCH_SOP_PUSH_TLS_GD[ ]+L1
+[ ]+[ ]+[ ]+12c: R_LARCH_SOP_ADD[ ]+\*ABS\*
+[ ]+[ ]+[ ]+12c: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x20
+[ ]+[ ]+[ ]+12c: R_LARCH_SOP_SL[ ]+\*ABS\*
+[ ]+[ ]+[ ]+12c: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x2c
+[ ]+[ ]+[ ]+12c: R_LARCH_SOP_SR[ ]+\*ABS\*
+[ ]+[ ]+[ ]+12c: R_LARCH_SOP_POP_32_S_5_20[ ]+\*ABS\*
+[ ]+130:[ ]+02800084 [ ]+addi.w[ ]+[ ]+\$a0, \$a0, 0
+[ ]+[ ]+[ ]+130: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x4
+[ ]+[ ]+[ ]+130: R_LARCH_SOP_PUSH_TLS_GD[ ]+L1
+[ ]+[ ]+[ ]+130: R_LARCH_SOP_ADD[ ]+\*ABS\*
+[ ]+[ ]+[ ]+130: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x804
+[ ]+[ ]+[ ]+130: R_LARCH_SOP_PUSH_TLS_GD[ ]+L1
+[ ]+[ ]+[ ]+130: R_LARCH_SOP_ADD[ ]+\*ABS\*
+[ ]+[ ]+[ ]+130: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0xc
+[ ]+[ ]+[ ]+130: R_LARCH_SOP_SR[ ]+\*ABS\*
+[ ]+[ ]+[ ]+130: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0xc
+[ ]+[ ]+[ ]+130: R_LARCH_SOP_SL[ ]+\*ABS\*
+[ ]+[ ]+[ ]+130: R_LARCH_SOP_SUB[ ]+\*ABS\*
+[ ]+[ ]+[ ]+130: R_LARCH_SOP_POP_32_S_10_12[ ]+\*ABS\*
+[ ]+134:[ ]+1c000004 [ ]+pcaddu12i[ ]+[ ]+\$a0, 0
+[ ]+[ ]+[ ]+134: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_
+[ ]+[ ]+[ ]+134: R_LARCH_SOP_PUSH_TLS_GD[ ]+L1
+[ ]+[ ]+[ ]+134: R_LARCH_SOP_ADD[ ]+\*ABS\*
+[ ]+[ ]+[ ]+134: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\-0x80000000
+[ ]+[ ]+[ ]+134: R_LARCH_SOP_PUSH_TLS_GD[ ]+L1
+[ ]+[ ]+[ ]+134: R_LARCH_SOP_ADD[ ]+\*ABS\*
+[ ]+[ ]+[ ]+134: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x20
+[ ]+[ ]+[ ]+134: R_LARCH_SOP_SR[ ]+\*ABS\*
+[ ]+[ ]+[ ]+134: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x20
+[ ]+[ ]+[ ]+134: R_LARCH_SOP_SL[ ]+\*ABS\*
+[ ]+[ ]+[ ]+134: R_LARCH_SOP_SUB[ ]+\*ABS\*
+[ ]+[ ]+[ ]+134: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x20
+[ ]+[ ]+[ ]+134: R_LARCH_SOP_SL[ ]+\*ABS\*
+[ ]+[ ]+[ ]+134: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x2c
+[ ]+[ ]+[ ]+134: R_LARCH_SOP_SR[ ]+\*ABS\*
+[ ]+[ ]+[ ]+134: R_LARCH_SOP_POP_32_S_5_20[ ]+\*ABS\*
+[ ]+138:[ ]+03800005 [ ]+ori[ ]+[ ]+\$a1, \$zero, 0x0
+[ ]+[ ]+[ ]+138: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\+0x4
+[ ]+[ ]+[ ]+138: R_LARCH_SOP_PUSH_TLS_GD[ ]+L1
+[ ]+[ ]+[ ]+138: R_LARCH_SOP_ADD[ ]+\*ABS\*
+[ ]+[ ]+[ ]+138: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\-0x7ffffffc
+[ ]+[ ]+[ ]+138: R_LARCH_SOP_PUSH_TLS_GD[ ]+L1
+[ ]+[ ]+[ ]+138: R_LARCH_SOP_ADD[ ]+\*ABS\*
+[ ]+[ ]+[ ]+138: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x20
+[ ]+[ ]+[ ]+138: R_LARCH_SOP_SR[ ]+\*ABS\*
+[ ]+[ ]+[ ]+138: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x20
+[ ]+[ ]+[ ]+138: R_LARCH_SOP_SL[ ]+\*ABS\*
+[ ]+[ ]+[ ]+138: R_LARCH_SOP_SUB[ ]+\*ABS\*
+[ ]+[ ]+[ ]+138: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0xfff
+[ ]+[ ]+[ ]+138: R_LARCH_SOP_AND[ ]+\*ABS\*
+[ ]+[ ]+[ ]+138: R_LARCH_SOP_POP_32_U_10_12[ ]+\*ABS\*
+[ ]+13c:[ ]+16000005 [ ]+lu32i.d[ ]+[ ]+\$a1, 0
+[ ]+[ ]+[ ]+13c: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\-0x7ffffff8
+[ ]+[ ]+[ ]+13c: R_LARCH_SOP_PUSH_TLS_GD[ ]+L1
+[ ]+[ ]+[ ]+13c: R_LARCH_SOP_ADD[ ]+\*ABS\*
+[ ]+[ ]+[ ]+13c: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0xc
+[ ]+[ ]+[ ]+13c: R_LARCH_SOP_SL[ ]+\*ABS\*
+[ ]+[ ]+[ ]+13c: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x2c
+[ ]+[ ]+[ ]+13c: R_LARCH_SOP_SR[ ]+\*ABS\*
+[ ]+[ ]+[ ]+13c: R_LARCH_SOP_POP_32_S_5_20[ ]+\*ABS\*
+[ ]+140:[ ]+030000a5 [ ]+lu52i.d[ ]+[ ]+\$a1, \$a1, 0
+[ ]+[ ]+[ ]+140: R_LARCH_SOP_PUSH_PCREL[ ]+_GLOBAL_OFFSET_TABLE_\-0x7ffffff4
+[ ]+[ ]+[ ]+140: R_LARCH_SOP_PUSH_TLS_GD[ ]+L1
+[ ]+[ ]+[ ]+140: R_LARCH_SOP_ADD[ ]+\*ABS\*
+[ ]+[ ]+[ ]+140: R_LARCH_SOP_PUSH_ABSOLUTE[ ]+\*ABS\*\+0x34
+[ ]+[ ]+[ ]+140: R_LARCH_SOP_SR[ ]+\*ABS\*
+[ ]+[ ]+[ ]+140: R_LARCH_SOP_POP_32_S_10_12[ ]+\*ABS\*
+[ ]+144:[ ]+00109484 [ ]+add.d[ ]+[ ]+\$a0, \$a0, \$a1
diff --git a/ld/testsuite/ld-loongarch-elf/macro_op_32.s b/ld/testsuite/ld-loongarch-elf/macro_op_32.s
new file mode 100644
index 00000000000..2e26b6b3f9b
--- /dev/null
+++ b/ld/testsuite/ld-loongarch-elf/macro_op_32.s
@@ -0,0 +1,29 @@
+.L1:
+ li.w $r4,0
+ li.w $r4,0xffffffff
+ li.w $r4,0
+ li.w $r4,0xffffffff
+ la $r4,L1
+ la.global $r4,L1
+ la.global $r4,$r5,L1
+ la.global $r4,L1
+ la.global $r4,$r5,L1
+ la.global $r4,L1
+ la.global $r4,$r5,L1
+ la.local $r4,L1
+ la.local $r4,$r5,L1
+ la.local $r4,L1
+ la.local $r4,$r5,L1
+ la.abs $r4,L1
+ la.pcrel $r4,L1
+ la.pcrel $r4,L1
+ la.pcrel $r4,$r5,L1
+ la.got $r4,L1
+ la.got $r4,$r5,L1
+ la.tls.le $r4,L1
+ la.tls.ie $r4,L1
+ la.tls.ie $r4,$r5,L1
+ la.tls.ld $r4,L1
+ la.tls.ld $r4,$r5,L1
+ la.tls.gd $r4,L1
+ la.tls.gd $r4,$r5,L1
--
2.31.1
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