[PATCH 0/2] Add RISC-V vendor extensions: XVentanaCondOps and XTheadCmo

[PATCH 0/2] Add RISC-V vendor extensions: XVentanaCondOps and XTheadCmo

[Christoph Muellner]

This series introduces two vendor extensions:
* XVentanaCondOps
* XTheadCmo

Patch #1 is a resend of the patch that Philipp sent on Jan 9 ([1]).
It was reviewed by Kito earlier today (no other responses so far).
I've just rebased the patch and cleaned up all conflicts.

Patch #2 is my patch for T-Heads CMO instruction.
This patch depends on some changes from patch #1
(common code for vendor extension support).
I've announced to work on this end of March as part of the conversation
about Heiko Stübner's Linux patch ([2]).
There is a similar patch on the Binutils list from today, that
seems to be requested by Palmer Dabbelt (to whom I responded about my
intend to work on this patch this week).
I leave this to the maintainers to resolve.

[1] https://sourceware.org/pipermail/binutils/2022-January/119236.html
[2] http://lists.infradead.org/pipermail/linux-riscv/2022-March/013087.html

Christoph Muellner (1):
  RISC-V: Add T-Head CMO vendor extension

Philipp Tomsich (1):
  RISC-V: Support XVentanaCondOps extension

 bfd/elfxx-riscv.c                           | 17 +++++-
 gas/doc/c-riscv.texi                        | 25 +++++++++
 gas/testsuite/gas/riscv/x-thead-cmo-fail.d  |  3 ++
 gas/testsuite/gas/riscv/x-thead-cmo-fail.l  | 22 ++++++++
 gas/testsuite/gas/riscv/x-thead-cmo-fail.s  | 22 ++++++++
 gas/testsuite/gas/riscv/x-thead-cmo.d       | 30 +++++++++++
 gas/testsuite/gas/riscv/x-thead-cmo.s       | 22 ++++++++
 gas/testsuite/gas/riscv/x-ventana-condops.d | 12 +++++
 gas/testsuite/gas/riscv/x-ventana-condops.s |  4 ++
 include/opcode/riscv-opc.h                  | 60 ++++++++++++++++++++-
 include/opcode/riscv.h                      |  2 +
 opcodes/riscv-opc.c                         | 29 ++++++++++
 12 files changed, 245 insertions(+), 3 deletions(-)
 create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo-fail.d
 create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo-fail.l
 create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo-fail.s
 create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo.d
 create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo.s
 create mode 100644 gas/testsuite/gas/riscv/x-ventana-condops.d
 create mode 100644 gas/testsuite/gas/riscv/x-ventana-condops.s

-- 
2.35.1

[PATCH 1/2] RISC-V: Support XVentanaCondOps extension

[Christoph Muellner]

From: Philipp Tomsich <philipp.tomsich@vrull.eu>

Ventana Micro has published the specification for their
XVentanaCondOps ("conditional ops") extension at
  https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf
which contains two new instructions
  - vt.maskc
  - vt.maskcn
that can be used in constructing branchless sequences for
various conditional-arithmetic, conditional-logical, and
conditional-select operations.

To support such vendor-defined instructions in the mainline binutils,
this change also adds a riscv_supported_vendor_x_ext secondary
dispatch table (but also keeps the behaviour of allowing any unknow
X-extension to be specified in addition to the known ones from this
table).

As discussed, this change already includes the planned/agreed future
requirements for X-extensions (which are likely to be captured in the
riscv-toolchain-conventions repository):
  - a public specification document is available (see above) and is
    referenced from the gas-documentation
  - the naming follows chapter 27 of the RISC-V ISA specification
  - instructions are prefixed by a vendor-prefix (vt for Ventana)
    to ensure that they neither conflict with future standard
    extensions nor clash with other vendors

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_get_default_ext_version): Add riscv_supported_vendor_x_ext.
	(riscv_multi_subset_supports): Recognize INSN_CLASS_XVENTANACONDOPS.

gas/ChangeLog:

	* doc/c-riscv.texi: Add section to list custom extensions and
          their documentation URLs.
	* testsuite/gas/riscv/x-ventana-condops.d: New test.
	* testsuite/gas/riscv/x-ventana-condops.s: New test.

include/ChangeLog:

	* opcode/riscv-opc.h Add vt.maskc and vt.maskcn.
	* opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_XVENTANACONDOPS.

opcodes/ChangeLog:

	* riscv-opc.c: Add vt.maskc and vt.maskcn.

v2:
- Rebase (no changes requested for v1; see
  https://sourceware.org/pipermail/binutils/2022-January/119236.html)

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
---
 bfd/elfxx-riscv.c                           | 13 +++++++++++--
 gas/doc/c-riscv.texi                        | 20 ++++++++++++++++++++
 gas/testsuite/gas/riscv/x-ventana-condops.d | 12 ++++++++++++
 gas/testsuite/gas/riscv/x-ventana-condops.s |  4 ++++
 include/opcode/riscv-opc.h                  | 17 ++++++++++++++++-
 include/opcode/riscv.h                      |  1 +
 opcodes/riscv-opc.c                         |  4 ++++
 7 files changed, 68 insertions(+), 3 deletions(-)
 create mode 100644 gas/testsuite/gas/riscv/x-ventana-condops.d
 create mode 100644 gas/testsuite/gas/riscv/x-ventana-condops.s

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index cb2cc146c04..723b30ddbfc 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1237,6 +1237,13 @@ static struct riscv_supported_ext riscv_supported_std_zxm_ext[] =
   {NULL, 0, 0, 0, 0}
 };
 
+static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
+{
+  /* XVentanaCondOps: https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf */
+  {"xventanacondops",	ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
+  {NULL, 0, 0, 0, 0}
+};
+
 const struct riscv_supported_ext *riscv_all_supported_ext[] =
 {
   riscv_supported_std_ext,
@@ -1244,6 +1251,7 @@ const struct riscv_supported_ext *riscv_all_supported_ext[] =
   riscv_supported_std_s_ext,
   riscv_supported_std_h_ext,
   riscv_supported_std_zxm_ext,
+  riscv_supported_vendor_x_ext,
   NULL
 };
 
@@ -1504,8 +1512,7 @@ riscv_get_default_ext_version (enum riscv_spec_class *default_isa_spec,
     case RV_ISA_CLASS_Z: table = riscv_supported_std_z_ext; break;
     case RV_ISA_CLASS_S: table = riscv_supported_std_s_ext; break;
     case RV_ISA_CLASS_H: table = riscv_supported_std_h_ext; break;
-    case RV_ISA_CLASS_X:
-      break;
+    case RV_ISA_CLASS_X: table = riscv_supported_vendor_x_ext; break;
     default:
       table = riscv_supported_std_ext;
     }
@@ -2402,6 +2409,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
 	      || riscv_subset_supports (rps, "zve32f"));
     case INSN_CLASS_SVINVAL:
       return riscv_subset_supports (rps, "svinval");
+    case INSN_CLASS_XVENTANACONDOPS:
+      return riscv_subset_supports (rps, "xventanacondops");
     default:
       rps->error_handler
         (_("internal: unreachable INSN_CLASS_*"));
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 21d867e9cf0..c75a5ad5a08 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -20,6 +20,7 @@
 * RISC-V-Modifiers::      RISC-V Assembler Modifiers
 * RISC-V-Formats::        RISC-V Instruction Formats
 * RISC-V-ATTRIBUTE::      RISC-V Object Attribute
+* RISC-V-CustomExts::     RISC-V Custom (Vendor-Defined) Extensions
 @end menu
 
 @node RISC-V-Options
@@ -692,3 +693,22 @@ the privileged specification.  It will report errors if object files of
 different privileged specification versions are merged.
 
 @end table
+
+@node RISC-V-CustomExts
+@section RISC-V Custom (Vendor-Defined) Extensions
+@cindex custom (vendor-defined) extensions, RISC-V
+@cindex RISC-V custom (vendor-defined) extensions
+
+The following table lists the custom (vendor-defined) RISC-V
+extensions supported and provides the location of their
+publicly-released documentation:
+
+@table @r
+@item XVentanaCondOps
+XVentanaCondOps extension provides instructions for branchless
+sequences that perform conditional arithmetic, conditional
+bitwise-logic, and conditional select operations.
+
+It is documented at @url{https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf}.
+
+@end table
diff --git a/gas/testsuite/gas/riscv/x-ventana-condops.d b/gas/testsuite/gas/riscv/x-ventana-condops.d
new file mode 100644
index 00000000000..cab0cc8dc12
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-ventana-condops.d
@@ -0,0 +1,12 @@
+#as: -march=rv64i_xventanacondops1p0
+#source: x-ventana-condops.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+0:[ 	]+00c5e57b[ 	]+vt.maskc[ 	]+a0,a1,a2
+[ 	]+4:[ 	]+00e6f57b[ 	]+vt.maskcn[ 	]+a0,a3,a4
diff --git a/gas/testsuite/gas/riscv/x-ventana-condops.s b/gas/testsuite/gas/riscv/x-ventana-condops.s
new file mode 100644
index 00000000000..562cf7384f7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-ventana-condops.s
@@ -0,0 +1,4 @@
+target:
+	vt.maskc	a0, a1, a2
+	vt.maskcn	a0, a3, a4
+
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 3eea33a5dae..419ed538da9 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2045,7 +2045,20 @@
 #define MASK_CBO_INVAL 0xfff07fff
 #define MATCH_CBO_ZERO 0x40200f
 #define MASK_CBO_ZERO 0xfff07fff
-/* Unprivileged Counter/Timers CSR addresses.  */
+/* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
+#define MATCH_VT_MASKC 0x607b
+#define MASK_VT_MASKC 0xfe00707f
+#define MATCH_VT_MASKCN 0x707b
+#define MASK_VT_MASKCN 0xfe00707f
+/* Privileged CSR addresses.  */
+#define CSR_USTATUS 0x0
+#define CSR_UIE 0x4
+#define CSR_UTVEC 0x5
+#define CSR_USCRATCH 0x40
+#define CSR_UEPC 0x41
+#define CSR_UCAUSE 0x42
+#define CSR_UTVAL 0x43
+#define CSR_UIP 0x44
 #define CSR_CYCLE 0xc00
 #define CSR_TIME 0xc01
 #define CSR_INSTRET 0xc02
@@ -2720,6 +2733,8 @@ DECLARE_INSN(hsv_b, MATCH_HSV_B, MASK_HSV_B)
 DECLARE_INSN(hsv_h, MATCH_HSV_H, MASK_HSV_H)
 DECLARE_INSN(hsv_w, MATCH_HSV_W, MASK_HSV_W)
 DECLARE_INSN(hsv_d, MATCH_HSV_D, MASK_HSV_D)
+DECLARE_INSN(vt_maskc, MATCH_VT_MASKC, MASK_VT_MASKC)
+DECLARE_INSN(vt_maskcn, MATCH_VT_MASKCN, MASK_VT_MASKCN)
 #endif /* DECLARE_INSN */
 #ifdef DECLARE_CSR
 /* Unprivileged Counter/Timers CSRs.  */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index b769769b4ec..3cbb68b5655 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -391,6 +391,7 @@ enum riscv_insn_class
   INSN_CLASS_ZICBOM,
   INSN_CLASS_ZICBOP,
   INSN_CLASS_ZICBOZ,
+  INSN_CLASS_XVENTANACONDOPS,
 };
 
 /* This structure holds information for a particular instruction.  */
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 00108ff24ae..052209f6fe2 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1762,6 +1762,10 @@ const struct riscv_opcode riscv_opcodes[] =
 {"hsv.w",       0, INSN_CLASS_I, "t,0(s)", MATCH_HSV_W, MASK_HSV_W, match_opcode, INSN_DREF|INSN_4_BYTE },
 {"hsv.d",      64, INSN_CLASS_I, "t,0(s)", MATCH_HSV_D, MASK_HSV_D, match_opcode, INSN_DREF|INSN_8_BYTE },
 
+/* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
+{"vt.maskc",    0, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 },
+{"vt.maskcn",   0, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKCN, MASK_VT_MASKCN, match_opcode, 0 },
+
 /* Terminate the list.  */
 {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
 };
-- 
2.35.1

[PATCH 2/2] RISC-V: Add T-Head CMO vendor extension

[Christoph Muellner]

T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.

This patch adds the XTheadCmo extension, a collection of T-Head specific
cache management operations.
The 'th' prefix and the "XTheadCmo" extension are documented in a PR
for the RISC-V toolchain conventions ([1]).

In total XTheadCmo introduces the following 21 instructions:

* DCACHE.{C,CI,I}ALL
* DCACHE.{C,CI,I}{PA,VA,SW} rs1
* DCACHE.C{PAL1,VAL1} rs1
* ICACHE.I{ALL,ALLS}
* ICACHE.I{PA,VA} rs1
* L2CACHE.{C,CI,I}ALL

Contrary to Zicbom, the XTheadCmo instructions don't have a constant
displacement, therefore we have a different syntax for the arguments.
To clarify this is intended behaviour, there is a set of negative test
for Zicbom-style arguments in x-thead-cmo-fail.s.

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Signed-off-by: Christoph Muellner <cmuellner@gcc.gnu.org>
---
 bfd/elfxx-riscv.c                          |  4 ++
 gas/doc/c-riscv.texi                       |  5 +++
 gas/testsuite/gas/riscv/x-thead-cmo-fail.d |  3 ++
 gas/testsuite/gas/riscv/x-thead-cmo-fail.l | 22 +++++++++++
 gas/testsuite/gas/riscv/x-thead-cmo-fail.s | 22 +++++++++++
 gas/testsuite/gas/riscv/x-thead-cmo.d      | 30 +++++++++++++++
 gas/testsuite/gas/riscv/x-thead-cmo.s      | 22 +++++++++++
 include/opcode/riscv-opc.h                 | 43 ++++++++++++++++++++++
 include/opcode/riscv.h                     |  1 +
 opcodes/riscv-opc.c                        | 25 +++++++++++++
 10 files changed, 177 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo-fail.d
 create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo-fail.l
 create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo-fail.s
 create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo.d
 create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo.s

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 723b30ddbfc..2719c245c4f 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1241,6 +1241,8 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
 {
   /* XVentanaCondOps: https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf */
   {"xventanacondops",	ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
+  /* XTheadCmo: https://github.com/T-head-Semi/openc910/blob/main/doc/%E7%8E%84%E9%93%81C910%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C.pdf */
+  {"xtheadcmo",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {NULL, 0, 0, 0, 0}
 };
 
@@ -2409,6 +2411,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
 	      || riscv_subset_supports (rps, "zve32f"));
     case INSN_CLASS_SVINVAL:
       return riscv_subset_supports (rps, "svinval");
+    case INSN_CLASS_XTHEADCMO:
+      return riscv_subset_supports (rps, "xtheadcmo");
     case INSN_CLASS_XVENTANACONDOPS:
       return riscv_subset_supports (rps, "xventanacondops");
     default:
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index c75a5ad5a08..17592a21922 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -711,4 +711,9 @@ bitwise-logic, and conditional select operations.
 
 It is documented at @url{https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf}.
 
+@item XTheadCmo
+The XTheadCmo extension provides instructions for cache management.
+
+It is documented at @url{https://github.com/T-head-Semi/openc910/blob/main/doc/%E7%8E%84%E9%93%81C910%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C.pdf}.
+
 @end table
diff --git a/gas/testsuite/gas/riscv/x-thead-cmo-fail.d b/gas/testsuite/gas/riscv/x-thead-cmo-fail.d
new file mode 100644
index 00000000000..de794ea5837
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-cmo-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv64i_xtheadcmo
+#source: x-thead-cmo-fail.s
+#error_output: x-thead-cmo-fail.l
diff --git a/gas/testsuite/gas/riscv/x-thead-cmo-fail.l b/gas/testsuite/gas/riscv/x-thead-cmo-fail.l
new file mode 100644
index 00000000000..4381fe19a99
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-cmo-fail.l
@@ -0,0 +1,22 @@
+.*: Assembler messages:
+.*: Error: illegal operands `th.dcache.call x1'
+.*: Error: illegal operands `th.dcache.ciall x1'
+.*: Error: illegal operands `th.dcache.iall x1'
+.*: Error: illegal operands `th.dcache.cpa 0\(x1\)'
+.*: Error: illegal operands `th.dcache.cipa 0\(x1\)'
+.*: Error: illegal operands `th.dcache.ipa 0\(x1\)'
+.*: Error: illegal operands `th.dcache.cva 0\(x1\)'
+.*: Error: illegal operands `th.dcache.civa 0\(x1\)'
+.*: Error: illegal operands `th.dcache.iva 0\(x1\)'
+.*: Error: illegal operands `th.dcache.csw 0\(x1\)'
+.*: Error: illegal operands `th.dcache.cisw 0\(x1\)'
+.*: Error: illegal operands `th.dcache.isw 0\(x1\)'
+.*: Error: illegal operands `th.dcache.cpal1 0\(x1\)'
+.*: Error: illegal operands `th.dcache.cval1 0\(x1\)'
+.*: Error: illegal operands `th.icache.iall x1'
+.*: Error: illegal operands `th.icache.ialls x1'
+.*: Error: illegal operands `th.icache.ipa 0\(x1\)'
+.*: Error: illegal operands `th.icache.iva 0\(x1\)'
+.*: Error: illegal operands `th.l2cache.call x1'
+.*: Error: illegal operands `th.l2cache.ciall x1'
+.*: Error: illegal operands `th.l2cache.iall x1'
diff --git a/gas/testsuite/gas/riscv/x-thead-cmo-fail.s b/gas/testsuite/gas/riscv/x-thead-cmo-fail.s
new file mode 100644
index 00000000000..591d982eae5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-cmo-fail.s
@@ -0,0 +1,22 @@
+target:
+	th.dcache.call	x1
+	th.dcache.ciall	x1
+	th.dcache.iall	x1
+	th.dcache.cpa	0(x1)
+	th.dcache.cipa	0(x1)
+	th.dcache.ipa	0(x1)
+	th.dcache.cva	0(x1)
+	th.dcache.civa	0(x1)
+	th.dcache.iva	0(x1)
+	th.dcache.csw	0(x1)
+	th.dcache.cisw	0(x1)
+	th.dcache.isw	0(x1)
+	th.dcache.cpal1	0(x1)
+	th.dcache.cval1	0(x1)
+	th.icache.iall	x1
+	th.icache.ialls	x1
+	th.icache.ipa	0(x1)
+	th.icache.iva	0(x1)
+	th.l2cache.call	x1
+	th.l2cache.ciall	x1
+	th.l2cache.iall	x1
diff --git a/gas/testsuite/gas/riscv/x-thead-cmo.d b/gas/testsuite/gas/riscv/x-thead-cmo.d
new file mode 100644
index 00000000000..f482ddcbc28
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-cmo.d
@@ -0,0 +1,30 @@
+#as: -march=rv64i_xtheadcmo
+#source: x-thead-cmo.s
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+0010000b[ 	]+th.dcache.call
+[ 	]+[0-9a-f]+:[ 	]+0030000b[ 	]+th.dcache.ciall
+[ 	]+[0-9a-f]+:[ 	]+0020000b[ 	]+th.dcache.iall
+[ 	]+[0-9a-f]+:[ 	]+0295000b[ 	]+th.dcache.cpa[ 	]+a0
+[ 	]+[0-9a-f]+:[ 	]+02b5800b[ 	]+th.dcache.cipa[ 	]+a1
+[ 	]+[0-9a-f]+:[ 	]+02a6000b[ 	]+th.dcache.ipa[ 	]+a2
+[ 	]+[0-9a-f]+:[ 	]+0256800b[ 	]+th.dcache.cva[ 	]+a3
+[ 	]+[0-9a-f]+:[ 	]+0277000b[ 	]+th.dcache.civa[ 	]+a4
+[ 	]+[0-9a-f]+:[ 	]+0267800b[ 	]+th.dcache.iva[ 	]+a5
+[ 	]+[0-9a-f]+:[ 	]+0218000b[ 	]+th.dcache.csw[ 	]+a6
+[ 	]+[0-9a-f]+:[ 	]+0238800b[ 	]+th.dcache.cisw[ 	]+a7
+[ 	]+[0-9a-f]+:[ 	]+0222800b[ 	]+th.dcache.isw[ 	]+t0
+[ 	]+[0-9a-f]+:[ 	]+0283000b[ 	]+th.dcache.cpal1[ 	]+t1
+[ 	]+[0-9a-f]+:[ 	]+0243800b[ 	]+th.dcache.cval1[ 	]+t2
+[ 	]+[0-9a-f]+:[ 	]+0100000b[ 	]+th.icache.iall
+[ 	]+[0-9a-f]+:[ 	]+0110000b[ 	]+th.icache.ialls
+[ 	]+[0-9a-f]+:[ 	]+038e000b[ 	]+th.icache.ipa[ 	]+t3
+[ 	]+[0-9a-f]+:[ 	]+030e800b[ 	]+th.icache.iva[ 	]+t4
+[ 	]+[0-9a-f]+:[ 	]+0150000b[ 	]+th.l2cache.call
+[ 	]+[0-9a-f]+:[ 	]+0170000b[ 	]+th.l2cache.ciall
+[ 	]+[0-9a-f]+:[ 	]+0160000b[ 	]+th.l2cache.iall
diff --git a/gas/testsuite/gas/riscv/x-thead-cmo.s b/gas/testsuite/gas/riscv/x-thead-cmo.s
new file mode 100644
index 00000000000..2a4b54a941b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-cmo.s
@@ -0,0 +1,22 @@
+target:
+	th.dcache.call
+	th.dcache.ciall
+	th.dcache.iall
+	th.dcache.cpa	a0
+	th.dcache.cipa	a1
+	th.dcache.ipa	a2
+	th.dcache.cva	a3
+	th.dcache.civa	a4
+	th.dcache.iva	a5
+	th.dcache.csw	a6
+	th.dcache.cisw	a7
+	th.dcache.isw	t0
+	th.dcache.cpal1	t1
+	th.dcache.cval1	t2
+	th.icache.iall
+	th.icache.ialls
+	th.icache.ipa	t3
+	th.icache.iva	t4
+	th.l2cache.call
+	th.l2cache.ciall
+	th.l2cache.iall
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 419ed538da9..513ee3bbd41 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2045,6 +2045,49 @@
 #define MASK_CBO_INVAL 0xfff07fff
 #define MATCH_CBO_ZERO 0x40200f
 #define MASK_CBO_ZERO 0xfff07fff
+/* Vendor-specific (T-Head) XTheadCmo instructions.  */
+#define MATCH_TH_DCACHE_CALL 0x0010000B
+#define MASK_TH_DCACHE_CALL 0xffffffff
+#define MATCH_TH_DCACHE_CIALL 0x0030000B
+#define MASK_TH_DCACHE_CIALL 0xffffffff
+#define MATCH_TH_DCACHE_IALL 0x0020000b
+#define MASK_TH_DCACHE_IALL 0xffffffff
+#define MATCH_TH_DCACHE_CPA 0x0290000b
+#define MASK_TH_DCACHE_CPA 0xfff07fff
+#define MATCH_TH_DCACHE_CIPA 0x02b0000b
+#define MASK_TH_DCACHE_CIPA 0xfff07fff
+#define MATCH_TH_DCACHE_IPA 0x02a0000b
+#define MASK_TH_DCACHE_IPA 0xfff07fff
+#define MATCH_TH_DCACHE_CVA 0x0250000b
+#define MASK_TH_DCACHE_CVA 0xfff07fff
+#define MATCH_TH_DCACHE_CIVA 0x0270000b
+#define MASK_TH_DCACHE_CIVA 0xfff07fff
+#define MATCH_TH_DCACHE_IVA 0x0260000b
+#define MASK_TH_DCACHE_IVA 0xfff07fff
+#define MATCH_TH_DCACHE_CSW 0x0210000b
+#define MASK_TH_DCACHE_CSW 0xfff07fff
+#define MATCH_TH_DCACHE_CISW 0x0230000b
+#define MASK_TH_DCACHE_CISW 0xfff07fff
+#define MATCH_TH_DCACHE_ISW 0x0220000b
+#define MASK_TH_DCACHE_ISW 0xfff07fff
+#define MATCH_TH_DCACHE_CPAL1 0x0280000b
+#define MASK_TH_DCACHE_CPAL1 0xfff07fff
+#define MATCH_TH_DCACHE_CVAL1 0x0240000b
+#define MASK_TH_DCACHE_CVAL1 0xfff07fff
+#define MATCH_TH_ICACHE_IALL 0x0100000b
+#define MASK_TH_ICACHE_IALL 0xffffffff
+#define MATCH_TH_ICACHE_IALLS 0x0110000b
+#define MASK_TH_ICACHE_IALLS 0xffffffff
+#define MATCH_TH_ICACHE_IPA 0x0380000b
+#define MASK_TH_ICACHE_IPA 0xfff07fff
+#define MATCH_TH_ICACHE_IVA 0x0300000b
+#define MASK_TH_ICACHE_IVA 0xfff07fff
+#define MATCH_TH_L2CACHE_CALL 0x0150000b
+#define MASK_TH_L2CACHE_CALL 0xffffffff
+#define MATCH_TH_L2CACHE_CIALL 0x0170000b
+#define MASK_TH_L2CACHE_CIALL 0xffffffff
+#define MATCH_TH_L2CACHE_IALL 0x0160000b
+#define MASK_TH_L2CACHE_IALL 0xffffffff
 /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
 #define MATCH_VT_MASKC 0x607b
 #define MASK_VT_MASKC 0xfe00707f
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 3cbb68b5655..7324146afb1 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -391,6 +391,7 @@ enum riscv_insn_class
   INSN_CLASS_ZICBOM,
   INSN_CLASS_ZICBOP,
   INSN_CLASS_ZICBOZ,
+  INSN_CLASS_XTHEADCMO,
   INSN_CLASS_XVENTANACONDOPS,
 };
 
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 052209f6fe2..d75d411269b 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1762,6 +1762,31 @@ const struct riscv_opcode riscv_opcodes[] =
 {"hsv.w",       0, INSN_CLASS_I, "t,0(s)", MATCH_HSV_W, MASK_HSV_W, match_opcode, INSN_DREF|INSN_4_BYTE },
 {"hsv.d",      64, INSN_CLASS_I, "t,0(s)", MATCH_HSV_D, MASK_HSV_D, match_opcode, INSN_DREF|INSN_8_BYTE },
 
+/* Vendor-specific (T-Head) XTheadCmo instructions.  */
+{"th.dcache.call",   0, INSN_CLASS_XTHEADCMO,   "",   MATCH_TH_DCACHE_CALL,   MASK_TH_DCACHE_CALL,   match_opcode, 0},
+{"th.dcache.ciall",  0, INSN_CLASS_XTHEADCMO,   "",   MATCH_TH_DCACHE_CIALL,  MASK_TH_DCACHE_CIALL,  match_opcode, 0},
+{"th.dcache.iall",   0, INSN_CLASS_XTHEADCMO,   "",   MATCH_TH_DCACHE_IALL,   MASK_TH_DCACHE_IALL,   match_opcode, 0},
+{"th.dcache.cpa",    0, INSN_CLASS_XTHEADCMO,   "s",  MATCH_TH_DCACHE_CPA,    MASK_TH_DCACHE_CPA,    match_opcode, 0},
+{"th.dcache.cipa",   0, INSN_CLASS_XTHEADCMO,   "s",  MATCH_TH_DCACHE_CIPA,   MASK_TH_DCACHE_CIPA,   match_opcode, 0},
+{"th.dcache.ipa",    0, INSN_CLASS_XTHEADCMO,   "s",  MATCH_TH_DCACHE_IPA,    MASK_TH_DCACHE_IPA,    match_opcode, 0},
+{"th.dcache.cva",    0, INSN_CLASS_XTHEADCMO,   "s",  MATCH_TH_DCACHE_CVA,    MASK_TH_DCACHE_CVA,    match_opcode, 0},
+{"th.dcache.civa",   0, INSN_CLASS_XTHEADCMO,   "s",  MATCH_TH_DCACHE_CIVA,   MASK_TH_DCACHE_CIVA,   match_opcode, 0},
+{"th.dcache.iva",    0, INSN_CLASS_XTHEADCMO,   "s",  MATCH_TH_DCACHE_IVA,    MASK_TH_DCACHE_IVA,    match_opcode, 0},
+{"th.dcache.csw",    0, INSN_CLASS_XTHEADCMO,   "s",  MATCH_TH_DCACHE_CSW,    MASK_TH_DCACHE_CSW,    match_opcode, 0},
+{"th.dcache.cisw",   0, INSN_CLASS_XTHEADCMO,   "s",  MATCH_TH_DCACHE_CISW,   MASK_TH_DCACHE_CISW,   match_opcode, 0},
+{"th.dcache.isw",    0, INSN_CLASS_XTHEADCMO,   "s",  MATCH_TH_DCACHE_ISW,    MASK_TH_DCACHE_ISW,    match_opcode, 0},
+{"th.dcache.cpal1",  0, INSN_CLASS_XTHEADCMO,   "s",  MATCH_TH_DCACHE_CPAL1,  MASK_TH_DCACHE_CPAL1,  match_opcode, 0},
+{"th.dcache.cval1",  0, INSN_CLASS_XTHEADCMO,   "s",  MATCH_TH_DCACHE_CVAL1,  MASK_TH_DCACHE_CVAL1,  match_opcode, 0},
+
+{"th.icache.iall",   0, INSN_CLASS_XTHEADCMO,   "",   MATCH_TH_ICACHE_IALL,   MASK_TH_ICACHE_IALL,   match_opcode, 0},
+{"th.icache.ialls",  0, INSN_CLASS_XTHEADCMO,   "",   MATCH_TH_ICACHE_IALLS,  MASK_TH_ICACHE_IALLS,  match_opcode, 0},
+{"th.icache.ipa",    0, INSN_CLASS_XTHEADCMO,   "s",  MATCH_TH_ICACHE_IPA,    MASK_TH_ICACHE_IPA,    match_opcode, 0},
+{"th.icache.iva",    0, INSN_CLASS_XTHEADCMO,   "s",  MATCH_TH_ICACHE_IVA,    MASK_TH_ICACHE_IVA,    match_opcode, 0},
+
+{"th.l2cache.call",  0, INSN_CLASS_XTHEADCMO,   "",   MATCH_TH_L2CACHE_CALL,  MASK_TH_L2CACHE_CALL,  match_opcode, 0},
+{"th.l2cache.ciall", 0, INSN_CLASS_XTHEADCMO,   "",   MATCH_TH_L2CACHE_CIALL, MASK_TH_L2CACHE_CIALL, match_opcode, 0},
+{"th.l2cache.iall",  0, INSN_CLASS_XTHEADCMO,   "",   MATCH_TH_L2CACHE_IALL,  MASK_TH_L2CACHE_IALL,  match_opcode, 0},
+
 /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
 {"vt.maskc",    0, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 },
 {"vt.maskcn",   0, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKCN, MASK_VT_MASKCN, match_opcode, 0 },
-- 
2.35.1

Re: [PATCH 1/2] RISC-V: Support XVentanaCondOps extension

[Nelson Chu]

On Wed, Apr 20, 2022 at 10:56 PM Christoph Muellner
<cmuellner@gcc.gnu.org> wrote:
>
> From: Philipp Tomsich <philipp.tomsich@vrull.eu>
>
> Ventana Micro has published the specification for their
> XVentanaCondOps ("conditional ops") extension at
>   https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf
> which contains two new instructions
>   - vt.maskc
>   - vt.maskcn
> that can be used in constructing branchless sequences for
> various conditional-arithmetic, conditional-logical, and
> conditional-select operations.
>
> To support such vendor-defined instructions in the mainline binutils,
> this change also adds a riscv_supported_vendor_x_ext secondary
> dispatch table (but also keeps the behaviour of allowing any unknow
> X-extension to be specified in addition to the known ones from this
> table).
>
> As discussed, this change already includes the planned/agreed future
> requirements for X-extensions (which are likely to be captured in the
> riscv-toolchain-conventions repository):
>   - a public specification document is available (see above) and is
>     referenced from the gas-documentation
>   - the naming follows chapter 27 of the RISC-V ISA specification
>   - instructions are prefixed by a vendor-prefix (vt for Ventana)
>     to ensure that they neither conflict with future standard
>     extensions nor clash with other vendors
>
> bfd/ChangeLog:
>
>         * elfxx-riscv.c (riscv_get_default_ext_version): Add riscv_supported_vendor_x_ext.
>         (riscv_multi_subset_supports): Recognize INSN_CLASS_XVENTANACONDOPS.
>
> gas/ChangeLog:
>
>         * doc/c-riscv.texi: Add section to list custom extensions and
>           their documentation URLs.
>         * testsuite/gas/riscv/x-ventana-condops.d: New test.
>         * testsuite/gas/riscv/x-ventana-condops.s: New test.
>
> include/ChangeLog:
>
>         * opcode/riscv-opc.h Add vt.maskc and vt.maskcn.
>         * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_XVENTANACONDOPS.
>
> opcodes/ChangeLog:
>
>         * riscv-opc.c: Add vt.maskc and vt.maskcn.
>
> v2:
> - Rebase (no changes requested for v1; see
>   https://sourceware.org/pipermail/binutils/2022-January/119236.html)
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> ---
>  bfd/elfxx-riscv.c                           | 13 +++++++++++--
>  gas/doc/c-riscv.texi                        | 20 ++++++++++++++++++++
>  gas/testsuite/gas/riscv/x-ventana-condops.d | 12 ++++++++++++
>  gas/testsuite/gas/riscv/x-ventana-condops.s |  4 ++++
>  include/opcode/riscv-opc.h                  | 17 ++++++++++++++++-
>  include/opcode/riscv.h                      |  1 +
>  opcodes/riscv-opc.c                         |  4 ++++
>  7 files changed, 68 insertions(+), 3 deletions(-)
>  create mode 100644 gas/testsuite/gas/riscv/x-ventana-condops.d
>  create mode 100644 gas/testsuite/gas/riscv/x-ventana-condops.s
>
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index cb2cc146c04..723b30ddbfc 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1237,6 +1237,13 @@ static struct riscv_supported_ext riscv_supported_std_zxm_ext[] =
>    {NULL, 0, 0, 0, 0}
>  };
>
> +static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
> +{
> +  /* XVentanaCondOps: https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf */
> +  {"xventanacondops",  ISA_SPEC_CLASS_DRAFT,   1, 0, 0 },
> +  {NULL, 0, 0, 0, 0}
> +};
> +
>  const struct riscv_supported_ext *riscv_all_supported_ext[] =
>  {
>    riscv_supported_std_ext,
> @@ -1244,6 +1251,7 @@ const struct riscv_supported_ext *riscv_all_supported_ext[] =
>    riscv_supported_std_s_ext,
>    riscv_supported_std_h_ext,
>    riscv_supported_std_zxm_ext,
> +  riscv_supported_vendor_x_ext,
>    NULL
>  };
>
> @@ -1504,8 +1512,7 @@ riscv_get_default_ext_version (enum riscv_spec_class *default_isa_spec,
>      case RV_ISA_CLASS_Z: table = riscv_supported_std_z_ext; break;
>      case RV_ISA_CLASS_S: table = riscv_supported_std_s_ext; break;
>      case RV_ISA_CLASS_H: table = riscv_supported_std_h_ext; break;
> -    case RV_ISA_CLASS_X:
> -      break;
> +    case RV_ISA_CLASS_X: table = riscv_supported_vendor_x_ext; break;
>      default:
>        table = riscv_supported_std_ext;
>      }
> @@ -2402,6 +2409,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
>               || riscv_subset_supports (rps, "zve32f"));
>      case INSN_CLASS_SVINVAL:
>        return riscv_subset_supports (rps, "svinval");
> +    case INSN_CLASS_XVENTANACONDOPS:
> +      return riscv_subset_supports (rps, "xventanacondops");
>      default:
>        rps->error_handler
>          (_("internal: unreachable INSN_CLASS_*"));
> diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
> index 21d867e9cf0..c75a5ad5a08 100644
> --- a/gas/doc/c-riscv.texi
> +++ b/gas/doc/c-riscv.texi
> @@ -20,6 +20,7 @@
>  * RISC-V-Modifiers::      RISC-V Assembler Modifiers
>  * RISC-V-Formats::        RISC-V Instruction Formats
>  * RISC-V-ATTRIBUTE::      RISC-V Object Attribute
> +* RISC-V-CustomExts::     RISC-V Custom (Vendor-Defined) Extensions
>  @end menu
>
>  @node RISC-V-Options
> @@ -692,3 +693,22 @@ the privileged specification.  It will report errors if object files of
>  different privileged specification versions are merged.
>
>  @end table
> +
> +@node RISC-V-CustomExts
> +@section RISC-V Custom (Vendor-Defined) Extensions
> +@cindex custom (vendor-defined) extensions, RISC-V
> +@cindex RISC-V custom (vendor-defined) extensions
> +
> +The following table lists the custom (vendor-defined) RISC-V
> +extensions supported and provides the location of their
> +publicly-released documentation:
> +
> +@table @r
> +@item XVentanaCondOps
> +XVentanaCondOps extension provides instructions for branchless
> +sequences that perform conditional arithmetic, conditional
> +bitwise-logic, and conditional select operations.
> +
> +It is documented at @url{https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf}.
> +
> +@end table
> diff --git a/gas/testsuite/gas/riscv/x-ventana-condops.d b/gas/testsuite/gas/riscv/x-ventana-condops.d
> new file mode 100644
> index 00000000000..cab0cc8dc12
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/x-ventana-condops.d
> @@ -0,0 +1,12 @@
> +#as: -march=rv64i_xventanacondops1p0
> +#source: x-ventana-condops.s
> +#objdump: -d
> +
> +.*:[   ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[      ]+0:[   ]+00c5e57b[     ]+vt.maskc[     ]+a0,a1,a2
> +[      ]+4:[   ]+00e6f57b[     ]+vt.maskcn[    ]+a0,a3,a4
> diff --git a/gas/testsuite/gas/riscv/x-ventana-condops.s b/gas/testsuite/gas/riscv/x-ventana-condops.s
> new file mode 100644
> index 00000000000..562cf7384f7
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/x-ventana-condops.s
> @@ -0,0 +1,4 @@
> +target:
> +       vt.maskc        a0, a1, a2
> +       vt.maskcn       a0, a3, a4
> +
> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
> index 3eea33a5dae..419ed538da9 100644
> --- a/include/opcode/riscv-opc.h
> +++ b/include/opcode/riscv-opc.h
> @@ -2045,7 +2045,20 @@
>  #define MASK_CBO_INVAL 0xfff07fff
>  #define MATCH_CBO_ZERO 0x40200f
>  #define MASK_CBO_ZERO 0xfff07fff
> -/* Unprivileged Counter/Timers CSR addresses.  */
> +/* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
> +#define MATCH_VT_MASKC 0x607b
> +#define MASK_VT_MASKC 0xfe00707f
> +#define MATCH_VT_MASKCN 0x707b
> +#define MASK_VT_MASKCN 0xfe00707f
> +/* Privileged CSR addresses.  */
> +#define CSR_USTATUS 0x0
> +#define CSR_UIE 0x4
> +#define CSR_UTVEC 0x5
> +#define CSR_USCRATCH 0x40
> +#define CSR_UEPC 0x41
> +#define CSR_UCAUSE 0x42
> +#define CSR_UTVAL 0x43
> +#define CSR_UIP 0x44

These N-ext CSRs should be removed since priv 1.12 spec, so it seems
like they are added by accident here ;)

I think it would be better to follow the rules in the PR for any
RISC-V vendor extension
(https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/17).
So once the pr is approved and merged, I will say LGTM for this patch
and am happy to support Ventana's vendor extension in the master
branch.

As for the t-head cache instruction, personally for me, it would be
better to move the whole support from the integration branch to
master, and keep the Alibaba's guys as the main author.  If they agree
with the vendor rules in the PR above, and could help to rebase their
patch, it would be great :)

Thanks
Nelson

>  #define CSR_CYCLE 0xc00
>  #define CSR_TIME 0xc01
>  #define CSR_INSTRET 0xc02
> @@ -2720,6 +2733,8 @@ DECLARE_INSN(hsv_b, MATCH_HSV_B, MASK_HSV_B)
>  DECLARE_INSN(hsv_h, MATCH_HSV_H, MASK_HSV_H)
>  DECLARE_INSN(hsv_w, MATCH_HSV_W, MASK_HSV_W)
>  DECLARE_INSN(hsv_d, MATCH_HSV_D, MASK_HSV_D)
> +DECLARE_INSN(vt_maskc, MATCH_VT_MASKC, MASK_VT_MASKC)
> +DECLARE_INSN(vt_maskcn, MATCH_VT_MASKCN, MASK_VT_MASKCN)
>  #endif /* DECLARE_INSN */
>  #ifdef DECLARE_CSR
>  /* Unprivileged Counter/Timers CSRs.  */
> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
> index b769769b4ec..3cbb68b5655 100644
> --- a/include/opcode/riscv.h
> +++ b/include/opcode/riscv.h
> @@ -391,6 +391,7 @@ enum riscv_insn_class
>    INSN_CLASS_ZICBOM,
>    INSN_CLASS_ZICBOP,
>    INSN_CLASS_ZICBOZ,
> +  INSN_CLASS_XVENTANACONDOPS,
>  };
>
>  /* This structure holds information for a particular instruction.  */
> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> index 00108ff24ae..052209f6fe2 100644
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -1762,6 +1762,10 @@ const struct riscv_opcode riscv_opcodes[] =
>  {"hsv.w",       0, INSN_CLASS_I, "t,0(s)", MATCH_HSV_W, MASK_HSV_W, match_opcode, INSN_DREF|INSN_4_BYTE },
>  {"hsv.d",      64, INSN_CLASS_I, "t,0(s)", MATCH_HSV_D, MASK_HSV_D, match_opcode, INSN_DREF|INSN_8_BYTE },
>
> +/* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
> +{"vt.maskc",    0, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 },
> +{"vt.maskcn",   0, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKCN, MASK_VT_MASKCN, match_opcode, 0 },
> +
>  /* Terminate the list.  */
>  {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
>  };
> --
> 2.35.1
>

Re: [PATCH 1/2] RISC-V: Support XVentanaCondOps extension

[Philipp Tomsich]

On Mon, 25 Apr 2022 at 11:54, Nelson Chu <nelson.chu@sifive.com> wrote:
>
> On Wed, Apr 20, 2022 at 10:56 PM Christoph Muellner
> <cmuellner@gcc.gnu.org> wrote:
> >
> > From: Philipp Tomsich <philipp.tomsich@vrull.eu>
> >
> > Ventana Micro has published the specification for their
> > XVentanaCondOps ("conditional ops") extension at
> >   https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf
> > which contains two new instructions
> >   - vt.maskc
> >   - vt.maskcn
> > that can be used in constructing branchless sequences for
> > various conditional-arithmetic, conditional-logical, and
> > conditional-select operations.
> >
> > To support such vendor-defined instructions in the mainline binutils,
> > this change also adds a riscv_supported_vendor_x_ext secondary
> > dispatch table (but also keeps the behaviour of allowing any unknow
> > X-extension to be specified in addition to the known ones from this
> > table).
> >
> > As discussed, this change already includes the planned/agreed future
> > requirements for X-extensions (which are likely to be captured in the
> > riscv-toolchain-conventions repository):
> >   - a public specification document is available (see above) and is
> >     referenced from the gas-documentation
> >   - the naming follows chapter 27 of the RISC-V ISA specification
> >   - instructions are prefixed by a vendor-prefix (vt for Ventana)
> >     to ensure that they neither conflict with future standard
> >     extensions nor clash with other vendors
> >
> > bfd/ChangeLog:
> >
> >         * elfxx-riscv.c (riscv_get_default_ext_version): Add riscv_supported_vendor_x_ext.
> >         (riscv_multi_subset_supports): Recognize INSN_CLASS_XVENTANACONDOPS.
> >
> > gas/ChangeLog:
> >
> >         * doc/c-riscv.texi: Add section to list custom extensions and
> >           their documentation URLs.
> >         * testsuite/gas/riscv/x-ventana-condops.d: New test.
> >         * testsuite/gas/riscv/x-ventana-condops.s: New test.
> >
> > include/ChangeLog:
> >
> >         * opcode/riscv-opc.h Add vt.maskc and vt.maskcn.
> >         * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_XVENTANACONDOPS.
> >
> > opcodes/ChangeLog:
> >
> >         * riscv-opc.c: Add vt.maskc and vt.maskcn.
> >
> > v2:
> > - Rebase (no changes requested for v1; see
> >   https://sourceware.org/pipermail/binutils/2022-January/119236.html)
> >
> > Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> > ---
> >  bfd/elfxx-riscv.c                           | 13 +++++++++++--
> >  gas/doc/c-riscv.texi                        | 20 ++++++++++++++++++++
> >  gas/testsuite/gas/riscv/x-ventana-condops.d | 12 ++++++++++++
> >  gas/testsuite/gas/riscv/x-ventana-condops.s |  4 ++++
> >  include/opcode/riscv-opc.h                  | 17 ++++++++++++++++-
> >  include/opcode/riscv.h                      |  1 +
> >  opcodes/riscv-opc.c                         |  4 ++++
> >  7 files changed, 68 insertions(+), 3 deletions(-)
> >  create mode 100644 gas/testsuite/gas/riscv/x-ventana-condops.d
> >  create mode 100644 gas/testsuite/gas/riscv/x-ventana-condops.s
> >
> > diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> > index cb2cc146c04..723b30ddbfc 100644
> > --- a/bfd/elfxx-riscv.c
> > +++ b/bfd/elfxx-riscv.c
> > @@ -1237,6 +1237,13 @@ static struct riscv_supported_ext riscv_supported_std_zxm_ext[] =
> >    {NULL, 0, 0, 0, 0}
> >  };
> >
> > +static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
> > +{
> > +  /* XVentanaCondOps: https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf */
> > +  {"xventanacondops",  ISA_SPEC_CLASS_DRAFT,   1, 0, 0 },
> > +  {NULL, 0, 0, 0, 0}
> > +};
> > +
> >  const struct riscv_supported_ext *riscv_all_supported_ext[] =
> >  {
> >    riscv_supported_std_ext,
> > @@ -1244,6 +1251,7 @@ const struct riscv_supported_ext *riscv_all_supported_ext[] =
> >    riscv_supported_std_s_ext,
> >    riscv_supported_std_h_ext,
> >    riscv_supported_std_zxm_ext,
> > +  riscv_supported_vendor_x_ext,
> >    NULL
> >  };
> >
> > @@ -1504,8 +1512,7 @@ riscv_get_default_ext_version (enum riscv_spec_class *default_isa_spec,
> >      case RV_ISA_CLASS_Z: table = riscv_supported_std_z_ext; break;
> >      case RV_ISA_CLASS_S: table = riscv_supported_std_s_ext; break;
> >      case RV_ISA_CLASS_H: table = riscv_supported_std_h_ext; break;
> > -    case RV_ISA_CLASS_X:
> > -      break;
> > +    case RV_ISA_CLASS_X: table = riscv_supported_vendor_x_ext; break;
> >      default:
> >        table = riscv_supported_std_ext;
> >      }
> > @@ -2402,6 +2409,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
> >               || riscv_subset_supports (rps, "zve32f"));
> >      case INSN_CLASS_SVINVAL:
> >        return riscv_subset_supports (rps, "svinval");
> > +    case INSN_CLASS_XVENTANACONDOPS:
> > +      return riscv_subset_supports (rps, "xventanacondops");
> >      default:
> >        rps->error_handler
> >          (_("internal: unreachable INSN_CLASS_*"));
> > diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
> > index 21d867e9cf0..c75a5ad5a08 100644
> > --- a/gas/doc/c-riscv.texi
> > +++ b/gas/doc/c-riscv.texi
> > @@ -20,6 +20,7 @@
> >  * RISC-V-Modifiers::      RISC-V Assembler Modifiers
> >  * RISC-V-Formats::        RISC-V Instruction Formats
> >  * RISC-V-ATTRIBUTE::      RISC-V Object Attribute
> > +* RISC-V-CustomExts::     RISC-V Custom (Vendor-Defined) Extensions
> >  @end menu
> >
> >  @node RISC-V-Options
> > @@ -692,3 +693,22 @@ the privileged specification.  It will report errors if object files of
> >  different privileged specification versions are merged.
> >
> >  @end table
> > +
> > +@node RISC-V-CustomExts
> > +@section RISC-V Custom (Vendor-Defined) Extensions
> > +@cindex custom (vendor-defined) extensions, RISC-V
> > +@cindex RISC-V custom (vendor-defined) extensions
> > +
> > +The following table lists the custom (vendor-defined) RISC-V
> > +extensions supported and provides the location of their
> > +publicly-released documentation:
> > +
> > +@table @r
> > +@item XVentanaCondOps
> > +XVentanaCondOps extension provides instructions for branchless
> > +sequences that perform conditional arithmetic, conditional
> > +bitwise-logic, and conditional select operations.
> > +
> > +It is documented at @url{https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf}.
> > +
> > +@end table
> > diff --git a/gas/testsuite/gas/riscv/x-ventana-condops.d b/gas/testsuite/gas/riscv/x-ventana-condops.d
> > new file mode 100644
> > index 00000000000..cab0cc8dc12
> > --- /dev/null
> > +++ b/gas/testsuite/gas/riscv/x-ventana-condops.d
> > @@ -0,0 +1,12 @@
> > +#as: -march=rv64i_xventanacondops1p0
> > +#source: x-ventana-condops.s
> > +#objdump: -d
> > +
> > +.*:[   ]+file format .*
> > +
> > +
> > +Disassembly of section .text:
> > +
> > +0+000 <target>:
> > +[      ]+0:[   ]+00c5e57b[     ]+vt.maskc[     ]+a0,a1,a2
> > +[      ]+4:[   ]+00e6f57b[     ]+vt.maskcn[    ]+a0,a3,a4
> > diff --git a/gas/testsuite/gas/riscv/x-ventana-condops.s b/gas/testsuite/gas/riscv/x-ventana-condops.s
> > new file mode 100644
> > index 00000000000..562cf7384f7
> > --- /dev/null
> > +++ b/gas/testsuite/gas/riscv/x-ventana-condops.s
> > @@ -0,0 +1,4 @@
> > +target:
> > +       vt.maskc        a0, a1, a2
> > +       vt.maskcn       a0, a3, a4
> > +
> > diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
> > index 3eea33a5dae..419ed538da9 100644
> > --- a/include/opcode/riscv-opc.h
> > +++ b/include/opcode/riscv-opc.h
> > @@ -2045,7 +2045,20 @@
> >  #define MASK_CBO_INVAL 0xfff07fff
> >  #define MATCH_CBO_ZERO 0x40200f
> >  #define MASK_CBO_ZERO 0xfff07fff
> > -/* Unprivileged Counter/Timers CSR addresses.  */
> > +/* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
> > +#define MATCH_VT_MASKC 0x607b
> > +#define MASK_VT_MASKC 0xfe00707f
> > +#define MATCH_VT_MASKCN 0x707b
> > +#define MASK_VT_MASKCN 0xfe00707f
> > +/* Privileged CSR addresses.  */
> > +#define CSR_USTATUS 0x0
> > +#define CSR_UIE 0x4
> > +#define CSR_UTVEC 0x5
> > +#define CSR_USCRATCH 0x40
> > +#define CSR_UEPC 0x41
> > +#define CSR_UCAUSE 0x42
> > +#define CSR_UTVAL 0x43
> > +#define CSR_UIP 0x44
>
> These N-ext CSRs should be removed since priv 1.12 spec, so it seems
> like they are added by accident here ;)

As my original patch
(https://sourceware.org/pipermail/binutils/2022-January/119236.html)
didn't have these, I'd say that this must be an artifact from "a
rebase gone wrong".  I guess this comes from the rebase mentioned in
Christoph's v2 changelog above...

> I think it would be better to follow the rules in the PR for an
> RISC-V vendor extension
> (https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/17).
> So once the pr is approved and merged, I will say LGTM for this patch
> and am happy to support Ventana's vendor extension in the master
> branch.
>
> As for the t-head cache instruction, personally for me, it would be
> better to move the whole support from the integration branch to
> master, and keep the Alibaba's guys as the main author.  If they agree
> with the vendor rules in the PR above, and could help to rebase their
> patch, it would be great :)

Which integration branch are you referring to?
AFAIK, there is no patch adding cache instructions floating around
(which is the reason why we created a cleanroom implementation for
these).

We have buy-in on the vendor rules (after all, Chen Wei from T-Head is
the vice-chair of the Software HC) from Alibaba, but you can expect
things to take a while to propagate through into their own trees and
documents.  Note that in a separate effort, I am talking to T-Head to
have their instructions grouped into multiple, separate extensions
(and hopefully also have their documentation updated to reflect this
in the same structure as we're using in the RISC-V documentation
elsewhere).

Cheers,
Philipp.


> Thanks
> Nelson
>
> >  #define CSR_CYCLE 0xc00
> >  #define CSR_TIME 0xc01
> >  #define CSR_INSTRET 0xc02
> > @@ -2720,6 +2733,8 @@ DECLARE_INSN(hsv_b, MATCH_HSV_B, MASK_HSV_B)
> >  DECLARE_INSN(hsv_h, MATCH_HSV_H, MASK_HSV_H)
> >  DECLARE_INSN(hsv_w, MATCH_HSV_W, MASK_HSV_W)
> >  DECLARE_INSN(hsv_d, MATCH_HSV_D, MASK_HSV_D)
> > +DECLARE_INSN(vt_maskc, MATCH_VT_MASKC, MASK_VT_MASKC)
> > +DECLARE_INSN(vt_maskcn, MATCH_VT_MASKCN, MASK_VT_MASKCN)
> >  #endif /* DECLARE_INSN */
> >  #ifdef DECLARE_CSR
> >  /* Unprivileged Counter/Timers CSRs.  */
> > diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
> > index b769769b4ec..3cbb68b5655 100644
> > --- a/include/opcode/riscv.h
> > +++ b/include/opcode/riscv.h
> > @@ -391,6 +391,7 @@ enum riscv_insn_class
> >    INSN_CLASS_ZICBOM,
> >    INSN_CLASS_ZICBOP,
> >    INSN_CLASS_ZICBOZ,
> > +  INSN_CLASS_XVENTANACONDOPS,
> >  };
> >
> >  /* This structure holds information for a particular instruction.  */
> > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> > index 00108ff24ae..052209f6fe2 100644
> > --- a/opcodes/riscv-opc.c
> > +++ b/opcodes/riscv-opc.c
> > @@ -1762,6 +1762,10 @@ const struct riscv_opcode riscv_opcodes[] =
> >  {"hsv.w",       0, INSN_CLASS_I, "t,0(s)", MATCH_HSV_W, MASK_HSV_W, match_opcode, INSN_DREF|INSN_4_BYTE },
> >  {"hsv.d",      64, INSN_CLASS_I, "t,0(s)", MATCH_HSV_D, MASK_HSV_D, match_opcode, INSN_DREF|INSN_8_BYTE },
> >
> > +/* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
> > +{"vt.maskc",    0, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 },
> > +{"vt.maskcn",   0, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKCN, MASK_VT_MASKCN, match_opcode, 0 },
> > +
> >  /* Terminate the list.  */
> >  {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
> >  };
> > --
> > 2.35.1
> >

Re: [PATCH 1/2] RISC-V: Support XVentanaCondOps extension

[Christoph Müllner]

On Mon, Apr 25, 2022 at 2:15 PM Philipp Tomsich <philipp.tomsich@vrull.eu>
wrote:

> On Mon, 25 Apr 2022 at 11:54, Nelson Chu <nelson.chu@sifive.com> wrote:
> >
> > On Wed, Apr 20, 2022 at 10:56 PM Christoph Muellner
> > <cmuellner@gcc.gnu.org> wrote:
> > >
> > > From: Philipp Tomsich <philipp.tomsich@vrull.eu>
> > >
> > > Ventana Micro has published the specification for their
> > > XVentanaCondOps ("conditional ops") extension at
> > >
> https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf
> > > which contains two new instructions
> > >   - vt.maskc
> > >   - vt.maskcn
> > > that can be used in constructing branchless sequences for
> > > various conditional-arithmetic, conditional-logical, and
> > > conditional-select operations.
> > >
> > > To support such vendor-defined instructions in the mainline binutils,
> > > this change also adds a riscv_supported_vendor_x_ext secondary
> > > dispatch table (but also keeps the behaviour of allowing any unknow
> > > X-extension to be specified in addition to the known ones from this
> > > table).
> > >
> > > As discussed, this change already includes the planned/agreed future
> > > requirements for X-extensions (which are likely to be captured in the
> > > riscv-toolchain-conventions repository):
> > >   - a public specification document is available (see above) and is
> > >     referenced from the gas-documentation
> > >   - the naming follows chapter 27 of the RISC-V ISA specification
> > >   - instructions are prefixed by a vendor-prefix (vt for Ventana)
> > >     to ensure that they neither conflict with future standard
> > >     extensions nor clash with other vendors
> > >
> > > bfd/ChangeLog:
> > >
> > >         * elfxx-riscv.c (riscv_get_default_ext_version): Add
> riscv_supported_vendor_x_ext.
> > >         (riscv_multi_subset_supports): Recognize
> INSN_CLASS_XVENTANACONDOPS.
> > >
> > > gas/ChangeLog:
> > >
> > >         * doc/c-riscv.texi: Add section to list custom extensions and
> > >           their documentation URLs.
> > >         * testsuite/gas/riscv/x-ventana-condops.d: New test.
> > >         * testsuite/gas/riscv/x-ventana-condops.s: New test.
> > >
> > > include/ChangeLog:
> > >
> > >         * opcode/riscv-opc.h Add vt.maskc and vt.maskcn.
> > >         * opcode/riscv.h (enum riscv_insn_class): Add
> INSN_CLASS_XVENTANACONDOPS.
> > >
> > > opcodes/ChangeLog:
> > >
> > >         * riscv-opc.c: Add vt.maskc and vt.maskcn.
> > >
> > > v2:
> > > - Rebase (no changes requested for v1; see
> > >   https://sourceware.org/pipermail/binutils/2022-January/119236.html)
> > >
> > > Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> > > ---
> > >  bfd/elfxx-riscv.c                           | 13 +++++++++++--
> > >  gas/doc/c-riscv.texi                        | 20 ++++++++++++++++++++
> > >  gas/testsuite/gas/riscv/x-ventana-condops.d | 12 ++++++++++++
> > >  gas/testsuite/gas/riscv/x-ventana-condops.s |  4 ++++
> > >  include/opcode/riscv-opc.h                  | 17 ++++++++++++++++-
> > >  include/opcode/riscv.h                      |  1 +
> > >  opcodes/riscv-opc.c                         |  4 ++++
> > >  7 files changed, 68 insertions(+), 3 deletions(-)
> > >  create mode 100644 gas/testsuite/gas/riscv/x-ventana-condops.d
> > >  create mode 100644 gas/testsuite/gas/riscv/x-ventana-condops.s
> > >
> > > diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> > > index cb2cc146c04..723b30ddbfc 100644
> > > --- a/bfd/elfxx-riscv.c
> > > +++ b/bfd/elfxx-riscv.c
> > > @@ -1237,6 +1237,13 @@ static struct riscv_supported_ext
> riscv_supported_std_zxm_ext[] =
> > >    {NULL, 0, 0, 0, 0}
> > >  };
> > >
> > > +static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
> > > +{
> > > +  /* XVentanaCondOps:
> https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf
> */
> > > +  {"xventanacondops",  ISA_SPEC_CLASS_DRAFT,   1, 0, 0 },
> > > +  {NULL, 0, 0, 0, 0}
> > > +};
> > > +
> > >  const struct riscv_supported_ext *riscv_all_supported_ext[] =
> > >  {
> > >    riscv_supported_std_ext,
> > > @@ -1244,6 +1251,7 @@ const struct riscv_supported_ext
> *riscv_all_supported_ext[] =
> > >    riscv_supported_std_s_ext,
> > >    riscv_supported_std_h_ext,
> > >    riscv_supported_std_zxm_ext,
> > > +  riscv_supported_vendor_x_ext,
> > >    NULL
> > >  };
> > >
> > > @@ -1504,8 +1512,7 @@ riscv_get_default_ext_version (enum
> riscv_spec_class *default_isa_spec,
> > >      case RV_ISA_CLASS_Z: table = riscv_supported_std_z_ext; break;
> > >      case RV_ISA_CLASS_S: table = riscv_supported_std_s_ext; break;
> > >      case RV_ISA_CLASS_H: table = riscv_supported_std_h_ext; break;
> > > -    case RV_ISA_CLASS_X:
> > > -      break;
> > > +    case RV_ISA_CLASS_X: table = riscv_supported_vendor_x_ext; break;
> > >      default:
> > >        table = riscv_supported_std_ext;
> > >      }
> > > @@ -2402,6 +2409,8 @@ riscv_multi_subset_supports
> (riscv_parse_subset_t *rps,
> > >               || riscv_subset_supports (rps, "zve32f"));
> > >      case INSN_CLASS_SVINVAL:
> > >        return riscv_subset_supports (rps, "svinval");
> > > +    case INSN_CLASS_XVENTANACONDOPS:
> > > +      return riscv_subset_supports (rps, "xventanacondops");
> > >      default:
> > >        rps->error_handler
> > >          (_("internal: unreachable INSN_CLASS_*"));
> > > diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
> > > index 21d867e9cf0..c75a5ad5a08 100644
> > > --- a/gas/doc/c-riscv.texi
> > > +++ b/gas/doc/c-riscv.texi
> > > @@ -20,6 +20,7 @@
> > >  * RISC-V-Modifiers::      RISC-V Assembler Modifiers
> > >  * RISC-V-Formats::        RISC-V Instruction Formats
> > >  * RISC-V-ATTRIBUTE::      RISC-V Object Attribute
> > > +* RISC-V-CustomExts::     RISC-V Custom (Vendor-Defined) Extensions
> > >  @end menu
> > >
> > >  @node RISC-V-Options
> > > @@ -692,3 +693,22 @@ the privileged specification.  It will report
> errors if object files of
> > >  different privileged specification versions are merged.
> > >
> > >  @end table
> > > +
> > > +@node RISC-V-CustomExts
> > > +@section RISC-V Custom (Vendor-Defined) Extensions
> > > +@cindex custom (vendor-defined) extensions, RISC-V
> > > +@cindex RISC-V custom (vendor-defined) extensions
> > > +
> > > +The following table lists the custom (vendor-defined) RISC-V
> > > +extensions supported and provides the location of their
> > > +publicly-released documentation:
> > > +
> > > +@table @r
> > > +@item XVentanaCondOps
> > > +XVentanaCondOps extension provides instructions for branchless
> > > +sequences that perform conditional arithmetic, conditional
> > > +bitwise-logic, and conditional select operations.
> > > +
> > > +It is documented at @url{
> https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf
> }.
> > > +
> > > +@end table
> > > diff --git a/gas/testsuite/gas/riscv/x-ventana-condops.d
> b/gas/testsuite/gas/riscv/x-ventana-condops.d
> > > new file mode 100644
> > > index 00000000000..cab0cc8dc12
> > > --- /dev/null
> > > +++ b/gas/testsuite/gas/riscv/x-ventana-condops.d
> > > @@ -0,0 +1,12 @@
> > > +#as: -march=rv64i_xventanacondops1p0
> > > +#source: x-ventana-condops.s
> > > +#objdump: -d
> > > +
> > > +.*:[   ]+file format .*
> > > +
> > > +
> > > +Disassembly of section .text:
> > > +
> > > +0+000 <target>:
> > > +[      ]+0:[   ]+00c5e57b[     ]+vt.maskc[     ]+a0,a1,a2
> > > +[      ]+4:[   ]+00e6f57b[     ]+vt.maskcn[    ]+a0,a3,a4
> > > diff --git a/gas/testsuite/gas/riscv/x-ventana-condops.s
> b/gas/testsuite/gas/riscv/x-ventana-condops.s
> > > new file mode 100644
> > > index 00000000000..562cf7384f7
> > > --- /dev/null
> > > +++ b/gas/testsuite/gas/riscv/x-ventana-condops.s
> > > @@ -0,0 +1,4 @@
> > > +target:
> > > +       vt.maskc        a0, a1, a2
> > > +       vt.maskcn       a0, a3, a4
> > > +
> > > diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
> > > index 3eea33a5dae..419ed538da9 100644
> > > --- a/include/opcode/riscv-opc.h
> > > +++ b/include/opcode/riscv-opc.h
> > > @@ -2045,7 +2045,20 @@
> > >  #define MASK_CBO_INVAL 0xfff07fff
> > >  #define MATCH_CBO_ZERO 0x40200f
> > >  #define MASK_CBO_ZERO 0xfff07fff
> > > -/* Unprivileged Counter/Timers CSR addresses.  */
> > > +/* Vendor-specific (Ventana Microsystems) XVentanaCondOps
> instructions */
> > > +#define MATCH_VT_MASKC 0x607b
> > > +#define MASK_VT_MASKC 0xfe00707f
> > > +#define MATCH_VT_MASKCN 0x707b
> > > +#define MASK_VT_MASKCN 0xfe00707f
> > > +/* Privileged CSR addresses.  */
> > > +#define CSR_USTATUS 0x0
> > > +#define CSR_UIE 0x4
> > > +#define CSR_UTVEC 0x5
> > > +#define CSR_USCRATCH 0x40
> > > +#define CSR_UEPC 0x41
> > > +#define CSR_UCAUSE 0x42
> > > +#define CSR_UTVAL 0x43
> > > +#define CSR_UIP 0x44
> >
> > These N-ext CSRs should be removed since priv 1.12 spec, so it seems
> > like they are added by accident here ;)
>
> As my original patch
> (https://sourceware.org/pipermail/binutils/2022-January/119236.html)
> didn't have these, I'd say that this must be an artifact from "a
> rebase gone wrong".  I guess this comes from the rebase mentioned in
> Christoph's v2 changelog above...
>

Yes, that's a rebase artifact.
I intend to rebase and resend once riscv-toolchain-convention#17 gets merged
unless Nelson wants to handle this directly.



>
> > I think it would be better to follow the rules in the PR for an
> > RISC-V vendor extension
> > (https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/17).
> > So once the pr is approved and merged, I will say LGTM for this patch
> > and am happy to support Ventana's vendor extension in the master
> > branch.
> >
> > As for the t-head cache instruction, personally for me, it would be
> > better to move the whole support from the integration branch to
> > master, and keep the Alibaba's guys as the main author.  If they agree
> > with the vendor rules in the PR above, and could help to rebase their
> > patch, it would be great :)
>
> Which integration branch are you referring to?
> AFAIK, there is no patch adding cache instructions floating around
> (which is the reason why we created a cleanroom implementation for
> these).
>
> We have buy-in on the vendor rules (after all, Chen Wei from T-Head is
> the vice-chair of the Software HC) from Alibaba, but you can expect
> things to take a while to propagate through into their own trees and
> documents.  Note that in a separate effort, I am talking to T-Head to
> have their instructions grouped into multiple, separate extensions
> (and hopefully also have their documentation updated to reflect this
> in the same structure as we're using in the RISC-V documentation
> elsewhere).
>
> Cheers,
> Philipp.
>
>
> > Thanks
> > Nelson
> >
> > >  #define CSR_CYCLE 0xc00
> > >  #define CSR_TIME 0xc01
> > >  #define CSR_INSTRET 0xc02
> > > @@ -2720,6 +2733,8 @@ DECLARE_INSN(hsv_b, MATCH_HSV_B, MASK_HSV_B)
> > >  DECLARE_INSN(hsv_h, MATCH_HSV_H, MASK_HSV_H)
> > >  DECLARE_INSN(hsv_w, MATCH_HSV_W, MASK_HSV_W)
> > >  DECLARE_INSN(hsv_d, MATCH_HSV_D, MASK_HSV_D)
> > > +DECLARE_INSN(vt_maskc, MATCH_VT_MASKC, MASK_VT_MASKC)
> > > +DECLARE_INSN(vt_maskcn, MATCH_VT_MASKCN, MASK_VT_MASKCN)
> > >  #endif /* DECLARE_INSN */
> > >  #ifdef DECLARE_CSR
> > >  /* Unprivileged Counter/Timers CSRs.  */
> > > diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
> > > index b769769b4ec..3cbb68b5655 100644
> > > --- a/include/opcode/riscv.h
> > > +++ b/include/opcode/riscv.h
> > > @@ -391,6 +391,7 @@ enum riscv_insn_class
> > >    INSN_CLASS_ZICBOM,
> > >    INSN_CLASS_ZICBOP,
> > >    INSN_CLASS_ZICBOZ,
> > > +  INSN_CLASS_XVENTANACONDOPS,
> > >  };
> > >
> > >  /* This structure holds information for a particular instruction.  */
> > > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> > > index 00108ff24ae..052209f6fe2 100644
> > > --- a/opcodes/riscv-opc.c
> > > +++ b/opcodes/riscv-opc.c
> > > @@ -1762,6 +1762,10 @@ const struct riscv_opcode riscv_opcodes[] =
> > >  {"hsv.w",       0, INSN_CLASS_I, "t,0(s)", MATCH_HSV_W, MASK_HSV_W,
> match_opcode, INSN_DREF|INSN_4_BYTE },
> > >  {"hsv.d",      64, INSN_CLASS_I, "t,0(s)", MATCH_HSV_D, MASK_HSV_D,
> match_opcode, INSN_DREF|INSN_8_BYTE },
> > >
> > > +/* Vendor-specific (Ventana Microsystems) XVentanaCondOps
> instructions */
> > > +{"vt.maskc",    0, INSN_CLASS_XVENTANACONDOPS, "d,s,t",
> MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 },
> > > +{"vt.maskcn",   0, INSN_CLASS_XVENTANACONDOPS, "d,s,t",
> MATCH_VT_MASKCN, MASK_VT_MASKCN, match_opcode, 0 },
> > > +
> > >  /* Terminate the list.  */
> > >  {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
> > >  };
> > > --
> > > 2.35.1
> > >
>

Re: [PATCH 1/2] RISC-V: Support XVentanaCondOps extension

[C-SKY]

On 2022/4/25 下午5:54, Nelson Chu wrote:
> On Wed, Apr 20, 2022 at 10:56 PM Christoph Muellner
> <cmuellner@gcc.gnu.org> wrote:
>> From: Philipp Tomsich <philipp.tomsich@vrull.eu>
>>
>> Ventana Micro has published the specification for their
>> XVentanaCondOps ("conditional ops") extension at
>>    https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf
>> which contains two new instructions
>>    - vt.maskc
>>    - vt.maskcn
>> that can be used in constructing branchless sequences for
>> various conditional-arithmetic, conditional-logical, and
>> conditional-select operations.
>>
>> To support such vendor-defined instructions in the mainline binutils,
>> this change also adds a riscv_supported_vendor_x_ext secondary
>> dispatch table (but also keeps the behaviour of allowing any unknow
>> X-extension to be specified in addition to the known ones from this
>> table).
>>
>> As discussed, this change already includes the planned/agreed future
>> requirements for X-extensions (which are likely to be captured in the
>> riscv-toolchain-conventions repository):
>>    - a public specification document is available (see above) and is
>>      referenced from the gas-documentation
>>    - the naming follows chapter 27 of the RISC-V ISA specification
>>    - instructions are prefixed by a vendor-prefix (vt for Ventana)
>>      to ensure that they neither conflict with future standard
>>      extensions nor clash with other vendors
>>
>> bfd/ChangeLog:
>>
>>          * elfxx-riscv.c (riscv_get_default_ext_version): Add riscv_supported_vendor_x_ext.
>>          (riscv_multi_subset_supports): Recognize INSN_CLASS_XVENTANACONDOPS.
>>
>> gas/ChangeLog:
>>
>>          * doc/c-riscv.texi: Add section to list custom extensions and
>>            their documentation URLs.
>>          * testsuite/gas/riscv/x-ventana-condops.d: New test.
>>          * testsuite/gas/riscv/x-ventana-condops.s: New test.
>>
>> include/ChangeLog:
>>
>>          * opcode/riscv-opc.h Add vt.maskc and vt.maskcn.
>>          * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_XVENTANACONDOPS.
>>
>> opcodes/ChangeLog:
>>
>>          * riscv-opc.c: Add vt.maskc and vt.maskcn.
>>
>> v2:
>> - Rebase (no changes requested for v1; see
>>    https://sourceware.org/pipermail/binutils/2022-January/119236.html)
>>
>> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
>> ---
>>   bfd/elfxx-riscv.c                           | 13 +++++++++++--
>>   gas/doc/c-riscv.texi                        | 20 ++++++++++++++++++++
>>   gas/testsuite/gas/riscv/x-ventana-condops.d | 12 ++++++++++++
>>   gas/testsuite/gas/riscv/x-ventana-condops.s |  4 ++++
>>   include/opcode/riscv-opc.h                  | 17 ++++++++++++++++-
>>   include/opcode/riscv.h                      |  1 +
>>   opcodes/riscv-opc.c                         |  4 ++++
>>   7 files changed, 68 insertions(+), 3 deletions(-)
>>   create mode 100644 gas/testsuite/gas/riscv/x-ventana-condops.d
>>   create mode 100644 gas/testsuite/gas/riscv/x-ventana-condops.s
>>
>> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
>> index cb2cc146c04..723b30ddbfc 100644
>> --- a/bfd/elfxx-riscv.c
>> +++ b/bfd/elfxx-riscv.c
>> @@ -1237,6 +1237,13 @@ static struct riscv_supported_ext riscv_supported_std_zxm_ext[] =
>>     {NULL, 0, 0, 0, 0}
>>   };
>>
>> +static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
>> +{
>> +  /* XVentanaCondOps: https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf */
>> +  {"xventanacondops",  ISA_SPEC_CLASS_DRAFT,   1, 0, 0 },
>> +  {NULL, 0, 0, 0, 0}
>> +};
>> +
>>   const struct riscv_supported_ext *riscv_all_supported_ext[] =
>>   {
>>     riscv_supported_std_ext,
>> @@ -1244,6 +1251,7 @@ const struct riscv_supported_ext *riscv_all_supported_ext[] =
>>     riscv_supported_std_s_ext,
>>     riscv_supported_std_h_ext,
>>     riscv_supported_std_zxm_ext,
>> +  riscv_supported_vendor_x_ext,
>>     NULL
>>   };
>>
>> @@ -1504,8 +1512,7 @@ riscv_get_default_ext_version (enum riscv_spec_class *default_isa_spec,
>>       case RV_ISA_CLASS_Z: table = riscv_supported_std_z_ext; break;
>>       case RV_ISA_CLASS_S: table = riscv_supported_std_s_ext; break;
>>       case RV_ISA_CLASS_H: table = riscv_supported_std_h_ext; break;
>> -    case RV_ISA_CLASS_X:
>> -      break;
>> +    case RV_ISA_CLASS_X: table = riscv_supported_vendor_x_ext; break;
>>       default:
>>         table = riscv_supported_std_ext;
>>       }
>> @@ -2402,6 +2409,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
>>                || riscv_subset_supports (rps, "zve32f"));
>>       case INSN_CLASS_SVINVAL:
>>         return riscv_subset_supports (rps, "svinval");
>> +    case INSN_CLASS_XVENTANACONDOPS:
>> +      return riscv_subset_supports (rps, "xventanacondops");
>>       default:
>>         rps->error_handler
>>           (_("internal: unreachable INSN_CLASS_*"));
>> diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
>> index 21d867e9cf0..c75a5ad5a08 100644
>> --- a/gas/doc/c-riscv.texi
>> +++ b/gas/doc/c-riscv.texi
>> @@ -20,6 +20,7 @@
>>   * RISC-V-Modifiers::      RISC-V Assembler Modifiers
>>   * RISC-V-Formats::        RISC-V Instruction Formats
>>   * RISC-V-ATTRIBUTE::      RISC-V Object Attribute
>> +* RISC-V-CustomExts::     RISC-V Custom (Vendor-Defined) Extensions
>>   @end menu
>>
>>   @node RISC-V-Options
>> @@ -692,3 +693,22 @@ the privileged specification.  It will report errors if object files of
>>   different privileged specification versions are merged.
>>
>>   @end table
>> +
>> +@node RISC-V-CustomExts
>> +@section RISC-V Custom (Vendor-Defined) Extensions
>> +@cindex custom (vendor-defined) extensions, RISC-V
>> +@cindex RISC-V custom (vendor-defined) extensions
>> +
>> +The following table lists the custom (vendor-defined) RISC-V
>> +extensions supported and provides the location of their
>> +publicly-released documentation:
>> +
>> +@table @r
>> +@item XVentanaCondOps
>> +XVentanaCondOps extension provides instructions for branchless
>> +sequences that perform conditional arithmetic, conditional
>> +bitwise-logic, and conditional select operations.
>> +
>> +It is documented at @url{https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf}.
>> +
>> +@end table
>> diff --git a/gas/testsuite/gas/riscv/x-ventana-condops.d b/gas/testsuite/gas/riscv/x-ventana-condops.d
>> new file mode 100644
>> index 00000000000..cab0cc8dc12
>> --- /dev/null
>> +++ b/gas/testsuite/gas/riscv/x-ventana-condops.d
>> @@ -0,0 +1,12 @@
>> +#as: -march=rv64i_xventanacondops1p0
>> +#source: x-ventana-condops.s
>> +#objdump: -d
>> +
>> +.*:[   ]+file format .*
>> +
>> +
>> +Disassembly of section .text:
>> +
>> +0+000 <target>:
>> +[      ]+0:[   ]+00c5e57b[     ]+vt.maskc[     ]+a0,a1,a2
>> +[      ]+4:[   ]+00e6f57b[     ]+vt.maskcn[    ]+a0,a3,a4
>> diff --git a/gas/testsuite/gas/riscv/x-ventana-condops.s b/gas/testsuite/gas/riscv/x-ventana-condops.s
>> new file mode 100644
>> index 00000000000..562cf7384f7
>> --- /dev/null
>> +++ b/gas/testsuite/gas/riscv/x-ventana-condops.s
>> @@ -0,0 +1,4 @@
>> +target:
>> +       vt.maskc        a0, a1, a2
>> +       vt.maskcn       a0, a3, a4
>> +
>> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
>> index 3eea33a5dae..419ed538da9 100644
>> --- a/include/opcode/riscv-opc.h
>> +++ b/include/opcode/riscv-opc.h
>> @@ -2045,7 +2045,20 @@
>>   #define MASK_CBO_INVAL 0xfff07fff
>>   #define MATCH_CBO_ZERO 0x40200f
>>   #define MASK_CBO_ZERO 0xfff07fff
>> -/* Unprivileged Counter/Timers CSR addresses.  */
>> +/* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
>> +#define MATCH_VT_MASKC 0x607b
>> +#define MASK_VT_MASKC 0xfe00707f
>> +#define MATCH_VT_MASKCN 0x707b
>> +#define MASK_VT_MASKCN 0xfe00707f
>> +/* Privileged CSR addresses.  */
>> +#define CSR_USTATUS 0x0
>> +#define CSR_UIE 0x4
>> +#define CSR_UTVEC 0x5
>> +#define CSR_USCRATCH 0x40
>> +#define CSR_UEPC 0x41
>> +#define CSR_UCAUSE 0x42
>> +#define CSR_UTVAL 0x43
>> +#define CSR_UIP 0x44
> These N-ext CSRs should be removed since priv 1.12 spec, so it seems
> like they are added by accident here ;)
>
> I think it would be better to follow the rules in the PR for any
> RISC-V vendor extension
> (https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/17).
> So once the pr is approved and merged, I will say LGTM for this patch
> and am happy to support Ventana's vendor extension in the master
> branch.
We are happy to see there is a rules to support vendor extension.
If other vendor's have no question about this, we'd like to follow this 
rules.
>
> As for the t-head cache instruction, personally for me, it would be
> better to move the whole support from the integration branch to
> master, and keep the Alibaba's guys as the main author.  If they agree
> with the vendor rules in the PR above, and could help to rebase their
> patch, it would be great :)
Personally, I perfer to move the framework from the integration branch 
to master. This's the base for all vendor extension.
@nelson, As you mentioned before, there are some improvement to do. Do 
you have any plan?

>
> Thanks
> Nelson
>
>>   #define CSR_CYCLE 0xc00
>>   #define CSR_TIME 0xc01
>>   #define CSR_INSTRET 0xc02
>> @@ -2720,6 +2733,8 @@ DECLARE_INSN(hsv_b, MATCH_HSV_B, MASK_HSV_B)
>>   DECLARE_INSN(hsv_h, MATCH_HSV_H, MASK_HSV_H)
>>   DECLARE_INSN(hsv_w, MATCH_HSV_W, MASK_HSV_W)
>>   DECLARE_INSN(hsv_d, MATCH_HSV_D, MASK_HSV_D)
>> +DECLARE_INSN(vt_maskc, MATCH_VT_MASKC, MASK_VT_MASKC)
>> +DECLARE_INSN(vt_maskcn, MATCH_VT_MASKCN, MASK_VT_MASKCN)
>>   #endif /* DECLARE_INSN */
>>   #ifdef DECLARE_CSR
>>   /* Unprivileged Counter/Timers CSRs.  */
>> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
>> index b769769b4ec..3cbb68b5655 100644
>> --- a/include/opcode/riscv.h
>> +++ b/include/opcode/riscv.h
>> @@ -391,6 +391,7 @@ enum riscv_insn_class
>>     INSN_CLASS_ZICBOM,
>>     INSN_CLASS_ZICBOP,
>>     INSN_CLASS_ZICBOZ,
>> +  INSN_CLASS_XVENTANACONDOPS,
>>   };
>>
>>   /* This structure holds information for a particular instruction.  */
>> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
>> index 00108ff24ae..052209f6fe2 100644
>> --- a/opcodes/riscv-opc.c
>> +++ b/opcodes/riscv-opc.c
>> @@ -1762,6 +1762,10 @@ const struct riscv_opcode riscv_opcodes[] =
>>   {"hsv.w",       0, INSN_CLASS_I, "t,0(s)", MATCH_HSV_W, MASK_HSV_W, match_opcode, INSN_DREF|INSN_4_BYTE },
>>   {"hsv.d",      64, INSN_CLASS_I, "t,0(s)", MATCH_HSV_D, MASK_HSV_D, match_opcode, INSN_DREF|INSN_8_BYTE },
>>
>> +/* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
>> +{"vt.maskc",    0, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 },
>> +{"vt.maskcn",   0, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKCN, MASK_VT_MASKCN, match_opcode, 0 },
>> +
>>   /* Terminate the list.  */
>>   {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
>>   };
>> --
>> 2.35.1
>>

Re: [PATCH 1/2] RISC-V: Support XVentanaCondOps extension

[Palmer Dabbelt]

On Mon, 25 Apr 2022 05:15:32 PDT (-0700), philipp.tomsich@vrull.eu wrote:
> On Mon, 25 Apr 2022 at 11:54, Nelson Chu <nelson.chu@sifive.com> wrote:
>>
>> On Wed, Apr 20, 2022 at 10:56 PM Christoph Muellner
>> <cmuellner@gcc.gnu.org> wrote:
>> >
>> > From: Philipp Tomsich <philipp.tomsich@vrull.eu>
>> >
>> > Ventana Micro has published the specification for their
>> > XVentanaCondOps ("conditional ops") extension at
>> >   https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf
>> > which contains two new instructions
>> >   - vt.maskc
>> >   - vt.maskcn
>> > that can be used in constructing branchless sequences for
>> > various conditional-arithmetic, conditional-logical, and
>> > conditional-select operations.
>> >
>> > To support such vendor-defined instructions in the mainline binutils,
>> > this change also adds a riscv_supported_vendor_x_ext secondary
>> > dispatch table (but also keeps the behaviour of allowing any unknow
>> > X-extension to be specified in addition to the known ones from this
>> > table).
>> >
>> > As discussed, this change already includes the planned/agreed future
>> > requirements for X-extensions (which are likely to be captured in the
>> > riscv-toolchain-conventions repository):
>> >   - a public specification document is available (see above) and is
>> >     referenced from the gas-documentation
>> >   - the naming follows chapter 27 of the RISC-V ISA specification
>> >   - instructions are prefixed by a vendor-prefix (vt for Ventana)
>> >     to ensure that they neither conflict with future standard
>> >     extensions nor clash with other vendors
>> >
>> > bfd/ChangeLog:
>> >
>> >         * elfxx-riscv.c (riscv_get_default_ext_version): Add riscv_supported_vendor_x_ext.
>> >         (riscv_multi_subset_supports): Recognize INSN_CLASS_XVENTANACONDOPS.
>> >
>> > gas/ChangeLog:
>> >
>> >         * doc/c-riscv.texi: Add section to list custom extensions and
>> >           their documentation URLs.
>> >         * testsuite/gas/riscv/x-ventana-condops.d: New test.
>> >         * testsuite/gas/riscv/x-ventana-condops.s: New test.
>> >
>> > include/ChangeLog:
>> >
>> >         * opcode/riscv-opc.h Add vt.maskc and vt.maskcn.
>> >         * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_XVENTANACONDOPS.
>> >
>> > opcodes/ChangeLog:
>> >
>> >         * riscv-opc.c: Add vt.maskc and vt.maskcn.
>> >
>> > v2:
>> > - Rebase (no changes requested for v1; see
>> >   https://sourceware.org/pipermail/binutils/2022-January/119236.html)
>> >
>> > Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
>> > ---
>> >  bfd/elfxx-riscv.c                           | 13 +++++++++++--
>> >  gas/doc/c-riscv.texi                        | 20 ++++++++++++++++++++
>> >  gas/testsuite/gas/riscv/x-ventana-condops.d | 12 ++++++++++++
>> >  gas/testsuite/gas/riscv/x-ventana-condops.s |  4 ++++
>> >  include/opcode/riscv-opc.h                  | 17 ++++++++++++++++-
>> >  include/opcode/riscv.h                      |  1 +
>> >  opcodes/riscv-opc.c                         |  4 ++++
>> >  7 files changed, 68 insertions(+), 3 deletions(-)
>> >  create mode 100644 gas/testsuite/gas/riscv/x-ventana-condops.d
>> >  create mode 100644 gas/testsuite/gas/riscv/x-ventana-condops.s
>> >
>> > diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
>> > index cb2cc146c04..723b30ddbfc 100644
>> > --- a/bfd/elfxx-riscv.c
>> > +++ b/bfd/elfxx-riscv.c
>> > @@ -1237,6 +1237,13 @@ static struct riscv_supported_ext riscv_supported_std_zxm_ext[] =
>> >    {NULL, 0, 0, 0, 0}
>> >  };
>> >
>> > +static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
>> > +{
>> > +  /* XVentanaCondOps: https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf */
>> > +  {"xventanacondops",  ISA_SPEC_CLASS_DRAFT,   1, 0, 0 },
>> > +  {NULL, 0, 0, 0, 0}
>> > +};
>> > +
>> >  const struct riscv_supported_ext *riscv_all_supported_ext[] =
>> >  {
>> >    riscv_supported_std_ext,
>> > @@ -1244,6 +1251,7 @@ const struct riscv_supported_ext *riscv_all_supported_ext[] =
>> >    riscv_supported_std_s_ext,
>> >    riscv_supported_std_h_ext,
>> >    riscv_supported_std_zxm_ext,
>> > +  riscv_supported_vendor_x_ext,
>> >    NULL
>> >  };
>> >
>> > @@ -1504,8 +1512,7 @@ riscv_get_default_ext_version (enum riscv_spec_class *default_isa_spec,
>> >      case RV_ISA_CLASS_Z: table = riscv_supported_std_z_ext; break;
>> >      case RV_ISA_CLASS_S: table = riscv_supported_std_s_ext; break;
>> >      case RV_ISA_CLASS_H: table = riscv_supported_std_h_ext; break;
>> > -    case RV_ISA_CLASS_X:
>> > -      break;
>> > +    case RV_ISA_CLASS_X: table = riscv_supported_vendor_x_ext; break;
>> >      default:
>> >        table = riscv_supported_std_ext;
>> >      }
>> > @@ -2402,6 +2409,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
>> >               || riscv_subset_supports (rps, "zve32f"));
>> >      case INSN_CLASS_SVINVAL:
>> >        return riscv_subset_supports (rps, "svinval");
>> > +    case INSN_CLASS_XVENTANACONDOPS:
>> > +      return riscv_subset_supports (rps, "xventanacondops");
>> >      default:
>> >        rps->error_handler
>> >          (_("internal: unreachable INSN_CLASS_*"));
>> > diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
>> > index 21d867e9cf0..c75a5ad5a08 100644
>> > --- a/gas/doc/c-riscv.texi
>> > +++ b/gas/doc/c-riscv.texi
>> > @@ -20,6 +20,7 @@
>> >  * RISC-V-Modifiers::      RISC-V Assembler Modifiers
>> >  * RISC-V-Formats::        RISC-V Instruction Formats
>> >  * RISC-V-ATTRIBUTE::      RISC-V Object Attribute
>> > +* RISC-V-CustomExts::     RISC-V Custom (Vendor-Defined) Extensions
>> >  @end menu
>> >
>> >  @node RISC-V-Options
>> > @@ -692,3 +693,22 @@ the privileged specification.  It will report errors if object files of
>> >  different privileged specification versions are merged.
>> >
>> >  @end table
>> > +
>> > +@node RISC-V-CustomExts
>> > +@section RISC-V Custom (Vendor-Defined) Extensions
>> > +@cindex custom (vendor-defined) extensions, RISC-V
>> > +@cindex RISC-V custom (vendor-defined) extensions
>> > +
>> > +The following table lists the custom (vendor-defined) RISC-V
>> > +extensions supported and provides the location of their
>> > +publicly-released documentation:
>> > +
>> > +@table @r
>> > +@item XVentanaCondOps
>> > +XVentanaCondOps extension provides instructions for branchless
>> > +sequences that perform conditional arithmetic, conditional
>> > +bitwise-logic, and conditional select operations.
>> > +
>> > +It is documented at @url{https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf}.
>> > +
>> > +@end table
>> > diff --git a/gas/testsuite/gas/riscv/x-ventana-condops.d b/gas/testsuite/gas/riscv/x-ventana-condops.d
>> > new file mode 100644
>> > index 00000000000..cab0cc8dc12
>> > --- /dev/null
>> > +++ b/gas/testsuite/gas/riscv/x-ventana-condops.d
>> > @@ -0,0 +1,12 @@
>> > +#as: -march=rv64i_xventanacondops1p0
>> > +#source: x-ventana-condops.s
>> > +#objdump: -d
>> > +
>> > +.*:[   ]+file format .*
>> > +
>> > +
>> > +Disassembly of section .text:
>> > +
>> > +0+000 <target>:
>> > +[      ]+0:[   ]+00c5e57b[     ]+vt.maskc[     ]+a0,a1,a2
>> > +[      ]+4:[   ]+00e6f57b[     ]+vt.maskcn[    ]+a0,a3,a4
>> > diff --git a/gas/testsuite/gas/riscv/x-ventana-condops.s b/gas/testsuite/gas/riscv/x-ventana-condops.s
>> > new file mode 100644
>> > index 00000000000..562cf7384f7
>> > --- /dev/null
>> > +++ b/gas/testsuite/gas/riscv/x-ventana-condops.s
>> > @@ -0,0 +1,4 @@
>> > +target:
>> > +       vt.maskc        a0, a1, a2
>> > +       vt.maskcn       a0, a3, a4
>> > +
>> > diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
>> > index 3eea33a5dae..419ed538da9 100644
>> > --- a/include/opcode/riscv-opc.h
>> > +++ b/include/opcode/riscv-opc.h
>> > @@ -2045,7 +2045,20 @@
>> >  #define MASK_CBO_INVAL 0xfff07fff
>> >  #define MATCH_CBO_ZERO 0x40200f
>> >  #define MASK_CBO_ZERO 0xfff07fff
>> > -/* Unprivileged Counter/Timers CSR addresses.  */
>> > +/* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
>> > +#define MATCH_VT_MASKC 0x607b
>> > +#define MASK_VT_MASKC 0xfe00707f
>> > +#define MATCH_VT_MASKCN 0x707b
>> > +#define MASK_VT_MASKCN 0xfe00707f
>> > +/* Privileged CSR addresses.  */
>> > +#define CSR_USTATUS 0x0
>> > +#define CSR_UIE 0x4
>> > +#define CSR_UTVEC 0x5
>> > +#define CSR_USCRATCH 0x40
>> > +#define CSR_UEPC 0x41
>> > +#define CSR_UCAUSE 0x42
>> > +#define CSR_UTVAL 0x43
>> > +#define CSR_UIP 0x44
>>
>> These N-ext CSRs should be removed since priv 1.12 spec, so it seems
>> like they are added by accident here ;)
>
> As my original patch
> (https://sourceware.org/pipermail/binutils/2022-January/119236.html)
> didn't have these, I'd say that this must be an artifact from "a
> rebase gone wrong".  I guess this comes from the rebase mentioned in
> Christoph's v2 changelog above...
>
>> I think it would be better to follow the rules in the PR for an
>> RISC-V vendor extension
>> (https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/17).
>> So once the pr is approved and merged, I will say LGTM for this patch
>> and am happy to support Ventana's vendor extension in the master
>> branch.
>>
>> As for the t-head cache instruction, personally for me, it would be
>> better to move the whole support from the integration branch to
>> master, and keep the Alibaba's guys as the main author.  If they agree
>> with the vendor rules in the PR above, and could help to rebase their
>> patch, it would be great :)
>
> Which integration branch are you referring to?
> AFAIK, there is no patch adding cache instructions floating around
> (which is the reason why we created a cleanroom implementation for
> these).

<https://sourceware.org/pipermail/binutils/2021-September/117867.html>, 
which was pointed out on Patrick's version of the patch 
<https://sourceware.org/pipermail/binutils/2022-April/120453.html>.  
Generally we go with the patch that was posted first, I can understand 
if you guys felt like we stepped on your toes by writing the code when 
you said you were going to so I'm fine dropping Patrick's patch, but 
Lifang's was sent many months ago.

> We have buy-in on the vendor rules (after all, Chen Wei from T-Head is
> the vice-chair of the Software HC) from Alibaba, but you can expect
> things to take a while to propagate through into their own trees and
> documents.  Note that in a separate effort, I am talking to T-Head to
> have their instructions grouped into multiple, separate extensions
> (and hopefully also have their documentation updated to reflect this
> in the same structure as we're using in the RISC-V documentation
> elsewhere).

The patch already has these split up, at least a bit.  I definately 
agree that whatever we have should match the ISA manual, so if that 
means updating the ISA manual that works for me.

>
> Cheers,
> Philipp.
>
>
>> Thanks
>> Nelson
>>
>> >  #define CSR_CYCLE 0xc00
>> >  #define CSR_TIME 0xc01
>> >  #define CSR_INSTRET 0xc02
>> > @@ -2720,6 +2733,8 @@ DECLARE_INSN(hsv_b, MATCH_HSV_B, MASK_HSV_B)
>> >  DECLARE_INSN(hsv_h, MATCH_HSV_H, MASK_HSV_H)
>> >  DECLARE_INSN(hsv_w, MATCH_HSV_W, MASK_HSV_W)
>> >  DECLARE_INSN(hsv_d, MATCH_HSV_D, MASK_HSV_D)
>> > +DECLARE_INSN(vt_maskc, MATCH_VT_MASKC, MASK_VT_MASKC)
>> > +DECLARE_INSN(vt_maskcn, MATCH_VT_MASKCN, MASK_VT_MASKCN)
>> >  #endif /* DECLARE_INSN */
>> >  #ifdef DECLARE_CSR
>> >  /* Unprivileged Counter/Timers CSRs.  */
>> > diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
>> > index b769769b4ec..3cbb68b5655 100644
>> > --- a/include/opcode/riscv.h
>> > +++ b/include/opcode/riscv.h
>> > @@ -391,6 +391,7 @@ enum riscv_insn_class
>> >    INSN_CLASS_ZICBOM,
>> >    INSN_CLASS_ZICBOP,
>> >    INSN_CLASS_ZICBOZ,
>> > +  INSN_CLASS_XVENTANACONDOPS,
>> >  };
>> >
>> >  /* This structure holds information for a particular instruction.  */
>> > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
>> > index 00108ff24ae..052209f6fe2 100644
>> > --- a/opcodes/riscv-opc.c
>> > +++ b/opcodes/riscv-opc.c
>> > @@ -1762,6 +1762,10 @@ const struct riscv_opcode riscv_opcodes[] =
>> >  {"hsv.w",       0, INSN_CLASS_I, "t,0(s)", MATCH_HSV_W, MASK_HSV_W, match_opcode, INSN_DREF|INSN_4_BYTE },
>> >  {"hsv.d",      64, INSN_CLASS_I, "t,0(s)", MATCH_HSV_D, MASK_HSV_D, match_opcode, INSN_DREF|INSN_8_BYTE },
>> >
>> > +/* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
>> > +{"vt.maskc",    0, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 },
>> > +{"vt.maskcn",   0, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKCN, MASK_VT_MASKCN, match_opcode, 0 },
>> > +
>> >  /* Terminate the list.  */
>> >  {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
>> >  };
>> > --
>> > 2.35.1
>> >