* [RFC PATCH] RISC-V: Add Zawrs ISA extension support
@ 2022-04-26 21:12 Christoph Muellner
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From: Christoph Muellner @ 2022-04-26 21:12 UTC (permalink / raw)
To: binutils, Nelson Chu, Kito Cheng, Jim Wilson, Philipp Tomsich,
Palmer Dabbelt
Cc: Christoph Muellner, Christoph Muellner
This patch adds support for the Zawrs ISA extension.
Additionally to the "wrs rs1" instruction with the rs1 argument
(that must be 0 on RV32), this patch also adds a pseudo instruction
"wrs" without arguments, that serves as a short form for "wrs zero".
The specification can be found here:
https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc
Note, that the Zawrs extension is not frozen or ratified yet.
Therefore this patch is an RFC and not intended to get merged.
Signed-off-by: Christoph Muellner <cmuellner@gcc.gnu.org>
---
bfd/elfxx-riscv.c | 5 +++++
gas/testsuite/gas/riscv/zawrs-32-fail.d | 3 +++
gas/testsuite/gas/riscv/zawrs-32-fail.l | 2 ++
gas/testsuite/gas/riscv/zawrs-32-fail.s | 2 ++
gas/testsuite/gas/riscv/zawrs-32.d | 11 +++++++++++
gas/testsuite/gas/riscv/zawrs-32.s | 3 +++
gas/testsuite/gas/riscv/zawrs.d | 12 ++++++++++++
gas/testsuite/gas/riscv/zawrs.s | 4 ++++
include/opcode/riscv-opc.h | 4 ++++
include/opcode/riscv.h | 1 +
opcodes/riscv-opc.c | 11 +++++++++++
11 files changed, 58 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zawrs-32-fail.d
create mode 100644 gas/testsuite/gas/riscv/zawrs-32-fail.l
create mode 100644 gas/testsuite/gas/riscv/zawrs-32-fail.s
create mode 100644 gas/testsuite/gas/riscv/zawrs-32.d
create mode 100644 gas/testsuite/gas/riscv/zawrs-32.s
create mode 100644 gas/testsuite/gas/riscv/zawrs.d
create mode 100644 gas/testsuite/gas/riscv/zawrs.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index cb2cc146c04..af420a5f690 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1218,6 +1218,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zvl16384b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl32768b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl65536b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{NULL, 0, 0, 0, 0}
};
@@ -2319,6 +2320,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
{
case INSN_CLASS_I:
return riscv_subset_supports (rps, "i");
+ case INSN_CLASS_ZAWRS:
+ return riscv_subset_supports (rps, "zawrs");
case INSN_CLASS_ZICBOM:
return riscv_subset_supports (rps, "zicbom");
case INSN_CLASS_ZICBOP:
@@ -2420,6 +2423,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
{
case INSN_CLASS_I:
return "i";
+ case INSN_CLASS_ZAWRS:
+ return "zawrs";
case INSN_CLASS_ZICSR:
return "zicsr";
case INSN_CLASS_ZIFENCEI:
diff --git a/gas/testsuite/gas/riscv/zawrs-32-fail.d b/gas/testsuite/gas/riscv/zawrs-32-fail.d
new file mode 100644
index 00000000000..41ac2678b58
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zawrs-32-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_zawrs
+#source: zawrs-32-fail.s
+#error_output: zawrs-32-fail.l
diff --git a/gas/testsuite/gas/riscv/zawrs-32-fail.l b/gas/testsuite/gas/riscv/zawrs-32-fail.l
new file mode 100644
index 00000000000..92f6284bab6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zawrs-32-fail.l
@@ -0,0 +1,2 @@
+.*: Assembler messages:
+.*: Error: illegal operands `wrs a0'
diff --git a/gas/testsuite/gas/riscv/zawrs-32-fail.s b/gas/testsuite/gas/riscv/zawrs-32-fail.s
new file mode 100644
index 00000000000..0ad2b736471
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zawrs-32-fail.s
@@ -0,0 +1,2 @@
+target:
+ wrs a0
diff --git a/gas/testsuite/gas/riscv/zawrs-32.d b/gas/testsuite/gas/riscv/zawrs-32.d
new file mode 100644
index 00000000000..cc6e896c430
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zawrs-32.d
@@ -0,0 +1,11 @@
+#as: -march=rv32i_zawrs
+#source: zawrs-32.s
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+01000073[ ]+wrs[ ]+zero
+[ ]+[0-9a-f]+:[ ]+01000073[ ]+wrs[ ]+zero
diff --git a/gas/testsuite/gas/riscv/zawrs-32.s b/gas/testsuite/gas/riscv/zawrs-32.s
new file mode 100644
index 00000000000..a8db019338c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zawrs-32.s
@@ -0,0 +1,3 @@
+target:
+ wrs
+ wrs x0
diff --git a/gas/testsuite/gas/riscv/zawrs.d b/gas/testsuite/gas/riscv/zawrs.d
new file mode 100644
index 00000000000..2a45e8382f2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zawrs.d
@@ -0,0 +1,12 @@
+#as: -march=rv64i_zawrs
+#source: zawrs.s
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+01000073[ ]+wrs[ ]+zero
+[ ]+[0-9a-f]+:[ ]+01000073[ ]+wrs[ ]+zero
+[ ]+[0-9a-f]+:[ ]+01050073[ ]+wrs[ ]+a0
diff --git a/gas/testsuite/gas/riscv/zawrs.s b/gas/testsuite/gas/riscv/zawrs.s
new file mode 100644
index 00000000000..bc5c05f822a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zawrs.s
@@ -0,0 +1,4 @@
+target:
+ wrs
+ wrs x0
+ wrs a0
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 3eea33a5dae..2d886dd921e 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2045,6 +2045,9 @@
#define MASK_CBO_INVAL 0xfff07fff
#define MATCH_CBO_ZERO 0x40200f
#define MASK_CBO_ZERO 0xfff07fff
+/* Zawrs intruction. */
+#define MATCH_WRS 0x1000073
+#define MASK_WRS 0xfff07fff
/* Unprivileged Counter/Timers CSR addresses. */
#define CSR_CYCLE 0xc00
#define CSR_TIME 0xc01
@@ -2720,6 +2723,7 @@ DECLARE_INSN(hsv_b, MATCH_HSV_B, MASK_HSV_B)
DECLARE_INSN(hsv_h, MATCH_HSV_H, MASK_HSV_H)
DECLARE_INSN(hsv_w, MATCH_HSV_W, MASK_HSV_W)
DECLARE_INSN(hsv_d, MATCH_HSV_D, MASK_HSV_D)
+DECLARE_INSN(wrs, MATCH_WRS, MASK_WRS)
#endif /* DECLARE_INSN */
#ifdef DECLARE_CSR
/* Unprivileged Counter/Timers CSRs. */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index b769769b4ec..4abb4020f0b 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -391,6 +391,7 @@ enum riscv_insn_class
INSN_CLASS_ZICBOM,
INSN_CLASS_ZICBOP,
INSN_CLASS_ZICBOZ,
+ INSN_CLASS_ZAWRS,
};
/* This structure holds information for a particular instruction. */
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 00108ff24ae..73297231838 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -152,6 +152,12 @@ match_rs1_eq_rs2 (const struct riscv_opcode *op, insn_t insn)
return match_opcode (op, insn) && rs1 == rs2;
}
+static int
+match_rs1_zero (const struct riscv_opcode *op, insn_t insn)
+{
+ return match_opcode (op, insn) && ((insn & MASK_RS1) == 0);
+}
+
static int
match_rd_nonzero (const struct riscv_opcode *op, insn_t insn)
{
@@ -852,6 +858,11 @@ const struct riscv_opcode riscv_opcodes[] =
{"sfence.vma", 0, INSN_CLASS_I, "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
{"wfi", 0, INSN_CLASS_I, "", MATCH_WFI, MASK_WFI, match_opcode, 0 },
+/* Zawrs instruction. */
+{"wrs", 64, INSN_CLASS_ZAWRS, "s", MATCH_WRS, MASK_WRS, match_opcode, 0 },
+{"wrs", 32, INSN_CLASS_ZAWRS, "s", MATCH_WRS, MASK_WRS, match_rs1_zero, 0 },
+{"wrs", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS, MASK_WRS|MASK_RS1, match_opcode, INSN_ALIAS },
+
/* Zicbom and Zicboz instructions. */
{"cbo.clean", 0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_CLEAN, MASK_CBO_CLEAN, match_opcode, 0 },
{"cbo.flush", 0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_FLUSH, MASK_CBO_FLUSH, match_opcode, 0 },
--
2.35.3
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