From: Yoshinori Sato <ysato@users.sourceforge.jp>
To: binutils@sourceware.org
Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Subject: [PATCH] opcodes: SH fix bank register disassemble.
Date: Wed, 14 Sep 2022 11:44:04 +0900 [thread overview]
Message-ID: <20220914024404.7204-1-ysato@users.sourceforge.jp> (raw)
Bit7 of LDC Rm,Rn_BANK and STC Rm_BANK,Rn is always 1.
Since it is not confirmed that this is 1 now,
it was outputting incorrect code as a correct instruction.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
opcodes/sh-dis.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/opcodes/sh-dis.c b/opcodes/sh-dis.c
index 0e46cb6f4d9..6c8bd7b1cd7 100644
--- a/opcodes/sh-dis.c
+++ b/opcodes/sh-dis.c
@@ -645,6 +645,8 @@ print_insn_sh (bfd_vma memaddr, struct disassemble_info *info)
rm = (nibs[n] & 0x3);
break;
case REG_B:
+ if (!(nibs[n] & 0x08)) /* always 1*/
+ goto fail;
rb = nibs[n] & 0x07;
break;
case SDT_REG_N:
--
2.30.2
next reply other threads:[~2022-09-14 2:44 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-14 2:44 Yoshinori Sato [this message]
2022-09-22 11:41 ` Nick Clifton
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