[PATCH] RISC-V: Added SiFive custom cache control extensions.

[PATCH] RISC-V: Added SiFive custom cache control extensions.

[Nelson Chu]

From: Nelson Chu <nelson.chu@sifive.com>

I totally forgot this patch which was committed to the riscv integration
branch long time ago...  So cherry-pick it back to mainline with adding
the "sf." prefix for opcodes, according to the vendor public rule.

According to the chapter 10 of the following U74-MC manual:
https://sifive.cdn.prismic.io/sifive/6d9a2510-2632-44f3-adb9-d0430f139372_sifive_coreip_U74MC_AXI4_rtl_v19_08p2p0_release_manual.pdf

And the implementations of freedom-metal:
https://github.com/sifive/freedom-metal/blob/v201908-branch/src/cache.c

* Encodings:
31-25   24-20 19-15 14-12  11-7  6-0
FUNCT7  RS2   RS1   FUNCT3 RD    OPCODE
1111110 00000 xxxxx 000    00000 1110011 CFLUSH.D.L1
1111110 00010 xxxxx 000    00000 1110011 CDISCARD.D.L1
1111110 00001 00000 000    00000 1110011 CFLUSH.I.L1

* Extension names:
xsfcflushdlone:   sf.cflush.d.l1.
xsfcdiscarddlone: sf.cdiscard.d.l1.
xsfcflushilone:   sf.cflush.i.l1.

bfd/
    * elfxx-riscv.c (riscv_supported_vendor_x_ext): Added SiFive cache control
    extensions.
    (riscv_multi_subset_supports): Likewise.
    (riscv_multi_subset_supports_ext): Likewise.
gas/
    * testsuite/gas/riscv/x-sifive-cache.d: New testcase.
    * testsuite/gas/riscv/x-sifive-cache.s: Likewise.
include/
    * opcode/riscv-opc.h: Added encodings of SiFive cache control instructions.
    * opcode/riscv.h (enum riscv_insn_class): Added INSN_CLASS_XSF_CDISCARDDLONE,
    INSN_CLASS_XSF_CFLUSHDLONE and INSN_CLASS_XSF_CFLUSHILONE.
opcodes/
    * riscv-opc.c (riscv_opcodes): Added SiFive cache control instructions.
---
 bfd/elfxx-riscv.c                        | 15 +++++++++++++++
 gas/testsuite/gas/riscv/x-sifive-cache.d | 12 ++++++++++++
 gas/testsuite/gas/riscv/x-sifive-cache.s |  4 ++++
 include/opcode/riscv-opc.h               | 11 +++++++++++
 include/opcode/riscv.h                   |  3 +++
 opcodes/riscv-opc.c                      |  5 +++++
 6 files changed, 50 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/x-sifive-cache.d
 create mode 100644 gas/testsuite/gas/riscv/x-sifive-cache.s

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 94bff0e0388..74bd5b9dd9c 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1243,6 +1243,9 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
   {"xtheadmemidx",	ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadmempair",	ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadsync",	ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
+  {"xsfcdiscarddlone",	ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
+  {"xsfcflushdlone",	ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
+  {"xsfcflushilone",	ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {NULL, 0, 0, 0, 0}
 };
 
@@ -2434,6 +2437,12 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "xtheadmempair");
     case INSN_CLASS_XTHEADSYNC:
       return riscv_subset_supports (rps, "xtheadsync");
+    case INSN_CLASS_XSF_CDISCARDDLONE:
+      return riscv_subset_supports (rps, "xsfcdiscarddlone");
+    case INSN_CLASS_XSF_CFLUSHDLONE:
+      return riscv_subset_supports (rps, "xsfcflushdlone");
+    case INSN_CLASS_XSF_CFLUSHILONE:
+      return riscv_subset_supports (rps, "xsfcflushilone");
     default:
       rps->error_handler
         (_("internal: unreachable INSN_CLASS_*"));
@@ -2588,6 +2597,12 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return "xtheadmempair";
     case INSN_CLASS_XTHEADSYNC:
       return "xtheadsync";
+    case INSN_CLASS_XSF_CDISCARDDLONE:
+      return "xsfcdiscarddlone";
+    case INSN_CLASS_XSF_CFLUSHDLONE:
+      return "xsfcflushdlone";
+    case INSN_CLASS_XSF_CFLUSHILONE:
+      return "xsfcflushilone";
     default:
       rps->error_handler
         (_("internal: unreachable INSN_CLASS_*"));
diff --git a/gas/testsuite/gas/riscv/x-sifive-cache.d b/gas/testsuite/gas/riscv/x-sifive-cache.d
new file mode 100644
index 00000000000..ac19f3461ef
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-sifive-cache.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_xsfcdiscarddlone_xsfcflushdlone_xsfcflushilone
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+0:[ 	]+fc050073[ 	]+sf.cflush.d.l1[ 	]+a0
+[ 	]+4:[ 	]+fc250073[ 	]+sf.cdiscard.d.l1[ 	]+a0
+[ 	]+8:[ 	]+fc100073[ 	]+sf.cflush.i.l1
diff --git a/gas/testsuite/gas/riscv/x-sifive-cache.s b/gas/testsuite/gas/riscv/x-sifive-cache.s
new file mode 100644
index 00000000000..55ef9433eac
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-sifive-cache.s
@@ -0,0 +1,4 @@
+target:
+	sf.cflush.d.l1 x10
+	sf.cdiscard.d.l1 x10
+	sf.cflush.i.l1
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index e40592159cd..154094de0c3 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2332,6 +2332,13 @@
 #define MASK_TH_SYNC_IS 0xffffffff
 #define MATCH_TH_SYNC_S 0x0190000b
 #define MASK_TH_SYNC_S 0xffffffff
+/* Vendor-specific SiFive cache control instructions.  */
+#define MATCH_SF_CFLUSH_D_L1 0xfc000073
+#define MASK_SF_CFLUSH_D_L1 0xfff07fff
+#define MATCH_SF_CDISCARD_D_L1 0xfc200073
+#define MASK_SF_CDISCARD_D_L1 0xfff07fff
+#define MATCH_SF_CFLUSH_I_L1 0xfc100073
+#define MASK_SF_CFLUSH_I_L1 0xffffffff
 /* Unprivileged Counter/Timers CSR addresses.  */
 #define CSR_CYCLE 0xc00
 #define CSR_TIME 0xc01
@@ -3186,6 +3193,10 @@ DECLARE_INSN(th_sync, MATCH_TH_SYNC, MASK_TH_SYNC)
 DECLARE_INSN(th_sync_i, MATCH_TH_SYNC_I, MASK_TH_SYNC_I)
 DECLARE_INSN(th_sync_is, MATCH_TH_SYNC_IS, MASK_TH_SYNC_IS)
 DECLARE_INSN(th_sync_s, MATCH_TH_SYNC_S, MASK_TH_SYNC_S)
+/* Vendor-specific SiFive cache control instructions.  */
+DECLARE_INSN(sf_cflush_d_l1, MATCH_SF_CFLUSH_D_L1, MASK_SF_CFLUSH_D_L1)
+DECLARE_INSN(sf_cdiscard_d_l1, MATCH_SF_CDISCARD_D_L1, MASK_SF_CDISCARD_D_L1)
+DECLARE_INSN(sf_cflush_i_l1, MATCH_SF_CFLUSH_I_L1, MASK_SF_CFLUSH_I_L1)
 #endif /* DECLARE_INSN */
 #ifdef DECLARE_CSR
 /* Unprivileged Counter/Timers CSRs.  */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index dddabfdd415..8b8877ee2af 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -420,6 +420,9 @@ enum riscv_insn_class
   INSN_CLASS_XTHEADMEMIDX,
   INSN_CLASS_XTHEADMEMPAIR,
   INSN_CLASS_XTHEADSYNC,
+  INSN_CLASS_XSF_CDISCARDDLONE,
+  INSN_CLASS_XSF_CFLUSHDLONE,
+  INSN_CLASS_XSF_CFLUSHILONE,
 };
 
 /* This structure holds information for a particular instruction.  */
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 4029c1881b8..343ee839e30 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2001,6 +2001,11 @@ const struct riscv_opcode riscv_opcodes[] =
 {"th.sync.is",       0, INSN_CLASS_XTHEADSYNC,  "",   MATCH_TH_SYNC_IS,       MASK_TH_SYNC_IS,       match_opcode, 0},
 {"th.sync.s",        0, INSN_CLASS_XTHEADSYNC,  "",   MATCH_TH_SYNC_S,        MASK_TH_SYNC_S,        match_opcode, 0},
 
+/* Vendor-specific SiFive cache control instructions.  */
+{"sf.cflush.d.l1",   0, INSN_CLASS_XSF_CFLUSHDLONE,   "s", MATCH_SF_CFLUSH_D_L1, MASK_SF_CFLUSH_D_L1, match_opcode, 0 },
+{"sf.cdiscard.d.l1", 0, INSN_CLASS_XSF_CDISCARDDLONE, "s", MATCH_SF_CDISCARD_D_L1, MASK_SF_CDISCARD_D_L1, match_opcode, 0 },
+{"sf.cflush.i.l1",   0, INSN_CLASS_XSF_CFLUSHILONE,   "",  MATCH_SF_CFLUSH_I_L1, MASK_SF_CFLUSH_I_L1, match_opcode, 0 },
+
 /* Terminate the list.  */
 {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
 };
-- 
2.37.0 (Apple Git-136)