* [PATCH] RISC-V: Correction of machine registers mapping to dwarf registers
@ 2022-12-06 5:39 Xiao Zeng
0 siblings, 0 replies; only message in thread
From: Xiao Zeng @ 2022-12-06 5:39 UTC (permalink / raw)
To: binutils; +Cc: kito.cheng, palmer, nelson, Xiao Zeng
According to the riscv psabi, the mapping relationship between the
dwarf registers and the machine registers are as follows:
DWARF Number | Register Name | Description
0 - 31 | x0 - x31 | Integer Registers
32 - 63 | f0 - f31 | Floating-point Registers
* gdb/riscv-tdep.c (riscv_dwarf_reg_to_regnum): Correct mapping
boundary register.
---
gdb/riscv-tdep.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index 0a050b272ff..a298623b449 100644
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -3623,10 +3623,10 @@ riscv_add_reggroups (struct gdbarch *gdbarch)
static int
riscv_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
{
- if (reg < RISCV_DWARF_REGNUM_X31)
+ if (reg <= RISCV_DWARF_REGNUM_X31)
return RISCV_ZERO_REGNUM + (reg - RISCV_DWARF_REGNUM_X0);
- else if (reg < RISCV_DWARF_REGNUM_F31)
+ else if (reg <= RISCV_DWARF_REGNUM_F31)
return RISCV_FIRST_FP_REGNUM + (reg - RISCV_DWARF_REGNUM_F0);
else if (reg >= RISCV_DWARF_FIRST_CSR && reg <= RISCV_DWARF_LAST_CSR)
--
2.34.1
^ permalink raw reply [flat|nested] only message in thread
only message in thread, other threads:[~2022-12-06 5:39 UTC | newest]
Thread overview: (only message) (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-12-06 5:39 [PATCH] RISC-V: Correction of machine registers mapping to dwarf registers Xiao Zeng
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).