* [PATCH v2 0/5] LoongArch: colored disassembly and readability tweaks
@ 2022-12-07 13:31 WANG Xuerui
2022-12-07 13:31 ` [PATCH v2 1/5] opcodes/loongarch: remove unused code WANG Xuerui
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: WANG Xuerui @ 2022-12-07 13:31 UTC (permalink / raw)
To: binutils; +Cc: Chenghua Xu, Zhensong Liu, Xi Ruoyao, WANG Xuerui
From: WANG Xuerui <git@xen0n.name>
Hi,
This series implements colored output for LoongArch disassembly, and
some minor tweaks to the output so there is less clutter.
The previous version was sent in August but there was no reply, so I've
rebased and added the tweaks mentioned before, for consideration of
inclusion into binutils 2.40.
WANG Xuerui (5):
opcodes/loongarch: remove unused code
opcodes/loongarch: implement style support in the disassembler
opcodes/loongarch: style disassembled address offsets as such
opcodes/loongarch: do not print hex notation for signed immediates
opcodes/loongarch: print unrecognized instruction words with .insn
prefix
include/opcode/loongarch.h | 5 ---
opcodes/disassemble.c | 5 +++
opcodes/loongarch-dis.c | 88 ++++++++++++++------------------------
opcodes/loongarch-opc.c | 50 +++++++++++-----------
4 files changed, 62 insertions(+), 86 deletions(-)
--
2.38.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 1/5] opcodes/loongarch: remove unused code
2022-12-07 13:31 [PATCH v2 0/5] LoongArch: colored disassembly and readability tweaks WANG Xuerui
@ 2022-12-07 13:31 ` WANG Xuerui
2022-12-07 13:31 ` [PATCH v2 2/5] opcodes/loongarch: implement style support in the disassembler WANG Xuerui
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: WANG Xuerui @ 2022-12-07 13:31 UTC (permalink / raw)
To: binutils; +Cc: Chenghua Xu, Zhensong Liu, Xi Ruoyao, WANG Xuerui
From: WANG Xuerui <git@xen0n.name>
Remove some unused declarations and code.
---
include/opcode/loongarch.h | 5 -----
opcodes/loongarch-dis.c | 35 -----------------------------------
2 files changed, 40 deletions(-)
diff --git a/include/opcode/loongarch.h b/include/opcode/loongarch.h
index c3922348a56..448e5e0bbc4 100644
--- a/include/opcode/loongarch.h
+++ b/include/opcode/loongarch.h
@@ -172,11 +172,6 @@ dec2 : [1-9][0-9]?
extern void loongarch_eliminate_adjacent_repeat_char (char *dest, char c);
- extern int loongarch_parse_dis_options (const char *opts_in);
- extern void loongarch_disassemble_one (
- int64_t pc, insn_t insn,
- int (*fprintf_func) (void *stream, const char *format, ...), void *stream);
-
extern const char *const loongarch_r_normal_name[32];
extern const char *const loongarch_r_lp64_name[32];
extern const char *const loongarch_r_lp64_name1[32];
diff --git a/opcodes/loongarch-dis.c b/opcodes/loongarch-dis.c
index 9dcf989d0df..c7c95e9e90f 100644
--- a/opcodes/loongarch-dis.c
+++ b/opcodes/loongarch-dis.c
@@ -305,38 +305,3 @@ with the -M switch (multiple options should be separated by commas):\n"));
numeric Print numeric register names, rather than ABI names.\n"));
fprintf (stream, _("\n"));
}
-
-int
-loongarch_parse_dis_options (const char *opts_in)
-{
- return parse_loongarch_dis_options (opts_in);
-}
-
-static void
-my_print_address_func (bfd_vma addr, struct disassemble_info *dinfo)
-{
- dinfo->fprintf_func (dinfo->stream, "0x%llx", (long long) addr);
-}
-
-void
-loongarch_disassemble_one (int64_t pc, insn_t insn,
- int (*fprintf_func) (void *stream,
- const char *format, ...),
- void *stream)
-{
- static struct disassemble_info my_disinfo =
- {
- .print_address_func = my_print_address_func,
- };
- static int not_init_yet = 1;
- if (not_init_yet)
- {
- loongarch_parse_dis_options (NULL);
- not_init_yet = 0;
- }
-
- my_disinfo.fprintf_func = fprintf_func;
- my_disinfo.stream = stream;
- my_disinfo.target = pc;
- disassemble_one (insn, &my_disinfo);
-}
--
2.38.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 2/5] opcodes/loongarch: implement style support in the disassembler
2022-12-07 13:31 [PATCH v2 0/5] LoongArch: colored disassembly and readability tweaks WANG Xuerui
2022-12-07 13:31 ` [PATCH v2 1/5] opcodes/loongarch: remove unused code WANG Xuerui
@ 2022-12-07 13:31 ` WANG Xuerui
2022-12-07 13:31 ` [PATCH v2 3/5] opcodes/loongarch: style disassembled address offsets as such WANG Xuerui
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: WANG Xuerui @ 2022-12-07 13:31 UTC (permalink / raw)
To: binutils; +Cc: Chenghua Xu, Zhensong Liu, Xi Ruoyao, WANG Xuerui
From: WANG Xuerui <git@xen0n.name>
Update the LoongArch disassembler to supply style information to the
disassembler output. The output formatting remains unchanged.
---
opcodes/disassemble.c | 5 +++++
opcodes/loongarch-dis.c | 41 ++++++++++++++++++++++-------------------
2 files changed, 27 insertions(+), 19 deletions(-)
diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c
index b8e0bd14b51..f4adbe555ee 100644
--- a/opcodes/disassemble.c
+++ b/opcodes/disassemble.c
@@ -647,6 +647,11 @@ disassemble_init_for_target (struct disassemble_info * info)
info->skip_zeroes = 16;
break;
#endif
+#ifdef ARCH_loongarch
+ case bfd_arch_loongarch:
+ info->created_styled_output = true;
+ break;
+#endif
#ifdef ARCH_tic4x
case bfd_arch_tic4x:
info->skip_zeroes = 32;
diff --git a/opcodes/loongarch-dis.c b/opcodes/loongarch-dis.c
index c7c95e9e90f..84e4946545d 100644
--- a/opcodes/loongarch-dis.c
+++ b/opcodes/loongarch-dis.c
@@ -130,7 +130,7 @@ dis_one_arg (char esc1, char esc2, const char *bit_field,
if (esc1)
{
if (need_comma)
- info->fprintf_func (info->stream, ", ");
+ info->fprintf_styled_func (info->stream, dis_style_text, ", ");
need_comma = 1;
imm = loongarch_decode_imm (bit_field, insn, 1);
u_imm = loongarch_decode_imm (bit_field, insn, 0);
@@ -139,35 +139,38 @@ dis_one_arg (char esc1, char esc2, const char *bit_field,
switch (esc1)
{
case 'r':
- info->fprintf_func (info->stream, "%s", loongarch_r_disname[u_imm]);
+ info->fprintf_styled_func (info->stream, dis_style_register, "%s", loongarch_r_disname[u_imm]);
break;
case 'f':
- info->fprintf_func (info->stream, "%s", loongarch_f_disname[u_imm]);
+ info->fprintf_styled_func (info->stream, dis_style_register, "%s", loongarch_f_disname[u_imm]);
break;
case 'c':
switch (esc2)
{
case 'r':
- info->fprintf_func (info->stream, "%s", loongarch_cr_disname[u_imm]);
+ info->fprintf_styled_func (info->stream, dis_style_register, "%s", loongarch_cr_disname[u_imm]);
break;
default:
- info->fprintf_func (info->stream, "%s", loongarch_c_disname[u_imm]);
+ info->fprintf_styled_func (info->stream, dis_style_register, "%s", loongarch_c_disname[u_imm]);
}
break;
case 'v':
- info->fprintf_func (info->stream, "%s", loongarch_v_disname[u_imm]);
+ info->fprintf_styled_func (info->stream, dis_style_register, "%s", loongarch_v_disname[u_imm]);
break;
case 'x':
- info->fprintf_func (info->stream, "%s", loongarch_x_disname[u_imm]);
+ info->fprintf_styled_func (info->stream, dis_style_register, "%s", loongarch_x_disname[u_imm]);
break;
case 'u':
- info->fprintf_func (info->stream, "0x%x", u_imm);
+ info->fprintf_styled_func (info->stream, dis_style_immediate, "0x%x", u_imm);
break;
case 's':
if (imm == 0)
- info->fprintf_func (info->stream, "%d", imm);
+ info->fprintf_styled_func (info->stream, dis_style_immediate, "%d", imm);
else
- info->fprintf_func (info->stream, "%d(0x%x)", imm, u_imm);
+ {
+ info->fprintf_styled_func (info->stream, dis_style_immediate, "%d", imm);
+ info->fprintf_styled_func (info->stream, dis_style_text, "(0x%x)", u_imm);
+ }
switch (esc2)
{
case 'b':
@@ -221,32 +224,32 @@ disassemble_one (insn_t insn, struct disassemble_info *info)
for (i = 31; 0 <= i; i--)
{
if (t & insn)
- info->fprintf_func (info->stream, "1");
+ info->fprintf_styled_func (info->stream, dis_style_text, "1");
else
- info->fprintf_func (info->stream, "0");
+ info->fprintf_styled_func (info->stream, dis_style_text, "0");
if (have_space[i])
- info->fprintf_func (info->stream, " ");
+ info->fprintf_styled_func (info->stream, dis_style_text, " ");
t = t >> 1;
}
- info->fprintf_func (info->stream, "\t");
+ info->fprintf_styled_func (info->stream, dis_style_text, "\t");
#endif
if (!opc)
{
info->insn_type = dis_noninsn;
- info->fprintf_func (info->stream, "0x%08x", insn);
+ info->fprintf_styled_func (info->stream, dis_style_immediate, "0x%08x", insn);
return;
}
info->insn_type = dis_nonbranch;
- info->fprintf_func (info->stream, "%-12s", opc->name);
+ info->fprintf_styled_func (info->stream, dis_style_mnemonic, "%-12s", opc->name);
{
char *fake_args = xmalloc (strlen (opc->format) + 1);
const char *fake_arg_strs[MAX_ARG_NUM_PLUS_2];
strcpy (fake_args, opc->format);
if (0 < loongarch_split_args_by_comma (fake_args, fake_arg_strs))
- info->fprintf_func (info->stream, "\t");
+ info->fprintf_styled_func (info->stream, dis_style_text, "\t");
info->private_data = &insn;
loongarch_foreach_args (opc->format, fake_arg_strs, dis_one_arg, info);
free (fake_args);
@@ -254,11 +257,11 @@ disassemble_one (insn_t insn, struct disassemble_info *info)
if (info->insn_type == dis_branch || info->insn_type == dis_condbranch
/* Someother if we have extra info to print. */)
- info->fprintf_func (info->stream, "\t#");
+ info->fprintf_styled_func (info->stream, dis_style_comment_start, "\t#");
if (info->insn_type == dis_branch || info->insn_type == dis_condbranch)
{
- info->fprintf_func (info->stream, " ");
+ info->fprintf_styled_func (info->stream, dis_style_text, " ");
info->print_address_func (info->target, info);
}
}
--
2.38.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 3/5] opcodes/loongarch: style disassembled address offsets as such
2022-12-07 13:31 [PATCH v2 0/5] LoongArch: colored disassembly and readability tweaks WANG Xuerui
2022-12-07 13:31 ` [PATCH v2 1/5] opcodes/loongarch: remove unused code WANG Xuerui
2022-12-07 13:31 ` [PATCH v2 2/5] opcodes/loongarch: implement style support in the disassembler WANG Xuerui
@ 2022-12-07 13:31 ` WANG Xuerui
2022-12-07 13:31 ` [PATCH v2 4/5] opcodes/loongarch: do not print hex notation for signed immediates WANG Xuerui
2022-12-07 13:31 ` [PATCH v2 5/5] opcodes/loongarch: print unrecognized instruction words with .insn prefix WANG Xuerui
4 siblings, 0 replies; 6+ messages in thread
From: WANG Xuerui @ 2022-12-07 13:31 UTC (permalink / raw)
To: binutils; +Cc: Chenghua Xu, Zhensong Liu, Xi Ruoyao, WANG Xuerui
From: WANG Xuerui <git@xen0n.name>
---
opcodes/loongarch-dis.c | 19 +++++++++++++---
opcodes/loongarch-opc.c | 50 ++++++++++++++++++++---------------------
2 files changed, 41 insertions(+), 28 deletions(-)
diff --git a/opcodes/loongarch-dis.c b/opcodes/loongarch-dis.c
index 84e4946545d..7ee18e14dd2 100644
--- a/opcodes/loongarch-dis.c
+++ b/opcodes/loongarch-dis.c
@@ -126,6 +126,7 @@ dis_one_arg (char esc1, char esc2, const char *bit_field,
struct disassemble_info *info = context;
insn_t insn = *(insn_t *) info->private_data;
int32_t imm, u_imm;
+ enum disassembler_style style;
if (esc1)
{
@@ -161,14 +162,26 @@ dis_one_arg (char esc1, char esc2, const char *bit_field,
info->fprintf_styled_func (info->stream, dis_style_register, "%s", loongarch_x_disname[u_imm]);
break;
case 'u':
- info->fprintf_styled_func (info->stream, dis_style_immediate, "0x%x", u_imm);
+ style = esc2 == 'o' ? dis_style_address_offset : dis_style_immediate;
+ info->fprintf_styled_func (info->stream, style, "0x%x", u_imm);
break;
case 's':
+ switch (esc2)
+ {
+ case 'b':
+ case 'o':
+ /* Both represent address offsets. */
+ style = dis_style_address_offset;
+ break;
+ default:
+ style = dis_style_immediate;
+ break;
+ }
if (imm == 0)
- info->fprintf_styled_func (info->stream, dis_style_immediate, "%d", imm);
+ info->fprintf_styled_func (info->stream, style, "%d", imm);
else
{
- info->fprintf_styled_func (info->stream, dis_style_immediate, "%d", imm);
+ info->fprintf_styled_func (info->stream, style, "%d", imm);
info->fprintf_styled_func (info->stream, dis_style_text, "(0x%x)", u_imm);
}
switch (esc2)
diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c
index 1b510048c29..2dc2fec5c86 100644
--- a/opcodes/loongarch-opc.c
+++ b/opcodes/loongarch-opc.c
@@ -645,26 +645,26 @@ static struct loongarch_opcode loongarch_4opt_double_float_opcodes[] =
static struct loongarch_opcode loongarch_load_store_opcodes[] =
{
/* match, mask, name, format, macro, include, exclude, pinfo. */
- { 0x20000000, 0xff000000, "ll.w", "r0:5,r5:5,s10:14<<2", 0, 0, 0, 0 },
- { 0x21000000, 0xff000000, "sc.w", "r0:5,r5:5,s10:14<<2", 0, 0, 0, 0 },
- { 0x22000000, 0xff000000, "ll.d", "r0:5,r5:5,s10:14<<2", 0, 0, 0, 0 },
- { 0x23000000, 0xff000000, "sc.d", "r0:5,r5:5,s10:14<<2", 0, 0, 0, 0 },
- { 0x24000000, 0xff000000, "ldptr.w", "r0:5,r5:5,s10:14<<2", 0, 0, 0, 0 },
- { 0x25000000, 0xff000000, "stptr.w", "r0:5,r5:5,s10:14<<2", 0, 0, 0, 0 },
- { 0x26000000, 0xff000000, "ldptr.d", "r0:5,r5:5,s10:14<<2", 0, 0, 0, 0 },
- { 0x27000000, 0xff000000, "stptr.d", "r0:5,r5:5,s10:14<<2", 0, 0, 0, 0 },
- { 0x28000000, 0xffc00000, "ld.b", "r0:5,r5:5,s10:12", 0, 0, 0, 0 },
- { 0x28400000, 0xffc00000, "ld.h", "r0:5,r5:5,s10:12", 0, 0, 0, 0 },
- { 0x28800000, 0xffc00000, "ld.w", "r0:5,r5:5,s10:12", 0, 0, 0, 0 },
- { 0x28c00000, 0xffc00000, "ld.d", "r0:5,r5:5,s10:12", 0, 0, 0, 0 },
- { 0x29000000, 0xffc00000, "st.b", "r0:5,r5:5,s10:12", 0, 0, 0, 0 },
- { 0x29400000, 0xffc00000, "st.h", "r0:5,r5:5,s10:12", 0, 0, 0, 0 },
- { 0x29800000, 0xffc00000, "st.w", "r0:5,r5:5,s10:12", 0, 0, 0, 0 },
- { 0x29c00000, 0xffc00000, "st.d", "r0:5,r5:5,s10:12", 0, 0, 0, 0 },
- { 0x2a000000, 0xffc00000, "ld.bu", "r0:5,r5:5,s10:12", 0, 0, 0, 0 },
- { 0x2a400000, 0xffc00000, "ld.hu", "r0:5,r5:5,s10:12", 0, 0, 0, 0 },
- { 0x2a800000, 0xffc00000, "ld.wu", "r0:5,r5:5,s10:12", 0, 0, 0, 0 },
- { 0x2ac00000, 0xffc00000, "preld", "u0:5,r5:5,s10:12", 0, 0, 0, 0 },
+ { 0x20000000, 0xff000000, "ll.w", "r0:5,r5:5,so10:14<<2", 0, 0, 0, 0 },
+ { 0x21000000, 0xff000000, "sc.w", "r0:5,r5:5,so10:14<<2", 0, 0, 0, 0 },
+ { 0x22000000, 0xff000000, "ll.d", "r0:5,r5:5,so10:14<<2", 0, 0, 0, 0 },
+ { 0x23000000, 0xff000000, "sc.d", "r0:5,r5:5,so10:14<<2", 0, 0, 0, 0 },
+ { 0x24000000, 0xff000000, "ldptr.w", "r0:5,r5:5,so10:14<<2", 0, 0, 0, 0 },
+ { 0x25000000, 0xff000000, "stptr.w", "r0:5,r5:5,so10:14<<2", 0, 0, 0, 0 },
+ { 0x26000000, 0xff000000, "ldptr.d", "r0:5,r5:5,so10:14<<2", 0, 0, 0, 0 },
+ { 0x27000000, 0xff000000, "stptr.d", "r0:5,r5:5,so10:14<<2", 0, 0, 0, 0 },
+ { 0x28000000, 0xffc00000, "ld.b", "r0:5,r5:5,so10:12", 0, 0, 0, 0 },
+ { 0x28400000, 0xffc00000, "ld.h", "r0:5,r5:5,so10:12", 0, 0, 0, 0 },
+ { 0x28800000, 0xffc00000, "ld.w", "r0:5,r5:5,so10:12", 0, 0, 0, 0 },
+ { 0x28c00000, 0xffc00000, "ld.d", "r0:5,r5:5,so10:12", 0, 0, 0, 0 },
+ { 0x29000000, 0xffc00000, "st.b", "r0:5,r5:5,so10:12", 0, 0, 0, 0 },
+ { 0x29400000, 0xffc00000, "st.h", "r0:5,r5:5,so10:12", 0, 0, 0, 0 },
+ { 0x29800000, 0xffc00000, "st.w", "r0:5,r5:5,so10:12", 0, 0, 0, 0 },
+ { 0x29c00000, 0xffc00000, "st.d", "r0:5,r5:5,so10:12", 0, 0, 0, 0 },
+ { 0x2a000000, 0xffc00000, "ld.bu", "r0:5,r5:5,so10:12", 0, 0, 0, 0 },
+ { 0x2a400000, 0xffc00000, "ld.hu", "r0:5,r5:5,so10:12", 0, 0, 0, 0 },
+ { 0x2a800000, 0xffc00000, "ld.wu", "r0:5,r5:5,so10:12", 0, 0, 0, 0 },
+ { 0x2ac00000, 0xffc00000, "preld", "u0:5,r5:5,so10:12", 0, 0, 0, 0 },
{ 0x38000000, 0xffff8000, "ldx.b", "r0:5,r5:5,r10:5", 0, 0, 0, 0 },
{ 0x38040000, 0xffff8000, "ldx.h", "r0:5,r5:5,r10:5", 0, 0, 0, 0 },
{ 0x38080000, 0xffff8000, "ldx.w", "r0:5,r5:5,r10:5", 0, 0, 0, 0 },
@@ -773,8 +773,8 @@ static struct loongarch_opcode loongarch_load_store_opcodes[] =
static struct loongarch_opcode loongarch_single_float_load_store_opcodes[] =
{
/* match, mask, name, format, macro, include, exclude, pinfo. */
- { 0x2b000000, 0xffc00000, "fld.s", "f0:5,r5:5,s10:12", 0, 0, 0, 0 },
- { 0x2b400000, 0xffc00000, "fst.s", "f0:5,r5:5,s10:12", 0, 0, 0, 0 },
+ { 0x2b000000, 0xffc00000, "fld.s", "f0:5,r5:5,so10:12", 0, 0, 0, 0 },
+ { 0x2b400000, 0xffc00000, "fst.s", "f0:5,r5:5,so10:12", 0, 0, 0, 0 },
{ 0x38300000, 0xffff8000, "fldx.s", "f0:5,r5:5,r10:5", 0, &LARCH_opts.ase_lp64, 0, 0 },
{ 0x38380000, 0xffff8000, "fstx.s", "f0:5,r5:5,r10:5", 0, &LARCH_opts.ase_lp64, 0, 0 },
{ 0x38740000, 0xffff8000, "fldgt.s", "f0:5,r5:5,r10:5", 0, &LARCH_opts.ase_lp64, 0, 0 },
@@ -787,8 +787,8 @@ static struct loongarch_opcode loongarch_single_float_load_store_opcodes[] =
static struct loongarch_opcode loongarch_double_float_load_store_opcodes[] =
{
/* match, mask, name, format, macro, include, exclude, pinfo. */
- { 0x2b800000, 0xffc00000, "fld.d", "f0:5,r5:5,s10:12", 0, 0, 0, 0 },
- { 0x2bc00000, 0xffc00000, "fst.d", "f0:5,r5:5,s10:12", 0, 0, 0, 0 },
+ { 0x2b800000, 0xffc00000, "fld.d", "f0:5,r5:5,so10:12", 0, 0, 0, 0 },
+ { 0x2bc00000, 0xffc00000, "fst.d", "f0:5,r5:5,so10:12", 0, 0, 0, 0 },
{ 0x38340000, 0xffff8000, "fldx.d", "f0:5,r5:5,r10:5", 0, &LARCH_opts.ase_lp64, 0, 0 },
{ 0x383c0000, 0xffff8000, "fstx.d", "f0:5,r5:5,r10:5", 0, &LARCH_opts.ase_lp64, 0, 0 },
{ 0x38748000, 0xffff8000, "fldgt.d", "f0:5,r5:5,r10:5", 0, &LARCH_opts.ase_lp64, 0, 0 },
@@ -814,7 +814,7 @@ static struct loongarch_opcode loongarch_jmp_opcodes[] =
{ 0x40000000, 0xfc000000, "beqz", "r5:5,sb0:5|10:16<<2", 0, 0, 0, 0 },
{ 0x0, 0x0, "bnez", "r,la", "bnez %1,%%b21(%2)", 0, 0, 0 },
{ 0x44000000, 0xfc000000, "bnez", "r5:5,sb0:5|10:16<<2", 0, 0, 0, 0 },
- { 0x4c000000, 0xfc000000, "jirl", "r0:5,r5:5,s10:16<<2", 0, 0, 0, 0 },
+ { 0x4c000000, 0xfc000000, "jirl", "r0:5,r5:5,so10:16<<2", 0, 0, 0, 0 },
{ 0x0, 0x0, "b", "la", "b %%b26(%1)", 0, 0, 0 },
{ 0x50000000, 0xfc000000, "b", "sb0:10|10:16<<2", 0, 0, 0, 0 },
{ 0x0, 0x0, "bl", "la", "bl %%b26(%1)", 0, 0, 0 },
--
2.38.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 4/5] opcodes/loongarch: do not print hex notation for signed immediates
2022-12-07 13:31 [PATCH v2 0/5] LoongArch: colored disassembly and readability tweaks WANG Xuerui
` (2 preceding siblings ...)
2022-12-07 13:31 ` [PATCH v2 3/5] opcodes/loongarch: style disassembled address offsets as such WANG Xuerui
@ 2022-12-07 13:31 ` WANG Xuerui
2022-12-07 13:31 ` [PATCH v2 5/5] opcodes/loongarch: print unrecognized instruction words with .insn prefix WANG Xuerui
4 siblings, 0 replies; 6+ messages in thread
From: WANG Xuerui @ 2022-12-07 13:31 UTC (permalink / raw)
To: binutils; +Cc: Chenghua Xu, Zhensong Liu, Xi Ruoyao, WANG Xuerui
From: WANG Xuerui <git@xen0n.name>
---
opcodes/loongarch-dis.c | 8 +-------
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/opcodes/loongarch-dis.c b/opcodes/loongarch-dis.c
index 7ee18e14dd2..164069b2ede 100644
--- a/opcodes/loongarch-dis.c
+++ b/opcodes/loongarch-dis.c
@@ -177,13 +177,7 @@ dis_one_arg (char esc1, char esc2, const char *bit_field,
style = dis_style_immediate;
break;
}
- if (imm == 0)
- info->fprintf_styled_func (info->stream, style, "%d", imm);
- else
- {
- info->fprintf_styled_func (info->stream, style, "%d", imm);
- info->fprintf_styled_func (info->stream, dis_style_text, "(0x%x)", u_imm);
- }
+ info->fprintf_styled_func (info->stream, style, "%d", imm);
switch (esc2)
{
case 'b':
--
2.38.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 5/5] opcodes/loongarch: print unrecognized instruction words with .insn prefix
2022-12-07 13:31 [PATCH v2 0/5] LoongArch: colored disassembly and readability tweaks WANG Xuerui
` (3 preceding siblings ...)
2022-12-07 13:31 ` [PATCH v2 4/5] opcodes/loongarch: do not print hex notation for signed immediates WANG Xuerui
@ 2022-12-07 13:31 ` WANG Xuerui
4 siblings, 0 replies; 6+ messages in thread
From: WANG Xuerui @ 2022-12-07 13:31 UTC (permalink / raw)
To: binutils; +Cc: Chenghua Xu, Zhensong Liu, Xi Ruoyao, WANG Xuerui
From: WANG Xuerui <git@xen0n.name>
---
opcodes/loongarch-dis.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/opcodes/loongarch-dis.c b/opcodes/loongarch-dis.c
index 164069b2ede..e4e52408490 100644
--- a/opcodes/loongarch-dis.c
+++ b/opcodes/loongarch-dis.c
@@ -244,6 +244,7 @@ disassemble_one (insn_t insn, struct disassemble_info *info)
if (!opc)
{
info->insn_type = dis_noninsn;
+ info->fprintf_styled_func (info->stream, dis_style_assembler_directive, ".insn\t\t");
info->fprintf_styled_func (info->stream, dis_style_immediate, "0x%08x", insn);
return;
}
--
2.38.1
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-12-07 13:32 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-12-07 13:31 [PATCH v2 0/5] LoongArch: colored disassembly and readability tweaks WANG Xuerui
2022-12-07 13:31 ` [PATCH v2 1/5] opcodes/loongarch: remove unused code WANG Xuerui
2022-12-07 13:31 ` [PATCH v2 2/5] opcodes/loongarch: implement style support in the disassembler WANG Xuerui
2022-12-07 13:31 ` [PATCH v2 3/5] opcodes/loongarch: style disassembled address offsets as such WANG Xuerui
2022-12-07 13:31 ` [PATCH v2 4/5] opcodes/loongarch: do not print hex notation for signed immediates WANG Xuerui
2022-12-07 13:31 ` [PATCH v2 5/5] opcodes/loongarch: print unrecognized instruction words with .insn prefix WANG Xuerui
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