From: Nelson Chu <nelson@rivosinc.com>
To: binutils@sourceware.org, jim.wilson.gcc@gmail.com,
palmer@dabbelt.com, kito.cheng@sifive.com
Cc: nelson@rivosinc.com
Subject: [PATCH 1/2] RISC-V: Relax R_RISCV_[PCREL_]LO12_I/S to R_RISCV_GPREL_I/S for undefined weak.
Date: Fri, 21 Apr 2023 16:28:38 +0800 [thread overview]
Message-ID: <20230421082839.41542-1-nelson@rivosinc.com> (raw)
bfd/
*elfnn-riscv.c (_bfd_riscv_relax_lui): For undefined weak symbol,
just relax the R_RISCV_LO12_I/S to R_RISCV_GPREL_I/S, and then don't
update the rs1 to zero until relocate_section.
(_bfd_riscv_relax_pc): Likewise, but for R_RISCV_PCREL_LO12_I/S.
---
bfd/elfnn-riscv.c | 55 ++++++-----------------------------------------
1 file changed, 6 insertions(+), 49 deletions(-)
diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
index e90e36b58bb..499f51ee857 100644
--- a/bfd/elfnn-riscv.c
+++ b/bfd/elfnn-riscv.c
@@ -4552,27 +4552,11 @@ _bfd_riscv_relax_lui (bfd *abfd,
switch (ELFNN_R_TYPE (rel->r_info))
{
case R_RISCV_LO12_I:
- if (undefined_weak)
- {
- /* Change the RS1 to zero. */
- bfd_vma insn = bfd_getl32 (contents + rel->r_offset);
- insn &= ~(OP_MASK_RS1 << OP_SH_RS1);
- bfd_putl32 (insn, contents + rel->r_offset);
- }
- else
- rel->r_info = ELFNN_R_INFO (sym, R_RISCV_GPREL_I);
+ rel->r_info = ELFNN_R_INFO (sym, R_RISCV_GPREL_I);
return true;
case R_RISCV_LO12_S:
- if (undefined_weak)
- {
- /* Change the RS1 to zero. */
- bfd_vma insn = bfd_getl32 (contents + rel->r_offset);
- insn &= ~(OP_MASK_RS1 << OP_SH_RS1);
- bfd_putl32 (insn, contents + rel->r_offset);
- }
- else
- rel->r_info = ELFNN_R_INFO (sym, R_RISCV_GPREL_S);
+ rel->r_info = ELFNN_R_INFO (sym, R_RISCV_GPREL_S);
return true;
case R_RISCV_HI20:
@@ -4737,7 +4721,6 @@ _bfd_riscv_relax_pc (bfd *abfd ATTRIBUTE_UNUSED,
bool undefined_weak)
{
struct riscv_elf_link_hash_table *htab = riscv_elf_hash_table (link_info);
- bfd_byte *contents = elf_section_data (sec)->this_hdr.contents;
bfd_vma gp = riscv_global_pointer_value (link_info);
BFD_ASSERT (rel->r_offset + 4 <= sec->size);
@@ -4830,39 +4813,13 @@ _bfd_riscv_relax_pc (bfd *abfd ATTRIBUTE_UNUSED,
switch (ELFNN_R_TYPE (rel->r_info))
{
case R_RISCV_PCREL_LO12_I:
- if (undefined_weak)
- {
- /* Change the RS1 to zero, and then modify the relocation
- type to R_RISCV_LO12_I. */
- bfd_vma insn = bfd_getl32 (contents + rel->r_offset);
- insn &= ~(OP_MASK_RS1 << OP_SH_RS1);
- bfd_putl32 (insn, contents + rel->r_offset);
- rel->r_info = ELFNN_R_INFO (sym, R_RISCV_LO12_I);
- rel->r_addend = hi_reloc.hi_addend;
- }
- else
- {
- rel->r_info = ELFNN_R_INFO (sym, R_RISCV_GPREL_I);
- rel->r_addend += hi_reloc.hi_addend;
- }
+ rel->r_info = ELFNN_R_INFO (sym, R_RISCV_GPREL_I);
+ rel->r_addend += hi_reloc.hi_addend;
return true;
case R_RISCV_PCREL_LO12_S:
- if (undefined_weak)
- {
- /* Change the RS1 to zero, and then modify the relocation
- type to R_RISCV_LO12_S. */
- bfd_vma insn = bfd_getl32 (contents + rel->r_offset);
- insn &= ~(OP_MASK_RS1 << OP_SH_RS1);
- bfd_putl32 (insn, contents + rel->r_offset);
- rel->r_info = ELFNN_R_INFO (sym, R_RISCV_LO12_S);
- rel->r_addend = hi_reloc.hi_addend;
- }
- else
- {
- rel->r_info = ELFNN_R_INFO (sym, R_RISCV_GPREL_S);
- rel->r_addend += hi_reloc.hi_addend;
- }
+ rel->r_info = ELFNN_R_INFO (sym, R_RISCV_GPREL_S);
+ rel->r_addend += hi_reloc.hi_addend;
return true;
case R_RISCV_PCREL_HI20:
--
2.39.2 (Apple Git-143)
next reply other threads:[~2023-04-21 8:28 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-21 8:28 Nelson Chu [this message]
2023-04-21 8:28 ` [PATCH 2/2] RISC-V: Enable x0 base relaxation for relax_pc even if --no-relax-gp Nelson Chu
2023-04-28 6:29 ` Nelson Chu
2023-04-28 7:09 ` Fangrui Song
2023-04-28 7:14 ` Kito Cheng
2023-04-28 6:28 ` [PATCH 1/2] RISC-V: Relax R_RISCV_[PCREL_]LO12_I/S to R_RISCV_GPREL_I/S for undefined weak Nelson Chu
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