From: Nelson Chu <nelson@rivosinc.com>
To: binutils@sourceware.org, jim.wilson.gcc@gmail.com,
palmer@dabbelt.com, kito.cheng@sifive.com
Subject: Re: [PATCH 2/2] RISC-V: Enable x0 base relaxation for relax_pc even if --no-relax-gp.
Date: Fri, 28 Apr 2023 14:29:54 +0800 [thread overview]
Message-ID: <CAPpQWtDs4RO2untFUvOsAizrO42j7HWUPmNwt6WMv2wyAuCEPg@mail.gmail.com> (raw)
In-Reply-To: <20230421082839.41542-2-nelson@rivosinc.com>
[-- Attachment #1: Type: text/plain, Size: 1928 bytes --]
Committed, thanks.
Nelson
On Fri, Apr 21, 2023 at 4:28 PM Nelson Chu <nelson@rivosinc.com> wrote:
> Let --no-relax-gp only disable the gp relaxation for lui and pcrel
> relaxations, since x0 base and gp relaxations are different optimizations
> in fact, but just use the same function to handle.
>
> bfd/
> * elfnn-riscv.c (_bfd_riscv_relax_pc): Like _bfd_riscv_relax_lui,
> set gp to zero when --no-relax-gp, then we should still keep the
> x0 base relaxation.
> (_bfd_riscv_relax_section): Enable _bfd_riscv_relax_pc when
> --no-relax-gp, we will disable the gp relaxation in the
> _bfd_riscv_relax_pc.
> ---
> bfd/elfnn-riscv.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
> index 499f51ee857..77a732b6a08 100644
> --- a/bfd/elfnn-riscv.c
> +++ b/bfd/elfnn-riscv.c
> @@ -4721,7 +4721,9 @@ _bfd_riscv_relax_pc (bfd *abfd ATTRIBUTE_UNUSED,
> bool undefined_weak)
> {
> struct riscv_elf_link_hash_table *htab = riscv_elf_hash_table
> (link_info);
> - bfd_vma gp = riscv_global_pointer_value (link_info);
> + bfd_vma gp = htab->params->relax_gp
> + ? riscv_global_pointer_value (link_info)
> + : 0;
>
> BFD_ASSERT (rel->r_offset + 4 <= sec->size);
>
> @@ -4942,7 +4944,7 @@ _bfd_riscv_relax_section (bfd *abfd, asection *sec,
> || type == R_RISCV_TPREL_LO12_I
> || type == R_RISCV_TPREL_LO12_S)
> relax_func = _bfd_riscv_relax_tls_le;
> - else if (!bfd_link_pic (info) && htab->params->relax_gp
> + else if (!bfd_link_pic (info)
> && (type == R_RISCV_PCREL_HI20
> || type == R_RISCV_PCREL_LO12_I
> || type == R_RISCV_PCREL_LO12_S))
> --
> 2.39.2 (Apple Git-143)
>
>
next prev parent reply other threads:[~2023-04-28 6:30 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-21 8:28 [PATCH 1/2] RISC-V: Relax R_RISCV_[PCREL_]LO12_I/S to R_RISCV_GPREL_I/S for undefined weak Nelson Chu
2023-04-21 8:28 ` [PATCH 2/2] RISC-V: Enable x0 base relaxation for relax_pc even if --no-relax-gp Nelson Chu
2023-04-28 6:29 ` Nelson Chu [this message]
2023-04-28 7:09 ` Fangrui Song
2023-04-28 7:14 ` Kito Cheng
2023-04-28 6:28 ` [PATCH 1/2] RISC-V: Relax R_RISCV_[PCREL_]LO12_I/S to R_RISCV_GPREL_I/S for undefined weak Nelson Chu
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