From: Li Xu <xuli1@eswincomputing.com>
To: binutils@sourceware.org
Cc: kito.cheng@gmail.com, palmer@dabbelt.com,
Li Xu <xuli1@eswincomputing.com>
Subject: [PATCH] RISC-V: Warn in AS if vsew/vlmul/vtype is reserved.
Date: Thu, 18 May 2023 06:59:50 +0000 [thread overview]
Message-ID: <20230518065950.6166-1-xuli1@eswincomputing.com> (raw)
Consider the following case:
vsetvli a0, a1, 0x4 # unrecognized vlmul
vsetvli a0, a1, 0x20 # unrecognized vsew
vsetvli a0, a1, 0x700 # unrecognized vtype
The current AS doesn't have any hints, so I think
it's better to give a warning.
After this patch:
test.s: Assembler messages:
test.s:1: Warning: The vtype encoding of vlmul = 0x4 is reserved.
test.s:2: Warning: The vtype encoding of vsew = 0x4 is reserved.
test.s:3: Warning: The vtype encoding of 0x700 is reserved.
gas/ChangeLog:
* config/tc-riscv.c (my_getVsetvliExpression): Warn if vsew/vlmul/vtype is reserved.
* testsuite/gas/riscv/vector-insns.d: move vsetvl to new file.
* testsuite/gas/riscv/vector-insns.s: Ditto.
* testsuite/gas/riscv/vector-insns-vsetvl.d: New test.
* testsuite/gas/riscv/vector-insns-vsetvl.s: New test.
* testsuite/gas/riscv/vector-insns-warning.l: New test.
---
gas/config/tc-riscv.c | 10 ++++++
gas/testsuite/gas/riscv/vector-insns-vsetvl.d | 33 +++++++++++++++++++
gas/testsuite/gas/riscv/vector-insns-vsetvl.s | 24 ++++++++++++++
.../gas/riscv/vector-insns-warning.l | 15 +++++++++
gas/testsuite/gas/riscv/vector-insns.d | 23 -------------
gas/testsuite/gas/riscv/vector-insns.s | 25 --------------
6 files changed, 82 insertions(+), 48 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/vector-insns-vsetvl.d
create mode 100644 gas/testsuite/gas/riscv/vector-insns-vsetvl.s
create mode 100644 gas/testsuite/gas/riscv/vector-insns-warning.l
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 0cc2484b049..521850f5191 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -2381,6 +2381,16 @@ my_getVsetvliExpression (expressionS *ep, char *str)
{
my_getExpression (ep, str);
str = expr_parse_end;
+ unsigned int imm_vlmul = EXTRACT_OPERAND (VLMUL, ep->X_add_number);
+ if (!riscv_vlmul[imm_vlmul])
+ as_warn (_("The vtype encoding of vlmul = %#x is reserved."), imm_vlmul);
+ unsigned int imm_vsew = EXTRACT_OPERAND (VSEW, ep->X_add_number);
+ if (!riscv_vsew[imm_vsew])
+ as_warn (_("The vtype encoding of vsew = %#x is reserved."), imm_vsew);
+ unsigned int imm_vtype_res = ep->X_add_number >> 8;
+ if (imm_vtype_res)
+ as_warn (_("The vtype encoding of %#lx is reserved."),
+ (unsigned long) ep->X_add_number);
}
}
diff --git a/gas/testsuite/gas/riscv/vector-insns-vsetvl.d b/gas/testsuite/gas/riscv/vector-insns-vsetvl.d
new file mode 100644
index 00000000000..549737ad936
--- /dev/null
+++ b/gas/testsuite/gas/riscv/vector-insns-vsetvl.d
@@ -0,0 +1,33 @@
+#as: -march=rv32ifv
+#warning_output: vector-insns-warning.l
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[ ]+[0-9a-f]+:[ ]+80c5f557[ ]+vsetvl[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+0005f557[ ]+vsetvli[ ]+a0,a1,e8,m1,tu,mu
+[ ]+[0-9a-f]+:[ ]+7ff5f557[ ]+vsetvli[ ]+a0,a1,2047
+[ ]+[0-9a-f]+:[ ]+0045f557[ ]+vsetvli[ ]+a0,a1,4
+[ ]+[0-9a-f]+:[ ]+0205f557[ ]+vsetvli[ ]+a0,a1,32
+[ ]+[0-9a-f]+:[ ]+0015f557[ ]+vsetvli[ ]+a0,a1,e8,m2,tu,mu
+[ ]+[0-9a-f]+:[ ]+04a5f557[ ]+vsetvli[ ]+a0,a1,e16,m4,ta,mu
+[ ]+[0-9a-f]+:[ ]+0165f557[ ]+vsetvli[ ]+a0,a1,e32,mf4,tu,mu
+[ ]+[0-9a-f]+:[ ]+09d5f557[ ]+vsetvli[ ]+a0,a1,e64,mf8,tu,ma
+[ ]+[0-9a-f]+:[ ]+c005f557[ ]+vsetivli[ ]+a0,11,e8,m1,tu,mu
+[ ]+[0-9a-f]+:[ ]+fff5f557[ ]+vsetivli[ ]+a0,11,1023
+[ ]+[0-9a-f]+:[ ]+c045f557[ ]+vsetivli[ ]+a0,11,4
+[ ]+[0-9a-f]+:[ ]+c205f557[ ]+vsetivli[ ]+a0,11,32
+[ ]+[0-9a-f]+:[ ]+c015f557[ ]+vsetivli[ ]+a0,11,e8,m2,tu,mu
+[ ]+[0-9a-f]+:[ ]+c4a5f557[ ]+vsetivli[ ]+a0,11,e16,m4,ta,mu
+[ ]+[0-9a-f]+:[ ]+c165f557[ ]+vsetivli[ ]+a0,11,e32,mf4,tu,mu
+[ ]+[0-9a-f]+:[ ]+c9d5f557[ ]+vsetivli[ ]+a0,11,e64,mf8,tu,ma
+[ ]+[0-9a-f]+:[ ]+7005f557[ ]+vsetvli[ ]+a0,a1,1792
+[ ]+[0-9a-f]+:[ ]+4005f557[ ]+vsetvli[ ]+a0,a1,1024
+[ ]+[0-9a-f]+:[ ]+3005f557[ ]+vsetvli[ ]+a0,a1,768
+[ ]+[0-9a-f]+:[ ]+1005f557[ ]+vsetvli[ ]+a0,a1,256
+[ ]+[0-9a-f]+:[ ]+f005f557[ ]+vsetivli[ ]+a0,11,768
+[ ]+[0-9a-f]+:[ ]+d005f557[ ]+vsetivli[ ]+a0,11,256
diff --git a/gas/testsuite/gas/riscv/vector-insns-vsetvl.s b/gas/testsuite/gas/riscv/vector-insns-vsetvl.s
new file mode 100644
index 00000000000..b42dc503d93
--- /dev/null
+++ b/gas/testsuite/gas/riscv/vector-insns-vsetvl.s
@@ -0,0 +1,24 @@
+ vsetvl a0, a1, a2
+ vsetvli a0, a1, 0
+ vsetvli a0, a1, 0x7ff
+ vsetvli a0, a1, 0x4 # unrecognized vlmul
+ vsetvli a0, a1, 0x20 # unrecognized vsew
+ vsetvli a0, a1, e8, m2
+ vsetvli a0, a1, e16, m4, ta
+ vsetvli a0, a1, e32, mf4, mu
+ vsetvli a0, a1, e64, mf8, tu, ma
+ vsetivli a0, 0xb, 0
+ vsetivli a0, 0xb, 0x3ff
+ vsetivli a0, 0xb, 0x4 # unrecognized vlmul
+ vsetivli a0, 0xb, 0x20 # unrecognized vsew
+ vsetivli a0, 0xb, e8, m2
+ vsetivli a0, 0xb, e16, m4, ta
+ vsetivli a0, 0xb, e32, mf4, mu
+ vsetivli a0, 0xb, e64, mf8, tu, ma
+
+ vsetvli a0, a1, 0x700
+ vsetvli a0, a1, 0x400
+ vsetvli a0, a1, 0x300
+ vsetvli a0, a1, 0x100
+ vsetivli a0, 0xb, 0x300
+ vsetivli a0, 0xb, 0x100
diff --git a/gas/testsuite/gas/riscv/vector-insns-warning.l b/gas/testsuite/gas/riscv/vector-insns-warning.l
new file mode 100644
index 00000000000..73d15eb8f21
--- /dev/null
+++ b/gas/testsuite/gas/riscv/vector-insns-warning.l
@@ -0,0 +1,15 @@
+.*Assembler messages:
+.*Warning: The vtype encoding of vsew = 0x7 is reserved.
+.*Warning: The vtype encoding of 0x7ff is reserved.
+.*Warning: The vtype encoding of vlmul = 0x4 is reserved.
+.*Warning: The vtype encoding of vsew = 0x4 is reserved.
+.*Warning: The vtype encoding of vsew = 0x7 is reserved.
+.*Warning: The vtype encoding of 0x3ff is reserved.
+.*Warning: The vtype encoding of vlmul = 0x4 is reserved.
+.*Warning: The vtype encoding of vsew = 0x4 is reserved.
+.*Warning: The vtype encoding of 0x700 is reserved.
+.*Warning: The vtype encoding of 0x400 is reserved.
+.*Warning: The vtype encoding of 0x300 is reserved.
+.*Warning: The vtype encoding of 0x100 is reserved.
+.*Warning: The vtype encoding of 0x300 is reserved.
+.*Warning: The vtype encoding of 0x100 is reserved.
diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d
index 71764aa1f34..ae4f36ca885 100644
--- a/gas/testsuite/gas/riscv/vector-insns.d
+++ b/gas/testsuite/gas/riscv/vector-insns.d
@@ -7,29 +7,6 @@
Disassembly of section .text:
0+000 <.text>:
-[ ]+[0-9a-f]+:[ ]+80c5f557[ ]+vsetvl[ ]+a0,a1,a2
-[ ]+[0-9a-f]+:[ ]+0005f557[ ]+vsetvli[ ]+a0,a1,e8,m1,tu,mu
-[ ]+[0-9a-f]+:[ ]+7ff5f557[ ]+vsetvli[ ]+a0,a1,2047
-[ ]+[0-9a-f]+:[ ]+0045f557[ ]+vsetvli[ ]+a0,a1,4
-[ ]+[0-9a-f]+:[ ]+0205f557[ ]+vsetvli[ ]+a0,a1,32
-[ ]+[0-9a-f]+:[ ]+0015f557[ ]+vsetvli[ ]+a0,a1,e8,m2,tu,mu
-[ ]+[0-9a-f]+:[ ]+04a5f557[ ]+vsetvli[ ]+a0,a1,e16,m4,ta,mu
-[ ]+[0-9a-f]+:[ ]+0165f557[ ]+vsetvli[ ]+a0,a1,e32,mf4,tu,mu
-[ ]+[0-9a-f]+:[ ]+09d5f557[ ]+vsetvli[ ]+a0,a1,e64,mf8,tu,ma
-[ ]+[0-9a-f]+:[ ]+c005f557[ ]+vsetivli[ ]+a0,11,e8,m1,tu,mu
-[ ]+[0-9a-f]+:[ ]+fff5f557[ ]+vsetivli[ ]+a0,11,1023
-[ ]+[0-9a-f]+:[ ]+c045f557[ ]+vsetivli[ ]+a0,11,4
-[ ]+[0-9a-f]+:[ ]+c205f557[ ]+vsetivli[ ]+a0,11,32
-[ ]+[0-9a-f]+:[ ]+c015f557[ ]+vsetivli[ ]+a0,11,e8,m2,tu,mu
-[ ]+[0-9a-f]+:[ ]+c4a5f557[ ]+vsetivli[ ]+a0,11,e16,m4,ta,mu
-[ ]+[0-9a-f]+:[ ]+c165f557[ ]+vsetivli[ ]+a0,11,e32,mf4,tu,mu
-[ ]+[0-9a-f]+:[ ]+c9d5f557[ ]+vsetivli[ ]+a0,11,e64,mf8,tu,ma
-[ ]+[0-9a-f]+:[ ]+7005f557[ ]+vsetvli[ ]+a0,a1,1792
-[ ]+[0-9a-f]+:[ ]+4005f557[ ]+vsetvli[ ]+a0,a1,1024
-[ ]+[0-9a-f]+:[ ]+3005f557[ ]+vsetvli[ ]+a0,a1,768
-[ ]+[0-9a-f]+:[ ]+1005f557[ ]+vsetvli[ ]+a0,a1,256
-[ ]+[0-9a-f]+:[ ]+f005f557[ ]+vsetivli[ ]+a0,11,768
-[ ]+[0-9a-f]+:[ ]+d005f557[ ]+vsetivli[ ]+a0,11,256
[ ]+[0-9a-f]+:[ ]+02b50207[ ]+vlm.v[ ]+v4,\(a0\)
[ ]+[0-9a-f]+:[ ]+02b50207[ ]+vlm.v[ ]+v4,\(a0\)
[ ]+[0-9a-f]+:[ ]+02b50207[ ]+vlm.v[ ]+v4,\(a0\)
diff --git a/gas/testsuite/gas/riscv/vector-insns.s b/gas/testsuite/gas/riscv/vector-insns.s
index a4b98d81026..76f0f179021 100644
--- a/gas/testsuite/gas/riscv/vector-insns.s
+++ b/gas/testsuite/gas/riscv/vector-insns.s
@@ -1,28 +1,3 @@
- vsetvl a0, a1, a2
- vsetvli a0, a1, 0
- vsetvli a0, a1, 0x7ff
- vsetvli a0, a1, 0x4 # unrecognized vlmul
- vsetvli a0, a1, 0x20 # unrecognized vsew
- vsetvli a0, a1, e8, m2
- vsetvli a0, a1, e16, m4, ta
- vsetvli a0, a1, e32, mf4, mu
- vsetvli a0, a1, e64, mf8, tu, ma
- vsetivli a0, 0xb, 0
- vsetivli a0, 0xb, 0x3ff
- vsetivli a0, 0xb, 0x4 # unrecognized vlmul
- vsetivli a0, 0xb, 0x20 # unrecognized vsew
- vsetivli a0, 0xb, e8, m2
- vsetivli a0, 0xb, e16, m4, ta
- vsetivli a0, 0xb, e32, mf4, mu
- vsetivli a0, 0xb, e64, mf8, tu, ma
-
- vsetvli a0, a1, 0x700
- vsetvli a0, a1, 0x400
- vsetvli a0, a1, 0x300
- vsetvli a0, a1, 0x100
- vsetivli a0, 0xb, 0x300
- vsetivli a0, 0xb, 0x100
-
vlm.v v4, (a0)
vlm.v v4, 0(a0)
vle1.v v4, (a0) # Alias of vlm.v
--
2.17.1
next reply other threads:[~2023-05-18 6:59 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-18 6:59 Li Xu [this message]
2023-05-19 6:21 ` Jan Beulich
2023-05-19 2:14 Li Xu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230518065950.6166-1-xuli1@eswincomputing.com \
--to=xuli1@eswincomputing.com \
--cc=binutils@sourceware.org \
--cc=kito.cheng@gmail.com \
--cc=palmer@dabbelt.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).