From: Liao Shihua <shihua@iscas.ac.cn>
To: binutils@sourceware.org
Cc: kito.cheng@sifive.com, jiawei@iscas.ac.cn, palmer@dabbelt.com,
guoren@kernel.org, wuwei2016@iscas.ac.cn, shiyulong@iscas.ac.cn,
chenyixuan@iscas.ac.cn, Liao Shihua <shihua@iscas.ac.cn>
Subject: [RFC PATCH 4/4] gdb/riscv : Add rv64 ilp32 support in gdb
Date: Fri, 19 May 2023 11:48:35 +0800 [thread overview]
Message-ID: <20230519034835.664-5-shihua@iscas.ac.cn> (raw)
In-Reply-To: <20230519034835.664-1-shihua@iscas.ac.cn>
This patch supports rv64 ilp32 in gdb. I know should send it
to gdb maillist, but due to its close correlation with the
previous patch, it is temporarily placed here.
It add a new gdb features abi_xlen.
ChangeLog:
* gdb/arch/riscv.h (struct riscv_gdbarch_features):Add abi_xlen .
* gdb/riscv-tdep.c (riscv_abi_xlen):Likewise
(riscv_features_from_bfd):Likewise
(riscv_gdbarch_init):change long_bit by abi_xlen.
---
gdb/arch/riscv.h | 10 +++++++++-
gdb/riscv-tdep.c | 20 ++++++++++++++++----
2 files changed, 25 insertions(+), 5 deletions(-)
diff --git a/gdb/arch/riscv.h b/gdb/arch/riscv.h
index 54610ed6c16..a41faba1168 100644
--- a/gdb/arch/riscv.h
+++ b/gdb/arch/riscv.h
@@ -41,6 +41,12 @@ struct riscv_gdbarch_features
uninitialised. */
int xlen = 0;
+ /* The size of the pointer_size in bytes. This is either 4 (ILP32), 8
+ (LP64). No other value is valid. Initialise to the
+ invalid 0 value so we can spot if one of these is used
+ uninitialised. */
+ int abi_xlen = 0;
+
/* The size of the f-registers in bytes. This is either 4 (RV32), 8
(RV64), or 16 (RV128). This can also hold the value 0 to indicate
that there are no f-registers. No other value is valid. */
@@ -68,6 +74,7 @@ struct riscv_gdbarch_features
bool operator== (const struct riscv_gdbarch_features &rhs) const
{
return (xlen == rhs.xlen && flen == rhs.flen
+ && abi_xlen == rhs.abi_xlen
&& embedded == rhs.embedded && vlen == rhs.vlen
&& has_fflags_reg == rhs.has_fflags_reg
&& has_frm_reg == rhs.has_frm_reg
@@ -88,8 +95,9 @@ struct riscv_gdbarch_features
| (has_frm_reg ? 1 : 0) << 12
| (has_fcsr_reg ? 1 : 0) << 13
| (xlen & 0x1f) << 5
+ | (abi_xlen & 0x1f) << 14
| (flen & 0x1f) << 0
- | (vlen & 0xfff) << 14);
+ | (vlen & 0xfff) << 19);
return val;
}
};
diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index 500279e1ae9..d4531896cc1 100644
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -774,7 +774,7 @@ int
riscv_abi_xlen (struct gdbarch *gdbarch)
{
riscv_gdbarch_tdep *tdep = gdbarch_tdep<riscv_gdbarch_tdep> (gdbarch);
- return tdep->abi_features.xlen;
+ return tdep->abi_features.abi_xlen;
}
/* See riscv-tdep.h. */
@@ -3835,9 +3835,15 @@ riscv_features_from_bfd (const bfd *abfd)
int e_flags = elf_elfheader (abfd)->e_flags;
if (eclass == ELFCLASS32)
- features.xlen = 4;
+ {
+ features.xlen == 4;
+ features.abi_xlen = 4;
+ }
else if (eclass == ELFCLASS64)
- features.xlen = 8;
+ {
+ features.xlen == 8;
+ features.abi_xlen = 8;
+ }
else
internal_error (_("unknown ELF header class %d"), eclass);
@@ -3846,6 +3852,12 @@ riscv_features_from_bfd (const bfd *abfd)
else if (e_flags & EF_RISCV_FLOAT_ABI_SINGLE)
features.flen = 4;
+ if (e_flags & EF_RISCV_X32)
+ {
+ features.xlen == 8;
+ features.abi_xlen = 4;
+ }
+
if (e_flags & EF_RISCV_RVE)
{
if (features.xlen == 8)
@@ -4175,7 +4187,7 @@ riscv_gdbarch_init (struct gdbarch_info info,
/* Target data types. */
set_gdbarch_short_bit (gdbarch, 16);
set_gdbarch_int_bit (gdbarch, 32);
- set_gdbarch_long_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8);
+ set_gdbarch_long_bit (gdbarch, riscv_abi_xlen (gdbarch) * 8);
set_gdbarch_long_long_bit (gdbarch, 64);
set_gdbarch_float_bit (gdbarch, 32);
set_gdbarch_double_bit (gdbarch, 64);
--
2.38.1.windows.1
prev parent reply other threads:[~2023-05-19 3:49 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-19 3:48 [RFC PATCH V2 0/4] RISC-V : Support ilp32 abi on rv64 isa Liao Shihua
2023-05-19 3:48 ` [RFC PATCH 1/4] RISC-V : Remove checking when -march=rv64XX and -mabi=ilp32X Liao Shihua
2023-05-19 6:25 ` Jan Beulich
2023-05-19 3:48 ` [RFC PATCH 2/4] RISC-V : Add support for rv64 arch using ilp32 abi Liao Shihua
2023-05-19 6:33 ` Jan Beulich
2023-05-19 6:58 ` shihua
2023-05-19 3:48 ` [RFC PATCH 3/4] RISC-V : Add rv64 ilp32 support in disassemble Liao Shihua
2023-05-25 15:35 ` Guo Ren
2023-05-19 3:48 ` Liao Shihua [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230519034835.664-5-shihua@iscas.ac.cn \
--to=shihua@iscas.ac.cn \
--cc=binutils@sourceware.org \
--cc=chenyixuan@iscas.ac.cn \
--cc=guoren@kernel.org \
--cc=jiawei@iscas.ac.cn \
--cc=kito.cheng@sifive.com \
--cc=palmer@dabbelt.com \
--cc=shiyulong@iscas.ac.cn \
--cc=wuwei2016@iscas.ac.cn \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).