* [PATCH v7 0/7] LoongArch: disassembler improvements & deprecate old register aliases
@ 2023-06-29 16:34 WANG Xuerui
2023-06-29 16:34 ` [PATCH v7 1/7] LoongArch: support disassembling certain pseudo-instructions WANG Xuerui
` (6 more replies)
0 siblings, 7 replies; 8+ messages in thread
From: WANG Xuerui @ 2023-06-29 16:34 UTC (permalink / raw)
To: binutils
Cc: Chenghua Xu, Zhensong Liu, Qinggang Meng, Lulu Cheng,
Fangrui Song, Xi Ruoyao, WANG Xuerui
From: WANG Xuerui <git@xen0n.name>
Hi,
This series implements colored output for LoongArch disassembly, and
some minor tweaks to the output so there is less clutter. While at it,
also deprecate the aliases $v0, $v1, $fv0, $fv1 and $x, so users don't
find it confusing in an era when $vrNN and $xrNN (LSX/LASX registers)
are also available. The patch is included last because its test case
would need tweaking if the disassembler changes first get merged anyway.
The 4th revision was sent back in February but at that time the Loongson
maintainers were busy with linker relaxation support; now that the work
was done let's try upstreaming this series again, hopefully for
inclusion in binutils 2.41.
Changes from v6:
- Fixed more test failures
Changes from v5:
- Rebased
- Added DCO (Signed-off-by) tags and changelog entries (I hate them but
it seems LoongArch patches usually carry some, so I went for
consistency)
- Absorbed the https://sourceware.org/pipermail/binutils/2023-June/128073.html
patch
- Minor tweaks to the commit messages
Changes from v4:
- Rebased (mainly test case changes)
Changes from v3:
- Fixed ld test cases (make check-gas and make check-ld both pass on
x86_64 and loongarch64)
- Branch target address is now correctly printed in comment style, plus
code simplification as suggested
Changes from v2:
- Fixed test cases
- Added the fixed "LoongArch: support disassembling certain pseudo-
instructions" patch into this series
- Fixed ".insn" in the last patch to say ".word" instead (MIPS muscle
memory strikes back hard)
- Fixed some commit messages
- Added mengqinggang to Cc list
WANG Xuerui (7):
LoongArch: support disassembling certain pseudo-instructions
opcodes/loongarch: remove unused code
opcodes/loongarch: implement style support in the disassembler
opcodes/loongarch: style disassembled address offsets as such
opcodes/loongarch: do not print hex notation for signed immediates
opcodes/loongarch: print unrecognized insn words with the .word
directive
LoongArch: Deprecate $v[01], $fv[01] and $x names per spec
gas/config/tc-loongarch.c | 45 +++++-
gas/testsuite/gas/loongarch/64_pcrel.d | 2 +-
.../gas/loongarch/deprecated_reg_aliases.d | 18 +++
.../gas/loongarch/deprecated_reg_aliases.l | 7 +
.../gas/loongarch/deprecated_reg_aliases.s | 5 +
gas/testsuite/gas/loongarch/imm_ins.d | 84 +++++------
gas/testsuite/gas/loongarch/imm_ins_32.d | 54 +++----
gas/testsuite/gas/loongarch/imm_op.d | 44 +++---
gas/testsuite/gas/loongarch/jmp_op.d | 44 +++---
gas/testsuite/gas/loongarch/li.d | 8 +-
gas/testsuite/gas/loongarch/load_store_op.d | 80 +++++-----
gas/testsuite/gas/loongarch/macro_op.d | 4 +-
gas/testsuite/gas/loongarch/macro_op_32.d | 4 +-
.../gas/loongarch/macro_op_large_abs.d | 12 +-
.../gas/loongarch/macro_op_large_pc.d | 12 +-
gas/testsuite/gas/loongarch/nop.d | 2 +-
gas/testsuite/gas/loongarch/privilege_op.d | 8 +-
gas/testsuite/gas/loongarch/raw-insn.d | 11 ++
gas/testsuite/gas/loongarch/raw-insn.s | 7 +
gas/testsuite/gas/loongarch/relax_align.d | 6 +-
gas/testsuite/gas/loongarch/reloc.d | 2 +-
gas/testsuite/gas/loongarch/uleb128.d | 22 +--
gas/testsuite/gas/loongarch/vector.d | 140 +++++++++---------
include/opcode/loongarch.h | 11 +-
ld/testsuite/ld-loongarch-elf/jmp_op.d | 40 ++---
ld/testsuite/ld-loongarch-elf/macro_op.d | 24 +--
ld/testsuite/ld-loongarch-elf/macro_op_32.d | 4 +-
ld/testsuite/ld-loongarch-elf/relax-align.dd | 4 +-
opcodes/disassemble.c | 5 +
opcodes/loongarch-dis.c | 118 ++++++---------
opcodes/loongarch-opc.c | 81 ++++++----
31 files changed, 495 insertions(+), 413 deletions(-)
create mode 100644 gas/testsuite/gas/loongarch/deprecated_reg_aliases.d
create mode 100644 gas/testsuite/gas/loongarch/deprecated_reg_aliases.l
create mode 100644 gas/testsuite/gas/loongarch/deprecated_reg_aliases.s
create mode 100644 gas/testsuite/gas/loongarch/raw-insn.d
create mode 100644 gas/testsuite/gas/loongarch/raw-insn.s
--
2.40.0
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v7 1/7] LoongArch: support disassembling certain pseudo-instructions
2023-06-29 16:34 [PATCH v7 0/7] LoongArch: disassembler improvements & deprecate old register aliases WANG Xuerui
@ 2023-06-29 16:34 ` WANG Xuerui
2023-06-29 16:34 ` [PATCH v7 2/7] opcodes/loongarch: remove unused code WANG Xuerui
` (5 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: WANG Xuerui @ 2023-06-29 16:34 UTC (permalink / raw)
To: binutils
Cc: Chenghua Xu, Zhensong Liu, Qinggang Meng, Lulu Cheng,
Fangrui Song, Xi Ruoyao, WANG Xuerui
From: WANG Xuerui <git@xen0n.name>
Add a flag in the pinfo field for being able to mark certain specialized
matchers as disassembler-only, so some degree of isolation between
assembler-side and disassembler-side can be achieved.
This isolation is necessary, firstly because some pseudo-instructions
cannot be fully described in the opcode table, like `li.[wd]`, so the
corresponding opcode entry cannot have meaningful match/mask values.
Secondly, some of these pseudo-instructions can be realized in more than
one plausible ways; e.g. `li.w rd, <something between 0 and 0x7ff>` can
be realized on LA64 with any of `addi.w`, `addi.d` or `ori`. If we tie
disassembly of such aliases with the corresponding GAS support, only one
canonical form among the above would be recognized as `li.w`, and it
would mildly impact the readability of disassembly output.
People wanting the exact disassembly can always set `-M no-aliases` to
get the original behavior back.
In addition, in certain cases, information is irreversibly lost after
assembling, so perfect round-trip would not be possible in such cases.
For example, `li.w` and `li.d` of immediates within int32_t range
produce the same code; in this patch, `addi.d rd, $zero, imm` is treated
as `li.d`, while `addi.w` and `ori` immediate loads are shown as `li.w`,
due to the expressible value range well within 32 bits.
gas/ChangeLog:
* config/tc-loongarch.c (get_loongarch_opcode): Ignore
disassembler-only aliases.
* testsuite/gas/loongarch/64_pcrel.d: Update test case.
* testsuite/gas/loongarch/imm_ins.d: Likewise.
* testsuite/gas/loongarch/imm_ins_32.d: Likewise.
* testsuite/gas/loongarch/jmp_op.d: Likewise.
* testsuite/gas/loongarch/li.d: Likewise.
* testsuite/gas/loongarch/macro_op.d: Likewise.
* testsuite/gas/loongarch/macro_op_32.d: Likewise.
* testsuite/gas/loongarch/macro_op_large_abs.d: Likewise.
* testsuite/gas/loongarch/macro_op_large_pc.d: Likewise.
* testsuite/gas/loongarch/nop.d: Likewise.
* testsuite/gas/loongarch/relax_align.d: Likewise.
* testsuite/gas/loongarch/reloc.d: Likewise.
include/ChangeLog:
* opcode/loongarch.h (INSN_DIS_ALIAS): Add.
ld/ChangeLog:
* testsuite/ld-loongarch-elf/jmp_op.d: Update test case.
* testsuite/ld-loongarch-elf/macro_op.d: Likewise.
* testsuite/ld-loongarch-elf/macro_op_32.d: Likewise.
* testsuite/ld-loongarch-elf/relax-align.dd: Likewise.
opcodes/ChangeLog:
* loongarch-dis.c: Move register name map declarations to top.
(get_loongarch_opcode_by_binfmt): Consider aliases when
disassembling without the no-aliases option.
(parse_loongarch_dis_option): Support the no-aliases option.
* loongarch-opc.c: Collect pseudo instructions into a new
dedicated table.
Signed-off-by: WANG Xuerui <git@xen0n.name>
---
gas/config/tc-loongarch.c | 3 ++-
gas/testsuite/gas/loongarch/64_pcrel.d | 2 +-
gas/testsuite/gas/loongarch/imm_ins.d | 4 +--
gas/testsuite/gas/loongarch/imm_ins_32.d | 2 +-
gas/testsuite/gas/loongarch/jmp_op.d | 12 ++++-----
gas/testsuite/gas/loongarch/li.d | 8 +++---
gas/testsuite/gas/loongarch/macro_op.d | 4 +--
gas/testsuite/gas/loongarch/macro_op_32.d | 4 +--
.../gas/loongarch/macro_op_large_abs.d | 12 ++++-----
.../gas/loongarch/macro_op_large_pc.d | 12 ++++-----
gas/testsuite/gas/loongarch/nop.d | 2 +-
gas/testsuite/gas/loongarch/relax_align.d | 6 ++---
gas/testsuite/gas/loongarch/reloc.d | 2 +-
include/opcode/loongarch.h | 2 ++
ld/testsuite/ld-loongarch-elf/jmp_op.d | 2 +-
ld/testsuite/ld-loongarch-elf/macro_op.d | 24 ++++++++---------
ld/testsuite/ld-loongarch-elf/macro_op_32.d | 4 +--
ld/testsuite/ld-loongarch-elf/relax-align.dd | 4 +--
opcodes/loongarch-dis.c | 26 ++++++++++++-------
opcodes/loongarch-opc.c | 23 ++++++++++++++--
20 files changed, 94 insertions(+), 64 deletions(-)
diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c
index 7366e766a49..6e8aa35e282 100644
--- a/gas/config/tc-loongarch.c
+++ b/gas/config/tc-loongarch.c
@@ -802,7 +802,8 @@ get_loongarch_opcode (struct loongarch_cl_insn *insn)
for (it = ase->opcodes; it->name; it++)
{
if ((!it->include || (it->include && *it->include))
- && (!it->exclude || (it->exclude && !(*it->exclude))))
+ && (!it->exclude || (it->exclude && !(*it->exclude)))
+ && !(it->pinfo & INSN_DIS_ALIAS))
str_hash_insert (ase->name_hash_entry, it->name,
(void *) it, 0);
}
diff --git a/gas/testsuite/gas/loongarch/64_pcrel.d b/gas/testsuite/gas/loongarch/64_pcrel.d
index 6d4654b795e..66b80a397fa 100644
--- a/gas/testsuite/gas/loongarch/64_pcrel.d
+++ b/gas/testsuite/gas/loongarch/64_pcrel.d
@@ -7,5 +7,5 @@
Disassembly of section .text:
00000000.* <.text>:
-[ ]+0:[ ]+03400000[ ]+andi[ ]+\$zero,[ ]+\$zero,[ ]+0x0
+[ ]+0:[ ]+03400000[ ]+nop[ ]+
[ ]+0:[ ]+R_LARCH_64_PCREL[ ]+\*ABS\*
diff --git a/gas/testsuite/gas/loongarch/imm_ins.d b/gas/testsuite/gas/loongarch/imm_ins.d
index 0ceaead3edf..c588b5e0e25 100644
--- a/gas/testsuite/gas/loongarch/imm_ins.d
+++ b/gas/testsuite/gas/loongarch/imm_ins.d
@@ -8,10 +8,10 @@
Disassembly of section .text:
00000000.* <.text>:
-[ ]+0:[ ]+03848c0c[ ]+ori[ ]+\$t0,[ ]+\$zero,[ ]+0x123
+[ ]+0:[ ]+03848c0c[ ]+li.w[ ]+\$t0,[ ]+0x123
[ ]+4:[ ]+15ffe00d[ ]+lu12i.w[ ]+\$t1,[ ]+-256\(0xfff00\)
[ ]+8:[ ]+16001fed[ ]+lu32i.d[ ]+\$t1,[ ]+255\(0xff\)
-[ ]+c:[ ]+02bffc0e[ ]+addi.w[ ]+\$t2,[ ]+\$zero,[ ]+-1\(0xfff\)
+[ ]+c:[ ]+02bffc0e[ ]+li.w[ ]+\$t2,[ ]+-1\(0xfff\)
[ ]+10:[ ]+1601ffee[ ]+lu32i.d[ ]+\$t2,[ ]+4095\(0xfff\)
[ ]+14:[ ]+0004b58b[ ]+alsl.w[ ]+\$a7,[ ]+\$t0,[ ]+\$t1,[ ]+0x2
[ ]+18:[ ]+0006b58b[ ]+alsl.wu[ ]+\$a7,[ ]+\$t0,[ ]+\$t1,[ ]+0x2
diff --git a/gas/testsuite/gas/loongarch/imm_ins_32.d b/gas/testsuite/gas/loongarch/imm_ins_32.d
index 0a826bfba5b..5fd5835a342 100644
--- a/gas/testsuite/gas/loongarch/imm_ins_32.d
+++ b/gas/testsuite/gas/loongarch/imm_ins_32.d
@@ -8,7 +8,7 @@
Disassembly of section .text:
00000000.* <.text>:
-[ ]+0:[ ]+03848c0c[ ]+ori[ ]+\$t0,[ ]+\$zero,[ ]+0x123
+[ ]+0:[ ]+03848c0c[ ]+li.w[ ]+\$t0,[ ]+0x123
[ ]+4:[ ]+0004b58b[ ]+alsl.w[ ]+\$a7,[ ]+\$t0,[ ]+\$t1,[ ]+0x2
[ ]+8:[ ]+0006b58b[ ]+alsl.wu[ ]+\$a7,[ ]+\$t0,[ ]+\$t1,[ ]+0x2
[ ]+c:[ ]+0009358b[ ]+bytepick.w[ ]+\$a7,[ ]+\$t0,[ ]+\$t1,[ ]+0x2
diff --git a/gas/testsuite/gas/loongarch/jmp_op.d b/gas/testsuite/gas/loongarch/jmp_op.d
index a4535c297c9..0ce804b831c 100644
--- a/gas/testsuite/gas/loongarch/jmp_op.d
+++ b/gas/testsuite/gas/loongarch/jmp_op.d
@@ -7,12 +7,12 @@
Disassembly of section .text:
00000000.* <.L1>:
-[ ]+0:[ ]+03400000[ ]+andi[ ]+\$zero,[ ]+\$zero,[ ]+0x0
-[ ]+4:[ ]+63fffc04[ ]+blt[ ]+\$zero,[ ]+\$a0,[ ]+-4\(0x3fffc\)[ ]+#[ ]+0[ ]+<\.L1>
+[ ]+0:[ ]+03400000[ ]+nop[ ]+
+[ ]+4:[ ]+63fffc04[ ]+bgtz[ ]+\$a0,[ ]+-4\(0x3fffc\)[ ]+#[ ]+0[ ]+<\.L1>
[ ]+4:[ ]+R_LARCH_B16[ ]+\.L1
-[ ]+8:[ ]+67fff880[ ]+bge[ ]+\$a0,[ ]+\$zero,[ ]+-8\(0x3fff8\)[ ]+#[ ]+0[ ]+<\.L1>
+[ ]+8:[ ]+67fff880[ ]+bgez[ ]+\$a0,[ ]+-8\(0x3fff8\)[ ]+#[ ]+0[ ]+<\.L1>
[ ]+8:[ ]+R_LARCH_B16[ ]+\.L1
-[ ]+c:[ ]+67fff404[ ]+bge[ ]+\$zero,[ ]+\$a0,[ ]+-12\(0x3fff4\)[ ]+#[ ]+0[ ]+<\.L1>
+[ ]+c:[ ]+67fff404[ ]+blez[ ]+\$a0,[ ]+-12\(0x3fff4\)[ ]+#[ ]+0[ ]+<\.L1>
[ ]+c:[ ]+R_LARCH_B16[ ]+\.L1
[ ]+10:[ ]+43fff09f[ ]+beqz[ ]+\$a0,[ ]+-16\(0x7ffff0\)[ ]+#[ ]+0[ ]+<\.L1>
[ ]+10:[ ]+R_LARCH_B21[ ]+\.L1
@@ -22,7 +22,7 @@ Disassembly of section .text:
[ ]+18:[ ]+R_LARCH_B21[ ]+\.L1
[ ]+1c:[ ]+4bffe51f[ ]+bcnez[ ]+\$fcc0,[ ]+-28\(0x7fffe4\)[ ]+#[ ]+0[ ]+<\.L1>
[ ]+1c:[ ]+R_LARCH_B21[ ]+\.L1
-[ ]+20:[ ]+4c000080[ ]+jirl[ ]+\$zero,[ ]+\$a0,[ ]+0
+[ ]+20:[ ]+4c000080[ ]+jr[ ]+\$a0
[ ]+24:[ ]+53ffdfff[ ]+b[ ]+-36\(0xfffffdc\)[ ]+#[ ]+0[ ]+<\.L1>
[ ]+24:[ ]+R_LARCH_B26[ ]+\.L1
[ ]+28:[ ]+57ffdbff[ ]+bl[ ]+-40\(0xfffffd8\)[ ]+#[ ]+0[ ]+<\.L1>
@@ -47,4 +47,4 @@ Disassembly of section .text:
[ ]+4c:[ ]+R_LARCH_B16[ ]+\.L1
[ ]+50:[ ]+6fffb0a4[ ]+bgeu[ ]+\$a1,[ ]+\$a0,[ ]+-80\(0x3ffb0\)[ ]+#[ ]+0[ ]+<\.L1>
[ ]+50:[ ]+R_LARCH_B16[ ]+\.L1
-[ ]+54:[ ]+4c000020[ ]+jirl[ ]+\$zero,[ ]+\$ra,[ ]+0
+[ ]+54:[ ]+4c000020[ ]+ret[ ]+
diff --git a/gas/testsuite/gas/loongarch/li.d b/gas/testsuite/gas/loongarch/li.d
index 2b37784f237..6f5bcd1dcb3 100644
--- a/gas/testsuite/gas/loongarch/li.d
+++ b/gas/testsuite/gas/loongarch/li.d
@@ -8,16 +8,16 @@
Disassembly of section .text:
00000000.* <_start>:
-[ ]+0:[ ]+03803c06[ ]+ori[ ]+\$a2,[ ]+\$zero,[ ]+0xf
+[ ]+0:[ ]+03803c06[ ]+li\.w[ ]+\$a2,[ ]+0xf
[ ]+4:[ ]+1a000005[ ]+pcalau12i[ ]+\$a1,[ ]+0
[ ]+4:[ ]+R_LARCH_PCALA_HI20[ ]+msg
[ ]+4:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+8:[ ]+02c000a5[ ]+addi\.d[ ]+\$a1,[ ]+\$a1,[ ]+0
[ ]+8:[ ]+R_LARCH_PCALA_LO12[ ]+msg
[ ]+8:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+c:[ ]+03800404[ ]+ori[ ]+\$a0,[ ]+\$zero,[ ]+0x1
-[ ]+10:[ ]+0381000b[ ]+ori[ ]+\$a7,[ ]+\$zero,[ ]+0x40
+[ ]+c:[ ]+03800404[ ]+li\.w[ ]+\$a0,[ ]+0x1
+[ ]+10:[ ]+0381000b[ ]+li\.w[ ]+\$a7,[ ]+0x40
[ ]+14:[ ]+002b0000[ ]+syscall[ ]+0x0
[ ]+18:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero
-[ ]+1c:[ ]+0381740b[ ]+ori[ ]+\$a7,[ ]+\$zero,[ ]+0x5d
+[ ]+1c:[ ]+0381740b[ ]+li\.w[ ]+\$a7,[ ]+0x5d
[ ]+20:[ ]+002b0000[ ]+syscall[ ]+0x0
diff --git a/gas/testsuite/gas/loongarch/macro_op.d b/gas/testsuite/gas/loongarch/macro_op.d
index 3465d11d50d..3f6518eddb0 100644
--- a/gas/testsuite/gas/loongarch/macro_op.d
+++ b/gas/testsuite/gas/loongarch/macro_op.d
@@ -9,9 +9,9 @@ Disassembly of section .text:
00000000.* <.text>:
[ ]+0:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero
-[ ]+4:[ ]+02bffc04[ ]+addi\.w[ ]+\$a0,[ ]+\$zero,[ ]+-1\(0xfff\)
+[ ]+4:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1\(0xfff\)
[ ]+8:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero
-[ ]+c:[ ]+02bffc04[ ]+addi\.w[ ]+\$a0,[ ]+\$zero,[ ]+-1\(0xfff\)
+[ ]+c:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1\(0xfff\)
[ ]+10:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+10:[ ]+R_LARCH_GOT_PC_HI20[ ]+\.L1
[ ]+10:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
diff --git a/gas/testsuite/gas/loongarch/macro_op_32.d b/gas/testsuite/gas/loongarch/macro_op_32.d
index f5a2b54dd9b..5ac15fdfea8 100644
--- a/gas/testsuite/gas/loongarch/macro_op_32.d
+++ b/gas/testsuite/gas/loongarch/macro_op_32.d
@@ -9,9 +9,9 @@ Disassembly of section .text:
00000000.* <.L1>:
[ ]+0:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero
-[ ]+4:[ ]+02bffc04[ ]+addi.w[ ]+\$a0,[ ]+\$zero,[ ]+-1\(0xfff\)
+[ ]+4:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1\(0xfff\)
[ ]+8:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero
-[ ]+c:[ ]+02bffc04[ ]+addi.w[ ]+\$a0,[ ]+\$zero,[ ]+-1\(0xfff\)
+[ ]+c:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1\(0xfff\)
[ ]+10:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+10:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1
[ ]+10:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
diff --git a/gas/testsuite/gas/loongarch/macro_op_large_abs.d b/gas/testsuite/gas/loongarch/macro_op_large_abs.d
index f3a3a4845b9..0c49f68e2ab 100644
--- a/gas/testsuite/gas/loongarch/macro_op_large_abs.d
+++ b/gas/testsuite/gas/loongarch/macro_op_large_abs.d
@@ -11,7 +11,7 @@ Disassembly of section .text:
[ ]+0:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+0:[ ]+R_LARCH_PCALA_HI20[ ]+.L1
[ ]+0:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+4:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+4:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0
[ ]+4:[ ]+R_LARCH_PCALA_LO12[ ]+.L1
[ ]+4:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+8:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
@@ -31,7 +31,7 @@ Disassembly of section .text:
[ ]+24:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+24:[ ]+R_LARCH_PCALA_HI20[ ]+.L1
[ ]+24:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+28:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+28:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0
[ ]+28:[ ]+R_LARCH_PCALA_LO12[ ]+.L1
[ ]+28:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+2c:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
@@ -42,7 +42,7 @@ Disassembly of section .text:
[ ]+38:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+38:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1
[ ]+38:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+3c:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+3c:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0
[ ]+3c:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1
[ ]+3c:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+40:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
@@ -56,7 +56,7 @@ Disassembly of section .text:
[ ]+50:[ ]+R_LARCH_TLS_LE_LO12[ ]+TLS1
[ ]+54:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+54:[ ]+R_LARCH_TLS_IE_PC_HI20[ ]+TLS1
-[ ]+58:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+58:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0
[ ]+58:[ ]+R_LARCH_TLS_IE_PC_LO12[ ]+TLS1
[ ]+5c:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
[ ]+5c:[ ]+R_LARCH_TLS_IE64_PC_LO20[ ]+TLS1
@@ -65,7 +65,7 @@ Disassembly of section .text:
[ ]+64:[ ]+380c1484[ ]+ldx.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1
[ ]+68:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+68:[ ]+R_LARCH_TLS_LD_PC_HI20[ ]+TLS1
-[ ]+6c:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+6c:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0
[ ]+6c:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1
[ ]+6c:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+70:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
@@ -75,7 +75,7 @@ Disassembly of section .text:
[ ]+78:[ ]+00109484[ ]+add.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1
[ ]+7c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+7c:[ ]+R_LARCH_TLS_GD_PC_HI20[ ]+TLS1
-[ ]+80:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+80:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0
[ ]+80:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1
[ ]+80:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+84:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
diff --git a/gas/testsuite/gas/loongarch/macro_op_large_pc.d b/gas/testsuite/gas/loongarch/macro_op_large_pc.d
index f3a3a4845b9..0c49f68e2ab 100644
--- a/gas/testsuite/gas/loongarch/macro_op_large_pc.d
+++ b/gas/testsuite/gas/loongarch/macro_op_large_pc.d
@@ -11,7 +11,7 @@ Disassembly of section .text:
[ ]+0:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+0:[ ]+R_LARCH_PCALA_HI20[ ]+.L1
[ ]+0:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+4:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+4:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0
[ ]+4:[ ]+R_LARCH_PCALA_LO12[ ]+.L1
[ ]+4:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+8:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
@@ -31,7 +31,7 @@ Disassembly of section .text:
[ ]+24:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+24:[ ]+R_LARCH_PCALA_HI20[ ]+.L1
[ ]+24:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+28:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+28:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0
[ ]+28:[ ]+R_LARCH_PCALA_LO12[ ]+.L1
[ ]+28:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+2c:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
@@ -42,7 +42,7 @@ Disassembly of section .text:
[ ]+38:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+38:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1
[ ]+38:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+3c:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+3c:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0
[ ]+3c:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1
[ ]+3c:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+40:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
@@ -56,7 +56,7 @@ Disassembly of section .text:
[ ]+50:[ ]+R_LARCH_TLS_LE_LO12[ ]+TLS1
[ ]+54:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+54:[ ]+R_LARCH_TLS_IE_PC_HI20[ ]+TLS1
-[ ]+58:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+58:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0
[ ]+58:[ ]+R_LARCH_TLS_IE_PC_LO12[ ]+TLS1
[ ]+5c:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
[ ]+5c:[ ]+R_LARCH_TLS_IE64_PC_LO20[ ]+TLS1
@@ -65,7 +65,7 @@ Disassembly of section .text:
[ ]+64:[ ]+380c1484[ ]+ldx.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1
[ ]+68:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+68:[ ]+R_LARCH_TLS_LD_PC_HI20[ ]+TLS1
-[ ]+6c:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+6c:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0
[ ]+6c:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1
[ ]+6c:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+70:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
@@ -75,7 +75,7 @@ Disassembly of section .text:
[ ]+78:[ ]+00109484[ ]+add.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1
[ ]+7c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+7c:[ ]+R_LARCH_TLS_GD_PC_HI20[ ]+TLS1
-[ ]+80:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+80:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0
[ ]+80:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1
[ ]+80:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+84:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
diff --git a/gas/testsuite/gas/loongarch/nop.d b/gas/testsuite/gas/loongarch/nop.d
index 4cdcc5ce0d2..222456e8b8c 100644
--- a/gas/testsuite/gas/loongarch/nop.d
+++ b/gas/testsuite/gas/loongarch/nop.d
@@ -7,4 +7,4 @@
Disassembly of section .text:
0+000 <target>:
-[ ]+0:[ ]+03400000[ ]+andi[ ]+\$zero, \$zero, 0x0
+[ ]+0:[ ]+03400000[ ]+nop[ ]+
diff --git a/gas/testsuite/gas/loongarch/relax_align.d b/gas/testsuite/gas/loongarch/relax_align.d
index 8a44573d406..1810eb4cae7 100644
--- a/gas/testsuite/gas/loongarch/relax_align.d
+++ b/gas/testsuite/gas/loongarch/relax_align.d
@@ -14,10 +14,10 @@ Disassembly of section .text:
[ ]+4:[ ]+02c00084[ ]+addi\.d[ ]+\$a0,[ ]+\$a0,[ ]+0
[ ]+4:[ ]+R_LARCH_PCALA_LO12[ ]+L1
[ ]+4:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+8:[ ]+03400000[ ]+andi[ ]+\$zero,[ ]+\$zero,[ ]+0x0
+[ ]+8:[ ]+03400000[ ]+nop[ ]+
[ ]+8:[ ]+R_LARCH_ALIGN[ ]+\*ABS\*\+0xc
-[ ]+c:[ ]+03400000[ ]+andi[ ]+\$zero,[ ]+\$zero,[ ]+0x0
-[ ]+10:[ ]+03400000[ ]+andi[ ]+\$zero,[ ]+\$zero,[ ]+0x0
+[ ]+c:[ ]+03400000[ ]+nop[ ]+
+[ ]+10:[ ]+03400000[ ]+nop[ ]+
[ ]+14:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+14:[ ]+R_LARCH_PCALA_HI20[ ]+L1
[ ]+14:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
diff --git a/gas/testsuite/gas/loongarch/reloc.d b/gas/testsuite/gas/loongarch/reloc.d
index 6f5f110b1af..c3820c55f98 100644
--- a/gas/testsuite/gas/loongarch/reloc.d
+++ b/gas/testsuite/gas/loongarch/reloc.d
@@ -8,7 +8,7 @@
Disassembly of section .text:
00000000.* <.text>:
-[ ]+0:[ ]+03400000[ ]+andi[ ]+\$zero,[ ]+\$zero,[ ]+0x0
+[ ]+0:[ ]+03400000[ ]+nop[ ]+
[ ]+4:[ ]+58000085[ ]+beq[ ]+\$a0,[ ]+\$a1,[ ]+0[ ]+#[ ]+0x4
[ ]+4:[ ]+R_LARCH_B16[ ]+.L1
[ ]+8:[ ]+5c000085[ ]+bne[ ]+\$a0,[ ]+\$a1,[ ]+0[ ]+#[ ]+0x8
diff --git a/include/opcode/loongarch.h b/include/opcode/loongarch.h
index aa2f3fb645d..60812fb4b1f 100644
--- a/include/opcode/loongarch.h
+++ b/include/opcode/loongarch.h
@@ -120,6 +120,8 @@ dec2 : [1-9][0-9]?
const unsigned long pinfo;
#define USELESS 0x0l
+/* Instruction is a simple alias only for disassembler use. */
+#define INSN_DIS_ALIAS 0x00000001l
};
struct hash_control;
diff --git a/ld/testsuite/ld-loongarch-elf/jmp_op.d b/ld/testsuite/ld-loongarch-elf/jmp_op.d
index 09f89100195..be8290711a5 100644
--- a/ld/testsuite/ld-loongarch-elf/jmp_op.d
+++ b/ld/testsuite/ld-loongarch-elf/jmp_op.d
@@ -1,5 +1,5 @@
#as:
-#objdump: -dr
+#objdump: -dr -M no-aliases
.*:[ ]+file format .*
diff --git a/ld/testsuite/ld-loongarch-elf/macro_op.d b/ld/testsuite/ld-loongarch-elf/macro_op.d
index 2649f63e566..c7f332e7c9d 100644
--- a/ld/testsuite/ld-loongarch-elf/macro_op.d
+++ b/ld/testsuite/ld-loongarch-elf/macro_op.d
@@ -8,9 +8,9 @@ Disassembly of section .text:
00000000.* <.L1>:
[ ]+0:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero
-[ ]+4:[ ]+02bffc04[ ]+addi.w[ ]+\$a0,[ ]+\$zero,[ ]+-1\(0xfff\)
+[ ]+4:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1\(0xfff\)
[ ]+8:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero
-[ ]+c:[ ]+02bffc04[ ]+addi.w[ ]+\$a0,[ ]+\$zero,[ ]+-1\(0xfff\)
+[ ]+c:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1\(0xfff\)
[ ]+10:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+10:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1
[ ]+10:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
@@ -26,7 +26,7 @@ Disassembly of section .text:
[ ]+20:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+20:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1
[ ]+20:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+24:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+24:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0
[ ]+24:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1
[ ]+24:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+28:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
@@ -43,7 +43,7 @@ Disassembly of section .text:
[ ]+3c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+3c:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1
[ ]+3c:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+40:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+40:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0
[ ]+40:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1
[ ]+40:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+44:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
@@ -60,7 +60,7 @@ Disassembly of section .text:
[ ]+58:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+58:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1
[ ]+58:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+5c:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+5c:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0
[ ]+5c:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1
[ ]+5c:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+60:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
@@ -77,7 +77,7 @@ Disassembly of section .text:
[ ]+74:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+74:[ ]+R_LARCH_PCALA_HI20[ ]+.L1
[ ]+74:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+78:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+78:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0
[ ]+78:[ ]+R_LARCH_PCALA_LO12[ ]+.L1
[ ]+78:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+7c:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
@@ -94,7 +94,7 @@ Disassembly of section .text:
[ ]+90:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+90:[ ]+R_LARCH_PCALA_HI20[ ]+.L1
[ ]+90:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+94:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+94:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0
[ ]+94:[ ]+R_LARCH_PCALA_LO12[ ]+.L1
[ ]+94:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+98:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
@@ -126,7 +126,7 @@ Disassembly of section .text:
[ ]+c4:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+c4:[ ]+R_LARCH_PCALA_HI20[ ]+.L1
[ ]+c4:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+c8:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+c8:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0
[ ]+c8:[ ]+R_LARCH_PCALA_LO12[ ]+.L1
[ ]+c8:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+cc:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
@@ -143,7 +143,7 @@ Disassembly of section .text:
[ ]+e0:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+e0:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1
[ ]+e0:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+e4:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+e4:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0
[ ]+e4:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1
[ ]+e4:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+e8:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
@@ -161,7 +161,7 @@ Disassembly of section .text:
[ ]+100:[ ]+R_LARCH_TLS_IE_PC_LO12[ ]+TLS1
[ ]+104:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+104:[ ]+R_LARCH_TLS_IE_PC_HI20[ ]+TLS1
-[ ]+108:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+108:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0
[ ]+108:[ ]+R_LARCH_TLS_IE_PC_LO12[ ]+TLS1
[ ]+10c:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
[ ]+10c:[ ]+R_LARCH_TLS_IE64_PC_LO20[ ]+TLS1
@@ -175,7 +175,7 @@ Disassembly of section .text:
[ ]+11c:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+120:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+120:[ ]+R_LARCH_TLS_LD_PC_HI20[ ]+TLS1
-[ ]+124:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+124:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0
[ ]+124:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1
[ ]+124:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+128:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
@@ -190,7 +190,7 @@ Disassembly of section .text:
[ ]+138:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+13c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+13c:[ ]+R_LARCH_TLS_GD_PC_HI20[ ]+TLS1
-[ ]+140:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+140:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0
[ ]+140:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1
[ ]+140:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+144:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
diff --git a/ld/testsuite/ld-loongarch-elf/macro_op_32.d b/ld/testsuite/ld-loongarch-elf/macro_op_32.d
index f5a2b54dd9b..5ac15fdfea8 100644
--- a/ld/testsuite/ld-loongarch-elf/macro_op_32.d
+++ b/ld/testsuite/ld-loongarch-elf/macro_op_32.d
@@ -9,9 +9,9 @@ Disassembly of section .text:
00000000.* <.L1>:
[ ]+0:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero
-[ ]+4:[ ]+02bffc04[ ]+addi.w[ ]+\$a0,[ ]+\$zero,[ ]+-1\(0xfff\)
+[ ]+4:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1\(0xfff\)
[ ]+8:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero
-[ ]+c:[ ]+02bffc04[ ]+addi.w[ ]+\$a0,[ ]+\$zero,[ ]+-1\(0xfff\)
+[ ]+c:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1\(0xfff\)
[ ]+10:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+10:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1
[ ]+10:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
diff --git a/ld/testsuite/ld-loongarch-elf/relax-align.dd b/ld/testsuite/ld-loongarch-elf/relax-align.dd
index 3149738ff71..5fce2255dda 100644
--- a/ld/testsuite/ld-loongarch-elf/relax-align.dd
+++ b/ld/testsuite/ld-loongarch-elf/relax-align.dd
@@ -1,7 +1,7 @@
#...
.*pcaddi.*
.*pcaddi.*
-.*andi.*
-.*andi.*
+.*nop.*
+.*nop.*
.*0:.*pcaddi.*
#pass
diff --git a/opcodes/loongarch-dis.c b/opcodes/loongarch-dis.c
index 0725270ed34..3a08da14763 100644
--- a/opcodes/loongarch-dis.c
+++ b/opcodes/loongarch-dis.c
@@ -25,6 +25,15 @@
#include "libiberty.h"
#include <stdlib.h>
+static bool loongarch_dis_show_aliases = true;
+static const char *const *loongarch_r_disname = NULL;
+static const char *const *loongarch_f_disname = NULL;
+static const char *const *loongarch_fc_disname = NULL;
+static const char *const *loongarch_c_disname = NULL;
+static const char *const *loongarch_cr_disname = NULL;
+static const char *const *loongarch_v_disname = NULL;
+static const char *const *loongarch_x_disname = NULL;
+
static const struct loongarch_opcode *
get_loongarch_opcode_by_binfmt (insn_t insn)
{
@@ -41,7 +50,9 @@ get_loongarch_opcode_by_binfmt (insn_t insn)
{
for (it = ase->opcodes; it->mask; it++)
if (!ase->opc_htab[LARCH_INSN_OPC (it->match)]
- && it->macro == NULL)
+ && it->macro == NULL
+ && (!(it->pinfo & INSN_DIS_ALIAS)
+ || loongarch_dis_show_aliases))
ase->opc_htab[LARCH_INSN_OPC (it->match)] = it;
for (i = 0; i < 16; i++)
if (!ase->opc_htab[i])
@@ -59,14 +70,6 @@ get_loongarch_opcode_by_binfmt (insn_t insn)
return NULL;
}
-static const char *const *loongarch_r_disname = NULL;
-static const char *const *loongarch_f_disname = NULL;
-static const char *const *loongarch_fc_disname = NULL;
-static const char *const *loongarch_c_disname = NULL;
-static const char *const *loongarch_cr_disname = NULL;
-static const char *const *loongarch_v_disname = NULL;
-static const char *const *loongarch_x_disname = NULL;
-
static void
set_default_loongarch_dis_options (void)
{
@@ -89,6 +92,9 @@ set_default_loongarch_dis_options (void)
static int
parse_loongarch_dis_option (const char *option)
{
+ if (strcmp (option, "no-aliases") == 0)
+ loongarch_dis_show_aliases = false;
+
if (strcmp (option, "numeric") == 0)
{
loongarch_r_disname = loongarch_r_normal_name;
@@ -310,6 +316,8 @@ print_loongarch_disassembler_options (FILE *stream)
The following LoongArch disassembler options are supported for use\n\
with the -M switch (multiple options should be separated by commas):\n"));
+ fprintf (stream, _("\n\
+ no-aliases Use canonical instruction forms.\n"));
fprintf (stream, _("\n\
numeric Print numeric register names, rather than ABI names.\n"));
fprintf (stream, _("\n"));
diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c
index bd104465ca7..3d1d2c761a5 100644
--- a/opcodes/loongarch-opc.c
+++ b/opcodes/loongarch-opc.c
@@ -344,9 +344,29 @@ static struct loongarch_opcode loongarch_macro_opcodes[] =
{ 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */
};
+static struct loongarch_opcode loongarch_alias_opcodes[] =
+{
+ /* match, mask, name, format, macro, include, exclude, pinfo. */
+ { 0x00150000, 0xfffffc00, "move", "r0:5,r5:5", 0, 0, 0, INSN_DIS_ALIAS }, /* or rd, rj, zero */
+ { 0x02800000, 0xffc003e0, "li.w", "r0:5,s10:12", 0, 0, 0, INSN_DIS_ALIAS }, /* addi.w rd, zero, simm */
+ { 0x02c00000, 0xffc003e0, "li.d", "r0:5,s10:12", 0, 0, 0, INSN_DIS_ALIAS }, /* addi.d rd, zero, simm */
+ { 0x03400000, 0xffffffff, "nop", "", 0, 0, 0, INSN_DIS_ALIAS }, /* andi zero, zero, 0 */
+ { 0x03800000, 0xffc003e0, "li.w", "r0:5,u10:12", 0, 0, 0, INSN_DIS_ALIAS }, /* ori rd, zero, uimm */
+ /* ret must come before jr because it is more specific. */
+ { 0x4c000020, 0xffffffff, "ret", "", 0, 0, 0, INSN_DIS_ALIAS }, /* jirl zero, ra, 0 */
+ { 0x4c000000, 0xfffffc1f, "jr", "r5:5", 0, 0, 0, INSN_DIS_ALIAS }, /* jirl zero, rj, 0 */
+ { 0x60000000, 0xfc00001f, "bltz", "r5:5,sb10:16<<2", 0, 0, 0, INSN_DIS_ALIAS }, /* blt rj, zero, offset */
+ { 0x60000000, 0xfc0003e0, "bgtz", "r0:5,sb10:16<<2", 0, 0, 0, INSN_DIS_ALIAS }, /* blt zero, rd, offset */
+ { 0x64000000, 0xfc00001f, "bgez", "r5:5,sb10:16<<2", 0, 0, 0, INSN_DIS_ALIAS }, /* bge rj, zero, offset */
+ { 0x64000000, 0xfc0003e0, "blez", "r0:5,sb10:16<<2", 0, 0, 0, INSN_DIS_ALIAS }, /* bge zero, rd, offset */
+ { 0 } /* Terminate the list. */
+};
+
+
static struct loongarch_opcode loongarch_fix_opcodes[] =
{
/* match, mask, name, format, macro, include, exclude, pinfo. */
+ { 0x0, 0x0, "move", "r,r", "or %1,%2,$r0", 0, 0, 0 },
{ 0x00001000, 0xfffffc00, "clo.w", "r0:5,r5:5", 0, 0, 0, 0 },
{ 0x00001400, 0xfffffc00, "clz.w", "r0:5,r5:5", 0, 0, 0, 0 },
{ 0x00001800, 0xfffffc00, "cto.w", "r0:5,r5:5", 0, 0, 0, 0 },
@@ -367,8 +387,6 @@ static struct loongarch_opcode loongarch_fix_opcodes[] =
{ 0x00005400, 0xfffffc00, "bitrev.d", "r0:5,r5:5", 0, 0, 0, 0 },
{ 0x00005800, 0xfffffc00, "ext.w.h", "r0:5,r5:5", 0, 0, 0, 0 },
{ 0x00005c00, 0xfffffc00, "ext.w.b", "r0:5,r5:5", 0, 0, 0, 0 },
- /* or %1,%2,$r0 */
- { 0x00150000, 0xfffffc00, "move", "r0:5,r5:5", 0, 0, 0, 0 },
{ 0x00006000, 0xfffffc00, "rdtimel.w", "r0:5,r5:5", 0, 0, 0, 0 },
{ 0x00006400, 0xfffffc00, "rdtimeh.w", "r0:5,r5:5", 0, 0, 0, 0 },
{ 0x00006800, 0xfffffc00, "rdtime.d", "r0:5,r5:5", 0, 0, 0, 0 },
@@ -2324,6 +2342,7 @@ static struct loongarch_opcode loongarch_lasx_opcodes[] =
struct loongarch_ase loongarch_ASEs[] =
{
{ &LARCH_opts.ase_ilp32, loongarch_macro_opcodes, 0, 0, { 0 }, 0, 0 },
+ { &LARCH_opts.ase_ilp32, loongarch_alias_opcodes, 0, 0, { 0 }, 0, 0 },
{ &LARCH_opts.ase_ilp32, loongarch_imm_opcodes, 0, 0, { 0 }, 0, 0 },
{ &LARCH_opts.ase_ilp32, loongarch_privilege_opcodes, 0, 0, { 0 }, 0, 0 },
{ &LARCH_opts.ase_ilp32, loongarch_load_store_opcodes, 0, 0, { 0 }, 0, 0 },
--
2.40.0
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v7 2/7] opcodes/loongarch: remove unused code
2023-06-29 16:34 [PATCH v7 0/7] LoongArch: disassembler improvements & deprecate old register aliases WANG Xuerui
2023-06-29 16:34 ` [PATCH v7 1/7] LoongArch: support disassembling certain pseudo-instructions WANG Xuerui
@ 2023-06-29 16:34 ` WANG Xuerui
2023-06-29 16:35 ` [PATCH v7 3/7] opcodes/loongarch: implement style support in the disassembler WANG Xuerui
` (4 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: WANG Xuerui @ 2023-06-29 16:34 UTC (permalink / raw)
To: binutils
Cc: Chenghua Xu, Zhensong Liu, Qinggang Meng, Lulu Cheng,
Fangrui Song, Xi Ruoyao, WANG Xuerui
From: WANG Xuerui <git@xen0n.name>
Remove some unused declarations and code.
include/ChangeLog:
* opcode/loongarch.h: Remove unused declarations.
opcodes/ChangeLog:
* loongarch-dis.c (loongarch_parse_dis_options): Remove.
(my_print_address_func): Likewise.
(loongarch_disassemble_one): Likewise.
Signed-off-by: WANG Xuerui <git@xen0n.name>
---
include/opcode/loongarch.h | 5 -----
opcodes/loongarch-dis.c | 35 -----------------------------------
2 files changed, 40 deletions(-)
diff --git a/include/opcode/loongarch.h b/include/opcode/loongarch.h
index 60812fb4b1f..e9632ad3361 100644
--- a/include/opcode/loongarch.h
+++ b/include/opcode/loongarch.h
@@ -176,11 +176,6 @@ dec2 : [1-9][0-9]?
extern void loongarch_eliminate_adjacent_repeat_char (char *dest, char c);
- extern int loongarch_parse_dis_options (const char *opts_in);
- extern void loongarch_disassemble_one (
- int64_t pc, insn_t insn,
- int (*fprintf_func) (void *stream, const char *format, ...), void *stream);
-
extern const char *const loongarch_r_normal_name[32];
extern const char *const loongarch_r_lp64_name[32];
extern const char *const loongarch_r_lp64_name1[32];
diff --git a/opcodes/loongarch-dis.c b/opcodes/loongarch-dis.c
index 3a08da14763..116b6667128 100644
--- a/opcodes/loongarch-dis.c
+++ b/opcodes/loongarch-dis.c
@@ -322,38 +322,3 @@ with the -M switch (multiple options should be separated by commas):\n"));
numeric Print numeric register names, rather than ABI names.\n"));
fprintf (stream, _("\n"));
}
-
-int
-loongarch_parse_dis_options (const char *opts_in)
-{
- return parse_loongarch_dis_options (opts_in);
-}
-
-static void
-my_print_address_func (bfd_vma addr, struct disassemble_info *dinfo)
-{
- dinfo->fprintf_func (dinfo->stream, "0x%llx", (long long) addr);
-}
-
-void
-loongarch_disassemble_one (int64_t pc, insn_t insn,
- int (*fprintf_func) (void *stream,
- const char *format, ...),
- void *stream)
-{
- static struct disassemble_info my_disinfo =
- {
- .print_address_func = my_print_address_func,
- };
- static int not_init_yet = 1;
- if (not_init_yet)
- {
- loongarch_parse_dis_options (NULL);
- not_init_yet = 0;
- }
-
- my_disinfo.fprintf_func = fprintf_func;
- my_disinfo.stream = stream;
- my_disinfo.target = pc;
- disassemble_one (insn, &my_disinfo);
-}
--
2.40.0
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v7 3/7] opcodes/loongarch: implement style support in the disassembler
2023-06-29 16:34 [PATCH v7 0/7] LoongArch: disassembler improvements & deprecate old register aliases WANG Xuerui
2023-06-29 16:34 ` [PATCH v7 1/7] LoongArch: support disassembling certain pseudo-instructions WANG Xuerui
2023-06-29 16:34 ` [PATCH v7 2/7] opcodes/loongarch: remove unused code WANG Xuerui
@ 2023-06-29 16:35 ` WANG Xuerui
2023-06-29 16:35 ` [PATCH v7 4/7] opcodes/loongarch: style disassembled address offsets as such WANG Xuerui
` (3 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: WANG Xuerui @ 2023-06-29 16:35 UTC (permalink / raw)
To: binutils
Cc: Chenghua Xu, Zhensong Liu, Qinggang Meng, Lulu Cheng,
Fangrui Song, Xi Ruoyao, WANG Xuerui
From: WANG Xuerui <git@xen0n.name>
Update the LoongArch disassembler to supply style information to the
disassembler output. The output formatting remains unchanged.
opcodes/ChangeLog:
* disassemble.c: Mark LoongArch as created_styled_output=true.
* loongarch-dis.c (dis_one_arg): Use fprintf_styled_func
throughout with proper styles.
Signed-off-by: WANG Xuerui <git@xen0n.name>
---
opcodes/disassemble.c | 5 +++++
opcodes/loongarch-dis.c | 45 ++++++++++++++++++++---------------------
2 files changed, 27 insertions(+), 23 deletions(-)
diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c
index 03cfccc562e..7a4a641c2b9 100644
--- a/opcodes/disassemble.c
+++ b/opcodes/disassemble.c
@@ -647,6 +647,11 @@ disassemble_init_for_target (struct disassemble_info * info)
info->skip_zeroes = 16;
break;
#endif
+#ifdef ARCH_loongarch
+ case bfd_arch_loongarch:
+ info->created_styled_output = true;
+ break;
+#endif
#ifdef ARCH_tic4x
case bfd_arch_tic4x:
info->skip_zeroes = 32;
diff --git a/opcodes/loongarch-dis.c b/opcodes/loongarch-dis.c
index 116b6667128..8d44dcebb4c 100644
--- a/opcodes/loongarch-dis.c
+++ b/opcodes/loongarch-dis.c
@@ -138,7 +138,7 @@ dis_one_arg (char esc1, char esc2, const char *bit_field,
if (esc1)
{
if (need_comma)
- info->fprintf_func (info->stream, ", ");
+ info->fprintf_styled_func (info->stream, dis_style_text, ", ");
need_comma = 1;
imm = loongarch_decode_imm (bit_field, insn, 1);
u_imm = loongarch_decode_imm (bit_field, insn, 0);
@@ -147,42 +147,45 @@ dis_one_arg (char esc1, char esc2, const char *bit_field,
switch (esc1)
{
case 'r':
- info->fprintf_func (info->stream, "%s", loongarch_r_disname[u_imm]);
+ info->fprintf_styled_func (info->stream, dis_style_register, "%s", loongarch_r_disname[u_imm]);
break;
case 'f':
switch (esc2)
{
case 'c':
- info->fprintf_func (info->stream, "%s", loongarch_fc_disname[u_imm]);
+ info->fprintf_styled_func (info->stream, dis_style_register, "%s", loongarch_fc_disname[u_imm]);
break;
default:
- info->fprintf_func (info->stream, "%s", loongarch_f_disname[u_imm]);
+ info->fprintf_styled_func (info->stream, dis_style_register, "%s", loongarch_f_disname[u_imm]);
}
break;
case 'c':
switch (esc2)
{
case 'r':
- info->fprintf_func (info->stream, "%s", loongarch_cr_disname[u_imm]);
+ info->fprintf_styled_func (info->stream, dis_style_register, "%s", loongarch_cr_disname[u_imm]);
break;
default:
- info->fprintf_func (info->stream, "%s", loongarch_c_disname[u_imm]);
+ info->fprintf_styled_func (info->stream, dis_style_register, "%s", loongarch_c_disname[u_imm]);
}
break;
case 'v':
- info->fprintf_func (info->stream, "%s", loongarch_v_disname[u_imm]);
+ info->fprintf_styled_func (info->stream, dis_style_register, "%s", loongarch_v_disname[u_imm]);
break;
case 'x':
- info->fprintf_func (info->stream, "%s", loongarch_x_disname[u_imm]);
+ info->fprintf_styled_func (info->stream, dis_style_register, "%s", loongarch_x_disname[u_imm]);
break;
case 'u':
- info->fprintf_func (info->stream, "0x%x", u_imm);
+ info->fprintf_styled_func (info->stream, dis_style_immediate, "0x%x", u_imm);
break;
case 's':
if (imm == 0)
- info->fprintf_func (info->stream, "%d", imm);
+ info->fprintf_styled_func (info->stream, dis_style_immediate, "%d", imm);
else
- info->fprintf_func (info->stream, "%d(0x%x)", imm, u_imm);
+ {
+ info->fprintf_styled_func (info->stream, dis_style_immediate, "%d", imm);
+ info->fprintf_styled_func (info->stream, dis_style_text, "(0x%x)", u_imm);
+ }
switch (esc2)
{
case 'b':
@@ -236,44 +239,40 @@ disassemble_one (insn_t insn, struct disassemble_info *info)
for (i = 31; 0 <= i; i--)
{
if (t & insn)
- info->fprintf_func (info->stream, "1");
+ info->fprintf_styled_func (info->stream, dis_style_text, "1");
else
- info->fprintf_func (info->stream, "0");
+ info->fprintf_styled_func (info->stream, dis_style_text, "0");
if (have_space[i])
- info->fprintf_func (info->stream, " ");
+ info->fprintf_styled_func (info->stream, dis_style_text, " ");
t = t >> 1;
}
- info->fprintf_func (info->stream, "\t");
+ info->fprintf_styled_func (info->stream, dis_style_text, "\t");
#endif
if (!opc)
{
info->insn_type = dis_noninsn;
- info->fprintf_func (info->stream, "0x%08x", insn);
+ info->fprintf_styled_func (info->stream, dis_style_immediate, "0x%08x", insn);
return;
}
info->insn_type = dis_nonbranch;
- info->fprintf_func (info->stream, "%-12s", opc->name);
+ info->fprintf_styled_func (info->stream, dis_style_mnemonic, "%-12s", opc->name);
{
char *fake_args = xmalloc (strlen (opc->format) + 1);
const char *fake_arg_strs[MAX_ARG_NUM_PLUS_2];
strcpy (fake_args, opc->format);
if (0 < loongarch_split_args_by_comma (fake_args, fake_arg_strs))
- info->fprintf_func (info->stream, "\t");
+ info->fprintf_styled_func (info->stream, dis_style_text, "\t");
info->private_data = &insn;
loongarch_foreach_args (opc->format, fake_arg_strs, dis_one_arg, info);
free (fake_args);
}
- if (info->insn_type == dis_branch || info->insn_type == dis_condbranch
- /* Someother if we have extra info to print. */)
- info->fprintf_func (info->stream, "\t#");
-
if (info->insn_type == dis_branch || info->insn_type == dis_condbranch)
{
- info->fprintf_func (info->stream, " ");
+ info->fprintf_styled_func (info->stream, dis_style_comment_start, "\t# ");
info->print_address_func (info->target, info);
}
}
--
2.40.0
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v7 4/7] opcodes/loongarch: style disassembled address offsets as such
2023-06-29 16:34 [PATCH v7 0/7] LoongArch: disassembler improvements & deprecate old register aliases WANG Xuerui
` (2 preceding siblings ...)
2023-06-29 16:35 ` [PATCH v7 3/7] opcodes/loongarch: implement style support in the disassembler WANG Xuerui
@ 2023-06-29 16:35 ` WANG Xuerui
2023-06-29 16:35 ` [PATCH v7 5/7] opcodes/loongarch: do not print hex notation for signed immediates WANG Xuerui
` (2 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: WANG Xuerui @ 2023-06-29 16:35 UTC (permalink / raw)
To: binutils
Cc: Chenghua Xu, Zhensong Liu, Qinggang Meng, Lulu Cheng,
Fangrui Song, Xi Ruoyao, WANG Xuerui
From: WANG Xuerui <git@xen0n.name>
Add a modifier char 'o' telling the disassembler to print the immediate
using the address offset style, and mark the memory access instructions'
offset operands as such.
opcodes/ChangeLog:
* loongarch-dis.c (dis_one_arg): Style disassembled address
offsets as such when the operand has a modifier char 'o'.
* loongarch-opc.c: Add 'o' to operands that represent address
offsets.
Signed-off-by: WANG Xuerui <git@xen0n.name>
---
opcodes/loongarch-dis.c | 19 +++++++++++++---
opcodes/loongarch-opc.c | 50 ++++++++++++++++++++---------------------
2 files changed, 41 insertions(+), 28 deletions(-)
diff --git a/opcodes/loongarch-dis.c b/opcodes/loongarch-dis.c
index 8d44dcebb4c..11e410f176a 100644
--- a/opcodes/loongarch-dis.c
+++ b/opcodes/loongarch-dis.c
@@ -134,6 +134,7 @@ dis_one_arg (char esc1, char esc2, const char *bit_field,
struct disassemble_info *info = context;
insn_t insn = *(insn_t *) info->private_data;
int32_t imm, u_imm;
+ enum disassembler_style style;
if (esc1)
{
@@ -176,14 +177,26 @@ dis_one_arg (char esc1, char esc2, const char *bit_field,
info->fprintf_styled_func (info->stream, dis_style_register, "%s", loongarch_x_disname[u_imm]);
break;
case 'u':
- info->fprintf_styled_func (info->stream, dis_style_immediate, "0x%x", u_imm);
+ style = esc2 == 'o' ? dis_style_address_offset : dis_style_immediate;
+ info->fprintf_styled_func (info->stream, style, "0x%x", u_imm);
break;
case 's':
+ switch (esc2)
+ {
+ case 'b':
+ case 'o':
+ /* Both represent address offsets. */
+ style = dis_style_address_offset;
+ break;
+ default:
+ style = dis_style_immediate;
+ break;
+ }
if (imm == 0)
- info->fprintf_styled_func (info->stream, dis_style_immediate, "%d", imm);
+ info->fprintf_styled_func (info->stream, style, "%d", imm);
else
{
- info->fprintf_styled_func (info->stream, dis_style_immediate, "%d", imm);
+ info->fprintf_styled_func (info->stream, style, "%d", imm);
info->fprintf_styled_func (info->stream, dis_style_text, "(0x%x)", u_imm);
}
switch (esc2)
diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c
index 3d1d2c761a5..8be227cd9a9 100644
--- a/opcodes/loongarch-opc.c
+++ b/opcodes/loongarch-opc.c
@@ -784,26 +784,26 @@ static struct loongarch_opcode loongarch_4opt_double_float_opcodes[] =
static struct loongarch_opcode loongarch_load_store_opcodes[] =
{
/* match, mask, name, format, macro, include, exclude, pinfo. */
- { 0x20000000, 0xff000000, "ll.w", "r0:5,r5:5,s10:14<<2", 0, 0, 0, 0 },
- { 0x21000000, 0xff000000, "sc.w", "r0:5,r5:5,s10:14<<2", 0, 0, 0, 0 },
- { 0x22000000, 0xff000000, "ll.d", "r0:5,r5:5,s10:14<<2", 0, 0, 0, 0 },
- { 0x23000000, 0xff000000, "sc.d", "r0:5,r5:5,s10:14<<2", 0, 0, 0, 0 },
- { 0x24000000, 0xff000000, "ldptr.w", "r0:5,r5:5,s10:14<<2", 0, 0, 0, 0 },
- { 0x25000000, 0xff000000, "stptr.w", "r0:5,r5:5,s10:14<<2", 0, 0, 0, 0 },
- { 0x26000000, 0xff000000, "ldptr.d", "r0:5,r5:5,s10:14<<2", 0, 0, 0, 0 },
- { 0x27000000, 0xff000000, "stptr.d", "r0:5,r5:5,s10:14<<2", 0, 0, 0, 0 },
- { 0x28000000, 0xffc00000, "ld.b", "r0:5,r5:5,s10:12", 0, 0, 0, 0 },
- { 0x28400000, 0xffc00000, "ld.h", "r0:5,r5:5,s10:12", 0, 0, 0, 0 },
- { 0x28800000, 0xffc00000, "ld.w", "r0:5,r5:5,s10:12", 0, 0, 0, 0 },
- { 0x28c00000, 0xffc00000, "ld.d", "r0:5,r5:5,s10:12", 0, 0, 0, 0 },
- { 0x29000000, 0xffc00000, "st.b", "r0:5,r5:5,s10:12", 0, 0, 0, 0 },
- { 0x29400000, 0xffc00000, "st.h", "r0:5,r5:5,s10:12", 0, 0, 0, 0 },
- { 0x29800000, 0xffc00000, "st.w", "r0:5,r5:5,s10:12", 0, 0, 0, 0 },
- { 0x29c00000, 0xffc00000, "st.d", "r0:5,r5:5,s10:12", 0, 0, 0, 0 },
- { 0x2a000000, 0xffc00000, "ld.bu", "r0:5,r5:5,s10:12", 0, 0, 0, 0 },
- { 0x2a400000, 0xffc00000, "ld.hu", "r0:5,r5:5,s10:12", 0, 0, 0, 0 },
- { 0x2a800000, 0xffc00000, "ld.wu", "r0:5,r5:5,s10:12", 0, 0, 0, 0 },
- { 0x2ac00000, 0xffc00000, "preld", "u0:5,r5:5,s10:12", 0, 0, 0, 0 },
+ { 0x20000000, 0xff000000, "ll.w", "r0:5,r5:5,so10:14<<2", 0, 0, 0, 0 },
+ { 0x21000000, 0xff000000, "sc.w", "r0:5,r5:5,so10:14<<2", 0, 0, 0, 0 },
+ { 0x22000000, 0xff000000, "ll.d", "r0:5,r5:5,so10:14<<2", 0, 0, 0, 0 },
+ { 0x23000000, 0xff000000, "sc.d", "r0:5,r5:5,so10:14<<2", 0, 0, 0, 0 },
+ { 0x24000000, 0xff000000, "ldptr.w", "r0:5,r5:5,so10:14<<2", 0, 0, 0, 0 },
+ { 0x25000000, 0xff000000, "stptr.w", "r0:5,r5:5,so10:14<<2", 0, 0, 0, 0 },
+ { 0x26000000, 0xff000000, "ldptr.d", "r0:5,r5:5,so10:14<<2", 0, 0, 0, 0 },
+ { 0x27000000, 0xff000000, "stptr.d", "r0:5,r5:5,so10:14<<2", 0, 0, 0, 0 },
+ { 0x28000000, 0xffc00000, "ld.b", "r0:5,r5:5,so10:12", 0, 0, 0, 0 },
+ { 0x28400000, 0xffc00000, "ld.h", "r0:5,r5:5,so10:12", 0, 0, 0, 0 },
+ { 0x28800000, 0xffc00000, "ld.w", "r0:5,r5:5,so10:12", 0, 0, 0, 0 },
+ { 0x28c00000, 0xffc00000, "ld.d", "r0:5,r5:5,so10:12", 0, 0, 0, 0 },
+ { 0x29000000, 0xffc00000, "st.b", "r0:5,r5:5,so10:12", 0, 0, 0, 0 },
+ { 0x29400000, 0xffc00000, "st.h", "r0:5,r5:5,so10:12", 0, 0, 0, 0 },
+ { 0x29800000, 0xffc00000, "st.w", "r0:5,r5:5,so10:12", 0, 0, 0, 0 },
+ { 0x29c00000, 0xffc00000, "st.d", "r0:5,r5:5,so10:12", 0, 0, 0, 0 },
+ { 0x2a000000, 0xffc00000, "ld.bu", "r0:5,r5:5,so10:12", 0, 0, 0, 0 },
+ { 0x2a400000, 0xffc00000, "ld.hu", "r0:5,r5:5,so10:12", 0, 0, 0, 0 },
+ { 0x2a800000, 0xffc00000, "ld.wu", "r0:5,r5:5,so10:12", 0, 0, 0, 0 },
+ { 0x2ac00000, 0xffc00000, "preld", "u0:5,r5:5,so10:12", 0, 0, 0, 0 },
{ 0x38000000, 0xffff8000, "ldx.b", "r0:5,r5:5,r10:5", 0, 0, 0, 0 },
{ 0x38040000, 0xffff8000, "ldx.h", "r0:5,r5:5,r10:5", 0, 0, 0, 0 },
{ 0x38080000, 0xffff8000, "ldx.w", "r0:5,r5:5,r10:5", 0, 0, 0, 0 },
@@ -936,8 +936,8 @@ static struct loongarch_opcode loongarch_load_store_opcodes[] =
static struct loongarch_opcode loongarch_single_float_load_store_opcodes[] =
{
/* match, mask, name, format, macro, include, exclude, pinfo. */
- { 0x2b000000, 0xffc00000, "fld.s", "f0:5,r5:5,s10:12", 0, 0, 0, 0 },
- { 0x2b400000, 0xffc00000, "fst.s", "f0:5,r5:5,s10:12", 0, 0, 0, 0 },
+ { 0x2b000000, 0xffc00000, "fld.s", "f0:5,r5:5,so10:12", 0, 0, 0, 0 },
+ { 0x2b400000, 0xffc00000, "fst.s", "f0:5,r5:5,so10:12", 0, 0, 0, 0 },
{ 0x38300000, 0xffff8000, "fldx.s", "f0:5,r5:5,r10:5", 0, &LARCH_opts.ase_lp64, 0, 0 },
{ 0x38380000, 0xffff8000, "fstx.s", "f0:5,r5:5,r10:5", 0, &LARCH_opts.ase_lp64, 0, 0 },
{ 0x38740000, 0xffff8000, "fldgt.s", "f0:5,r5:5,r10:5", 0, &LARCH_opts.ase_lp64, 0, 0 },
@@ -950,8 +950,8 @@ static struct loongarch_opcode loongarch_single_float_load_store_opcodes[] =
static struct loongarch_opcode loongarch_double_float_load_store_opcodes[] =
{
/* match, mask, name, format, macro, include, exclude, pinfo. */
- { 0x2b800000, 0xffc00000, "fld.d", "f0:5,r5:5,s10:12", 0, 0, 0, 0 },
- { 0x2bc00000, 0xffc00000, "fst.d", "f0:5,r5:5,s10:12", 0, 0, 0, 0 },
+ { 0x2b800000, 0xffc00000, "fld.d", "f0:5,r5:5,so10:12", 0, 0, 0, 0 },
+ { 0x2bc00000, 0xffc00000, "fst.d", "f0:5,r5:5,so10:12", 0, 0, 0, 0 },
{ 0x38340000, 0xffff8000, "fldx.d", "f0:5,r5:5,r10:5", 0, &LARCH_opts.ase_lp64, 0, 0 },
{ 0x383c0000, 0xffff8000, "fstx.d", "f0:5,r5:5,r10:5", 0, &LARCH_opts.ase_lp64, 0, 0 },
{ 0x38748000, 0xffff8000, "fldgt.d", "f0:5,r5:5,r10:5", 0, &LARCH_opts.ase_lp64, 0, 0 },
@@ -977,7 +977,7 @@ static struct loongarch_opcode loongarch_jmp_opcodes[] =
{ 0x40000000, 0xfc000000, "beqz", "r5:5,sb0:5|10:16<<2", 0, 0, 0, 0 },
{ 0x0, 0x0, "bnez", "r,la", "bnez %1,%%b21(%2)", 0, 0, 0 },
{ 0x44000000, 0xfc000000, "bnez", "r5:5,sb0:5|10:16<<2", 0, 0, 0, 0 },
- { 0x4c000000, 0xfc000000, "jirl", "r0:5,r5:5,s10:16<<2", 0, 0, 0, 0 },
+ { 0x4c000000, 0xfc000000, "jirl", "r0:5,r5:5,so10:16<<2", 0, 0, 0, 0 },
{ 0x0, 0x0, "b", "la", "b %%b26(%1)", 0, 0, 0 },
{ 0x50000000, 0xfc000000, "b", "sb0:10|10:16<<2", 0, 0, 0, 0 },
{ 0x0, 0x0, "bl", "la", "bl %%b26(%1)", 0, 0, 0 },
--
2.40.0
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v7 5/7] opcodes/loongarch: do not print hex notation for signed immediates
2023-06-29 16:34 [PATCH v7 0/7] LoongArch: disassembler improvements & deprecate old register aliases WANG Xuerui
` (3 preceding siblings ...)
2023-06-29 16:35 ` [PATCH v7 4/7] opcodes/loongarch: style disassembled address offsets as such WANG Xuerui
@ 2023-06-29 16:35 ` WANG Xuerui
2023-06-29 16:35 ` [PATCH v7 6/7] opcodes/loongarch: print unrecognized insn words with the .word directive WANG Xuerui
2023-06-29 16:35 ` [PATCH v7 7/7] LoongArch: Deprecate $v[01], $fv[01] and $x names per spec WANG Xuerui
6 siblings, 0 replies; 8+ messages in thread
From: WANG Xuerui @ 2023-06-29 16:35 UTC (permalink / raw)
To: binutils
Cc: Chenghua Xu, Zhensong Liu, Qinggang Meng, Lulu Cheng,
Fangrui Song, Xi Ruoyao, WANG Xuerui
From: WANG Xuerui <git@xen0n.name>
The additional hex notation was minimally useful when one had to
inspect code with heavy bit manipulation, or of unclear signedness, but
it clutters the output, and the style is not regular assembly language
syntax either.
Precisely how one approaches the original use case is not taken care of
in this patch (maybe we want a disassembler option forcing a certain
style for immediates, like for example printing every immediate in
decimal or hexadecimal notation), but at least let's stop the current
practice.
ChangeLog:
* testsuite/gas/loongarch/imm_ins.d: Update test case.
* testsuite/gas/loongarch/imm_ins_32.d: Likewise.
* testsuite/gas/loongarch/imm_op.d: Likewise.
* testsuite/gas/loongarch/jmp_op.d: Likewise.
* testsuite/gas/loongarch/load_store_op.d: Likewise.
* testsuite/gas/loongarch/macro_op.d: Likewise.
* testsuite/gas/loongarch/macro_op_32.d: Likewise.
* testsuite/gas/loongarch/privilege_op.d: Likewise.
* testsuite/gas/loongarch/uleb128.d: Likewise.
* testsuite/gas/loongarch/vector.d: Likewise.
ld/ChangeLog:
* testsuite/ld-loongarch-elf/jmp_op.d: Update test case.
* testsuite/ld-loongarch-elf/macro_op.d: Likewise.
* testsuite/ld-loongarch-elf/macro_op_32.d: Likewise.
opcodes/ChangeLog:
* loongarch-dis.c (dis_one_arg): Remove the "(0x%x)" part from
disassembly output of signed immediate operands.
Signed-off-by: WANG Xuerui <git@xen0n.name>
---
gas/testsuite/gas/loongarch/imm_ins.d | 82 ++++++------
gas/testsuite/gas/loongarch/imm_ins_32.d | 52 ++++----
gas/testsuite/gas/loongarch/imm_op.d | 44 +++---
gas/testsuite/gas/loongarch/jmp_op.d | 38 +++---
gas/testsuite/gas/loongarch/load_store_op.d | 80 +++++------
gas/testsuite/gas/loongarch/macro_op.d | 4 +-
gas/testsuite/gas/loongarch/macro_op_32.d | 4 +-
gas/testsuite/gas/loongarch/privilege_op.d | 8 +-
gas/testsuite/gas/loongarch/uleb128.d | 2 +-
gas/testsuite/gas/loongarch/vector.d | 140 ++++++++++----------
ld/testsuite/ld-loongarch-elf/jmp_op.d | 38 +++---
ld/testsuite/ld-loongarch-elf/macro_op.d | 4 +-
ld/testsuite/ld-loongarch-elf/macro_op_32.d | 4 +-
opcodes/loongarch-dis.c | 8 +-
14 files changed, 251 insertions(+), 257 deletions(-)
diff --git a/gas/testsuite/gas/loongarch/imm_ins.d b/gas/testsuite/gas/loongarch/imm_ins.d
index c588b5e0e25..f00110cd8a3 100644
--- a/gas/testsuite/gas/loongarch/imm_ins.d
+++ b/gas/testsuite/gas/loongarch/imm_ins.d
@@ -9,10 +9,10 @@ Disassembly of section .text:
00000000.* <.text>:
[ ]+0:[ ]+03848c0c[ ]+li.w[ ]+\$t0,[ ]+0x123
-[ ]+4:[ ]+15ffe00d[ ]+lu12i.w[ ]+\$t1,[ ]+-256\(0xfff00\)
-[ ]+8:[ ]+16001fed[ ]+lu32i.d[ ]+\$t1,[ ]+255\(0xff\)
-[ ]+c:[ ]+02bffc0e[ ]+li.w[ ]+\$t2,[ ]+-1\(0xfff\)
-[ ]+10:[ ]+1601ffee[ ]+lu32i.d[ ]+\$t2,[ ]+4095\(0xfff\)
+[ ]+4:[ ]+15ffe00d[ ]+lu12i.w[ ]+\$t1,[ ]+-256
+[ ]+8:[ ]+16001fed[ ]+lu32i.d[ ]+\$t1,[ ]+255
+[ ]+c:[ ]+02bffc0e[ ]+li.w[ ]+\$t2,[ ]+-1
+[ ]+10:[ ]+1601ffee[ ]+lu32i.d[ ]+\$t2,[ ]+4095
[ ]+14:[ ]+0004b58b[ ]+alsl.w[ ]+\$a7,[ ]+\$t0,[ ]+\$t1,[ ]+0x2
[ ]+18:[ ]+0006b58b[ ]+alsl.wu[ ]+\$a7,[ ]+\$t0,[ ]+\$t1,[ ]+0x2
[ ]+1c:[ ]+0009358b[ ]+bytepick.w[ ]+\$a7,[ ]+\$t0,[ ]+\$t1,[ ]+0x2
@@ -31,50 +31,50 @@ Disassembly of section .text:
[ ]+50:[ ]+008209ac[ ]+bstrins.d[ ]+\$t0,[ ]+\$t1,[ ]+0x2,[ ]+0x2
[ ]+54:[ ]+00c209ac[ ]+bstrpick.d[ ]+\$t0,[ ]+\$t1,[ ]+0x2,[ ]+0x2
[ ]+58:[ ]+00c209ac[ ]+bstrpick.d[ ]+\$t0,[ ]+\$t1,[ ]+0x2,[ ]+0x2
-[ ]+5c:[ ]+02048dac[ ]+slti[ ]+\$t0,[ ]+\$t1,[ ]+291\(0x123\)
-[ ]+60:[ ]+02448dac[ ]+sltui[ ]+\$t0,[ ]+\$t1,[ ]+291\(0x123\)
-[ ]+64:[ ]+02848dac[ ]+addi.w[ ]+\$t0,[ ]+\$t1,[ ]+291\(0x123\)
-[ ]+68:[ ]+02c48dac[ ]+addi.d[ ]+\$t0,[ ]+\$t1,[ ]+291\(0x123\)
-[ ]+6c:[ ]+03048dac[ ]+lu52i.d[ ]+\$t0,[ ]+\$t1,[ ]+291\(0x123\)
+[ ]+5c:[ ]+02048dac[ ]+slti[ ]+\$t0,[ ]+\$t1,[ ]+291
+[ ]+60:[ ]+02448dac[ ]+sltui[ ]+\$t0,[ ]+\$t1,[ ]+291
+[ ]+64:[ ]+02848dac[ ]+addi.w[ ]+\$t0,[ ]+\$t1,[ ]+291
+[ ]+68:[ ]+02c48dac[ ]+addi.d[ ]+\$t0,[ ]+\$t1,[ ]+291
+[ ]+6c:[ ]+03048dac[ ]+lu52i.d[ ]+\$t0,[ ]+\$t1,[ ]+291
[ ]+70:[ ]+034009ac[ ]+andi[ ]+\$t0,[ ]+\$t1,[ ]+0x2
[ ]+74:[ ]+038009ac[ ]+ori[ ]+\$t0,[ ]+\$t1,[ ]+0x2
[ ]+78:[ ]+03c009ac[ ]+xori[ ]+\$t0,[ ]+\$t1,[ ]+0x2
-[ ]+7c:[ ]+100009ac[ ]+addu16i.d[ ]+\$t0,[ ]+\$t1,[ ]+2\(0x2\)
-[ ]+80:[ ]+1400246c[ ]+lu12i.w[ ]+\$t0,[ ]+291\(0x123\)
-[ ]+84:[ ]+1600246c[ ]+lu32i.d[ ]+\$t0,[ ]+291\(0x123\)
-[ ]+88:[ ]+1800246c[ ]+pcaddi[ ]+\$t0,[ ]+291\(0x123\)
-[ ]+8c:[ ]+1a00246c[ ]+pcalau12i[ ]+\$t0,[ ]+291\(0x123\)
-[ ]+90:[ ]+1c00246c[ ]+pcaddu12i[ ]+\$t0,[ ]+291\(0x123\)
-[ ]+94:[ ]+1e00246c[ ]+pcaddu18i[ ]+\$t0,[ ]+291\(0x123\)
+[ ]+7c:[ ]+100009ac[ ]+addu16i.d[ ]+\$t0,[ ]+\$t1,[ ]+2
+[ ]+80:[ ]+1400246c[ ]+lu12i.w[ ]+\$t0,[ ]+291
+[ ]+84:[ ]+1600246c[ ]+lu32i.d[ ]+\$t0,[ ]+291
+[ ]+88:[ ]+1800246c[ ]+pcaddi[ ]+\$t0,[ ]+291
+[ ]+8c:[ ]+1a00246c[ ]+pcalau12i[ ]+\$t0,[ ]+291
+[ ]+90:[ ]+1c00246c[ ]+pcaddu12i[ ]+\$t0,[ ]+291
+[ ]+94:[ ]+1e00246c[ ]+pcaddu18i[ ]+\$t0,[ ]+291
[ ]+98:[ ]+04048c0c[ ]+csrrd[ ]+\$t0,[ ]+0x123
[ ]+9c:[ ]+04048c2c[ ]+csrwr[ ]+\$t0,[ ]+0x123
[ ]+a0:[ ]+040009ac[ ]+csrxchg[ ]+\$t0,[ ]+\$t1,[ ]+0x2
-[ ]+a4:[ ]+060009a2[ ]+cacop[ ]+0x2,[ ]+\$t1,[ ]+2\(0x2\)
+[ ]+a4:[ ]+060009a2[ ]+cacop[ ]+0x2,[ ]+\$t1,[ ]+2
[ ]+a8:[ ]+064009ac[ ]+lddir[ ]+\$t0,[ ]+\$t1,[ ]+0x2
[ ]+ac:[ ]+06440980[ ]+ldpte[ ]+\$t0,[ ]+0x2
[ ]+b0:[ ]+0649b9a2[ ]+invtlb[ ]+0x2,[ ]+\$t1,[ ]+\$t2
-[ ]+b4:[ ]+200101ac[ ]+ll.w[ ]+\$t0,[ ]+\$t1,[ ]+256\(0x100\)
-[ ]+b8:[ ]+210101ac[ ]+sc.w[ ]+\$t0,[ ]+\$t1,[ ]+256\(0x100\)
-[ ]+bc:[ ]+220101ac[ ]+ll.d[ ]+\$t0,[ ]+\$t1,[ ]+256\(0x100\)
-[ ]+c0:[ ]+230101ac[ ]+sc.d[ ]+\$t0,[ ]+\$t1,[ ]+256\(0x100\)
-[ ]+c4:[ ]+240101ac[ ]+ldptr.w[ ]+\$t0,[ ]+\$t1,[ ]+256\(0x100\)
-[ ]+c8:[ ]+250101ac[ ]+stptr.w[ ]+\$t0,[ ]+\$t1,[ ]+256\(0x100\)
-[ ]+cc:[ ]+260101ac[ ]+ldptr.d[ ]+\$t0,[ ]+\$t1,[ ]+256\(0x100\)
-[ ]+d0:[ ]+270101ac[ ]+stptr.d[ ]+\$t0,[ ]+\$t1,[ ]+256\(0x100\)
-[ ]+d4:[ ]+280401ac[ ]+ld.b[ ]+\$t0,[ ]+\$t1,[ ]+256\(0x100\)
-[ ]+d8:[ ]+284401ac[ ]+ld.h[ ]+\$t0,[ ]+\$t1,[ ]+256\(0x100\)
-[ ]+dc:[ ]+288401ac[ ]+ld.w[ ]+\$t0,[ ]+\$t1,[ ]+256\(0x100\)
-[ ]+e0:[ ]+28c401ac[ ]+ld.d[ ]+\$t0,[ ]+\$t1,[ ]+256\(0x100\)
-[ ]+e4:[ ]+290401ac[ ]+st.b[ ]+\$t0,[ ]+\$t1,[ ]+256\(0x100\)
-[ ]+e8:[ ]+294401ac[ ]+st.h[ ]+\$t0,[ ]+\$t1,[ ]+256\(0x100\)
-[ ]+ec:[ ]+298401ac[ ]+st.w[ ]+\$t0,[ ]+\$t1,[ ]+256\(0x100\)
-[ ]+f0:[ ]+29c401ac[ ]+st.d[ ]+\$t0,[ ]+\$t1,[ ]+256\(0x100\)
-[ ]+f4:[ ]+2a0401ac[ ]+ld.bu[ ]+\$t0,[ ]+\$t1,[ ]+256\(0x100\)
-[ ]+f8:[ ]+2a4401ac[ ]+ld.hu[ ]+\$t0,[ ]+\$t1,[ ]+256\(0x100\)
-[ ]+fc:[ ]+2a8401ac[ ]+ld.wu[ ]+\$t0,[ ]+\$t1,[ ]+256\(0x100\)
-[ ]+100:[ ]+2ac401a2[ ]+preld[ ]+0x2,[ ]+\$t1,[ ]+256\(0x100\)
+[ ]+b4:[ ]+200101ac[ ]+ll.w[ ]+\$t0,[ ]+\$t1,[ ]+256
+[ ]+b8:[ ]+210101ac[ ]+sc.w[ ]+\$t0,[ ]+\$t1,[ ]+256
+[ ]+bc:[ ]+220101ac[ ]+ll.d[ ]+\$t0,[ ]+\$t1,[ ]+256
+[ ]+c0:[ ]+230101ac[ ]+sc.d[ ]+\$t0,[ ]+\$t1,[ ]+256
+[ ]+c4:[ ]+240101ac[ ]+ldptr.w[ ]+\$t0,[ ]+\$t1,[ ]+256
+[ ]+c8:[ ]+250101ac[ ]+stptr.w[ ]+\$t0,[ ]+\$t1,[ ]+256
+[ ]+cc:[ ]+260101ac[ ]+ldptr.d[ ]+\$t0,[ ]+\$t1,[ ]+256
+[ ]+d0:[ ]+270101ac[ ]+stptr.d[ ]+\$t0,[ ]+\$t1,[ ]+256
+[ ]+d4:[ ]+280401ac[ ]+ld.b[ ]+\$t0,[ ]+\$t1,[ ]+256
+[ ]+d8:[ ]+284401ac[ ]+ld.h[ ]+\$t0,[ ]+\$t1,[ ]+256
+[ ]+dc:[ ]+288401ac[ ]+ld.w[ ]+\$t0,[ ]+\$t1,[ ]+256
+[ ]+e0:[ ]+28c401ac[ ]+ld.d[ ]+\$t0,[ ]+\$t1,[ ]+256
+[ ]+e4:[ ]+290401ac[ ]+st.b[ ]+\$t0,[ ]+\$t1,[ ]+256
+[ ]+e8:[ ]+294401ac[ ]+st.h[ ]+\$t0,[ ]+\$t1,[ ]+256
+[ ]+ec:[ ]+298401ac[ ]+st.w[ ]+\$t0,[ ]+\$t1,[ ]+256
+[ ]+f0:[ ]+29c401ac[ ]+st.d[ ]+\$t0,[ ]+\$t1,[ ]+256
+[ ]+f4:[ ]+2a0401ac[ ]+ld.bu[ ]+\$t0,[ ]+\$t1,[ ]+256
+[ ]+f8:[ ]+2a4401ac[ ]+ld.hu[ ]+\$t0,[ ]+\$t1,[ ]+256
+[ ]+fc:[ ]+2a8401ac[ ]+ld.wu[ ]+\$t0,[ ]+\$t1,[ ]+256
+[ ]+100:[ ]+2ac401a2[ ]+preld[ ]+0x2,[ ]+\$t1,[ ]+256
[ ]+104:[ ]+382c39a2[ ]+preldx[ ]+0x2,[ ]+\$t1,[ ]+\$t2
-[ ]+108:[ ]+2b048d8a[ ]+fld.s[ ]+\$ft2,[ ]+\$t0,[ ]+291\(0x123\)
-[ ]+10c:[ ]+2b448d8a[ ]+fst.s[ ]+\$ft2,[ ]+\$t0,[ ]+291\(0x123\)
-[ ]+110:[ ]+2b848d8a[ ]+fld.d[ ]+\$ft2,[ ]+\$t0,[ ]+291\(0x123\)
-[ ]+114:[ ]+2bc48d8a[ ]+fst.d[ ]+\$ft2,[ ]+\$t0,[ ]+291\(0x123\)
+[ ]+108:[ ]+2b048d8a[ ]+fld.s[ ]+\$ft2,[ ]+\$t0,[ ]+291
+[ ]+10c:[ ]+2b448d8a[ ]+fst.s[ ]+\$ft2,[ ]+\$t0,[ ]+291
+[ ]+110:[ ]+2b848d8a[ ]+fld.d[ ]+\$ft2,[ ]+\$t0,[ ]+291
+[ ]+114:[ ]+2bc48d8a[ ]+fst.d[ ]+\$ft2,[ ]+\$t0,[ ]+291
diff --git a/gas/testsuite/gas/loongarch/imm_ins_32.d b/gas/testsuite/gas/loongarch/imm_ins_32.d
index 5fd5835a342..dc2eeb9ed51 100644
--- a/gas/testsuite/gas/loongarch/imm_ins_32.d
+++ b/gas/testsuite/gas/loongarch/imm_ins_32.d
@@ -19,39 +19,39 @@ Disassembly of section .text:
[ ]+20:[ ]+0044898b[ ]+srli.w[ ]+\$a7,[ ]+\$t0,[ ]+0x2
[ ]+24:[ ]+004889ac[ ]+srai.w[ ]+\$t0,[ ]+\$t1,[ ]+0x2
[ ]+28:[ ]+006209ac[ ]+bstrins.w[ ]+\$t0,[ ]+\$t1,[ ]+0x2,[ ]+0x2
-[ ]+2c:[ ]+02048dac[ ]+slti[ ]+\$t0,[ ]+\$t1,[ ]+291\(0x123\)
-[ ]+30:[ ]+02448dac[ ]+sltui[ ]+\$t0,[ ]+\$t1,[ ]+291\(0x123\)
-[ ]+34:[ ]+02848dac[ ]+addi.w[ ]+\$t0,[ ]+\$t1,[ ]+291\(0x123\)
+[ ]+2c:[ ]+02048dac[ ]+slti[ ]+\$t0,[ ]+\$t1,[ ]+291
+[ ]+30:[ ]+02448dac[ ]+sltui[ ]+\$t0,[ ]+\$t1,[ ]+291
+[ ]+34:[ ]+02848dac[ ]+addi.w[ ]+\$t0,[ ]+\$t1,[ ]+291
[ ]+38:[ ]+034009ac[ ]+andi[ ]+\$t0,[ ]+\$t1,[ ]+0x2
[ ]+3c:[ ]+038009ac[ ]+ori[ ]+\$t0,[ ]+\$t1,[ ]+0x2
[ ]+40:[ ]+03c009ac[ ]+xori[ ]+\$t0,[ ]+\$t1,[ ]+0x2
-[ ]+44:[ ]+1400246c[ ]+lu12i.w[ ]+\$t0,[ ]+291\(0x123\)
-[ ]+48:[ ]+1800246c[ ]+pcaddi[ ]+\$t0,[ ]+291\(0x123\)
-[ ]+4c:[ ]+1a00246c[ ]+pcalau12i[ ]+\$t0,[ ]+291\(0x123\)
-[ ]+50:[ ]+1c00246c[ ]+pcaddu12i[ ]+\$t0,[ ]+291\(0x123\)
-[ ]+54:[ ]+1e00246c[ ]+pcaddu18i[ ]+\$t0,[ ]+291\(0x123\)
+[ ]+44:[ ]+1400246c[ ]+lu12i.w[ ]+\$t0,[ ]+291
+[ ]+48:[ ]+1800246c[ ]+pcaddi[ ]+\$t0,[ ]+291
+[ ]+4c:[ ]+1a00246c[ ]+pcalau12i[ ]+\$t0,[ ]+291
+[ ]+50:[ ]+1c00246c[ ]+pcaddu12i[ ]+\$t0,[ ]+291
+[ ]+54:[ ]+1e00246c[ ]+pcaddu18i[ ]+\$t0,[ ]+291
[ ]+58:[ ]+04048c0c[ ]+csrrd[ ]+\$t0,[ ]+0x123
[ ]+5c:[ ]+04048c2c[ ]+csrwr[ ]+\$t0,[ ]+0x123
[ ]+60:[ ]+040009ac[ ]+csrxchg[ ]+\$t0,[ ]+\$t1,[ ]+0x2
-[ ]+64:[ ]+060009a2[ ]+cacop[ ]+0x2,[ ]+\$t1,[ ]+2\(0x2\)
+[ ]+64:[ ]+060009a2[ ]+cacop[ ]+0x2,[ ]+\$t1,[ ]+2
[ ]+68:[ ]+064009ac[ ]+lddir[ ]+\$t0,[ ]+\$t1,[ ]+0x2
[ ]+6c:[ ]+06440980[ ]+ldpte[ ]+\$t0,[ ]+0x2
[ ]+70:[ ]+0649b9a2[ ]+invtlb[ ]+0x2,[ ]+\$t1,[ ]+\$t2
-[ ]+74:[ ]+200101ac[ ]+ll.w[ ]+\$t0,[ ]+\$t1,[ ]+256\(0x100\)
-[ ]+78:[ ]+210101ac[ ]+sc.w[ ]+\$t0,[ ]+\$t1,[ ]+256\(0x100\)
-[ ]+7c:[ ]+220101ac[ ]+ll.d[ ]+\$t0,[ ]+\$t1,[ ]+256\(0x100\)
-[ ]+80:[ ]+230101ac[ ]+sc.d[ ]+\$t0,[ ]+\$t1,[ ]+256\(0x100\)
-[ ]+84:[ ]+240101ac[ ]+ldptr.w[ ]+\$t0,[ ]+\$t1,[ ]+256\(0x100\)
-[ ]+88:[ ]+250101ac[ ]+stptr.w[ ]+\$t0,[ ]+\$t1,[ ]+256\(0x100\)
-[ ]+8c:[ ]+284401ac[ ]+ld.h[ ]+\$t0,[ ]+\$t1,[ ]+256\(0x100\)
-[ ]+90:[ ]+288401ac[ ]+ld.w[ ]+\$t0,[ ]+\$t1,[ ]+256\(0x100\)
-[ ]+94:[ ]+290401ac[ ]+st.b[ ]+\$t0,[ ]+\$t1,[ ]+256\(0x100\)
-[ ]+98:[ ]+294401ac[ ]+st.h[ ]+\$t0,[ ]+\$t1,[ ]+256\(0x100\)
-[ ]+9c:[ ]+298401ac[ ]+st.w[ ]+\$t0,[ ]+\$t1,[ ]+256\(0x100\)
-[ ]+a0:[ ]+2a0401ac[ ]+ld.bu[ ]+\$t0,[ ]+\$t1,[ ]+256\(0x100\)
-[ ]+a4:[ ]+2a4401ac[ ]+ld.hu[ ]+\$t0,[ ]+\$t1,[ ]+256\(0x100\)
-[ ]+a8:[ ]+2a8401ac[ ]+ld.wu[ ]+\$t0,[ ]+\$t1,[ ]+256\(0x100\)
-[ ]+ac:[ ]+2ac401a2[ ]+preld[ ]+0x2,[ ]+\$t1,[ ]+256\(0x100\)
+[ ]+74:[ ]+200101ac[ ]+ll.w[ ]+\$t0,[ ]+\$t1,[ ]+256
+[ ]+78:[ ]+210101ac[ ]+sc.w[ ]+\$t0,[ ]+\$t1,[ ]+256
+[ ]+7c:[ ]+220101ac[ ]+ll.d[ ]+\$t0,[ ]+\$t1,[ ]+256
+[ ]+80:[ ]+230101ac[ ]+sc.d[ ]+\$t0,[ ]+\$t1,[ ]+256
+[ ]+84:[ ]+240101ac[ ]+ldptr.w[ ]+\$t0,[ ]+\$t1,[ ]+256
+[ ]+88:[ ]+250101ac[ ]+stptr.w[ ]+\$t0,[ ]+\$t1,[ ]+256
+[ ]+8c:[ ]+284401ac[ ]+ld.h[ ]+\$t0,[ ]+\$t1,[ ]+256
+[ ]+90:[ ]+288401ac[ ]+ld.w[ ]+\$t0,[ ]+\$t1,[ ]+256
+[ ]+94:[ ]+290401ac[ ]+st.b[ ]+\$t0,[ ]+\$t1,[ ]+256
+[ ]+98:[ ]+294401ac[ ]+st.h[ ]+\$t0,[ ]+\$t1,[ ]+256
+[ ]+9c:[ ]+298401ac[ ]+st.w[ ]+\$t0,[ ]+\$t1,[ ]+256
+[ ]+a0:[ ]+2a0401ac[ ]+ld.bu[ ]+\$t0,[ ]+\$t1,[ ]+256
+[ ]+a4:[ ]+2a4401ac[ ]+ld.hu[ ]+\$t0,[ ]+\$t1,[ ]+256
+[ ]+a8:[ ]+2a8401ac[ ]+ld.wu[ ]+\$t0,[ ]+\$t1,[ ]+256
+[ ]+ac:[ ]+2ac401a2[ ]+preld[ ]+0x2,[ ]+\$t1,[ ]+256
[ ]+b0:[ ]+382c39a2[ ]+preldx[ ]+0x2,[ ]+\$t1,[ ]+\$t2
-[ ]+b4:[ ]+2b048d8a[ ]+fld.s[ ]+\$ft2,[ ]+\$t0,[ ]+291\(0x123\)
-[ ]+b8:[ ]+2b448d8a[ ]+fst.s[ ]+\$ft2,[ ]+\$t0,[ ]+291\(0x123\)
+[ ]+b4:[ ]+2b048d8a[ ]+fld.s[ ]+\$ft2,[ ]+\$t0,[ ]+291
+[ ]+b8:[ ]+2b448d8a[ ]+fst.s[ ]+\$ft2,[ ]+\$t0,[ ]+291
diff --git a/gas/testsuite/gas/loongarch/imm_op.d b/gas/testsuite/gas/loongarch/imm_op.d
index a017aaf5bf7..3d4cba45586 100644
--- a/gas/testsuite/gas/loongarch/imm_op.d
+++ b/gas/testsuite/gas/loongarch/imm_op.d
@@ -8,20 +8,20 @@ Disassembly of section .text:
00000000.* <.text>:
[ ]+0:[ ]+020000a4 [ ]+slti[ ]+[ ]+\$a0, \$a1, 0
-[ ]+4:[ ]+021ffca4 [ ]+slti[ ]+[ ]+\$a0, \$a1, 2047\(0x7ff\)
-[ ]+8:[ ]+022004a4 [ ]+slti[ ]+[ ]+\$a0, \$a1, -2047\(0x801\)
+[ ]+4:[ ]+021ffca4 [ ]+slti[ ]+[ ]+\$a0, \$a1, 2047
+[ ]+8:[ ]+022004a4 [ ]+slti[ ]+[ ]+\$a0, \$a1, -2047
[ ]+c:[ ]+024000a4 [ ]+sltui[ ]+[ ]+\$a0, \$a1, 0
-[ ]+10:[ ]+025ffca4 [ ]+sltui[ ]+[ ]+\$a0, \$a1, 2047\(0x7ff\)
-[ ]+14:[ ]+026004a4 [ ]+sltui[ ]+[ ]+\$a0, \$a1, -2047\(0x801\)
+[ ]+10:[ ]+025ffca4 [ ]+sltui[ ]+[ ]+\$a0, \$a1, 2047
+[ ]+14:[ ]+026004a4 [ ]+sltui[ ]+[ ]+\$a0, \$a1, -2047
[ ]+18:[ ]+028000a4 [ ]+addi.w[ ]+[ ]+\$a0, \$a1, 0
-[ ]+1c:[ ]+029ffca4 [ ]+addi.w[ ]+[ ]+\$a0, \$a1, 2047\(0x7ff\)
-[ ]+20:[ ]+02a004a4 [ ]+addi.w[ ]+[ ]+\$a0, \$a1, -2047\(0x801\)
+[ ]+1c:[ ]+029ffca4 [ ]+addi.w[ ]+[ ]+\$a0, \$a1, 2047
+[ ]+20:[ ]+02a004a4 [ ]+addi.w[ ]+[ ]+\$a0, \$a1, -2047
[ ]+24:[ ]+02c000a4 [ ]+addi.d[ ]+[ ]+\$a0, \$a1, 0
-[ ]+28:[ ]+02dffca4 [ ]+addi.d[ ]+[ ]+\$a0, \$a1, 2047\(0x7ff\)
-[ ]+2c:[ ]+02e004a4 [ ]+addi.d[ ]+[ ]+\$a0, \$a1, -2047\(0x801\)
+[ ]+28:[ ]+02dffca4 [ ]+addi.d[ ]+[ ]+\$a0, \$a1, 2047
+[ ]+2c:[ ]+02e004a4 [ ]+addi.d[ ]+[ ]+\$a0, \$a1, -2047
[ ]+30:[ ]+030000a4 [ ]+lu52i.d[ ]+[ ]+\$a0, \$a1, 0
-[ ]+34:[ ]+031ffca4 [ ]+lu52i.d[ ]+[ ]+\$a0, \$a1, 2047\(0x7ff\)
-[ ]+38:[ ]+032004a4 [ ]+lu52i.d[ ]+[ ]+\$a0, \$a1, -2047\(0x801\)
+[ ]+34:[ ]+031ffca4 [ ]+lu52i.d[ ]+[ ]+\$a0, \$a1, 2047
+[ ]+38:[ ]+032004a4 [ ]+lu52i.d[ ]+[ ]+\$a0, \$a1, -2047
[ ]+3c:[ ]+034000a4 [ ]+andi[ ]+[ ]+\$a0, \$a1, 0x0
[ ]+40:[ ]+035ffca4 [ ]+andi[ ]+[ ]+\$a0, \$a1, 0x7ff
[ ]+44:[ ]+038000a4 [ ]+ori[ ]+[ ]+\$a0, \$a1, 0x0
@@ -29,20 +29,20 @@ Disassembly of section .text:
[ ]+4c:[ ]+03c000a4 [ ]+xori[ ]+[ ]+\$a0, \$a1, 0x0
[ ]+50:[ ]+03dffca4 [ ]+xori[ ]+[ ]+\$a0, \$a1, 0x7ff
[ ]+54:[ ]+100000a4 [ ]+addu16i.d[ ]+[ ]+\$a0, \$a1, 0
-[ ]+58:[ ]+11fffca4 [ ]+addu16i.d[ ]+[ ]+\$a0, \$a1, 32767\(0x7fff\)
-[ ]+5c:[ ]+120004a4 [ ]+addu16i.d[ ]+[ ]+\$a0, \$a1, -32767\(0x8001\)
+[ ]+58:[ ]+11fffca4 [ ]+addu16i.d[ ]+[ ]+\$a0, \$a1, 32767
+[ ]+5c:[ ]+120004a4 [ ]+addu16i.d[ ]+[ ]+\$a0, \$a1, -32767
[ ]+60:[ ]+14000004 [ ]+lu12i.w[ ]+[ ]+\$a0, 0
-[ ]+64:[ ]+14ffffe4 [ ]+lu12i.w[ ]+[ ]+\$a0, 524287\(0x7ffff\)
-[ ]+68:[ ]+17000024 [ ]+lu32i.d[ ]+[ ]+\$a0, -524287\(0x80001\)
+[ ]+64:[ ]+14ffffe4 [ ]+lu12i.w[ ]+[ ]+\$a0, 524287
+[ ]+68:[ ]+17000024 [ ]+lu32i.d[ ]+[ ]+\$a0, -524287
[ ]+6c:[ ]+18000004 [ ]+pcaddi[ ]+[ ]+\$a0, 0
-[ ]+70:[ ]+18ffffe4 [ ]+pcaddi[ ]+[ ]+\$a0, 524287\(0x7ffff\)
-[ ]+74:[ ]+19000024 [ ]+pcaddi[ ]+[ ]+\$a0, -524287\(0x80001\)
+[ ]+70:[ ]+18ffffe4 [ ]+pcaddi[ ]+[ ]+\$a0, 524287
+[ ]+74:[ ]+19000024 [ ]+pcaddi[ ]+[ ]+\$a0, -524287
[ ]+78:[ ]+1a000004 [ ]+pcalau12i[ ]+[ ]+\$a0, 0
-[ ]+7c:[ ]+1affffe4 [ ]+pcalau12i[ ]+[ ]+\$a0, 524287\(0x7ffff\)
-[ ]+80:[ ]+1b000024 [ ]+pcalau12i[ ]+[ ]+\$a0, -524287\(0x80001\)
+[ ]+7c:[ ]+1affffe4 [ ]+pcalau12i[ ]+[ ]+\$a0, 524287
+[ ]+80:[ ]+1b000024 [ ]+pcalau12i[ ]+[ ]+\$a0, -524287
[ ]+84:[ ]+1c000004 [ ]+pcaddu12i[ ]+[ ]+\$a0, 0
-[ ]+88:[ ]+1cffffe4 [ ]+pcaddu12i[ ]+[ ]+\$a0, 524287\(0x7ffff\)
-[ ]+8c:[ ]+1d000024 [ ]+pcaddu12i[ ]+[ ]+\$a0, -524287\(0x80001\)
+[ ]+88:[ ]+1cffffe4 [ ]+pcaddu12i[ ]+[ ]+\$a0, 524287
+[ ]+8c:[ ]+1d000024 [ ]+pcaddu12i[ ]+[ ]+\$a0, -524287
[ ]+90:[ ]+1e000004 [ ]+pcaddu18i[ ]+[ ]+\$a0, 0
-[ ]+94:[ ]+1effffe4 [ ]+pcaddu18i[ ]+[ ]+\$a0, 524287\(0x7ffff\)
-[ ]+98:[ ]+1f000024 [ ]+pcaddu18i[ ]+[ ]+\$a0, -524287\(0x80001\)
+[ ]+94:[ ]+1effffe4 [ ]+pcaddu18i[ ]+[ ]+\$a0, 524287
+[ ]+98:[ ]+1f000024 [ ]+pcaddu18i[ ]+[ ]+\$a0, -524287
diff --git a/gas/testsuite/gas/loongarch/jmp_op.d b/gas/testsuite/gas/loongarch/jmp_op.d
index 0ce804b831c..cc544f11ca3 100644
--- a/gas/testsuite/gas/loongarch/jmp_op.d
+++ b/gas/testsuite/gas/loongarch/jmp_op.d
@@ -8,43 +8,43 @@ Disassembly of section .text:
00000000.* <.L1>:
[ ]+0:[ ]+03400000[ ]+nop[ ]+
-[ ]+4:[ ]+63fffc04[ ]+bgtz[ ]+\$a0,[ ]+-4\(0x3fffc\)[ ]+#[ ]+0[ ]+<\.L1>
+[ ]+4:[ ]+63fffc04[ ]+bgtz[ ]+\$a0,[ ]+-4[ ]+#[ ]+0[ ]+<\.L1>
[ ]+4:[ ]+R_LARCH_B16[ ]+\.L1
-[ ]+8:[ ]+67fff880[ ]+bgez[ ]+\$a0,[ ]+-8\(0x3fff8\)[ ]+#[ ]+0[ ]+<\.L1>
+[ ]+8:[ ]+67fff880[ ]+bgez[ ]+\$a0,[ ]+-8[ ]+#[ ]+0[ ]+<\.L1>
[ ]+8:[ ]+R_LARCH_B16[ ]+\.L1
-[ ]+c:[ ]+67fff404[ ]+blez[ ]+\$a0,[ ]+-12\(0x3fff4\)[ ]+#[ ]+0[ ]+<\.L1>
+[ ]+c:[ ]+67fff404[ ]+blez[ ]+\$a0,[ ]+-12[ ]+#[ ]+0[ ]+<\.L1>
[ ]+c:[ ]+R_LARCH_B16[ ]+\.L1
-[ ]+10:[ ]+43fff09f[ ]+beqz[ ]+\$a0,[ ]+-16\(0x7ffff0\)[ ]+#[ ]+0[ ]+<\.L1>
+[ ]+10:[ ]+43fff09f[ ]+beqz[ ]+\$a0,[ ]+-16[ ]+#[ ]+0[ ]+<\.L1>
[ ]+10:[ ]+R_LARCH_B21[ ]+\.L1
-[ ]+14:[ ]+47ffec9f[ ]+bnez[ ]+\$a0,[ ]+-20\(0x7fffec\)[ ]+#[ ]+0[ ]+<\.L1>
+[ ]+14:[ ]+47ffec9f[ ]+bnez[ ]+\$a0,[ ]+-20[ ]+#[ ]+0[ ]+<\.L1>
[ ]+14:[ ]+R_LARCH_B21[ ]+\.L1
-[ ]+18:[ ]+4bffe81f[ ]+bceqz[ ]+\$fcc0,[ ]+-24\(0x7fffe8\)[ ]+#[ ]+0[ ]+<\.L1>
+[ ]+18:[ ]+4bffe81f[ ]+bceqz[ ]+\$fcc0,[ ]+-24[ ]+#[ ]+0[ ]+<\.L1>
[ ]+18:[ ]+R_LARCH_B21[ ]+\.L1
-[ ]+1c:[ ]+4bffe51f[ ]+bcnez[ ]+\$fcc0,[ ]+-28\(0x7fffe4\)[ ]+#[ ]+0[ ]+<\.L1>
+[ ]+1c:[ ]+4bffe51f[ ]+bcnez[ ]+\$fcc0,[ ]+-28[ ]+#[ ]+0[ ]+<\.L1>
[ ]+1c:[ ]+R_LARCH_B21[ ]+\.L1
[ ]+20:[ ]+4c000080[ ]+jr[ ]+\$a0
-[ ]+24:[ ]+53ffdfff[ ]+b[ ]+-36\(0xfffffdc\)[ ]+#[ ]+0[ ]+<\.L1>
+[ ]+24:[ ]+53ffdfff[ ]+b[ ]+-36[ ]+#[ ]+0[ ]+<\.L1>
[ ]+24:[ ]+R_LARCH_B26[ ]+\.L1
-[ ]+28:[ ]+57ffdbff[ ]+bl[ ]+-40\(0xfffffd8\)[ ]+#[ ]+0[ ]+<\.L1>
+[ ]+28:[ ]+57ffdbff[ ]+bl[ ]+-40[ ]+#[ ]+0[ ]+<\.L1>
[ ]+28:[ ]+R_LARCH_B26[ ]+\.L1
-[ ]+2c:[ ]+5bffd485[ ]+beq[ ]+\$a0,[ ]+\$a1,[ ]+-44\(0x3ffd4\)[ ]+#[ ]+0[ ]+<\.L1>
+[ ]+2c:[ ]+5bffd485[ ]+beq[ ]+\$a0,[ ]+\$a1,[ ]+-44[ ]+#[ ]+0[ ]+<\.L1>
[ ]+2c:[ ]+R_LARCH_B16[ ]+\.L1
-[ ]+30:[ ]+5fffd085[ ]+bne[ ]+\$a0,[ ]+\$a1,[ ]+-48\(0x3ffd0\)[ ]+#[ ]+0[ ]+<\.L1>
+[ ]+30:[ ]+5fffd085[ ]+bne[ ]+\$a0,[ ]+\$a1,[ ]+-48[ ]+#[ ]+0[ ]+<\.L1>
[ ]+30:[ ]+R_LARCH_B16[ ]+\.L1
-[ ]+34:[ ]+63ffcc85[ ]+blt[ ]+\$a0,[ ]+\$a1,[ ]+-52\(0x3ffcc\)[ ]+#[ ]+0[ ]+<\.L1>
+[ ]+34:[ ]+63ffcc85[ ]+blt[ ]+\$a0,[ ]+\$a1,[ ]+-52[ ]+#[ ]+0[ ]+<\.L1>
[ ]+34:[ ]+R_LARCH_B16[ ]+\.L1
-[ ]+38:[ ]+63ffc8a4[ ]+blt[ ]+\$a1,[ ]+\$a0,[ ]+-56\(0x3ffc8\)[ ]+#[ ]+0[ ]+<\.L1>
+[ ]+38:[ ]+63ffc8a4[ ]+blt[ ]+\$a1,[ ]+\$a0,[ ]+-56[ ]+#[ ]+0[ ]+<\.L1>
[ ]+38:[ ]+R_LARCH_B16[ ]+\.L1
-[ ]+3c:[ ]+67ffc485[ ]+bge[ ]+\$a0,[ ]+\$a1,[ ]+-60\(0x3ffc4\)[ ]+#[ ]+0[ ]+<\.L1>
+[ ]+3c:[ ]+67ffc485[ ]+bge[ ]+\$a0,[ ]+\$a1,[ ]+-60[ ]+#[ ]+0[ ]+<\.L1>
[ ]+3c:[ ]+R_LARCH_B16[ ]+\.L1
-[ ]+40:[ ]+67ffc0a4[ ]+bge[ ]+\$a1,[ ]+\$a0,[ ]+-64\(0x3ffc0\)[ ]+#[ ]+0[ ]+<\.L1>
+[ ]+40:[ ]+67ffc0a4[ ]+bge[ ]+\$a1,[ ]+\$a0,[ ]+-64[ ]+#[ ]+0[ ]+<\.L1>
[ ]+40:[ ]+R_LARCH_B16[ ]+\.L1
-[ ]+44:[ ]+6bffbc85[ ]+bltu[ ]+\$a0,[ ]+\$a1,[ ]+-68\(0x3ffbc\)[ ]+#[ ]+0[ ]+<\.L1>
+[ ]+44:[ ]+6bffbc85[ ]+bltu[ ]+\$a0,[ ]+\$a1,[ ]+-68[ ]+#[ ]+0[ ]+<\.L1>
[ ]+44:[ ]+R_LARCH_B16[ ]+\.L1
-[ ]+48:[ ]+6bffb8a4[ ]+bltu[ ]+\$a1,[ ]+\$a0,[ ]+-72\(0x3ffb8\)[ ]+#[ ]+0[ ]+<\.L1>
+[ ]+48:[ ]+6bffb8a4[ ]+bltu[ ]+\$a1,[ ]+\$a0,[ ]+-72[ ]+#[ ]+0[ ]+<\.L1>
[ ]+48:[ ]+R_LARCH_B16[ ]+\.L1
-[ ]+4c:[ ]+6fffb485[ ]+bgeu[ ]+\$a0,[ ]+\$a1,[ ]+-76\(0x3ffb4\)[ ]+#[ ]+0[ ]+<\.L1>
+[ ]+4c:[ ]+6fffb485[ ]+bgeu[ ]+\$a0,[ ]+\$a1,[ ]+-76[ ]+#[ ]+0[ ]+<\.L1>
[ ]+4c:[ ]+R_LARCH_B16[ ]+\.L1
-[ ]+50:[ ]+6fffb0a4[ ]+bgeu[ ]+\$a1,[ ]+\$a0,[ ]+-80\(0x3ffb0\)[ ]+#[ ]+0[ ]+<\.L1>
+[ ]+50:[ ]+6fffb0a4[ ]+bgeu[ ]+\$a1,[ ]+\$a0,[ ]+-80[ ]+#[ ]+0[ ]+<\.L1>
[ ]+50:[ ]+R_LARCH_B16[ ]+\.L1
[ ]+54:[ ]+4c000020[ ]+ret[ ]+
diff --git a/gas/testsuite/gas/loongarch/load_store_op.d b/gas/testsuite/gas/loongarch/load_store_op.d
index fc15773c1f4..e1b4dea1851 100644
--- a/gas/testsuite/gas/loongarch/load_store_op.d
+++ b/gas/testsuite/gas/loongarch/load_store_op.d
@@ -8,69 +8,69 @@ Disassembly of section .text:
00000000.* <.text>:
[ ]+0:[ ]+200000a4 [ ]+ll.w[ ]+[ ]+\$a0, \$a1, 0
-[ ]+4:[ ]+203ffca4 [ ]+ll.w[ ]+[ ]+\$a0, \$a1, 16380\(0x3ffc\)
+[ ]+4:[ ]+203ffca4 [ ]+ll.w[ ]+[ ]+\$a0, \$a1, 16380
[ ]+8:[ ]+210000a4 [ ]+sc.w[ ]+[ ]+\$a0, \$a1, 0
-[ ]+c:[ ]+213ffca4 [ ]+sc.w[ ]+[ ]+\$a0, \$a1, 16380\(0x3ffc\)
+[ ]+c:[ ]+213ffca4 [ ]+sc.w[ ]+[ ]+\$a0, \$a1, 16380
[ ]+10:[ ]+220000a4 [ ]+ll.d[ ]+[ ]+\$a0, \$a1, 0
-[ ]+14:[ ]+223ffca4 [ ]+ll.d[ ]+[ ]+\$a0, \$a1, 16380\(0x3ffc\)
+[ ]+14:[ ]+223ffca4 [ ]+ll.d[ ]+[ ]+\$a0, \$a1, 16380
[ ]+18:[ ]+230000a4 [ ]+sc.d[ ]+[ ]+\$a0, \$a1, 0
-[ ]+1c:[ ]+233ffca4 [ ]+sc.d[ ]+[ ]+\$a0, \$a1, 16380\(0x3ffc\)
+[ ]+1c:[ ]+233ffca4 [ ]+sc.d[ ]+[ ]+\$a0, \$a1, 16380
[ ]+20:[ ]+240000a4 [ ]+ldptr.w[ ]+[ ]+\$a0, \$a1, 0
-[ ]+24:[ ]+243ffca4 [ ]+ldptr.w[ ]+[ ]+\$a0, \$a1, 16380\(0x3ffc\)
+[ ]+24:[ ]+243ffca4 [ ]+ldptr.w[ ]+[ ]+\$a0, \$a1, 16380
[ ]+28:[ ]+250000a4 [ ]+stptr.w[ ]+[ ]+\$a0, \$a1, 0
-[ ]+2c:[ ]+253ffca4 [ ]+stptr.w[ ]+[ ]+\$a0, \$a1, 16380\(0x3ffc\)
+[ ]+2c:[ ]+253ffca4 [ ]+stptr.w[ ]+[ ]+\$a0, \$a1, 16380
[ ]+30:[ ]+260000a4 [ ]+ldptr.d[ ]+[ ]+\$a0, \$a1, 0
-[ ]+34:[ ]+263ffca4 [ ]+ldptr.d[ ]+[ ]+\$a0, \$a1, 16380\(0x3ffc\)
+[ ]+34:[ ]+263ffca4 [ ]+ldptr.d[ ]+[ ]+\$a0, \$a1, 16380
[ ]+38:[ ]+270000a4 [ ]+stptr.d[ ]+[ ]+\$a0, \$a1, 0
-[ ]+3c:[ ]+273ffca4 [ ]+stptr.d[ ]+[ ]+\$a0, \$a1, 16380\(0x3ffc\)
+[ ]+3c:[ ]+273ffca4 [ ]+stptr.d[ ]+[ ]+\$a0, \$a1, 16380
[ ]+40:[ ]+280000a4 [ ]+ld.b[ ]+[ ]+\$a0, \$a1, 0
-[ ]+44:[ ]+281ffca4 [ ]+ld.b[ ]+[ ]+\$a0, \$a1, 2047\(0x7ff\)
-[ ]+48:[ ]+282004a4 [ ]+ld.b[ ]+[ ]+\$a0, \$a1, -2047\(0x801\)
+[ ]+44:[ ]+281ffca4 [ ]+ld.b[ ]+[ ]+\$a0, \$a1, 2047
+[ ]+48:[ ]+282004a4 [ ]+ld.b[ ]+[ ]+\$a0, \$a1, -2047
[ ]+4c:[ ]+284000a4 [ ]+ld.h[ ]+[ ]+\$a0, \$a1, 0
-[ ]+50:[ ]+285ffca4 [ ]+ld.h[ ]+[ ]+\$a0, \$a1, 2047\(0x7ff\)
-[ ]+54:[ ]+286004a4 [ ]+ld.h[ ]+[ ]+\$a0, \$a1, -2047\(0x801\)
+[ ]+50:[ ]+285ffca4 [ ]+ld.h[ ]+[ ]+\$a0, \$a1, 2047
+[ ]+54:[ ]+286004a4 [ ]+ld.h[ ]+[ ]+\$a0, \$a1, -2047
[ ]+58:[ ]+288000a4 [ ]+ld.w[ ]+[ ]+\$a0, \$a1, 0
-[ ]+5c:[ ]+289ffca4 [ ]+ld.w[ ]+[ ]+\$a0, \$a1, 2047\(0x7ff\)
-[ ]+60:[ ]+28a004a4 [ ]+ld.w[ ]+[ ]+\$a0, \$a1, -2047\(0x801\)
+[ ]+5c:[ ]+289ffca4 [ ]+ld.w[ ]+[ ]+\$a0, \$a1, 2047
+[ ]+60:[ ]+28a004a4 [ ]+ld.w[ ]+[ ]+\$a0, \$a1, -2047
[ ]+64:[ ]+28c000a4 [ ]+ld.d[ ]+[ ]+\$a0, \$a1, 0
-[ ]+68:[ ]+28dffca4 [ ]+ld.d[ ]+[ ]+\$a0, \$a1, 2047\(0x7ff\)
-[ ]+6c:[ ]+28e004a4 [ ]+ld.d[ ]+[ ]+\$a0, \$a1, -2047\(0x801\)
+[ ]+68:[ ]+28dffca4 [ ]+ld.d[ ]+[ ]+\$a0, \$a1, 2047
+[ ]+6c:[ ]+28e004a4 [ ]+ld.d[ ]+[ ]+\$a0, \$a1, -2047
[ ]+70:[ ]+290000a4 [ ]+st.b[ ]+[ ]+\$a0, \$a1, 0
-[ ]+74:[ ]+291ffca4 [ ]+st.b[ ]+[ ]+\$a0, \$a1, 2047\(0x7ff\)
-[ ]+78:[ ]+292004a4 [ ]+st.b[ ]+[ ]+\$a0, \$a1, -2047\(0x801\)
+[ ]+74:[ ]+291ffca4 [ ]+st.b[ ]+[ ]+\$a0, \$a1, 2047
+[ ]+78:[ ]+292004a4 [ ]+st.b[ ]+[ ]+\$a0, \$a1, -2047
[ ]+7c:[ ]+294000a4 [ ]+st.h[ ]+[ ]+\$a0, \$a1, 0
-[ ]+80:[ ]+295ffca4 [ ]+st.h[ ]+[ ]+\$a0, \$a1, 2047\(0x7ff\)
-[ ]+84:[ ]+296004a4 [ ]+st.h[ ]+[ ]+\$a0, \$a1, -2047\(0x801\)
+[ ]+80:[ ]+295ffca4 [ ]+st.h[ ]+[ ]+\$a0, \$a1, 2047
+[ ]+84:[ ]+296004a4 [ ]+st.h[ ]+[ ]+\$a0, \$a1, -2047
[ ]+88:[ ]+298000a4 [ ]+st.w[ ]+[ ]+\$a0, \$a1, 0
-[ ]+8c:[ ]+299ffca4 [ ]+st.w[ ]+[ ]+\$a0, \$a1, 2047\(0x7ff\)
-[ ]+90:[ ]+29a004a4 [ ]+st.w[ ]+[ ]+\$a0, \$a1, -2047\(0x801\)
+[ ]+8c:[ ]+299ffca4 [ ]+st.w[ ]+[ ]+\$a0, \$a1, 2047
+[ ]+90:[ ]+29a004a4 [ ]+st.w[ ]+[ ]+\$a0, \$a1, -2047
[ ]+94:[ ]+29c000a4 [ ]+st.d[ ]+[ ]+\$a0, \$a1, 0
-[ ]+98:[ ]+29dffca4 [ ]+st.d[ ]+[ ]+\$a0, \$a1, 2047\(0x7ff\)
-[ ]+9c:[ ]+29e004a4 [ ]+st.d[ ]+[ ]+\$a0, \$a1, -2047\(0x801\)
+[ ]+98:[ ]+29dffca4 [ ]+st.d[ ]+[ ]+\$a0, \$a1, 2047
+[ ]+9c:[ ]+29e004a4 [ ]+st.d[ ]+[ ]+\$a0, \$a1, -2047
[ ]+a0:[ ]+2a0000a4 [ ]+ld.bu[ ]+[ ]+\$a0, \$a1, 0
-[ ]+a4:[ ]+2a1ffca4 [ ]+ld.bu[ ]+[ ]+\$a0, \$a1, 2047\(0x7ff\)
-[ ]+a8:[ ]+2a2004a4 [ ]+ld.bu[ ]+[ ]+\$a0, \$a1, -2047\(0x801\)
+[ ]+a4:[ ]+2a1ffca4 [ ]+ld.bu[ ]+[ ]+\$a0, \$a1, 2047
+[ ]+a8:[ ]+2a2004a4 [ ]+ld.bu[ ]+[ ]+\$a0, \$a1, -2047
[ ]+ac:[ ]+2a4000a4 [ ]+ld.hu[ ]+[ ]+\$a0, \$a1, 0
-[ ]+b0:[ ]+2a5ffca4 [ ]+ld.hu[ ]+[ ]+\$a0, \$a1, 2047\(0x7ff\)
-[ ]+b4:[ ]+2a6004a4 [ ]+ld.hu[ ]+[ ]+\$a0, \$a1, -2047\(0x801\)
+[ ]+b0:[ ]+2a5ffca4 [ ]+ld.hu[ ]+[ ]+\$a0, \$a1, 2047
+[ ]+b4:[ ]+2a6004a4 [ ]+ld.hu[ ]+[ ]+\$a0, \$a1, -2047
[ ]+b8:[ ]+2a8000a4 [ ]+ld.wu[ ]+[ ]+\$a0, \$a1, 0
-[ ]+bc:[ ]+2a9ffca4 [ ]+ld.wu[ ]+[ ]+\$a0, \$a1, 2047\(0x7ff\)
-[ ]+c0:[ ]+2aa004a4 [ ]+ld.wu[ ]+[ ]+\$a0, \$a1, -2047\(0x801\)
+[ ]+bc:[ ]+2a9ffca4 [ ]+ld.wu[ ]+[ ]+\$a0, \$a1, 2047
+[ ]+c0:[ ]+2aa004a4 [ ]+ld.wu[ ]+[ ]+\$a0, \$a1, -2047
[ ]+c4:[ ]+2ac000a0 [ ]+preld[ ]+[ ]+0x0, \$a1, 0
-[ ]+c8:[ ]+2adffcbf [ ]+preld[ ]+[ ]+0x1f, \$a1, 2047\(0x7ff\)
-[ ]+cc:[ ]+2ae004bf [ ]+preld[ ]+[ ]+0x1f, \$a1, -2047\(0x801\)
+[ ]+c8:[ ]+2adffcbf [ ]+preld[ ]+[ ]+0x1f, \$a1, 2047
+[ ]+cc:[ ]+2ae004bf [ ]+preld[ ]+[ ]+0x1f, \$a1, -2047
[ ]+d0:[ ]+2b0000a0 [ ]+fld.s[ ]+[ ]+\$fa0, \$a1, 0
-[ ]+d4:[ ]+2b1ffca0 [ ]+fld.s[ ]+[ ]+\$fa0, \$a1, 2047\(0x7ff\)
-[ ]+d8:[ ]+2b2004a0 [ ]+fld.s[ ]+[ ]+\$fa0, \$a1, -2047\(0x801\)
+[ ]+d4:[ ]+2b1ffca0 [ ]+fld.s[ ]+[ ]+\$fa0, \$a1, 2047
+[ ]+d8:[ ]+2b2004a0 [ ]+fld.s[ ]+[ ]+\$fa0, \$a1, -2047
[ ]+dc:[ ]+2b4000a0 [ ]+fst.s[ ]+[ ]+\$fa0, \$a1, 0
-[ ]+e0:[ ]+2b5ffca0 [ ]+fst.s[ ]+[ ]+\$fa0, \$a1, 2047\(0x7ff\)
-[ ]+e4:[ ]+2b6004a0 [ ]+fst.s[ ]+[ ]+\$fa0, \$a1, -2047\(0x801\)
+[ ]+e0:[ ]+2b5ffca0 [ ]+fst.s[ ]+[ ]+\$fa0, \$a1, 2047
+[ ]+e4:[ ]+2b6004a0 [ ]+fst.s[ ]+[ ]+\$fa0, \$a1, -2047
[ ]+e8:[ ]+2b8000a0 [ ]+fld.d[ ]+[ ]+\$fa0, \$a1, 0
-[ ]+ec:[ ]+2b9ffca0 [ ]+fld.d[ ]+[ ]+\$fa0, \$a1, 2047\(0x7ff\)
-[ ]+f0:[ ]+2ba004a0 [ ]+fld.d[ ]+[ ]+\$fa0, \$a1, -2047\(0x801\)
+[ ]+ec:[ ]+2b9ffca0 [ ]+fld.d[ ]+[ ]+\$fa0, \$a1, 2047
+[ ]+f0:[ ]+2ba004a0 [ ]+fld.d[ ]+[ ]+\$fa0, \$a1, -2047
[ ]+f4:[ ]+2bc000a0 [ ]+fst.d[ ]+[ ]+\$fa0, \$a1, 0
-[ ]+f8:[ ]+2bdffca0 [ ]+fst.d[ ]+[ ]+\$fa0, \$a1, 2047\(0x7ff\)
-[ ]+fc:[ ]+2be004a0 [ ]+fst.d[ ]+[ ]+\$fa0, \$a1, -2047\(0x801\)
+[ ]+f8:[ ]+2bdffca0 [ ]+fst.d[ ]+[ ]+\$fa0, \$a1, 2047
+[ ]+fc:[ ]+2be004a0 [ ]+fst.d[ ]+[ ]+\$fa0, \$a1, -2047
100:[ ]+380018a4 [ ]+ldx.b[ ]+[ ]+\$a0, \$a1, \$a2
104:[ ]+380418a4 [ ]+ldx.h[ ]+[ ]+\$a0, \$a1, \$a2
108:[ ]+380818a4 [ ]+ldx.w[ ]+[ ]+\$a0, \$a1, \$a2
diff --git a/gas/testsuite/gas/loongarch/macro_op.d b/gas/testsuite/gas/loongarch/macro_op.d
index 3f6518eddb0..32860864704 100644
--- a/gas/testsuite/gas/loongarch/macro_op.d
+++ b/gas/testsuite/gas/loongarch/macro_op.d
@@ -9,9 +9,9 @@ Disassembly of section .text:
00000000.* <.text>:
[ ]+0:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero
-[ ]+4:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1\(0xfff\)
+[ ]+4:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1
[ ]+8:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero
-[ ]+c:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1\(0xfff\)
+[ ]+c:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1
[ ]+10:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+10:[ ]+R_LARCH_GOT_PC_HI20[ ]+\.L1
[ ]+10:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
diff --git a/gas/testsuite/gas/loongarch/macro_op_32.d b/gas/testsuite/gas/loongarch/macro_op_32.d
index 5ac15fdfea8..188026a5780 100644
--- a/gas/testsuite/gas/loongarch/macro_op_32.d
+++ b/gas/testsuite/gas/loongarch/macro_op_32.d
@@ -9,9 +9,9 @@ Disassembly of section .text:
00000000.* <.L1>:
[ ]+0:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero
-[ ]+4:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1\(0xfff\)
+[ ]+4:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1
[ ]+8:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero
-[ ]+c:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1\(0xfff\)
+[ ]+c:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1
[ ]+10:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+10:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1
[ ]+10:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
diff --git a/gas/testsuite/gas/loongarch/privilege_op.d b/gas/testsuite/gas/loongarch/privilege_op.d
index 12d4790a027..73925f21a37 100644
--- a/gas/testsuite/gas/loongarch/privilege_op.d
+++ b/gas/testsuite/gas/loongarch/privilege_op.d
@@ -15,10 +15,10 @@ Disassembly of section .text:
[ ]+14:[ ]+04fffca4 [ ]+csrxchg[ ]+[ ]+\$a0, \$a1, 0x3fff
[ ]+18:[ ]+060000a0 [ ]+cacop[ ]+[ ]+0x0, \$a1, 0
[ ]+1c:[ ]+060000bf [ ]+cacop[ ]+[ ]+0x1f, \$a1, 0
-[ ]+20:[ ]+061ffca0 [ ]+cacop[ ]+[ ]+0x0, \$a1, 2047\(0x7ff\)
-[ ]+24:[ ]+061ffcbf [ ]+cacop[ ]+[ ]+0x1f, \$a1, 2047\(0x7ff\)
-[ ]+28:[ ]+062004a0 [ ]+cacop[ ]+[ ]+0x0, \$a1, -2047\(0x801\)
-[ ]+2c:[ ]+062004bf [ ]+cacop[ ]+[ ]+0x1f, \$a1, -2047\(0x801\)
+[ ]+20:[ ]+061ffca0 [ ]+cacop[ ]+[ ]+0x0, \$a1, 2047
+[ ]+24:[ ]+061ffcbf [ ]+cacop[ ]+[ ]+0x1f, \$a1, 2047
+[ ]+28:[ ]+062004a0 [ ]+cacop[ ]+[ ]+0x0, \$a1, -2047
+[ ]+2c:[ ]+062004bf [ ]+cacop[ ]+[ ]+0x1f, \$a1, -2047
[ ]+30:[ ]+064000a4 [ ]+lddir[ ]+[ ]+\$a0, \$a1, 0x0
[ ]+34:[ ]+0643fca4 [ ]+lddir[ ]+[ ]+\$a0, \$a1, 0xff
[ ]+38:[ ]+064400a0 [ ]+ldpte[ ]+[ ]+\$a1, 0x0
diff --git a/gas/testsuite/gas/loongarch/uleb128.d b/gas/testsuite/gas/loongarch/uleb128.d
index 41ed8ff870f..df66587b692 100644
--- a/gas/testsuite/gas/loongarch/uleb128.d
+++ b/gas/testsuite/gas/loongarch/uleb128.d
@@ -16,7 +16,7 @@ Disassembly of section .data:
0000000000000005[ ]+<L1>:
[ ]+\.\.\.
[ ]+81:[ ]+ff040000[ ]+0xff040000
-[ ]+85:[ ]+cacop[ ]+0x1f,[ ]+\$t3,[ ]+1\(0x1\)
+[ ]+85:[ ]+cacop[ ]+0x1f,[ ]+\$t3,[ ]+1
0000000000000086[ ]+<L2>:
[ ]+86:[ ]+07060005[ ]+0x07060005
diff --git a/gas/testsuite/gas/loongarch/vector.d b/gas/testsuite/gas/loongarch/vector.d
index f5139bfc525..1a092bca3b8 100644
--- a/gas/testsuite/gas/loongarch/vector.d
+++ b/gas/testsuite/gas/loongarch/vector.d
@@ -116,30 +116,30 @@ Disassembly of section .text:
[ ]+1a4:[ ]+0caa8820[ ]+xvfcmp.sor.d[ ]+\$xr0,[ ]+\$xr1,[ ]+\$xr2
[ ]+1a8:[ ]+0cac0820[ ]+xvfcmp.cune.d[ ]+\$xr0,[ ]+\$xr1,[ ]+\$xr2
[ ]+1ac:[ ]+0cac8820[ ]+xvfcmp.sune.d[ ]+\$xr0,[ ]+\$xr1,[ ]+\$xr2
-[ ]+1b0:[ ]+2c000420[ ]+vld[ ]+\$vr0,[ ]+\$ra,[ ]+1\(0x1\)
-[ ]+1b4:[ ]+2c400420[ ]+vst[ ]+\$vr0,[ ]+\$ra,[ ]+1\(0x1\)
-[ ]+1b8:[ ]+2c800420[ ]+xvld[ ]+\$xr0,[ ]+\$ra,[ ]+1\(0x1\)
-[ ]+1bc:[ ]+2cc00420[ ]+xvst[ ]+\$xr0,[ ]+\$ra,[ ]+1\(0x1\)
+[ ]+1b0:[ ]+2c000420[ ]+vld[ ]+\$vr0,[ ]+\$ra,[ ]+1
+[ ]+1b4:[ ]+2c400420[ ]+vst[ ]+\$vr0,[ ]+\$ra,[ ]+1
+[ ]+1b8:[ ]+2c800420[ ]+xvld[ ]+\$xr0,[ ]+\$ra,[ ]+1
+[ ]+1bc:[ ]+2cc00420[ ]+xvst[ ]+\$xr0,[ ]+\$ra,[ ]+1
[ ]+1c0:[ ]+38400820[ ]+vldx[ ]+\$vr0,[ ]+\$ra,[ ]+\$tp
[ ]+1c4:[ ]+38440820[ ]+vstx[ ]+\$vr0,[ ]+\$ra,[ ]+\$tp
[ ]+1c8:[ ]+38480820[ ]+xvldx[ ]+\$xr0,[ ]+\$ra,[ ]+\$tp
[ ]+1cc:[ ]+384c0820[ ]+xvstx[ ]+\$xr0,[ ]+\$ra,[ ]+\$tp
-[ ]+1d0:[ ]+3011f420[ ]+vldrepl.d[ ]+\$vr0,[ ]+\$ra,[ ]+1000\(0x3e8\)
-[ ]+1d4:[ ]+30206420[ ]+vldrepl.w[ ]+\$vr0,[ ]+\$ra,[ ]+100\(0x64\)
-[ ]+1d8:[ ]+30401420[ ]+vldrepl.h[ ]+\$vr0,[ ]+\$ra,[ ]+10\(0xa\)
-[ ]+1dc:[ ]+30800420[ ]+vldrepl.b[ ]+\$vr0,[ ]+\$ra,[ ]+1\(0x1\)
-[ ]+1e0:[ ]+3115f420[ ]+vstelm.d[ ]+\$vr0,[ ]+\$ra,[ ]+1000\(0x3e8\),[ ]+0x1
-[ ]+1e4:[ ]+31246420[ ]+vstelm.w[ ]+\$vr0,[ ]+\$ra,[ ]+100\(0x64\),[ ]+0x1
-[ ]+1e8:[ ]+31441420[ ]+vstelm.h[ ]+\$vr0,[ ]+\$ra,[ ]+10\(0xa\),[ ]+0x1
-[ ]+1ec:[ ]+31840420[ ]+vstelm.b[ ]+\$vr0,[ ]+\$ra,[ ]+1\(0x1\),[ ]+0x1
-[ ]+1f0:[ ]+3211f420[ ]+xvldrepl.d[ ]+\$xr0,[ ]+\$ra,[ ]+1000\(0x3e8\)
-[ ]+1f4:[ ]+32206420[ ]+xvldrepl.w[ ]+\$xr0,[ ]+\$ra,[ ]+100\(0x64\)
-[ ]+1f8:[ ]+32401420[ ]+xvldrepl.h[ ]+\$xr0,[ ]+\$ra,[ ]+10\(0xa\)
-[ ]+1fc:[ ]+32800420[ ]+xvldrepl.b[ ]+\$xr0,[ ]+\$ra,[ ]+1\(0x1\)
-[ ]+200:[ ]+3315f420[ ]+xvstelm.d[ ]+\$xr0,[ ]+\$ra,[ ]+1000\(0x3e8\),[ ]+0x1
-[ ]+204:[ ]+33246420[ ]+xvstelm.w[ ]+\$xr0,[ ]+\$ra,[ ]+100\(0x64\),[ ]+0x1
-[ ]+208:[ ]+33441420[ ]+xvstelm.h[ ]+\$xr0,[ ]+\$ra,[ ]+10\(0xa\),[ ]+0x1
-[ ]+20c:[ ]+33840420[ ]+xvstelm.b[ ]+\$xr0,[ ]+\$ra,[ ]+1\(0x1\),[ ]+0x1
+[ ]+1d0:[ ]+3011f420[ ]+vldrepl.d[ ]+\$vr0,[ ]+\$ra,[ ]+1000
+[ ]+1d4:[ ]+30206420[ ]+vldrepl.w[ ]+\$vr0,[ ]+\$ra,[ ]+100
+[ ]+1d8:[ ]+30401420[ ]+vldrepl.h[ ]+\$vr0,[ ]+\$ra,[ ]+10
+[ ]+1dc:[ ]+30800420[ ]+vldrepl.b[ ]+\$vr0,[ ]+\$ra,[ ]+1
+[ ]+1e0:[ ]+3115f420[ ]+vstelm.d[ ]+\$vr0,[ ]+\$ra,[ ]+1000,[ ]+0x1
+[ ]+1e4:[ ]+31246420[ ]+vstelm.w[ ]+\$vr0,[ ]+\$ra,[ ]+100,[ ]+0x1
+[ ]+1e8:[ ]+31441420[ ]+vstelm.h[ ]+\$vr0,[ ]+\$ra,[ ]+10,[ ]+0x1
+[ ]+1ec:[ ]+31840420[ ]+vstelm.b[ ]+\$vr0,[ ]+\$ra,[ ]+1,[ ]+0x1
+[ ]+1f0:[ ]+3211f420[ ]+xvldrepl.d[ ]+\$xr0,[ ]+\$ra,[ ]+1000
+[ ]+1f4:[ ]+32206420[ ]+xvldrepl.w[ ]+\$xr0,[ ]+\$ra,[ ]+100
+[ ]+1f8:[ ]+32401420[ ]+xvldrepl.h[ ]+\$xr0,[ ]+\$ra,[ ]+10
+[ ]+1fc:[ ]+32800420[ ]+xvldrepl.b[ ]+\$xr0,[ ]+\$ra,[ ]+1
+[ ]+200:[ ]+3315f420[ ]+xvstelm.d[ ]+\$xr0,[ ]+\$ra,[ ]+1000,[ ]+0x1
+[ ]+204:[ ]+33246420[ ]+xvstelm.w[ ]+\$xr0,[ ]+\$ra,[ ]+100,[ ]+0x1
+[ ]+208:[ ]+33441420[ ]+xvstelm.h[ ]+\$xr0,[ ]+\$ra,[ ]+10,[ ]+0x1
+[ ]+20c:[ ]+33840420[ ]+xvstelm.b[ ]+\$xr0,[ ]+\$ra,[ ]+1,[ ]+0x1
[ ]+210:[ ]+70000820[ ]+vseq.b[ ]+\$vr0,[ ]+\$vr1,[ ]+\$vr2
[ ]+214:[ ]+70008820[ ]+vseq.h[ ]+\$vr0,[ ]+\$vr1,[ ]+\$vr2
[ ]+218:[ ]+70010820[ ]+vseq.w[ ]+\$vr0,[ ]+\$vr1,[ ]+\$vr2
@@ -421,22 +421,22 @@ Disassembly of section .text:
[ ]+668:[ ]+717a8820[ ]+vshuf.h[ ]+\$vr0,[ ]+\$vr1,[ ]+\$vr2
[ ]+66c:[ ]+717b0820[ ]+vshuf.w[ ]+\$vr0,[ ]+\$vr1,[ ]+\$vr2
[ ]+670:[ ]+717b8820[ ]+vshuf.d[ ]+\$vr0,[ ]+\$vr1,[ ]+\$vr2
-[ ]+674:[ ]+72800420[ ]+vseqi.b[ ]+\$vr0,[ ]+\$vr1,[ ]+1\(0x1\)
-[ ]+678:[ ]+72808420[ ]+vseqi.h[ ]+\$vr0,[ ]+\$vr1,[ ]+1\(0x1\)
-[ ]+67c:[ ]+72810420[ ]+vseqi.w[ ]+\$vr0,[ ]+\$vr1,[ ]+1\(0x1\)
-[ ]+680:[ ]+72818420[ ]+vseqi.d[ ]+\$vr0,[ ]+\$vr1,[ ]+1\(0x1\)
-[ ]+684:[ ]+72820420[ ]+vslei.b[ ]+\$vr0,[ ]+\$vr1,[ ]+1\(0x1\)
-[ ]+688:[ ]+72828420[ ]+vslei.h[ ]+\$vr0,[ ]+\$vr1,[ ]+1\(0x1\)
-[ ]+68c:[ ]+72830420[ ]+vslei.w[ ]+\$vr0,[ ]+\$vr1,[ ]+1\(0x1\)
-[ ]+690:[ ]+72838420[ ]+vslei.d[ ]+\$vr0,[ ]+\$vr1,[ ]+1\(0x1\)
+[ ]+674:[ ]+72800420[ ]+vseqi.b[ ]+\$vr0,[ ]+\$vr1,[ ]+1
+[ ]+678:[ ]+72808420[ ]+vseqi.h[ ]+\$vr0,[ ]+\$vr1,[ ]+1
+[ ]+67c:[ ]+72810420[ ]+vseqi.w[ ]+\$vr0,[ ]+\$vr1,[ ]+1
+[ ]+680:[ ]+72818420[ ]+vseqi.d[ ]+\$vr0,[ ]+\$vr1,[ ]+1
+[ ]+684:[ ]+72820420[ ]+vslei.b[ ]+\$vr0,[ ]+\$vr1,[ ]+1
+[ ]+688:[ ]+72828420[ ]+vslei.h[ ]+\$vr0,[ ]+\$vr1,[ ]+1
+[ ]+68c:[ ]+72830420[ ]+vslei.w[ ]+\$vr0,[ ]+\$vr1,[ ]+1
+[ ]+690:[ ]+72838420[ ]+vslei.d[ ]+\$vr0,[ ]+\$vr1,[ ]+1
[ ]+694:[ ]+72840420[ ]+vslei.bu[ ]+\$vr0,[ ]+\$vr1,[ ]+0x1
[ ]+698:[ ]+72848420[ ]+vslei.hu[ ]+\$vr0,[ ]+\$vr1,[ ]+0x1
[ ]+69c:[ ]+72850420[ ]+vslei.wu[ ]+\$vr0,[ ]+\$vr1,[ ]+0x1
[ ]+6a0:[ ]+72858420[ ]+vslei.du[ ]+\$vr0,[ ]+\$vr1,[ ]+0x1
-[ ]+6a4:[ ]+72860420[ ]+vslti.b[ ]+\$vr0,[ ]+\$vr1,[ ]+1\(0x1\)
-[ ]+6a8:[ ]+72868420[ ]+vslti.h[ ]+\$vr0,[ ]+\$vr1,[ ]+1\(0x1\)
-[ ]+6ac:[ ]+72870420[ ]+vslti.w[ ]+\$vr0,[ ]+\$vr1,[ ]+1\(0x1\)
-[ ]+6b0:[ ]+72878420[ ]+vslti.d[ ]+\$vr0,[ ]+\$vr1,[ ]+1\(0x1\)
+[ ]+6a4:[ ]+72860420[ ]+vslti.b[ ]+\$vr0,[ ]+\$vr1,[ ]+1
+[ ]+6a8:[ ]+72868420[ ]+vslti.h[ ]+\$vr0,[ ]+\$vr1,[ ]+1
+[ ]+6ac:[ ]+72870420[ ]+vslti.w[ ]+\$vr0,[ ]+\$vr1,[ ]+1
+[ ]+6b0:[ ]+72878420[ ]+vslti.d[ ]+\$vr0,[ ]+\$vr1,[ ]+1
[ ]+6b4:[ ]+72880420[ ]+vslti.bu[ ]+\$vr0,[ ]+\$vr1,[ ]+0x1
[ ]+6b8:[ ]+72888420[ ]+vslti.hu[ ]+\$vr0,[ ]+\$vr1,[ ]+0x1
[ ]+6bc:[ ]+72890420[ ]+vslti.wu[ ]+\$vr0,[ ]+\$vr1,[ ]+0x1
@@ -451,14 +451,14 @@ Disassembly of section .text:
[ ]+6e0:[ ]+728d8420[ ]+vsubi.du[ ]+\$vr0,[ ]+\$vr1,[ ]+0x1
[ ]+6e4:[ ]+728e0420[ ]+vbsll.v[ ]+\$vr0,[ ]+\$vr1,[ ]+0x1
[ ]+6e8:[ ]+728e8420[ ]+vbsrl.v[ ]+\$vr0,[ ]+\$vr1,[ ]+0x1
-[ ]+6ec:[ ]+72900420[ ]+vmaxi.b[ ]+\$vr0,[ ]+\$vr1,[ ]+1\(0x1\)
-[ ]+6f0:[ ]+72908420[ ]+vmaxi.h[ ]+\$vr0,[ ]+\$vr1,[ ]+1\(0x1\)
-[ ]+6f4:[ ]+72910420[ ]+vmaxi.w[ ]+\$vr0,[ ]+\$vr1,[ ]+1\(0x1\)
-[ ]+6f8:[ ]+72918420[ ]+vmaxi.d[ ]+\$vr0,[ ]+\$vr1,[ ]+1\(0x1\)
-[ ]+6fc:[ ]+72920420[ ]+vmini.b[ ]+\$vr0,[ ]+\$vr1,[ ]+1\(0x1\)
-[ ]+700:[ ]+72928420[ ]+vmini.h[ ]+\$vr0,[ ]+\$vr1,[ ]+1\(0x1\)
-[ ]+704:[ ]+72930420[ ]+vmini.w[ ]+\$vr0,[ ]+\$vr1,[ ]+1\(0x1\)
-[ ]+708:[ ]+72938420[ ]+vmini.d[ ]+\$vr0,[ ]+\$vr1,[ ]+1\(0x1\)
+[ ]+6ec:[ ]+72900420[ ]+vmaxi.b[ ]+\$vr0,[ ]+\$vr1,[ ]+1
+[ ]+6f0:[ ]+72908420[ ]+vmaxi.h[ ]+\$vr0,[ ]+\$vr1,[ ]+1
+[ ]+6f4:[ ]+72910420[ ]+vmaxi.w[ ]+\$vr0,[ ]+\$vr1,[ ]+1
+[ ]+6f8:[ ]+72918420[ ]+vmaxi.d[ ]+\$vr0,[ ]+\$vr1,[ ]+1
+[ ]+6fc:[ ]+72920420[ ]+vmini.b[ ]+\$vr0,[ ]+\$vr1,[ ]+1
+[ ]+700:[ ]+72928420[ ]+vmini.h[ ]+\$vr0,[ ]+\$vr1,[ ]+1
+[ ]+704:[ ]+72930420[ ]+vmini.w[ ]+\$vr0,[ ]+\$vr1,[ ]+1
+[ ]+708:[ ]+72938420[ ]+vmini.d[ ]+\$vr0,[ ]+\$vr1,[ ]+1
[ ]+70c:[ ]+72940420[ ]+vmaxi.bu[ ]+\$vr0,[ ]+\$vr1,[ ]+0x1
[ ]+710:[ ]+72948420[ ]+vmaxi.hu[ ]+\$vr0,[ ]+\$vr1,[ ]+0x1
[ ]+714:[ ]+72950420[ ]+vmaxi.wu[ ]+\$vr0,[ ]+\$vr1,[ ]+0x1
@@ -696,7 +696,7 @@ Disassembly of section .text:
[ ]+ab4:[ ]+73d40420[ ]+vori.b[ ]+\$vr0,[ ]+\$vr1,[ ]+0x1
[ ]+ab8:[ ]+73d80420[ ]+vxori.b[ ]+\$vr0,[ ]+\$vr1,[ ]+0x1
[ ]+abc:[ ]+73dc0420[ ]+vnori.b[ ]+\$vr0,[ ]+\$vr1,[ ]+0x1
-[ ]+ac0:[ ]+73e00020[ ]+vldi[ ]+\$vr0,[ ]+1\(0x1\)
+[ ]+ac0:[ ]+73e00020[ ]+vldi[ ]+\$vr0,[ ]+1
[ ]+ac4:[ ]+701e0820[ ]+vaddwev.h.b[ ]+\$vr0,[ ]+\$vr1,[ ]+\$vr2
[ ]+ac8:[ ]+701e8820[ ]+vaddwev.w.h[ ]+\$vr0,[ ]+\$vr1,[ ]+\$vr2
[ ]+acc:[ ]+701f0820[ ]+vaddwev.d.w[ ]+\$vr0,[ ]+\$vr1,[ ]+\$vr2
@@ -785,10 +785,10 @@ Disassembly of section .text:
[ ]+c18:[ ]+70348820[ ]+vsubwod.w.hu[ ]+\$vr0,[ ]+\$vr1,[ ]+\$vr2
[ ]+c1c:[ ]+70350820[ ]+vsubwod.d.wu[ ]+\$vr0,[ ]+\$vr1,[ ]+\$vr2
[ ]+c20:[ ]+70358820[ ]+vsubwod.q.du[ ]+\$vr0,[ ]+\$vr1,[ ]+\$vr2
-[ ]+c24:[ ]+73e18020[ ]+vldi[ ]+\$vr0,[ ]+3073\(0xc01\)
-[ ]+c28:[ ]+73e08020[ ]+vldi[ ]+\$vr0,[ ]+1025\(0x401\)
-[ ]+c2c:[ ]+73e10020[ ]+vldi[ ]+\$vr0,[ ]+2049\(0x801\)
-[ ]+c30:[ ]+73e00020[ ]+vldi[ ]+\$vr0,[ ]+1\(0x1\)
+[ ]+c24:[ ]+73e18020[ ]+vldi[ ]+\$vr0,[ ]+3073
+[ ]+c28:[ ]+73e08020[ ]+vldi[ ]+\$vr0,[ ]+1025
+[ ]+c2c:[ ]+73e10020[ ]+vldi[ ]+\$vr0,[ ]+2049
+[ ]+c30:[ ]+73e00020[ ]+vldi[ ]+\$vr0,[ ]+1
[ ]+c34:[ ]+73e40420[ ]+vpermi.w[ ]+\$vr0,[ ]+\$vr1,[ ]+0x1
[ ]+c38:[ ]+74000820[ ]+xvseq.b[ ]+\$xr0,[ ]+\$xr1,[ ]+\$xr2
[ ]+c3c:[ ]+74008820[ ]+xvseq.h[ ]+\$xr0,[ ]+\$xr1,[ ]+\$xr2
@@ -1160,22 +1160,22 @@ Disassembly of section .text:
[ ]+11f4:[ ]+757b0820[ ]+xvshuf.w[ ]+\$xr0,[ ]+\$xr1,[ ]+\$xr2
[ ]+11f8:[ ]+757b8820[ ]+xvshuf.d[ ]+\$xr0,[ ]+\$xr1,[ ]+\$xr2
[ ]+11fc:[ ]+757d0820[ ]+xvperm.w[ ]+\$xr0,[ ]+\$xr1,[ ]+\$xr2
-[ ]+1200:[ ]+76800420[ ]+xvseqi.b[ ]+\$xr0,[ ]+\$xr1,[ ]+1\(0x1\)
-[ ]+1204:[ ]+76808420[ ]+xvseqi.h[ ]+\$xr0,[ ]+\$xr1,[ ]+1\(0x1\)
-[ ]+1208:[ ]+76810420[ ]+xvseqi.w[ ]+\$xr0,[ ]+\$xr1,[ ]+1\(0x1\)
-[ ]+120c:[ ]+76818420[ ]+xvseqi.d[ ]+\$xr0,[ ]+\$xr1,[ ]+1\(0x1\)
-[ ]+1210:[ ]+76820420[ ]+xvslei.b[ ]+\$xr0,[ ]+\$xr1,[ ]+1\(0x1\)
-[ ]+1214:[ ]+76828420[ ]+xvslei.h[ ]+\$xr0,[ ]+\$xr1,[ ]+1\(0x1\)
-[ ]+1218:[ ]+76830420[ ]+xvslei.w[ ]+\$xr0,[ ]+\$xr1,[ ]+1\(0x1\)
-[ ]+121c:[ ]+76838420[ ]+xvslei.d[ ]+\$xr0,[ ]+\$xr1,[ ]+1\(0x1\)
+[ ]+1200:[ ]+76800420[ ]+xvseqi.b[ ]+\$xr0,[ ]+\$xr1,[ ]+1
+[ ]+1204:[ ]+76808420[ ]+xvseqi.h[ ]+\$xr0,[ ]+\$xr1,[ ]+1
+[ ]+1208:[ ]+76810420[ ]+xvseqi.w[ ]+\$xr0,[ ]+\$xr1,[ ]+1
+[ ]+120c:[ ]+76818420[ ]+xvseqi.d[ ]+\$xr0,[ ]+\$xr1,[ ]+1
+[ ]+1210:[ ]+76820420[ ]+xvslei.b[ ]+\$xr0,[ ]+\$xr1,[ ]+1
+[ ]+1214:[ ]+76828420[ ]+xvslei.h[ ]+\$xr0,[ ]+\$xr1,[ ]+1
+[ ]+1218:[ ]+76830420[ ]+xvslei.w[ ]+\$xr0,[ ]+\$xr1,[ ]+1
+[ ]+121c:[ ]+76838420[ ]+xvslei.d[ ]+\$xr0,[ ]+\$xr1,[ ]+1
[ ]+1220:[ ]+76840420[ ]+xvslei.bu[ ]+\$xr0,[ ]+\$xr1,[ ]+0x1
[ ]+1224:[ ]+76848420[ ]+xvslei.hu[ ]+\$xr0,[ ]+\$xr1,[ ]+0x1
[ ]+1228:[ ]+76850420[ ]+xvslei.wu[ ]+\$xr0,[ ]+\$xr1,[ ]+0x1
[ ]+122c:[ ]+76858420[ ]+xvslei.du[ ]+\$xr0,[ ]+\$xr1,[ ]+0x1
-[ ]+1230:[ ]+76860420[ ]+xvslti.b[ ]+\$xr0,[ ]+\$xr1,[ ]+1\(0x1\)
-[ ]+1234:[ ]+76868420[ ]+xvslti.h[ ]+\$xr0,[ ]+\$xr1,[ ]+1\(0x1\)
-[ ]+1238:[ ]+76870420[ ]+xvslti.w[ ]+\$xr0,[ ]+\$xr1,[ ]+1\(0x1\)
-[ ]+123c:[ ]+76878420[ ]+xvslti.d[ ]+\$xr0,[ ]+\$xr1,[ ]+1\(0x1\)
+[ ]+1230:[ ]+76860420[ ]+xvslti.b[ ]+\$xr0,[ ]+\$xr1,[ ]+1
+[ ]+1234:[ ]+76868420[ ]+xvslti.h[ ]+\$xr0,[ ]+\$xr1,[ ]+1
+[ ]+1238:[ ]+76870420[ ]+xvslti.w[ ]+\$xr0,[ ]+\$xr1,[ ]+1
+[ ]+123c:[ ]+76878420[ ]+xvslti.d[ ]+\$xr0,[ ]+\$xr1,[ ]+1
[ ]+1240:[ ]+76880420[ ]+xvslti.bu[ ]+\$xr0,[ ]+\$xr1,[ ]+0x1
[ ]+1244:[ ]+76888420[ ]+xvslti.hu[ ]+\$xr0,[ ]+\$xr1,[ ]+0x1
[ ]+1248:[ ]+76890420[ ]+xvslti.wu[ ]+\$xr0,[ ]+\$xr1,[ ]+0x1
@@ -1190,14 +1190,14 @@ Disassembly of section .text:
[ ]+126c:[ ]+768d8420[ ]+xvsubi.du[ ]+\$xr0,[ ]+\$xr1,[ ]+0x1
[ ]+1270:[ ]+768e0420[ ]+xvbsll.v[ ]+\$xr0,[ ]+\$xr1,[ ]+0x1
[ ]+1274:[ ]+768e8420[ ]+xvbsrl.v[ ]+\$xr0,[ ]+\$xr1,[ ]+0x1
-[ ]+1278:[ ]+76900420[ ]+xvmaxi.b[ ]+\$xr0,[ ]+\$xr1,[ ]+1\(0x1\)
-[ ]+127c:[ ]+76908420[ ]+xvmaxi.h[ ]+\$xr0,[ ]+\$xr1,[ ]+1\(0x1\)
-[ ]+1280:[ ]+76910420[ ]+xvmaxi.w[ ]+\$xr0,[ ]+\$xr1,[ ]+1\(0x1\)
-[ ]+1284:[ ]+76918420[ ]+xvmaxi.d[ ]+\$xr0,[ ]+\$xr1,[ ]+1\(0x1\)
-[ ]+1288:[ ]+76920420[ ]+xvmini.b[ ]+\$xr0,[ ]+\$xr1,[ ]+1\(0x1\)
-[ ]+128c:[ ]+76928420[ ]+xvmini.h[ ]+\$xr0,[ ]+\$xr1,[ ]+1\(0x1\)
-[ ]+1290:[ ]+76930420[ ]+xvmini.w[ ]+\$xr0,[ ]+\$xr1,[ ]+1\(0x1\)
-[ ]+1294:[ ]+76938420[ ]+xvmini.d[ ]+\$xr0,[ ]+\$xr1,[ ]+1\(0x1\)
+[ ]+1278:[ ]+76900420[ ]+xvmaxi.b[ ]+\$xr0,[ ]+\$xr1,[ ]+1
+[ ]+127c:[ ]+76908420[ ]+xvmaxi.h[ ]+\$xr0,[ ]+\$xr1,[ ]+1
+[ ]+1280:[ ]+76910420[ ]+xvmaxi.w[ ]+\$xr0,[ ]+\$xr1,[ ]+1
+[ ]+1284:[ ]+76918420[ ]+xvmaxi.d[ ]+\$xr0,[ ]+\$xr1,[ ]+1
+[ ]+1288:[ ]+76920420[ ]+xvmini.b[ ]+\$xr0,[ ]+\$xr1,[ ]+1
+[ ]+128c:[ ]+76928420[ ]+xvmini.h[ ]+\$xr0,[ ]+\$xr1,[ ]+1
+[ ]+1290:[ ]+76930420[ ]+xvmini.w[ ]+\$xr0,[ ]+\$xr1,[ ]+1
+[ ]+1294:[ ]+76938420[ ]+xvmini.d[ ]+\$xr0,[ ]+\$xr1,[ ]+1
[ ]+1298:[ ]+76940420[ ]+xvmaxi.bu[ ]+\$xr0,[ ]+\$xr1,[ ]+0x1
[ ]+129c:[ ]+76948420[ ]+xvmaxi.hu[ ]+\$xr0,[ ]+\$xr1,[ ]+0x1
[ ]+12a0:[ ]+76950420[ ]+xvmaxi.wu[ ]+\$xr0,[ ]+\$xr1,[ ]+0x1
@@ -1451,11 +1451,11 @@ Disassembly of section .text:
[ ]+1680:[ ]+77d40420[ ]+xvori.b[ ]+\$xr0,[ ]+\$xr1,[ ]+0x1
[ ]+1684:[ ]+77d80420[ ]+xvxori.b[ ]+\$xr0,[ ]+\$xr1,[ ]+0x1
[ ]+1688:[ ]+77dc0420[ ]+xvnori.b[ ]+\$xr0,[ ]+\$xr1,[ ]+0x1
-[ ]+168c:[ ]+77e00020[ ]+xvldi[ ]+\$xr0,[ ]+1\(0x1\)
-[ ]+1690:[ ]+77e18020[ ]+xvldi[ ]+\$xr0,[ ]+3073\(0xc01\)
-[ ]+1694:[ ]+77e08020[ ]+xvldi[ ]+\$xr0,[ ]+1025\(0x401\)
-[ ]+1698:[ ]+77e10020[ ]+xvldi[ ]+\$xr0,[ ]+2049\(0x801\)
-[ ]+169c:[ ]+77e00020[ ]+xvldi[ ]+\$xr0,[ ]+1\(0x1\)
+[ ]+168c:[ ]+77e00020[ ]+xvldi[ ]+\$xr0,[ ]+1
+[ ]+1690:[ ]+77e18020[ ]+xvldi[ ]+\$xr0,[ ]+3073
+[ ]+1694:[ ]+77e08020[ ]+xvldi[ ]+\$xr0,[ ]+1025
+[ ]+1698:[ ]+77e10020[ ]+xvldi[ ]+\$xr0,[ ]+2049
+[ ]+169c:[ ]+77e00020[ ]+xvldi[ ]+\$xr0,[ ]+1
[ ]+16a0:[ ]+77e40420[ ]+xvpermi.w[ ]+\$xr0,[ ]+\$xr1,[ ]+0x1
[ ]+16a4:[ ]+77e80420[ ]+xvpermi.d[ ]+\$xr0,[ ]+\$xr1,[ ]+0x1
[ ]+16a8:[ ]+77ec0420[ ]+xvpermi.q[ ]+\$xr0,[ ]+\$xr1,[ ]+0x1
diff --git a/ld/testsuite/ld-loongarch-elf/jmp_op.d b/ld/testsuite/ld-loongarch-elf/jmp_op.d
index be8290711a5..231d780923e 100644
--- a/ld/testsuite/ld-loongarch-elf/jmp_op.d
+++ b/ld/testsuite/ld-loongarch-elf/jmp_op.d
@@ -8,43 +8,43 @@ Disassembly of section .text:
00000000.* <.L1>:
[ ]+0:[ ]+03400000[ ]+andi[ ]+\$zero,[ ]+\$zero,[ ]+0x0
-[ ]+4:[ ]+63fffc04[ ]+blt[ ]+\$zero,[ ]+\$a0,[ ]+-4\(0x3fffc\)[ ]+#[ ]+0[ ]+<.L1>
+[ ]+4:[ ]+63fffc04[ ]+blt[ ]+\$zero,[ ]+\$a0,[ ]+-4[ ]+#[ ]+0[ ]+<.L1>
[ ]+4:[ ]+R_LARCH_B16[ ]+.L1
-[ ]+8:[ ]+67fff880[ ]+bge[ ]+\$a0,[ ]+\$zero,[ ]+-8\(0x3fff8\)[ ]+#[ ]+0[ ]+<.L1>
+[ ]+8:[ ]+67fff880[ ]+bge[ ]+\$a0,[ ]+\$zero,[ ]+-8[ ]+#[ ]+0[ ]+<.L1>
[ ]+8:[ ]+R_LARCH_B16[ ]+.L1
-[ ]+c:[ ]+67fff404[ ]+bge[ ]+\$zero,[ ]+\$a0,[ ]+-12\(0x3fff4\)[ ]+#[ ]+0[ ]+<.L1>
+[ ]+c:[ ]+67fff404[ ]+bge[ ]+\$zero,[ ]+\$a0,[ ]+-12[ ]+#[ ]+0[ ]+<.L1>
[ ]+c:[ ]+R_LARCH_B16[ ]+.L1
-[ ]+10:[ ]+43fff09f[ ]+beqz[ ]+\$a0,[ ]+-16\(0x7ffff0\)[ ]+#[ ]+0[ ]+<.L1>
+[ ]+10:[ ]+43fff09f[ ]+beqz[ ]+\$a0,[ ]+-16[ ]+#[ ]+0[ ]+<.L1>
[ ]+10:[ ]+R_LARCH_B21[ ]+.L1
-[ ]+14:[ ]+47ffec9f[ ]+bnez[ ]+\$a0,[ ]+-20\(0x7fffec\)[ ]+#[ ]+0[ ]+<.L1>
+[ ]+14:[ ]+47ffec9f[ ]+bnez[ ]+\$a0,[ ]+-20[ ]+#[ ]+0[ ]+<.L1>
[ ]+14:[ ]+R_LARCH_B21[ ]+.L1
-[ ]+18:[ ]+4bffe81f[ ]+bceqz[ ]+\$fcc0,[ ]+-24\(0x7fffe8\)[ ]+#[ ]+0[ ]+<.L1>
+[ ]+18:[ ]+4bffe81f[ ]+bceqz[ ]+\$fcc0,[ ]+-24[ ]+#[ ]+0[ ]+<.L1>
[ ]+18:[ ]+R_LARCH_B21[ ]+.L1
-[ ]+1c:[ ]+4bffe51f[ ]+bcnez[ ]+\$fcc0,[ ]+-28\(0x7fffe4\)[ ]+#[ ]+0[ ]+<.L1>
+[ ]+1c:[ ]+4bffe51f[ ]+bcnez[ ]+\$fcc0,[ ]+-28[ ]+#[ ]+0[ ]+<.L1>
[ ]+1c:[ ]+R_LARCH_B21[ ]+.L1
[ ]+20:[ ]+4c000080[ ]+jirl[ ]+\$zero,[ ]+\$a0,[ ]+0
-[ ]+24:[ ]+53ffdfff[ ]+b[ ]+-36\(0xfffffdc\)[ ]+#[ ]+0[ ]+<.L1>
+[ ]+24:[ ]+53ffdfff[ ]+b[ ]+-36[ ]+#[ ]+0[ ]+<.L1>
[ ]+24:[ ]+R_LARCH_B26[ ]+.L1
-[ ]+28:[ ]+57ffdbff[ ]+bl[ ]+-40\(0xfffffd8\)[ ]+#[ ]+0[ ]+<.L1>
+[ ]+28:[ ]+57ffdbff[ ]+bl[ ]+-40[ ]+#[ ]+0[ ]+<.L1>
[ ]+28:[ ]+R_LARCH_B26[ ]+.L1
-[ ]+2c:[ ]+5bffd485[ ]+beq[ ]+\$a0,[ ]+\$a1,[ ]+-44\(0x3ffd4\)[ ]+#[ ]+0[ ]+<.L1>
+[ ]+2c:[ ]+5bffd485[ ]+beq[ ]+\$a0,[ ]+\$a1,[ ]+-44[ ]+#[ ]+0[ ]+<.L1>
[ ]+2c:[ ]+R_LARCH_B16[ ]+.L1
-[ ]+30:[ ]+5fffd085[ ]+bne[ ]+\$a0,[ ]+\$a1,[ ]+-48\(0x3ffd0\)[ ]+#[ ]+0[ ]+<.L1>
+[ ]+30:[ ]+5fffd085[ ]+bne[ ]+\$a0,[ ]+\$a1,[ ]+-48[ ]+#[ ]+0[ ]+<.L1>
[ ]+30:[ ]+R_LARCH_B16[ ]+.L1
-[ ]+34:[ ]+63ffcc85[ ]+blt[ ]+\$a0,[ ]+\$a1,[ ]+-52\(0x3ffcc\)[ ]+#[ ]+0[ ]+<.L1>
+[ ]+34:[ ]+63ffcc85[ ]+blt[ ]+\$a0,[ ]+\$a1,[ ]+-52[ ]+#[ ]+0[ ]+<.L1>
[ ]+34:[ ]+R_LARCH_B16[ ]+.L1
-[ ]+38:[ ]+63ffc8a4[ ]+blt[ ]+\$a1,[ ]+\$a0,[ ]+-56\(0x3ffc8\)[ ]+#[ ]+0[ ]+<.L1>
+[ ]+38:[ ]+63ffc8a4[ ]+blt[ ]+\$a1,[ ]+\$a0,[ ]+-56[ ]+#[ ]+0[ ]+<.L1>
[ ]+38:[ ]+R_LARCH_B16[ ]+.L1
-[ ]+3c:[ ]+67ffc485[ ]+bge[ ]+\$a0,[ ]+\$a1,[ ]+-60\(0x3ffc4\)[ ]+#[ ]+0[ ]+<.L1>
+[ ]+3c:[ ]+67ffc485[ ]+bge[ ]+\$a0,[ ]+\$a1,[ ]+-60[ ]+#[ ]+0[ ]+<.L1>
[ ]+3c:[ ]+R_LARCH_B16[ ]+.L1
-[ ]+40:[ ]+67ffc0a4[ ]+bge[ ]+\$a1,[ ]+\$a0,[ ]+-64\(0x3ffc0\)[ ]+#[ ]+0[ ]+<.L1>
+[ ]+40:[ ]+67ffc0a4[ ]+bge[ ]+\$a1,[ ]+\$a0,[ ]+-64[ ]+#[ ]+0[ ]+<.L1>
[ ]+40:[ ]+R_LARCH_B16[ ]+.L1
-[ ]+44:[ ]+6bffbc85[ ]+bltu[ ]+\$a0,[ ]+\$a1,[ ]+-68\(0x3ffbc\)[ ]+#[ ]+0[ ]+<.L1>
+[ ]+44:[ ]+6bffbc85[ ]+bltu[ ]+\$a0,[ ]+\$a1,[ ]+-68[ ]+#[ ]+0[ ]+<.L1>
[ ]+44:[ ]+R_LARCH_B16[ ]+.L1
-[ ]+48:[ ]+6bffb8a4[ ]+bltu[ ]+\$a1,[ ]+\$a0,[ ]+-72\(0x3ffb8\)[ ]+#[ ]+0[ ]+<.L1>
+[ ]+48:[ ]+6bffb8a4[ ]+bltu[ ]+\$a1,[ ]+\$a0,[ ]+-72[ ]+#[ ]+0[ ]+<.L1>
[ ]+48:[ ]+R_LARCH_B16[ ]+.L1
-[ ]+4c:[ ]+6fffb485[ ]+bgeu[ ]+\$a0,[ ]+\$a1,[ ]+-76\(0x3ffb4\)[ ]+#[ ]+0[ ]+<.L1>
+[ ]+4c:[ ]+6fffb485[ ]+bgeu[ ]+\$a0,[ ]+\$a1,[ ]+-76[ ]+#[ ]+0[ ]+<.L1>
[ ]+4c:[ ]+R_LARCH_B16[ ]+.L1
-[ ]+50:[ ]+6fffb0a4[ ]+bgeu[ ]+\$a1,[ ]+\$a0,[ ]+-80\(0x3ffb0\)[ ]+#[ ]+0[ ]+<.L1>
+[ ]+50:[ ]+6fffb0a4[ ]+bgeu[ ]+\$a1,[ ]+\$a0,[ ]+-80[ ]+#[ ]+0[ ]+<.L1>
[ ]+50:[ ]+R_LARCH_B16[ ]+.L1
[ ]+54:[ ]+4c000020[ ]+jirl[ ]+\$zero,[ ]+\$ra,[ ]+0
diff --git a/ld/testsuite/ld-loongarch-elf/macro_op.d b/ld/testsuite/ld-loongarch-elf/macro_op.d
index c7f332e7c9d..edc71bc0dbf 100644
--- a/ld/testsuite/ld-loongarch-elf/macro_op.d
+++ b/ld/testsuite/ld-loongarch-elf/macro_op.d
@@ -8,9 +8,9 @@ Disassembly of section .text:
00000000.* <.L1>:
[ ]+0:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero
-[ ]+4:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1\(0xfff\)
+[ ]+4:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1
[ ]+8:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero
-[ ]+c:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1\(0xfff\)
+[ ]+c:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1
[ ]+10:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+10:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1
[ ]+10:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
diff --git a/ld/testsuite/ld-loongarch-elf/macro_op_32.d b/ld/testsuite/ld-loongarch-elf/macro_op_32.d
index 5ac15fdfea8..188026a5780 100644
--- a/ld/testsuite/ld-loongarch-elf/macro_op_32.d
+++ b/ld/testsuite/ld-loongarch-elf/macro_op_32.d
@@ -9,9 +9,9 @@ Disassembly of section .text:
00000000.* <.L1>:
[ ]+0:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero
-[ ]+4:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1\(0xfff\)
+[ ]+4:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1
[ ]+8:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero
-[ ]+c:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1\(0xfff\)
+[ ]+c:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1
[ ]+10:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+10:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1
[ ]+10:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
diff --git a/opcodes/loongarch-dis.c b/opcodes/loongarch-dis.c
index 11e410f176a..c45c4fc617c 100644
--- a/opcodes/loongarch-dis.c
+++ b/opcodes/loongarch-dis.c
@@ -192,13 +192,7 @@ dis_one_arg (char esc1, char esc2, const char *bit_field,
style = dis_style_immediate;
break;
}
- if (imm == 0)
- info->fprintf_styled_func (info->stream, style, "%d", imm);
- else
- {
- info->fprintf_styled_func (info->stream, style, "%d", imm);
- info->fprintf_styled_func (info->stream, dis_style_text, "(0x%x)", u_imm);
- }
+ info->fprintf_styled_func (info->stream, style, "%d", imm);
switch (esc2)
{
case 'b':
--
2.40.0
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v7 6/7] opcodes/loongarch: print unrecognized insn words with the .word directive
2023-06-29 16:34 [PATCH v7 0/7] LoongArch: disassembler improvements & deprecate old register aliases WANG Xuerui
` (4 preceding siblings ...)
2023-06-29 16:35 ` [PATCH v7 5/7] opcodes/loongarch: do not print hex notation for signed immediates WANG Xuerui
@ 2023-06-29 16:35 ` WANG Xuerui
2023-06-29 16:35 ` [PATCH v7 7/7] LoongArch: Deprecate $v[01], $fv[01] and $x names per spec WANG Xuerui
6 siblings, 0 replies; 8+ messages in thread
From: WANG Xuerui @ 2023-06-29 16:35 UTC (permalink / raw)
To: binutils
Cc: Chenghua Xu, Zhensong Liu, Qinggang Meng, Lulu Cheng,
Fangrui Song, Xi Ruoyao, WANG Xuerui
From: WANG Xuerui <git@xen0n.name>
For better round-trip fidelity and readability in general.
gas/ChangeLog:
* testsuite/gas/loongarch/uleb128.d: Update test case.
* testsuite/gas/loongarch/raw-insn.d: New test.
* testsuite/gas/loongarch/raw-insn.s: Likewise.
opcodes/ChangeLog:
* loongarch-dis.c (disassemble_one): Print ".word" if !opc.
Signed-off-by: WANG Xuerui <git@xen0n.name>
---
gas/testsuite/gas/loongarch/raw-insn.d | 11 +++++++++++
gas/testsuite/gas/loongarch/raw-insn.s | 7 +++++++
gas/testsuite/gas/loongarch/uleb128.d | 20 ++++++++++----------
opcodes/loongarch-dis.c | 1 +
4 files changed, 29 insertions(+), 10 deletions(-)
create mode 100644 gas/testsuite/gas/loongarch/raw-insn.d
create mode 100644 gas/testsuite/gas/loongarch/raw-insn.s
diff --git a/gas/testsuite/gas/loongarch/raw-insn.d b/gas/testsuite/gas/loongarch/raw-insn.d
new file mode 100644
index 00000000000..64980e47f7b
--- /dev/null
+++ b/gas/testsuite/gas/loongarch/raw-insn.d
@@ -0,0 +1,11 @@
+#as:
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+0:[ ]+00000000[ ]+.word[ ]+0x00000000
+[ ]+4:[ ]+feedf00d[ ]+.word[ ]+0xfeedf00d
diff --git a/gas/testsuite/gas/loongarch/raw-insn.s b/gas/testsuite/gas/loongarch/raw-insn.s
new file mode 100644
index 00000000000..528b15263ae
--- /dev/null
+++ b/gas/testsuite/gas/loongarch/raw-insn.s
@@ -0,0 +1,7 @@
+target:
+ .word 0
+ # Given how the LoongArch encoding space is apparently centrally-
+ # managed and sequentially allocated in chunks of prefixes, it is
+ # highly unlikely this would become a valid LoongArch instruction in
+ # the foreseeable future.
+ .word 0xfeedf00d
diff --git a/gas/testsuite/gas/loongarch/uleb128.d b/gas/testsuite/gas/loongarch/uleb128.d
index df66587b692..ad67ded9e7d 100644
--- a/gas/testsuite/gas/loongarch/uleb128.d
+++ b/gas/testsuite/gas/loongarch/uleb128.d
@@ -8,29 +8,29 @@
Disassembly of section .data:
00000000.* <L1-0x5>:
-[ ]+0:[ ]+80030201[ ]+0x80030201
+[ ]+0:[ ]+80030201[ ]+\.word[ ]+0x80030201
[ ]+3:[ ]+R_LARCH_ADD_ULEB128[ ]+L2
[ ]+3:[ ]+R_LARCH_SUB_ULEB128[ ]+L1
[ ]+\.\.\.
0000000000000005[ ]+<L1>:
[ ]+\.\.\.
-[ ]+81:[ ]+ff040000[ ]+0xff040000
+[ ]+81:[ ]+ff040000[ ]+\.word[ ]+0xff040000
[ ]+85:[ ]+cacop[ ]+0x1f,[ ]+\$t3,[ ]+1
0000000000000086[ ]+<L2>:
-[ ]+86:[ ]+07060005[ ]+0x07060005
-[ ]+8a:[ ]+0x00008080
+[ ]+86:[ ]+07060005[ ]+\.word[ ]+0x07060005
+[ ]+8a:[ ]+\.word[ ]+0x00008080
[ ]+8a:[ ]+R_LARCH_ADD_ULEB128[ ]+L4
[ ]+8a:[ ]+R_LARCH_SUB_ULEB128[ ]+L3
000000000000008d[ ]+<L3>:
[ ]+\.\.\.
-[ ]+4089:[ ]+ff080000[ ]+0xff080000
-[ ]+408d:[ ]+0x09ffffff
+[ ]+4089:[ ]+ff080000[ ]+\.word[ ]+0xff080000
+[ ]+408d:[ ]+\.word[ ]+0x09ffffff
0000000000004090[ ]+<L4>:
-[ ]+4090:[ ]+09090909[ ]+0x09090909
-[ ]+4094:[ ]+09090909[ ]+0x09090909
-[ ]+4098:[ ]+09090909[ ]+0x09090909
-[ ]+409c:[ ]+09090909[ ]+0x09090909
+[ ]+4090:[ ]+09090909[ ]+\.word[ ]+0x09090909
+[ ]+4094:[ ]+09090909[ ]+\.word[ ]+0x09090909
+[ ]+4098:[ ]+09090909[ ]+\.word[ ]+0x09090909
+[ ]+409c:[ ]+09090909[ ]+\.word[ ]+0x09090909
diff --git a/opcodes/loongarch-dis.c b/opcodes/loongarch-dis.c
index c45c4fc617c..8d72519be9f 100644
--- a/opcodes/loongarch-dis.c
+++ b/opcodes/loongarch-dis.c
@@ -259,6 +259,7 @@ disassemble_one (insn_t insn, struct disassemble_info *info)
if (!opc)
{
info->insn_type = dis_noninsn;
+ info->fprintf_styled_func (info->stream, dis_style_assembler_directive, ".word\t\t");
info->fprintf_styled_func (info->stream, dis_style_immediate, "0x%08x", insn);
return;
}
--
2.40.0
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v7 7/7] LoongArch: Deprecate $v[01], $fv[01] and $x names per spec
2023-06-29 16:34 [PATCH v7 0/7] LoongArch: disassembler improvements & deprecate old register aliases WANG Xuerui
` (5 preceding siblings ...)
2023-06-29 16:35 ` [PATCH v7 6/7] opcodes/loongarch: print unrecognized insn words with the .word directive WANG Xuerui
@ 2023-06-29 16:35 ` WANG Xuerui
6 siblings, 0 replies; 8+ messages in thread
From: WANG Xuerui @ 2023-06-29 16:35 UTC (permalink / raw)
To: binutils
Cc: Chenghua Xu, Zhensong Liu, Qinggang Meng, Lulu Cheng,
Fangrui Song, Xi Ruoyao, WANG Xuerui
From: WANG Xuerui <git@xen0n.name>
As outlined in the LoongArch ELF psABI spec [1], it is actually already
2 versions after the initial LoongArch support, and the $v[01] and
$fv[01] names should really get sunset by now.
In addition, the "$x" name for $r21 was never included in any released
version of the ABI spec, and such usages are all fixed to say just $r21
for every project I could think of that accepted a LoongArch port.
Plus, the upcoming LSX/LASX support makes use of registers named
"$vrNN" and "$xrNN", so having "$vN" and "$x" alongside would almost
certainly create confusion for developers.
Issue warnings for such usages per the deprecation procedure detailed
in the spec, so we can finally remove support in the next release cycle
after this.
[1]: https://loongson.github.io/LoongArch-Documentation/LoongArch-ELF-ABI-EN.html
gas/ChangeLog:
* config/tc-loongarch.c: Init canonical register ABI name
mappings and deprecated register names.
(loongarch_args_parser_can_match_arg_helper): Warn in case of
deprecated register name usage.
* testsuite/gas/loongarch/deprecated_reg_aliases.d: New test.
* testsuite/gas/loongarch/deprecated_reg_aliases.l: Likewise.
* testsuite/gas/loongarch/deprecated_reg_aliases.s: Likewise.
include/ChangeLog:
* opcode/loongarch.h: Rename global variables.
opcodes/ChangeLog:
* loongarch-opc.c: Rename the alternate/deprecated register name
mappings, and move $x to the deprecated name map.
Signed-off-by: WANG Xuerui <git@xen0n.name>
---
gas/config/tc-loongarch.c | 42 ++++++++++++++++---
.../gas/loongarch/deprecated_reg_aliases.d | 18 ++++++++
.../gas/loongarch/deprecated_reg_aliases.l | 7 ++++
.../gas/loongarch/deprecated_reg_aliases.s | 5 +++
include/opcode/loongarch.h | 4 +-
opcodes/loongarch-opc.c | 8 ++--
6 files changed, 73 insertions(+), 11 deletions(-)
create mode 100644 gas/testsuite/gas/loongarch/deprecated_reg_aliases.d
create mode 100644 gas/testsuite/gas/loongarch/deprecated_reg_aliases.l
create mode 100644 gas/testsuite/gas/loongarch/deprecated_reg_aliases.s
diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c
index 6e8aa35e282..d23506cd023 100644
--- a/gas/config/tc-loongarch.c
+++ b/gas/config/tc-loongarch.c
@@ -223,8 +223,12 @@ md_parse_option (int c, const char *arg)
return ret;
}
+static const char *const *r_abi_names = NULL;
+static const char *const *f_abi_names = NULL;
static struct htab *r_htab = NULL;
+static struct htab *r_deprecated_htab = NULL;
static struct htab *f_htab = NULL;
+static struct htab *f_deprecated_htab = NULL;
static struct htab *fc_htab = NULL;
static struct htab *fcn_htab = NULL;
static struct htab *c_htab = NULL;
@@ -272,7 +276,11 @@ loongarch_after_parse_args ()
/* Init ilp32/lp64 registers names. */
if (!r_htab)
r_htab = str_htab_create (), str_hash_insert (r_htab, "", 0, 0);
+ if (!r_deprecated_htab)
+ r_deprecated_htab = str_htab_create (),
+ str_hash_insert (r_deprecated_htab, "", 0, 0);
+ r_abi_names = loongarch_r_normal_name;
for (i = 0; i < ARRAY_SIZE (loongarch_r_normal_name); i++)
str_hash_insert (r_htab, loongarch_r_normal_name[i], (void *) (i + 1), 0);
@@ -287,7 +295,11 @@ loongarch_after_parse_args ()
{
if (!f_htab)
f_htab = str_htab_create (), str_hash_insert (f_htab, "", 0, 0);
+ if (!f_deprecated_htab)
+ f_deprecated_htab = str_htab_create (),
+ str_hash_insert (f_deprecated_htab, "", 0, 0);
+ f_abi_names = loongarch_f_normal_name;
for (i = 0; i < ARRAY_SIZE (loongarch_f_normal_name); i++)
str_hash_insert (f_htab, loongarch_f_normal_name[i], (void *) (i + 1),
0);
@@ -338,22 +350,24 @@ loongarch_after_parse_args ()
/* Init lp64 registers alias. */
if (LARCH_opts.ase_lp64)
{
+ r_abi_names = loongarch_r_lp64_name;
for (i = 0; i < ARRAY_SIZE (loongarch_r_lp64_name); i++)
str_hash_insert (r_htab, loongarch_r_lp64_name[i], (void *) (i + 1),
0);
- for (i = 0; i < ARRAY_SIZE (loongarch_r_lp64_name1); i++)
- str_hash_insert (r_htab, loongarch_r_lp64_name1[i], (void *) (i + 1),
- 0);
+ for (i = 0; i < ARRAY_SIZE (loongarch_r_lp64_name_deprecated); i++)
+ str_hash_insert (r_deprecated_htab, loongarch_r_lp64_name_deprecated[i],
+ (void *) (i + 1), 0);
}
/* Init float-lp64 registers alias */
if ((LARCH_opts.ase_sf || LARCH_opts.ase_df) && LARCH_opts.ase_lp64)
{
+ f_abi_names = loongarch_f_lp64_name;
for (i = 0; i < ARRAY_SIZE (loongarch_f_lp64_name); i++)
str_hash_insert (f_htab, loongarch_f_lp64_name[i],
(void *) (i + 1), 0);
- for (i = 0; i < ARRAY_SIZE (loongarch_f_lp64_name1); i++)
- str_hash_insert (f_htab, loongarch_f_lp64_name1[i],
+ for (i = 0; i < ARRAY_SIZE (loongarch_f_lp64_name_deprecated); i++)
+ str_hash_insert (f_deprecated_htab, loongarch_f_lp64_name_deprecated[i],
(void *) (i + 1), 0);
}
}
@@ -684,6 +698,15 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2,
imm = (intptr_t) str_hash_find (r_htab, arg);
ip->match_now = 0 < imm;
ret = imm - 1;
+ if (ip->match_now)
+ break;
+ /* Handle potential usage of deprecated register aliases. */
+ imm = (intptr_t) str_hash_find (r_deprecated_htab, arg);
+ ip->match_now = 0 < imm;
+ ret = imm - 1;
+ if (ip->match_now && !ip->macro_id)
+ as_warn (_("register alias %s is deprecated, use %s instead"),
+ arg, r_abi_names[ret]);
break;
case 'f':
switch (esc_ch2)
@@ -700,6 +723,15 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2,
}
ip->match_now = 0 < imm;
ret = imm - 1;
+ if (ip->match_now && !ip->macro_id)
+ break;
+ /* Handle potential usage of deprecated register aliases. */
+ imm = (intptr_t) str_hash_find (f_deprecated_htab, arg);
+ ip->match_now = 0 < imm;
+ ret = imm - 1;
+ if (ip->match_now)
+ as_warn (_("register alias %s is deprecated, use %s instead"),
+ arg, f_abi_names[ret]);
break;
case 'c':
switch (esc_ch2)
diff --git a/gas/testsuite/gas/loongarch/deprecated_reg_aliases.d b/gas/testsuite/gas/loongarch/deprecated_reg_aliases.d
new file mode 100644
index 00000000000..3ea0806765f
--- /dev/null
+++ b/gas/testsuite/gas/loongarch/deprecated_reg_aliases.d
@@ -0,0 +1,18 @@
+#name: Deprecated register aliases
+#as-new:
+#objdump: -d
+#warning_output: deprecated_reg_aliases.l
+#skip: loongarch32-*-*
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0000000000000000 <foo>:
+[ ]+0:[ ]+14acf125[ ]+lu12i\.w[ ]+\$a1, 354185
+[ ]+4:[ ]+038048a5[ ]+ori[ ]+\$a1, \$a1, 0x12
+[ ]+8:[ ]+16024685[ ]+lu32i\.d[ ]+\$a1, 4660
+[ ]+c:[ ]+08200420[ ]+fmadd\.d[ ]+\$fa0, \$fa1, \$fa1, \$fa0
+[ ]+10:[ ]+380c16a4[ ]+ldx\.d[ ]+\$a0, \$r21, \$a1
+[ ]+14:[ ]+4c000020[ ]+ret[ ]+
diff --git a/gas/testsuite/gas/loongarch/deprecated_reg_aliases.l b/gas/testsuite/gas/loongarch/deprecated_reg_aliases.l
new file mode 100644
index 00000000000..b82c209e541
--- /dev/null
+++ b/gas/testsuite/gas/loongarch/deprecated_reg_aliases.l
@@ -0,0 +1,7 @@
+.*Assembler messages:
+.*:2: Warning: register alias \$v1 is deprecated, use \$a1 instead
+.*:3: Warning: register alias \$fv0 is deprecated, use \$fa0 instead
+.*:3: Warning: register alias \$fv1 is deprecated, use \$fa1 instead
+.*:3: Warning: register alias \$fv1 is deprecated, use \$fa1 instead
+.*:4: Warning: register alias \$v0 is deprecated, use \$a0 instead
+.*:4: Warning: register alias \$x is deprecated, use \$r21 instead
diff --git a/gas/testsuite/gas/loongarch/deprecated_reg_aliases.s b/gas/testsuite/gas/loongarch/deprecated_reg_aliases.s
new file mode 100644
index 00000000000..7848346e6ae
--- /dev/null
+++ b/gas/testsuite/gas/loongarch/deprecated_reg_aliases.s
@@ -0,0 +1,5 @@
+foo:
+ li.d $v1, 0x123456789012
+ fmadd.d $fv0, $fv1, $fv1, $fa0
+ ldx.d $v0, $x, $a1
+ ret
diff --git a/include/opcode/loongarch.h b/include/opcode/loongarch.h
index e9632ad3361..6d399f70a98 100644
--- a/include/opcode/loongarch.h
+++ b/include/opcode/loongarch.h
@@ -178,10 +178,10 @@ dec2 : [1-9][0-9]?
extern const char *const loongarch_r_normal_name[32];
extern const char *const loongarch_r_lp64_name[32];
- extern const char *const loongarch_r_lp64_name1[32];
+ extern const char *const loongarch_r_lp64_name_deprecated[32];
extern const char *const loongarch_f_normal_name[32];
extern const char *const loongarch_f_lp64_name[32];
- extern const char *const loongarch_f_lp64_name1[32];
+ extern const char *const loongarch_f_lp64_name_deprecated[32];
extern const char *const loongarch_fc_normal_name[4];
extern const char *const loongarch_fc_numeric_name[4];
extern const char *const loongarch_c_normal_name[8];
diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c
index 8be227cd9a9..05cf4eb463c 100644
--- a/opcodes/loongarch-opc.c
+++ b/opcodes/loongarch-opc.c
@@ -45,14 +45,14 @@ const char *const loongarch_r_lp64_name[32] =
{
"$zero", "$ra", "$tp", "$sp", "$a0", "$a1", "$a2", "$a3",
"$a4", "$a5", "$a6", "$a7", "$t0", "$t1", "$t2", "$t3",
- "$t4", "$t5", "$t6", "$t7", "$t8", "$x", "$fp", "$s0",
+ "$t4", "$t5", "$t6", "$t7", "$t8", "$r21","$fp", "$s0",
"$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7", "$s8",
};
-const char *const loongarch_r_lp64_name1[32] =
+const char *const loongarch_r_lp64_name_deprecated[32] =
{
"", "", "", "", "$v0", "$v1", "", "", "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "$x", "", "", "", "", "", "", "", "", "", "",
};
const char *const loongarch_f_normal_name[32] =
@@ -71,7 +71,7 @@ const char *const loongarch_f_lp64_name[32] =
"$fs0", "$fs1", "$fs2", "$fs3", "$fs4", "$fs5", "$fs6", "$fs7",
};
-const char *const loongarch_f_lp64_name1[32] =
+const char *const loongarch_f_lp64_name_deprecated[32] =
{
"$fv0", "$fv1", "", "", "", "", "", "", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "",
--
2.40.0
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2023-06-29 16:35 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-06-29 16:34 [PATCH v7 0/7] LoongArch: disassembler improvements & deprecate old register aliases WANG Xuerui
2023-06-29 16:34 ` [PATCH v7 1/7] LoongArch: support disassembling certain pseudo-instructions WANG Xuerui
2023-06-29 16:34 ` [PATCH v7 2/7] opcodes/loongarch: remove unused code WANG Xuerui
2023-06-29 16:35 ` [PATCH v7 3/7] opcodes/loongarch: implement style support in the disassembler WANG Xuerui
2023-06-29 16:35 ` [PATCH v7 4/7] opcodes/loongarch: style disassembled address offsets as such WANG Xuerui
2023-06-29 16:35 ` [PATCH v7 5/7] opcodes/loongarch: do not print hex notation for signed immediates WANG Xuerui
2023-06-29 16:35 ` [PATCH v7 6/7] opcodes/loongarch: print unrecognized insn words with the .word directive WANG Xuerui
2023-06-29 16:35 ` [PATCH v7 7/7] LoongArch: Deprecate $v[01], $fv[01] and $x names per spec WANG Xuerui
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