From: cailulu <cailulu@loongson.cn>
To: binutils@sourceware.org
Cc: xuchenghua@loongson.cn, chenglulu@loongson.cn,
liuzhensong@loongson.cn, mengqinggang@loongson.cn,
xry111@xry111.site, i.swmail@xen0n.name, maskray@google.com,
cailulu <cailulu@loongson.cn>
Subject: [PATCH 2/2] Add testcase for generation of 32/64_PCREL.
Date: Fri, 1 Sep 2023 11:09:01 +0800 [thread overview]
Message-ID: <20230901030901.2519730-2-cailulu@loongson.cn> (raw)
In-Reply-To: <20230901030901.2519730-1-cailulu@loongson.cn>
---
gas/testsuite/gas/loongarch/pcrel_norelax.d | 56 +++++++++++++++++++
gas/testsuite/gas/loongarch/pcrel_norelax.s | 42 +++++++++++++++
gas/testsuite/gas/loongarch/pcrel_relax.d | 60 +++++++++++++++++++++
gas/testsuite/gas/loongarch/pcrel_relax.s | 46 ++++++++++++++++
4 files changed, 204 insertions(+)
create mode 100644 gas/testsuite/gas/loongarch/pcrel_norelax.d
create mode 100644 gas/testsuite/gas/loongarch/pcrel_norelax.s
create mode 100644 gas/testsuite/gas/loongarch/pcrel_relax.d
create mode 100644 gas/testsuite/gas/loongarch/pcrel_relax.s
diff --git a/gas/testsuite/gas/loongarch/pcrel_norelax.d b/gas/testsuite/gas/loongarch/pcrel_norelax.d
new file mode 100644
index 00000000000..842c8d48e0e
--- /dev/null
+++ b/gas/testsuite/gas/loongarch/pcrel_norelax.d
@@ -0,0 +1,56 @@
+#as: -mno-relax
+#objdump: -Dr
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+00000000.* <.L1>:
+[ ]+...
+[ ]+0:[ ]+R_LARCH_32_PCREL[ ]+.L3
+[ ]+4:[ ]+R_LARCH_32_PCREL[ ]+.L3\+0x4
+
+0*00000008[ ]+<.L2>:
+[ ]+...
+[ ]+8:[ ]+R_LARCH_64_PCREL[ ]+.L3
+[ ]+10:[ ]+R_LARCH_64_PCREL[ ]+.L3\+0x8
+
+Disassembly[ ]+of[ ]+section[ ]+sx:
+
+0*00000000[ ]+<.L3>:
+[ ]+0:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4
+[ ]+4:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4
+[ ]+8:[ ]+ffffffff[ ]+.word[ ]+0xffffffff
+
+0*0000000c[ ]+<.L4>:
+[ ]+...
+[ ]+c:[ ]+R_LARCH_ADD32[ ]+.L4
+[ ]+c:[ ]+R_LARCH_SUB32[ ]+.L5
+[ ]+10:[ ]+R_LARCH_ADD64[ ]+.L4
+[ ]+10:[ ]+R_LARCH_SUB64[ ]+.L5
+
+Disassembly[ ]+of[ ]+section[ ]+sy:
+
+0*00000000[ ]+<.L5>:
+[ ]+...
+[ ]+0:[ ]+R_LARCH_32_PCREL[ ]+.L1
+[ ]+4:[ ]+R_LARCH_32_PCREL[ ]+.L2\+0x4
+[ ]+8:[ ]+R_LARCH_64_PCREL[ ]+.L1\+0x8
+[ ]+10:[ ]+R_LARCH_64_PCREL[ ]+.L2\+0x10
+
+Disassembly[ ]+of[ ]+section[ ]+sz:
+
+0*00000000[ ]+<sz>:
+[ ]+0:[ ]+fffffff8[ ]+.word[ ]+0xfffffff8
+[ ]+4:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4
+[ ]+8:[ ]+00000000[ ]+.word[ ]+0x00000000
+[ ]+8:[ ]+R_LARCH_ADD32[ ]+.L2
+[ ]+8:[ ]+R_LARCH_SUB32[ ]+.L3
+[ ]+c:[ ]+fffffff8[ ]+.word[ ]+0xfffffff8
+[ ]+10:[ ]+ffffffff[ ]+.word[ ]+0xffffffff
+[ ]+14:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4
+[ ]+18:[ ]+ffffffff[ ]+.word[ ]+0xffffffff
+[ ]+...
+[ ]+1c:[ ]+R_LARCH_ADD64[ ]+.L2
+[ ]+1c:[ ]+R_LARCH_SUB64[ ]+.L3
diff --git a/gas/testsuite/gas/loongarch/pcrel_norelax.s b/gas/testsuite/gas/loongarch/pcrel_norelax.s
new file mode 100644
index 00000000000..09527f146a9
--- /dev/null
+++ b/gas/testsuite/gas/loongarch/pcrel_norelax.s
@@ -0,0 +1,42 @@
+ .section .text
+.L1:
+ # 32_pcrel
+ .4byte .L3-.L1
+ .4byte .L3-.L1
+.L2:
+ # 64_pcrel
+ .8byte .L3-.L2
+ .8byte .L3-.L2
+
+ .section sx
+.L3:
+ # no relocation
+ .4byte .L3-.L4
+ .8byte .L3-.L4
+.L4:
+ # add32+sub32
+ .4byte .L4-.L5
+ # add64+sub64
+ .8byte .L4-.L5
+
+ .section sy
+.L5:
+ # 32_pcrel
+ .4byte .L1-.L5
+ .4byte .L2-.L5
+ # 64_pcrel
+ .8byte .L1-.L5
+ .8byte .L2-.L5
+
+ .section sz
+ # no relocation
+ .4byte .L1-.L2
+ .4byte .L3-.L4
+ # add32+sub32
+ .4byte .L2-.L3
+
+ # no relocation
+ .8byte .L1-.L2
+ .8byte .L3-.L4
+ # add64+sub64
+ .8byte .L2-.L3
diff --git a/gas/testsuite/gas/loongarch/pcrel_relax.d b/gas/testsuite/gas/loongarch/pcrel_relax.d
new file mode 100644
index 00000000000..d6f875259be
--- /dev/null
+++ b/gas/testsuite/gas/loongarch/pcrel_relax.d
@@ -0,0 +1,60 @@
+#as:
+#objdump: -Dr
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+00000000.* <.L1>:
+[ ]+...
+[ ]+0:[ ]+R_LARCH_32_PCREL[ ]+.L3
+[ ]+4:[ ]+R_LARCH_ADD32[ ]+.L3
+[ ]+4:[ ]+R_LARCH_SUB32[ ]+.L1
+
+0*00000008[ ]+<.L2>:
+[ ]+...
+[ ]+8:[ ]+R_LARCH_64_PCREL[ ]+.L3
+[ ]+10:[ ]+R_LARCH_ADD64[ ]+.L3
+[ ]+10:[ ]+R_LARCH_SUB64[ ]+.L2
+
+Disassembly[ ]+of[ ]+section[ ]+sx:
+
+0*00000000[ ]+<.L3>:
+[ ]+0:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4
+[ ]+4:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4
+[ ]+8:[ ]+ffffffff[ ]+.word[ ]+0xffffffff
+
+0*0000000c[ ]+<.L4>:
+[ ]+...
+[ ]+c:[ ]+R_LARCH_ADD32[ ]+.L4
+[ ]+c:[ ]+R_LARCH_SUB32[ ]+.L5
+[ ]+10:[ ]+R_LARCH_ADD64[ ]+.L4
+[ ]+10:[ ]+R_LARCH_SUB64[ ]+.L5
+
+Disassembly[ ]+of[ ]+section[ ]+sy:
+
+0*00000000[ ]+<.L5>:
+[ ]+...
+[ ]+0:[ ]+R_LARCH_32_PCREL[ ]+.L1
+[ ]+4:[ ]+R_LARCH_32_PCREL[ ]+.L3\+0x4
+[ ]+8:[ ]+R_LARCH_64_PCREL[ ]+.L1\+0x8
+[ ]+10:[ ]+R_LARCH_64_PCREL[ ]+.L3\+0x10
+
+Disassembly[ ]+of[ ]+section[ ]+sz:
+
+0*00000000[ ]+<sz>:
+[ ]+0:[ ]+00000000[ ]+.word[ ]+0x00000000
+[ ]+0:[ ]+R_LARCH_ADD32[ ]+.L1
+[ ]+0:[ ]+R_LARCH_SUB32[ ]+.L2
+[ ]+4:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4
+[ ]+...
+[ ]+8:[ ]+R_LARCH_ADD32[ ]+.L3
+[ ]+8:[ ]+R_LARCH_SUB32[ ]+.L5
+[ ]+c:[ ]+R_LARCH_ADD64[ ]+.L1
+[ ]+c:[ ]+R_LARCH_SUB64[ ]+.L2
+[ ]+14:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4
+[ ]+18:[ ]+ffffffff[ ]+.word[ ]+0xffffffff
+[ ]+...
+[ ]+1c:[ ]+R_LARCH_ADD64[ ]+.L3
+[ ]+1c:[ ]+R_LARCH_SUB64[ ]+.L5
diff --git a/gas/testsuite/gas/loongarch/pcrel_relax.s b/gas/testsuite/gas/loongarch/pcrel_relax.s
new file mode 100644
index 00000000000..ded275fa72c
--- /dev/null
+++ b/gas/testsuite/gas/loongarch/pcrel_relax.s
@@ -0,0 +1,46 @@
+ .section .text
+.L1:
+ # 32_pcrel
+ .4byte .L3-.L1
+ # add32+sub32
+ .4byte .L3-.L1
+.L2:
+ # 64_pcrel
+ .8byte .L3-.L2
+ # add64+sub64
+ .8byte .L3-.L2
+
+ .section sx
+.L3:
+ # no relocation
+ .4byte .L3-.L4
+ .8byte .L3-.L4
+.L4:
+ # add32+sub32
+ .4byte .L4-.L5
+ # add64+sub64
+ .8byte .L4-.L5
+
+ .section sy
+.L5:
+ # 32_pcrel
+ .4byte .L1-.L5
+ .4byte .L3-.L5
+ # 64_pcrel
+ .8byte .L1-.L5
+ .8byte .L3-.L5
+
+ .section sz
+ # add32+sub32
+ .4byte .L1-.L2
+ # no relocation
+ .4byte .L3-.L4
+ # add32+sub32
+ .4byte .L3-.L5
+
+ #add64+sub64
+ .8byte .L1-.L2
+ # no relocation
+ .8byte .L3-.L4
+ #add64+sub64
+ .8byte .L3-.L5
--
2.31.1
prev parent reply other threads:[~2023-09-01 3:09 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-01 3:09 [PATCH 1/2] Use 32/64_PCREL to replace a pair of ADD32/64 and SUB32/64 cailulu
2023-09-01 3:09 ` cailulu [this message]
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