* [PATCH 1/2] Use 32/64_PCREL to replace a pair of ADD32/64 and SUB32/64.
@ 2023-09-01 3:09 cailulu
2023-09-01 3:09 ` [PATCH 2/2] Add testcase for generation of 32/64_PCREL cailulu
0 siblings, 1 reply; 2+ messages in thread
From: cailulu @ 2023-09-01 3:09 UTC (permalink / raw)
To: binutils
Cc: xuchenghua, chenglulu, liuzhensong, mengqinggang, xry111,
i.swmail, maskray, cailulu
Subtraction for labels that require static relocation
usually generates ADD32/64 and SUB32/64.
If subsy of BFD_RELOC_32/64 and PC in same segment,
and disable relax or PC at start of subsy or enable
relax but not in SEC_CODE, we generate 32/64_PCREL
to replace a pair of ADD32/64 and SUB32/64.
---
gas/config/tc-loongarch.c | 22 ++++++++++++----------
gas/config/tc-loongarch.h | 12 ++++++++++--
2 files changed, 22 insertions(+), 12 deletions(-)
diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c
index 2e8a259d147..57faffeb14d 100644
--- a/gas/config/tc-loongarch.c
+++ b/gas/config/tc-loongarch.c
@@ -1195,7 +1195,6 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
static int64_t stack_top;
static int last_reloc_is_sop_push_pcrel_1 = 0;
int last_reloc_is_sop_push_pcrel = last_reloc_is_sop_push_pcrel_1;
- segT sub_segment;
last_reloc_is_sop_push_pcrel_1 = 0;
char *buf = fixP->fx_frag->fr_literal + fixP->fx_where;
@@ -1273,16 +1272,19 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
(use md_number_to_chars (buf, 0, fixP->fx_size)). */
case BFD_RELOC_64:
case BFD_RELOC_32:
- if (fixP->fx_r_type == BFD_RELOC_32
- && fixP->fx_addsy && fixP->fx_subsy
- && (sub_segment = S_GET_SEGMENT (fixP->fx_subsy))
- && strcmp (sub_segment->name, ".eh_frame") == 0
- && S_GET_VALUE (fixP->fx_subsy)
- == fixP->fx_frag->fr_address + fixP->fx_where)
+ if (fixP->fx_pcrel)
{
- fixP->fx_r_type = BFD_RELOC_LARCH_32_PCREL;
- fixP->fx_subsy = NULL;
- break;
+ switch (fixP->fx_r_type)
+ {
+ case BFD_RELOC_64:
+ fixP->fx_r_type = BFD_RELOC_LARCH_64_PCREL;
+ break;
+ case BFD_RELOC_32:
+ fixP->fx_r_type = BFD_RELOC_LARCH_32_PCREL;
+ break;
+ default:
+ break;
+ }
}
if (fixP->fx_addsy && fixP->fx_subsy)
diff --git a/gas/config/tc-loongarch.h b/gas/config/tc-loongarch.h
index a9f2a0a17cc..d353f18d0d2 100644
--- a/gas/config/tc-loongarch.h
+++ b/gas/config/tc-loongarch.h
@@ -71,8 +71,16 @@ extern bool loongarch_frag_align_code (int);
relaxation, so do not resolve such expressions in the assembler. */
#define md_allow_local_subtract(l,r,s) 0
-/* Values passed to md_apply_fix don't include symbol values. */
-#define TC_FORCE_RELOCATION_SUB_LOCAL(FIX, SEG) 1
+/* If subsy of BFD_RELOC32/64 and PC in same segment, and without relax
+ or PC at start of subsy or with relax but sub_symbol_segment not in
+ SEC_CODE, we generate 32/64_PCREL. */
+#define TC_FORCE_RELOCATION_SUB_LOCAL(FIX, SEG) \
+ (!((BFD_RELOC_32 || BFD_RELOC_64) \
+ &&(!LARCH_opts.relax \
+ || S_GET_VALUE (FIX->fx_subsy) \
+ == FIX->fx_frag->fr_address + FIX->fx_where \
+ || (LARCH_opts.relax \
+ && ((S_GET_SEGMENT (FIX->fx_subsy)->flags & SEC_CODE) == 0)))))
#define TC_VALIDATE_FIX_SUB(FIX, SEG) 1
#define DIFF_EXPR_OK 1
--
2.31.1
^ permalink raw reply [flat|nested] 2+ messages in thread
* [PATCH 2/2] Add testcase for generation of 32/64_PCREL.
2023-09-01 3:09 [PATCH 1/2] Use 32/64_PCREL to replace a pair of ADD32/64 and SUB32/64 cailulu
@ 2023-09-01 3:09 ` cailulu
0 siblings, 0 replies; 2+ messages in thread
From: cailulu @ 2023-09-01 3:09 UTC (permalink / raw)
To: binutils
Cc: xuchenghua, chenglulu, liuzhensong, mengqinggang, xry111,
i.swmail, maskray, cailulu
---
gas/testsuite/gas/loongarch/pcrel_norelax.d | 56 +++++++++++++++++++
gas/testsuite/gas/loongarch/pcrel_norelax.s | 42 +++++++++++++++
gas/testsuite/gas/loongarch/pcrel_relax.d | 60 +++++++++++++++++++++
gas/testsuite/gas/loongarch/pcrel_relax.s | 46 ++++++++++++++++
4 files changed, 204 insertions(+)
create mode 100644 gas/testsuite/gas/loongarch/pcrel_norelax.d
create mode 100644 gas/testsuite/gas/loongarch/pcrel_norelax.s
create mode 100644 gas/testsuite/gas/loongarch/pcrel_relax.d
create mode 100644 gas/testsuite/gas/loongarch/pcrel_relax.s
diff --git a/gas/testsuite/gas/loongarch/pcrel_norelax.d b/gas/testsuite/gas/loongarch/pcrel_norelax.d
new file mode 100644
index 00000000000..842c8d48e0e
--- /dev/null
+++ b/gas/testsuite/gas/loongarch/pcrel_norelax.d
@@ -0,0 +1,56 @@
+#as: -mno-relax
+#objdump: -Dr
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+00000000.* <.L1>:
+[ ]+...
+[ ]+0:[ ]+R_LARCH_32_PCREL[ ]+.L3
+[ ]+4:[ ]+R_LARCH_32_PCREL[ ]+.L3\+0x4
+
+0*00000008[ ]+<.L2>:
+[ ]+...
+[ ]+8:[ ]+R_LARCH_64_PCREL[ ]+.L3
+[ ]+10:[ ]+R_LARCH_64_PCREL[ ]+.L3\+0x8
+
+Disassembly[ ]+of[ ]+section[ ]+sx:
+
+0*00000000[ ]+<.L3>:
+[ ]+0:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4
+[ ]+4:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4
+[ ]+8:[ ]+ffffffff[ ]+.word[ ]+0xffffffff
+
+0*0000000c[ ]+<.L4>:
+[ ]+...
+[ ]+c:[ ]+R_LARCH_ADD32[ ]+.L4
+[ ]+c:[ ]+R_LARCH_SUB32[ ]+.L5
+[ ]+10:[ ]+R_LARCH_ADD64[ ]+.L4
+[ ]+10:[ ]+R_LARCH_SUB64[ ]+.L5
+
+Disassembly[ ]+of[ ]+section[ ]+sy:
+
+0*00000000[ ]+<.L5>:
+[ ]+...
+[ ]+0:[ ]+R_LARCH_32_PCREL[ ]+.L1
+[ ]+4:[ ]+R_LARCH_32_PCREL[ ]+.L2\+0x4
+[ ]+8:[ ]+R_LARCH_64_PCREL[ ]+.L1\+0x8
+[ ]+10:[ ]+R_LARCH_64_PCREL[ ]+.L2\+0x10
+
+Disassembly[ ]+of[ ]+section[ ]+sz:
+
+0*00000000[ ]+<sz>:
+[ ]+0:[ ]+fffffff8[ ]+.word[ ]+0xfffffff8
+[ ]+4:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4
+[ ]+8:[ ]+00000000[ ]+.word[ ]+0x00000000
+[ ]+8:[ ]+R_LARCH_ADD32[ ]+.L2
+[ ]+8:[ ]+R_LARCH_SUB32[ ]+.L3
+[ ]+c:[ ]+fffffff8[ ]+.word[ ]+0xfffffff8
+[ ]+10:[ ]+ffffffff[ ]+.word[ ]+0xffffffff
+[ ]+14:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4
+[ ]+18:[ ]+ffffffff[ ]+.word[ ]+0xffffffff
+[ ]+...
+[ ]+1c:[ ]+R_LARCH_ADD64[ ]+.L2
+[ ]+1c:[ ]+R_LARCH_SUB64[ ]+.L3
diff --git a/gas/testsuite/gas/loongarch/pcrel_norelax.s b/gas/testsuite/gas/loongarch/pcrel_norelax.s
new file mode 100644
index 00000000000..09527f146a9
--- /dev/null
+++ b/gas/testsuite/gas/loongarch/pcrel_norelax.s
@@ -0,0 +1,42 @@
+ .section .text
+.L1:
+ # 32_pcrel
+ .4byte .L3-.L1
+ .4byte .L3-.L1
+.L2:
+ # 64_pcrel
+ .8byte .L3-.L2
+ .8byte .L3-.L2
+
+ .section sx
+.L3:
+ # no relocation
+ .4byte .L3-.L4
+ .8byte .L3-.L4
+.L4:
+ # add32+sub32
+ .4byte .L4-.L5
+ # add64+sub64
+ .8byte .L4-.L5
+
+ .section sy
+.L5:
+ # 32_pcrel
+ .4byte .L1-.L5
+ .4byte .L2-.L5
+ # 64_pcrel
+ .8byte .L1-.L5
+ .8byte .L2-.L5
+
+ .section sz
+ # no relocation
+ .4byte .L1-.L2
+ .4byte .L3-.L4
+ # add32+sub32
+ .4byte .L2-.L3
+
+ # no relocation
+ .8byte .L1-.L2
+ .8byte .L3-.L4
+ # add64+sub64
+ .8byte .L2-.L3
diff --git a/gas/testsuite/gas/loongarch/pcrel_relax.d b/gas/testsuite/gas/loongarch/pcrel_relax.d
new file mode 100644
index 00000000000..d6f875259be
--- /dev/null
+++ b/gas/testsuite/gas/loongarch/pcrel_relax.d
@@ -0,0 +1,60 @@
+#as:
+#objdump: -Dr
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+00000000.* <.L1>:
+[ ]+...
+[ ]+0:[ ]+R_LARCH_32_PCREL[ ]+.L3
+[ ]+4:[ ]+R_LARCH_ADD32[ ]+.L3
+[ ]+4:[ ]+R_LARCH_SUB32[ ]+.L1
+
+0*00000008[ ]+<.L2>:
+[ ]+...
+[ ]+8:[ ]+R_LARCH_64_PCREL[ ]+.L3
+[ ]+10:[ ]+R_LARCH_ADD64[ ]+.L3
+[ ]+10:[ ]+R_LARCH_SUB64[ ]+.L2
+
+Disassembly[ ]+of[ ]+section[ ]+sx:
+
+0*00000000[ ]+<.L3>:
+[ ]+0:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4
+[ ]+4:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4
+[ ]+8:[ ]+ffffffff[ ]+.word[ ]+0xffffffff
+
+0*0000000c[ ]+<.L4>:
+[ ]+...
+[ ]+c:[ ]+R_LARCH_ADD32[ ]+.L4
+[ ]+c:[ ]+R_LARCH_SUB32[ ]+.L5
+[ ]+10:[ ]+R_LARCH_ADD64[ ]+.L4
+[ ]+10:[ ]+R_LARCH_SUB64[ ]+.L5
+
+Disassembly[ ]+of[ ]+section[ ]+sy:
+
+0*00000000[ ]+<.L5>:
+[ ]+...
+[ ]+0:[ ]+R_LARCH_32_PCREL[ ]+.L1
+[ ]+4:[ ]+R_LARCH_32_PCREL[ ]+.L3\+0x4
+[ ]+8:[ ]+R_LARCH_64_PCREL[ ]+.L1\+0x8
+[ ]+10:[ ]+R_LARCH_64_PCREL[ ]+.L3\+0x10
+
+Disassembly[ ]+of[ ]+section[ ]+sz:
+
+0*00000000[ ]+<sz>:
+[ ]+0:[ ]+00000000[ ]+.word[ ]+0x00000000
+[ ]+0:[ ]+R_LARCH_ADD32[ ]+.L1
+[ ]+0:[ ]+R_LARCH_SUB32[ ]+.L2
+[ ]+4:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4
+[ ]+...
+[ ]+8:[ ]+R_LARCH_ADD32[ ]+.L3
+[ ]+8:[ ]+R_LARCH_SUB32[ ]+.L5
+[ ]+c:[ ]+R_LARCH_ADD64[ ]+.L1
+[ ]+c:[ ]+R_LARCH_SUB64[ ]+.L2
+[ ]+14:[ ]+fffffff4[ ]+.word[ ]+0xfffffff4
+[ ]+18:[ ]+ffffffff[ ]+.word[ ]+0xffffffff
+[ ]+...
+[ ]+1c:[ ]+R_LARCH_ADD64[ ]+.L3
+[ ]+1c:[ ]+R_LARCH_SUB64[ ]+.L5
diff --git a/gas/testsuite/gas/loongarch/pcrel_relax.s b/gas/testsuite/gas/loongarch/pcrel_relax.s
new file mode 100644
index 00000000000..ded275fa72c
--- /dev/null
+++ b/gas/testsuite/gas/loongarch/pcrel_relax.s
@@ -0,0 +1,46 @@
+ .section .text
+.L1:
+ # 32_pcrel
+ .4byte .L3-.L1
+ # add32+sub32
+ .4byte .L3-.L1
+.L2:
+ # 64_pcrel
+ .8byte .L3-.L2
+ # add64+sub64
+ .8byte .L3-.L2
+
+ .section sx
+.L3:
+ # no relocation
+ .4byte .L3-.L4
+ .8byte .L3-.L4
+.L4:
+ # add32+sub32
+ .4byte .L4-.L5
+ # add64+sub64
+ .8byte .L4-.L5
+
+ .section sy
+.L5:
+ # 32_pcrel
+ .4byte .L1-.L5
+ .4byte .L3-.L5
+ # 64_pcrel
+ .8byte .L1-.L5
+ .8byte .L3-.L5
+
+ .section sz
+ # add32+sub32
+ .4byte .L1-.L2
+ # no relocation
+ .4byte .L3-.L4
+ # add32+sub32
+ .4byte .L3-.L5
+
+ #add64+sub64
+ .8byte .L1-.L2
+ # no relocation
+ .8byte .L3-.L4
+ #add64+sub64
+ .8byte .L3-.L5
--
2.31.1
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2023-09-01 3:09 [PATCH 1/2] Use 32/64_PCREL to replace a pair of ADD32/64 and SUB32/64 cailulu
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