From: Mary Bennett <mary.bennett@embecosm.com>
To: binutils@sourceware.org
Cc: kito.cheng@gmail.com, nelson@rivosinc.com, research_trasio@irq.a4lg.com
Subject: [PATCH v2 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions
Date: Tue, 12 Sep 2023 15:24:18 +0100 [thread overview]
Message-ID: <20230912142420.767433-1-mary.bennett@embecosm.com> (raw)
In-Reply-To: <20230905145300.652455-1-mary.bennett@embecosm.com>
Changes: v1 -> v2
- Added MASK_<INSN> for each instruction, as suggested
- Changed operand 'x' to operand 'X', as suggested
This patch series presents the comprehensive implementation of the MAC and ALU
extension for CORE-V.
Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
ensure its correctness and compatibility with the existing codebase.
However, your input, reviews, and suggestions are invaluable in making this
extension even more robust.
The CORE-V instructions are described in the specification [1] and work can be
found in the OpenHW group's Github repository [2].
[1] docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
[2] github.com/openhwgroup/corev-binutils-gdb
Contributors:
Mary Bennett <mary.bennett@embecosm.com>
Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Pietra Ferreira <pietra.ferreira@embecosm.com>
Charlie Keaney
Jessica Mills
Craig Blackmore <craig.blackmore@embecosm.com>
Simon Cook <simon.cook@embecosm.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
Helene Chelin <helene.chelin@embecosm.com>
RISC-V: Add support for XCValu extension in CV32E40P
RISC-V: Add support for XCVmac extension in CV32E40P
bfd/elfxx-riscv.c | 11 ++
gas/config/tc-riscv.c | 42 +++++
gas/doc/c-riscv.texi | 10 ++
gas/testsuite/gas/riscv/cv-alu-boundaries.d | 3 +
gas/testsuite/gas/riscv/cv-alu-boundaries.l | 14 ++
gas/testsuite/gas/riscv/cv-alu-boundaries.s | 27 +++
gas/testsuite/gas/riscv/cv-alu-fail-march.d | 3 +
gas/testsuite/gas/riscv/cv-alu-fail-march.l | 32 ++++
gas/testsuite/gas/riscv/cv-alu-fail-march.s | 33 ++++
.../gas/riscv/cv-alu-fail-operand-01.d | 3 +
.../gas/riscv/cv-alu-fail-operand-01.l | 32 ++++
.../gas/riscv/cv-alu-fail-operand-01.s | 33 ++++
.../gas/riscv/cv-alu-fail-operand-02.d | 3 +
.../gas/riscv/cv-alu-fail-operand-02.l | 32 ++++
.../gas/riscv/cv-alu-fail-operand-02.s | 33 ++++
.../gas/riscv/cv-alu-fail-operand-03.d | 3 +
.../gas/riscv/cv-alu-fail-operand-03.l | 25 +++
.../gas/riscv/cv-alu-fail-operand-03.s | 26 +++
.../gas/riscv/cv-alu-fail-operand-04.d | 3 +
.../gas/riscv/cv-alu-fail-operand-04.l | 3 +
.../gas/riscv/cv-alu-fail-operand-04.s | 4 +
.../gas/riscv/cv-alu-fail-operand-05.d | 3 +
.../gas/riscv/cv-alu-fail-operand-05.l | 9 +
.../gas/riscv/cv-alu-fail-operand-05.s | 10 ++
.../gas/riscv/cv-alu-fail-operand-06.d | 3 +
.../gas/riscv/cv-alu-fail-operand-06.l | 9 +
.../gas/riscv/cv-alu-fail-operand-06.s | 10 ++
.../gas/riscv/cv-alu-fail-operand-07.d | 3 +
.../gas/riscv/cv-alu-fail-operand-07.l | 33 ++++
.../gas/riscv/cv-alu-fail-operand-07.s | 34 ++++
gas/testsuite/gas/riscv/cv-alu-insns.d | 102 ++++++++++++
gas/testsuite/gas/riscv/cv-alu-insns.s | 124 ++++++++++++++
gas/testsuite/gas/riscv/cv-mac-fail-march.d | 3 +
gas/testsuite/gas/riscv/cv-mac-fail-march.l | 23 +++
gas/testsuite/gas/riscv/cv-mac-fail-march.s | 24 +++
gas/testsuite/gas/riscv/cv-mac-fail-operand.d | 3 +
gas/testsuite/gas/riscv/cv-mac-fail-operand.l | 147 +++++++++++++++++
gas/testsuite/gas/riscv/cv-mac-fail-operand.s | 156 ++++++++++++++++++
gas/testsuite/gas/riscv/cv-mac-insns.d | 87 ++++++++++
gas/testsuite/gas/riscv/cv-mac-insns.s | 81 +++++++++
include/opcode/riscv-opc.h | 104 ++++++++++++
include/opcode/riscv.h | 12 ++
opcodes/riscv-dis.c | 13 ++
opcodes/riscv-opc.c | 61 +++++++
44 files changed, 1429 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-boundaries.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-march.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-01.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-02.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-03.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-04.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-05.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-06.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.l
create mode 100644 gas/testsuite/gas/riscv/cv-alu-fail-operand-07.s
create mode 100644 gas/testsuite/gas/riscv/cv-alu-insns.d
create mode 100644 gas/testsuite/gas/riscv/cv-alu-insns.s
create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.d
create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.l
create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-march.s
create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.d
create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.l
create mode 100644 gas/testsuite/gas/riscv/cv-mac-fail-operand.s
create mode 100644 gas/testsuite/gas/riscv/cv-mac-insns.d
create mode 100644 gas/testsuite/gas/riscv/cv-mac-insns.s
--
2.34.1
next prev parent reply other threads:[~2023-09-12 14:24 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-05 14:52 [PATCH " Mary Bennett
2023-09-05 14:52 ` [PATCH 1/2] RISC-V: Add support for XCVmac extension in CV32E40P Mary Bennett
2023-09-07 4:35 ` Nelson Chu
2023-09-05 14:53 ` [PATCH 2/2] RISC-V: Add support for XCValu " Mary Bennett
2023-09-07 4:37 ` Nelson Chu
2023-09-07 4:49 ` [PATCH 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions Nelson Chu
2023-09-07 6:57 ` Kito Cheng
2023-09-07 10:11 ` Tsukasa OI
2023-09-12 14:24 ` Mary Bennett [this message]
2023-09-12 14:24 ` [PATCH v2 1/2] RISC-V: Add support for XCVmac extension in CV32E40P Mary Bennett
2023-09-12 14:24 ` [PATCH v2 2/2] RISC-V: Add support for XCValu " Mary Bennett
2023-10-02 2:02 ` [PATCH v3 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions Mary Bennett
2023-10-02 2:02 ` [PATCH v3 1/2] RISC-V: Add support for XCVmac extension in CV32E40P Mary Bennett
2023-10-02 2:02 ` [PATCH v3 2/2] RISC-V: Add support for XCValu " Mary Bennett
2023-11-06 17:27 ` [PATCH v3 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions Mary Bennett
2023-11-07 4:12 ` Nelson Chu
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