* [PATCH 0/7] arc: Add new ARCv3 isa support to ARC's backend
@ 2023-09-19 8:12 Claudiu Zissulescu
2023-09-19 8:12 ` [PATCH 1/7] arc: Add new GAS tests for ARCv3 Claudiu Zissulescu
` (6 more replies)
0 siblings, 7 replies; 8+ messages in thread
From: Claudiu Zissulescu @ 2023-09-19 8:12 UTC (permalink / raw)
To: binutils
Hi all,
Before pushing the new ARCv3 ISA modifications to ARC's backend. I
would like to publish the mods here for flushing out any
missunderstanding of my modifications which are tuching the mainline
configuration files.
The new ARCv3 ISA is represented by two new new DesignWare ARC HS5x
and HS6x processor IP families for high-performance embedded
applications. The 32-bit ARC HS5x and 64-bit HS6x processors,
available in single-core and multicore versions, are implementations
of a new superscalar ARCv3 Instruction Set Architecture (ISA). The
HS5x processors feature a 32-bit pipeline that can execute all ARCv3
32-bit instructions, while the HS6x processors feature a full 64-bit
pipeline and register file that can execute both 32-bit and 64-bit
instructions. In addition, the ARC HS6x supports 64-bit virtual and
52-bit physical address spaces to enable direct addressing of current
and future large memories, as well as 128-bit loads and stores for
efficient data movement. Like all ARC processors, the HS5x and HS6x
processors are highly configurable and implement ARC Processor
EXtension (APEX) technology that enables the support of custom
instructions to meet the unique performance, power, and area
requirements of each target application.
The new ARCv3 isa support is using the current ARCv1/ARCv2 binutils
backend adding a number of modifications:
- Uses a new `bfd/elfnn-arc.c` BFD template file to generate the
ARCv1/ARCv2 bfd file, ARC32 bfd file and ARC64 bfd file.
- All ARCv3 32/64bit tests are placed in coresponding `gas/arc64` and
`ld/arc64` folders.
- Two new ARC machines are recognized, namely arc32-*-* and arc64-*-*.
- New ARC 32/64 bit relocations are added.
- GAS configure produces two new defines used by ARC, namely
TARGET_ARCV3_64 and TARGET_ARCv3_32. These defines are used to
select the rigth parts in tc-arc.{c,h}.
- ARCv3 ISA uses a new FPU unit which requires separate register file.
Contributors:
Claudiu Zissulescu <claziss@synopsys.com>
Cupertino Miranda <cupertino.miranda@oracle.com> <cmiranda@synopsys.com>
Claudiu Zissulescu (7):
arc: Add new GAS tests for ARCv3.
arc: Add new LD tests for ARCv3.
arc: Add new ARCv3 ISA to BFD.
arc: Add new linker emulation and scripts for ARCv3 ISA.
arc: Update opcode related include files for ARCv3.
arc: Update ARC's Gnu Assembler backend with ARCv3 ISA.
arc: Add new opcode functions for ARCv3 ISA.
bfd/Makefile.am | 23 +-
bfd/Makefile.in | 27 +-
bfd/arc-got.h | 253 +-
bfd/arc-plt.c | 121 +
bfd/arc-plt.def | 127 +-
bfd/arc-plt.h | 93 +-
bfd/archures.c | 5 +
bfd/bfd-in2.h | 25 +
bfd/config.bfd | 20 +-
bfd/configure | 6 +-
bfd/configure.ac | 6 +-
bfd/cpu-arc.c | 79 +-
bfd/cpu-arc64.c | 75 +
bfd/{elf32-arc.c => elfnn-arc.c} | 1486 +++++---
bfd/libbfd.h | 22 +
bfd/reloc.c | 44 +
bfd/targets.c | 6 +
gas/config.in | 6 +
gas/config/tc-arc.c | 723 ++--
gas/config/tc-arc.h | 46 +-
gas/configure | 14 +-
gas/configure.ac | 10 +-
gas/configure.tgt | 5 +-
gas/testsuite/gas/arc64/arc64.exp | 24 +
gas/testsuite/gas/arc64/float01.d | 65 +
gas/testsuite/gas/arc64/float01.s | 64 +
gas/testsuite/gas/arc64/ldd.d | 46 +
gas/testsuite/gas/arc64/ldd.s | 55 +
gas/testsuite/gas/arc64/lddl.d | 48 +
gas/testsuite/gas/arc64/lddl.s | 54 +
gas/testsuite/gas/arc64/load.d | 70 +
gas/testsuite/gas/arc64/load.s | 82 +
gas/testsuite/gas/arc64/st.d | 61 +
gas/testsuite/gas/arc64/st.s | 68 +
gas/testsuite/gas/arc64/std.d | 55 +
gas/testsuite/gas/arc64/std.s | 60 +
gas/testsuite/gas/arc64/stdl.d | 35 +
gas/testsuite/gas/arc64/stdl.s | 37 +
gas/testsuite/gas/arc64/stl.d | 46 +
gas/testsuite/gas/arc64/stl.s | 50 +
include/elf/arc-cpu.def | 63 +-
include/elf/arc-reloc.def | 171 +-
include/elf/arc.h | 1 +
include/opcode/arc-attrs.h | 4 +-
include/opcode/arc-func.h | 188 +-
include/opcode/arc.h | 121 +-
ld/Makefile.am | 4 +
ld/Makefile.in | 8 +
ld/configure.tgt | 21 +-
ld/emulparams/arc64elf32.sh | 12 +
ld/emulparams/arc64elf64.sh | 12 +
ld/emulparams/arc64linux32.sh | 22 +
ld/emulparams/arc64linux64.sh | 22 +
ld/scripttempl/elfarc.sc | 18 +-
ld/testsuite/ld-arc/got-weak.d | 12 -
ld/testsuite/ld-arc/got-weak.s | 7 -
.../ld-arc64/arcv3_64-reloc-near-exe.dd | 29 +
.../ld-arc64/arcv3_64-reloc-near-so.dd | 21 +
ld/testsuite/ld-arc64/arcv3_64-reloc-near.s | 11 +
ld/testsuite/ld-arc64/arcv3_64.exp | 48 +
ld/testsuite/ld-arc64/bl34.dd | 12 +
ld/testsuite/ld-arc64/bl34.s | 13 +
ld/testsuite/ld-arc64/linkscript.ld | 5 +
ld/testsuite/ld-arc64/plt34-got.dd | 9 +
ld/testsuite/ld-arc64/plt34-got.s | 9 +
ld/testsuite/ld-arc64/plt34-reloc.dd | 12 +
ld/testsuite/ld-arc64/plt34-reloc.s | 14 +
opcodes/Makefile.am | 1 +
opcodes/Makefile.in | 2 +
opcodes/arc-dis.c | 290 +-
opcodes/arc-ext-tbl.h | 124 -
opcodes/arc-flag-classes.def | 125 +
opcodes/arc-flag.def | 179 +
opcodes/arc-fxi.h | 60 +
opcodes/arc-opc.c | 2990 +----------------
opcodes/arc-operands.def | 502 +++
opcodes/arc-regs.h | 8 +-
opcodes/arc64-opc.c | 834 +++++
opcodes/arcxx-opc.inc | 1840 ++++++++++
opcodes/configure | 1 +
opcodes/configure.ac | 1 +
opcodes/disassemble.c | 6 +
82 files changed, 7686 insertions(+), 4288 deletions(-)
create mode 100644 bfd/arc-plt.c
create mode 100644 bfd/cpu-arc64.c
rename bfd/{elf32-arc.c => elfnn-arc.c} (68%)
create mode 100644 gas/testsuite/gas/arc64/arc64.exp
create mode 100644 gas/testsuite/gas/arc64/float01.d
create mode 100644 gas/testsuite/gas/arc64/float01.s
create mode 100644 gas/testsuite/gas/arc64/ldd.d
create mode 100644 gas/testsuite/gas/arc64/ldd.s
create mode 100644 gas/testsuite/gas/arc64/lddl.d
create mode 100644 gas/testsuite/gas/arc64/lddl.s
create mode 100644 gas/testsuite/gas/arc64/load.d
create mode 100644 gas/testsuite/gas/arc64/load.s
create mode 100644 gas/testsuite/gas/arc64/st.d
create mode 100644 gas/testsuite/gas/arc64/st.s
create mode 100644 gas/testsuite/gas/arc64/std.d
create mode 100644 gas/testsuite/gas/arc64/std.s
create mode 100644 gas/testsuite/gas/arc64/stdl.d
create mode 100644 gas/testsuite/gas/arc64/stdl.s
create mode 100644 gas/testsuite/gas/arc64/stl.d
create mode 100644 gas/testsuite/gas/arc64/stl.s
create mode 100644 ld/emulparams/arc64elf32.sh
create mode 100644 ld/emulparams/arc64elf64.sh
create mode 100644 ld/emulparams/arc64linux32.sh
create mode 100644 ld/emulparams/arc64linux64.sh
delete mode 100644 ld/testsuite/ld-arc/got-weak.d
delete mode 100644 ld/testsuite/ld-arc/got-weak.s
create mode 100644 ld/testsuite/ld-arc64/arcv3_64-reloc-near-exe.dd
create mode 100644 ld/testsuite/ld-arc64/arcv3_64-reloc-near-so.dd
create mode 100644 ld/testsuite/ld-arc64/arcv3_64-reloc-near.s
create mode 100644 ld/testsuite/ld-arc64/arcv3_64.exp
create mode 100644 ld/testsuite/ld-arc64/bl34.dd
create mode 100644 ld/testsuite/ld-arc64/bl34.s
create mode 100644 ld/testsuite/ld-arc64/linkscript.ld
create mode 100644 ld/testsuite/ld-arc64/plt34-got.dd
create mode 100644 ld/testsuite/ld-arc64/plt34-got.s
create mode 100644 ld/testsuite/ld-arc64/plt34-reloc.dd
create mode 100644 ld/testsuite/ld-arc64/plt34-reloc.s
delete mode 100644 opcodes/arc-ext-tbl.h
create mode 100644 opcodes/arc-flag-classes.def
create mode 100644 opcodes/arc-flag.def
create mode 100644 opcodes/arc-operands.def
create mode 100644 opcodes/arc64-opc.c
create mode 100644 opcodes/arcxx-opc.inc
--
2.30.2
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH 1/7] arc: Add new GAS tests for ARCv3. 2023-09-19 8:12 [PATCH 0/7] arc: Add new ARCv3 isa support to ARC's backend Claudiu Zissulescu @ 2023-09-19 8:12 ` Claudiu Zissulescu 2023-09-19 8:12 ` [PATCH 2/7] arc: Add new LD " Claudiu Zissulescu ` (5 subsequent siblings) 6 siblings, 0 replies; 8+ messages in thread From: Claudiu Zissulescu @ 2023-09-19 8:12 UTC (permalink / raw) To: binutils; +Cc: Claudiu Zissulescu From: Claudiu Zissulescu <claziss@synopsys.com> Add new assembler tests for ARCv3 ISA. All the new tests are added in a distinct folder named arc64. gas/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * gas/testsuite/gas/arc64/arc64.exp: New file. * gas/testsuite/gas/arc64/float01.d: Likewise. * gas/testsuite/gas/arc64/float01.s: Likewise. * gas/testsuite/gas/arc64/ldd.d: Likewise. * gas/testsuite/gas/arc64/ldd.s: Likewise. * gas/testsuite/gas/arc64/lddl.d: Likewise. * gas/testsuite/gas/arc64/lddl.s: Likewise. * gas/testsuite/gas/arc64/load.d: Likewise. * gas/testsuite/gas/arc64/load.s: Likewise. * gas/testsuite/gas/arc64/st.d: Likewise. * gas/testsuite/gas/arc64/st.s: Likewise. * gas/testsuite/gas/arc64/std.d: Likewise. * gas/testsuite/gas/arc64/std.s: Likewise. * gas/testsuite/gas/arc64/stdl.d: Likewise. * gas/testsuite/gas/arc64/stdl.s: Likewise. * gas/testsuite/gas/arc64/stl.d: Likewise. * gas/testsuite/gas/arc64/stl.s: Likewise. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com> --- gas/testsuite/gas/arc64/arc64.exp | 24 +++++++++ gas/testsuite/gas/arc64/float01.d | 65 ++++++++++++++++++++++++ gas/testsuite/gas/arc64/float01.s | 64 ++++++++++++++++++++++++ gas/testsuite/gas/arc64/ldd.d | 46 +++++++++++++++++ gas/testsuite/gas/arc64/ldd.s | 55 +++++++++++++++++++++ gas/testsuite/gas/arc64/lddl.d | 48 ++++++++++++++++++ gas/testsuite/gas/arc64/lddl.s | 54 ++++++++++++++++++++ gas/testsuite/gas/arc64/load.d | 70 ++++++++++++++++++++++++++ gas/testsuite/gas/arc64/load.s | 82 +++++++++++++++++++++++++++++++ gas/testsuite/gas/arc64/st.d | 61 +++++++++++++++++++++++ gas/testsuite/gas/arc64/st.s | 68 +++++++++++++++++++++++++ gas/testsuite/gas/arc64/std.d | 55 +++++++++++++++++++++ gas/testsuite/gas/arc64/std.s | 60 ++++++++++++++++++++++ gas/testsuite/gas/arc64/stdl.d | 35 +++++++++++++ gas/testsuite/gas/arc64/stdl.s | 37 ++++++++++++++ gas/testsuite/gas/arc64/stl.d | 46 +++++++++++++++++ gas/testsuite/gas/arc64/stl.s | 50 +++++++++++++++++++ 17 files changed, 920 insertions(+) create mode 100644 gas/testsuite/gas/arc64/arc64.exp create mode 100644 gas/testsuite/gas/arc64/float01.d create mode 100644 gas/testsuite/gas/arc64/float01.s create mode 100644 gas/testsuite/gas/arc64/ldd.d create mode 100644 gas/testsuite/gas/arc64/ldd.s create mode 100644 gas/testsuite/gas/arc64/lddl.d create mode 100644 gas/testsuite/gas/arc64/lddl.s create mode 100644 gas/testsuite/gas/arc64/load.d create mode 100644 gas/testsuite/gas/arc64/load.s create mode 100644 gas/testsuite/gas/arc64/st.d create mode 100644 gas/testsuite/gas/arc64/st.s create mode 100644 gas/testsuite/gas/arc64/std.d create mode 100644 gas/testsuite/gas/arc64/std.s create mode 100644 gas/testsuite/gas/arc64/stdl.d create mode 100644 gas/testsuite/gas/arc64/stdl.s create mode 100644 gas/testsuite/gas/arc64/stl.d create mode 100644 gas/testsuite/gas/arc64/stl.s diff --git a/gas/testsuite/gas/arc64/arc64.exp b/gas/testsuite/gas/arc64/arc64.exp new file mode 100644 index 00000000000..dd0c0c88f94 --- /dev/null +++ b/gas/testsuite/gas/arc64/arc64.exp @@ -0,0 +1,24 @@ +# Copyright (C) 2021 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +if { ![istarget arc64-*-*] && ![istarget arc32-*-*] } { + return +} + +# ARC base instruction set + +# ARC library extensions +run_dump_tests [lsort [glob -nocomplain $srcdir/$subdir/*.d]] diff --git a/gas/testsuite/gas/arc64/float01.d b/gas/testsuite/gas/arc64/float01.d new file mode 100644 index 00000000000..d0bb692c0f3 --- /dev/null +++ b/gas/testsuite/gas/arc64/float01.d @@ -0,0 +1,65 @@ +#as: -mcpu=hs6x +#source: float01.s +#objdump: -d --prefix-addresses --show-raw-insn + +.*: +file format elf64-.*arc64 + + +Disassembly of section .text: +0x[0-9a-f]+ e310 0062\s+vfhadd f1,f2,f3 +0x[0-9a-f]+ e311 0062\s+vfhsub f1,f2,f3 +0x[0-9a-f]+ e312 0062\s+vfhmul f1,f2,f3 +0x[0-9a-f]+ e313 0062\s+vfhdiv f1,f2,f3 +0x[0-9a-f]+ e314 0062\s+vfhadds f1,f2,f3 +0x[0-9a-f]+ e315 0062\s+vfhsubs f1,f2,f3 +0x[0-9a-f]+ e316 0062\s+vfhmuls f1,f2,f3 +0x[0-9a-f]+ e317 0062\s+vfhdivs f1,f2,f3 +0x[0-9a-f]+ e518 00e4\s+vfhunpkl f3,f4,f5 +0x[0-9a-f]+ e519 00e4\s+vfhunpkm f3,f4,f5 +0x[0-9a-f]+ e51a 00e4\s+vfhpackl f3,f4,f5 +0x[0-9a-f]+ e51b 00e4\s+vfhpackm f3,f4,f5 +0x[0-9a-f]+ e51c 00e4\s+vfhbflyl f3,f4,f5 +0x[0-9a-f]+ e51d 00e4\s+vfhbflym f3,f4,f5 +0x[0-9a-f]+ e51e 00e4\s+vfhaddsub f3,f4,f5 +0x[0-9a-f]+ e51f 00e4\s+vfhsubadd f3,f4,f5 +0x[0-9a-f]+ e010 51a7\s+vfsadd f6,f7,f8 +0x[0-9a-f]+ e011 51a7\s+vfssub f6,f7,f8 +0x[0-9a-f]+ e012 51a7\s+vfsmul f6,f7,f8 +0x[0-9a-f]+ e013 51a7\s+vfsdiv f6,f7,f8 +0x[0-9a-f]+ e014 51a7\s+vfsadds f6,f7,f8 +0x[0-9a-f]+ e015 51a7\s+vfssubs f6,f7,f8 +0x[0-9a-f]+ e016 51a7\s+vfsmuls f6,f7,f8 +0x[0-9a-f]+ e017 51a7\s+vfsdivs f6,f7,f8 +0x[0-9a-f]+ e218 51e9\s+vfsunpkl f7,f9,f10 +0x[0-9a-f]+ e219 51e9\s+vfsunpkm f7,f9,f10 +0x[0-9a-f]+ e21a 51e9\s+vfspackl f7,f9,f10 +0x[0-9a-f]+ e21b 51e9\s+vfspackm f7,f9,f10 +0x[0-9a-f]+ e21c 51e9\s+vfsbflyl f7,f9,f10 +0x[0-9a-f]+ e21d 51e9\s+vfsbflym f7,f9,f10 +0x[0-9a-f]+ e21e 51e9\s+vfsaddsub f7,f9,f10 +0x[0-9a-f]+ e21f 51e9\s+vfssubadd f7,f9,f10 +0x[0-9a-f]+ e610 b2b8\s+vfdadd f10f11,f24f25,f30f31 +0x[0-9a-f]+ e611 b2b8\s+vfdsub f10f11,f24f25,f30f31 +0x[0-9a-f]+ e612 b2b8\s+vfdmul f10f11,f24f25,f30f31 +0x[0-9a-f]+ e613 b2b8\s+vfddiv f10f11,f24f25,f30f31 +0x[0-9a-f]+ e614 b2b8\s+vfdadds f10f11,f24f25,f30f31 +0x[0-9a-f]+ e615 b2b8\s+vfdsubs f10f11,f24f25,f30f31 +0x[0-9a-f]+ e616 b2b8\s+vfdmuls f10f11,f24f25,f30f31 +0x[0-9a-f]+ e617 b2b8\s+vfddivs f10f11,f24f25,f30f31 +0x[0-9a-f]+ e218 a42c\s+vfdunpkl\s+f16f17,f12f13,f18f19 +0x[0-9a-f]+ e219 a42c\s+vfdunpkm\s+f16f17,f12f13,f18f19 +0x[0-9a-f]+ e21a a42c\s+vfdpackl\s+f16f17,f12f13,f18f19 +0x[0-9a-f]+ e21b a42c\s+vfdpackm\s+f16f17,f12f13,f18f19 +0x[0-9a-f]+ e21c a42c\s+vfdbflyl\s+f16f17,f12f13,f18f19 +0x[0-9a-f]+ e21d a42c\s+vfdbflym\s+f16f17,f12f13,f18f19 +0x[0-9a-f]+ e21e a42c\s+vfdaddsub\s+f16f17,f12f13,f18f19 +0x[0-9a-f]+ e21f a42c\s+vfdsubadd\s+f16f17,f12f13,f18f19 +0x[0-9a-f]+ e040 07ed\s+fhsqrt f31,f13 +0x[0-9a-f]+ e040 47ed\s+fssqrt f31,f13 +0x[0-9a-f]+ e040 87ed\s+fdsqrt f31,f13 +0x[0-9a-f]+ e041 0461\s+vfhsqrt f17,f1 +0x[0-9a-f]+ e041 4461\s+vfssqrt f17,f1 +0x[0-9a-f]+ e041 82bc\s+vfdsqrt f10f11,f28f29 +0x[0-9a-f]+ e042 02ef\s+vfhexch f11,f15 +0x[0-9a-f]+ e042 42ef\s+vfsexch f11,f15 +0x[0-9a-f]+ e042 823a\s+vfdexch f8f9,f26f27 diff --git a/gas/testsuite/gas/arc64/float01.s b/gas/testsuite/gas/arc64/float01.s new file mode 100644 index 00000000000..833fbb270e6 --- /dev/null +++ b/gas/testsuite/gas/arc64/float01.s @@ -0,0 +1,64 @@ + vfhadd f1,f2,f3 + vfhsub f1,f2,f3 + vfhmul f1,f2,f3 + vfhdiv f1,f2,f3 + vfhadds f1,f2,f3 + vfhsubs f1,f2,f3 + vfhmuls f1,f2,f3 + vfhdivs f1,f2,f3 + + vfhunpkl f3,f4,f5 + vfhunpkm f3,f4,f5 + vfhpackl f3,f4,f5 + vfhpackm f3,f4,f5 + vfhbflyl f3,f4,f5 + vfhbflym f3,f4,f5 + vfhaddsub f3,f4,f5 + vfhsubadd f3,f4,f5 + + vfsadd f6,f7,f8 + vfssub f6,f7,f8 + vfsmul f6,f7,f8 + vfsdiv f6,f7,f8 + vfsadds f6,f7,f8 + vfssubs f6,f7,f8 + vfsmuls f6,f7,f8 + vfsdivs f6,f7,f8 + + vfsunpkl f7,f9,f10 + vfsunpkm f7,f9,f10 + vfspackl f7,f9,f10 + vfspackm f7,f9,f10 + vfsbflyl f7,f9,f10 + vfsbflym f7,f9,f10 + vfsaddsub f7,f9,f10 + vfssubadd f7,f9,f10 + + vfdadd f10,f24,f30 + vfdsub f10,f24,f30 + vfdmul f10,f24,f30 + vfddiv f10,f24,f30 + vfdadds f10,f24,f30 + vfdsubs f10,f24,f30 + vfdmuls f10,f24,f30 + vfddivs f10,f24,f30 + + vfdunpkl f16,f12,f18 + vfdunpkm f16,f12,f18 + vfdpackl f16,f12,f18 + vfdpackm f16,f12,f18 + vfdbflyl f16,f12,f18 + vfdbflym f16,f12,f18 + vfdaddsub f16,f12,f18 + vfdsubadd f16,f12,f18 + + fhsqrt f31,f13 + fssqrt f31,f13 + fdsqrt f31,f13 + vfhsqrt f17,f1 + vfssqrt f17,f1 + vfdsqrt f10,f28 + + vfhexch f11,f15 + vfsexch f11,f15 + vfdexch f8,f26 diff --git a/gas/testsuite/gas/arc64/ldd.d b/gas/testsuite/gas/arc64/ldd.d new file mode 100644 index 00000000000..1a73169aa31 --- /dev/null +++ b/gas/testsuite/gas/arc64/ldd.d @@ -0,0 +1,46 @@ +#as: -mcpu=hs5x +#source: ldd.s +#objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format elf32-.*arc64 + +Disassembly of section .text: +0x[0-9a-f]+ 1100 0180 ldd r0r1,\[r1\] +0x[0-9a-f]+ 1100 0980 ldd.di r0r1,\[r1\] +0x[0-9a-f]+ 1100 0380 ldd.aw r0r1,\[r1\] +0x[0-9a-f]+ 1100 0b80 ldd.di.aw r0r1,\[r1] +0x[0-9a-f]+ 1100 0580 ldd.ab r0r1,\[r1\] +0x[0-9a-f]+ 1100 0d80 ldd.di.ab r0r1,\[r1] +0x[0-9a-f]+ 1100 0780 ldd.as r0r1,\[r1\] +0x[0-9a-f]+ 1100 0f80 ldd.di.as r0r1,\[r1] +0x[0-9a-f]+ 13ff 0184 ldd r4r5,\[r3,255\] +0x[0-9a-f]+ 1100 8986 ldd.di r6r7,\[r1,-256] +0x[0-9a-f]+ 177b 0380 ldd.aw r0r1,\[r7,123] +0x[0-9a-f]+ 1185 8b84 ldd.di.aw r4r5,\[r1,-123] +0x[0-9a-f]+ 110a 0582 ldd.ab r2r3,\[r1,10\] +0x[0-9a-f]+ 11ff 8d80 ldd.di.ab r0r1,\[r1,-1] +0x[0-9a-f]+ 11ff 0784 ldd.as r4r5,\[r1,255] +0x[0-9a-f]+ 110a 8f84 ldd.di.as r4r5,\[r1,-246] +0x[0-9a-f]+ 1600 7780 0000 0000 ldd.as r0r1,\[0\] +0x[0-9a-f]+ 1600 7980 0000 0255 ldd.di r0r1,\[0x255\] +0x[0-9a-f]+ 1600 7180 ffff ff00 ldd r0r1,\[0xffffff00] +0x[0-9a-f]+ 1600 7184 8765 4321 ldd r4r5,\[0x87654321] +0x[0-9a-f]+ 2136 0080 ldd r0r1,\[r1,r2\] +0x[0-9a-f]+ 2336 8102 ldd.di r2r3,\[r3,r4\] +0x[0-9a-f]+ 2576 0184 ldd.aw r4r5,\[r5,r6\] +0x[0-9a-f]+ 2676 8106 ldd.di.aw r6r7,\[r6,r4] +0x[0-9a-f]+ 24b6 0080 ldd.ab r0r1,\[r4,r2\] +0x[0-9a-f]+ 21b6 80c2 ldd.di.ab r2r3,\[r1,r3] +0x[0-9a-f]+ 23f6 0144 ldd.as r4r5,\[r3,r5\] +0x[0-9a-f]+ 25f6 8046 ldd.di.as r6r7,\[r5,r1] +0x[0-9a-f]+ 2536 0f84 0000 0102 ldd r4r5,\[r5,0x102\] +0x[0-9a-f]+ 21f6 0f84 0000 0100 ldd.as r4r5,\[r1,0x100] +0x[0-9a-f]+ 2376 0f80 1234 5678 ldd.aw r0r1,\[r3,0x12345678] +0x[0-9a-f]+ 24b6 8f82 edcb a988 ldd.di.ab r2r3,\[r4,0xedcba988] +0x[0-9a-f]+ 2636 7084 0000 0104 ldd r4r5,\[0x104,r2\] +0x[0-9a-f]+ 26f6 7044 0000 0100 ldd.as r4r5,\[0x100,r1] +0x[0-9a-f]+ 2636 7044 0000 00ff ldd r4r5,\[0xff,r1\] +0x[0-9a-f]+ 2636 f140 1234 5678 ldd.di r0r1,\[0x12345678,r5] +0x[0-9a-f]+ 26f6 f102 edcb a988 ldd.di.as r2r3,\[0xedcba988,r4] +0x[0-9a-f]+ 2136 0f80 0000 0100 ldd r0r1,\[r1,0x100\] +0x[0-9a-f]+ 2336 0f82 0000 0104 ldd r2r3,\[r3,0x104\] diff --git a/gas/testsuite/gas/arc64/ldd.s b/gas/testsuite/gas/arc64/ldd.s new file mode 100644 index 00000000000..514f49378e3 --- /dev/null +++ b/gas/testsuite/gas/arc64/ldd.s @@ -0,0 +1,55 @@ +; 64-bit double loads + +; ldd a, [b] +ldd r0, [r1] +ldd.di r0, [r1] +ldd.aw r0, [r1] +ldd.aw.di r0, [r1] +ldd.ab r0, [r1] +ldd.ab.di r0, [r1] +ldd.as r0, [r1] +ldd.as.di r0, [r1] + +; ldd a, [b, s9] +ldd r4, [r3, 255] +ldd.di r6, [r1, -256] +ldd.aw r0, [r7, 123] +ldd.aw.di r4, [r1, -123] +ldd.ab r2, [r1, 10] +ldd.ab.di r0, [r1, -1] +ldd.as r4, [r1, 255] +ldd.as.di r4, [r1, -246] + +; ldd a, [limm] -> no writeback (.aw, .ab) can be used +ldd.as r0, [0x0] +ldd.di r0, [0x255] +ldd r0, [-256] +ldd r4, [0x87654321] + +; ldd a, [b, c] +ldd r0, [r1, r2] +ldd.di r2, [r3, r4] +ldd.aw r4, [r5, r6] +ldd.aw.di r6, [r6, r4] +ldd.ab r0, [r4, r2] +ldd.ab.di r2, [r1, r3] +ldd.as r4, [r3, r5] +ldd.as.di r6, [r5, r1] + +; ldd a, [b, limm] +ldd r4, [r5, 258] +ldd.as r4, [r1, 256] +ldd.aw r0, [r3, 0x12345678] +ldd.ab.di r2, [r4, -0x12345678] + +; ldd a, [limm, c] -> no writeback (.aw, .ab) can be used +ldd r4, [260, r2] +ldd.as r4, [256, r1] +ldd r4, [255, r1] +ldd.di r0, [ 0x12345678, r5] +ldd.as.di r2, [-0x12345678, r4] + +; ldd a, [b, s9] +; use adress-scaling to fit numbers into 4-byte instructions +ldd r0, [r1, 256] +ldd r2, [r3, 260] diff --git a/gas/testsuite/gas/arc64/lddl.d b/gas/testsuite/gas/arc64/lddl.d new file mode 100644 index 00000000000..03a6dca3fc3 --- /dev/null +++ b/gas/testsuite/gas/arc64/lddl.d @@ -0,0 +1,48 @@ +#as: -mcpu=hs6x +#source: lddl.s +#objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format elf64-.*arc64 + +Disassembly of section .text: +0x[0-9a-f]+ 21f2 0080 lddl r0r1,\[r1,r2\] +0x[0-9a-f]+ 22f2 0f06 0000 0100 lddl r6r7,\[r2,256@s32\] +0x[0-9a-f]+ 22f2 0f02 ffff feff lddl r2r3,\[r2,-257@s32\] +0x[0-9a-f]+ 26f2 7144 8000 0000 lddl r4r5,\[0x80000000,r5\] +0x[0-9a-f]+ 24f2 7144 ffff ff9c lddl r4r5,\[-100@s32,r5\] +0x[0-9a-f]+ 1000 0682 lddl r2r3,\[r0\] +0x[0-9a-f]+ 17ff 0686 lddl r6r7,\[r7,255\] +0x[0-9a-f]+ 1700 8686 lddl r6r7,\[r7,-256\] +0x[0-9a-f]+ 1400 7680 1337 1338 lddl r0r1,\[322376504@s32\] +0x[0-9a-f]+ 1600 7682 8000 0000 lddl r2r3,\[0x80000000\] +0x[0-9a-f]+ 1400 7682 8000 0000 lddl r2r3,\[-2147483648@s32\] +0x[0-9a-f]+ 21f3 0080 lddl.aw r0r1,\[r1,r2\] +0x[0-9a-f]+ 22f3 0f06 0000 0100 lddl.aw r6r7,\[r2,256@s32\] +0x[0-9a-f]+ 22f3 0f02 ffff feff lddl.aw r2r3,\[r2,-257@s32\] +0x[0-9a-f]+ 1000 06c2 lddl.aw r2r3,\[r0\] +0x[0-9a-f]+ 17ff 06c6 lddl.aw r6r7,\[r7,255\] +0x[0-9a-f]+ 1700 86c6 lddl.aw r6r7,\[r7,-256\] +0x[0-9a-f]+ 21f3 0080 lddl.aw r0r1,\[r1,r2\] +0x[0-9a-f]+ 22f3 0f06 0000 0100 lddl.aw r6r7,\[r2,256@s32\] +0x[0-9a-f]+ 22f3 0f02 ffff feff lddl.aw r2r3,\[r2,-257@s32\] +0x[0-9a-f]+ 1000 06c2 lddl.aw r2r3,\[r0\] +0x[0-9a-f]+ 17ff 06c6 lddl.aw r6r7,\[r7,255\] +0x[0-9a-f]+ 1700 86c6 lddl.aw r6r7,\[r7,-256\] +0x[0-9a-f]+ 21f3 8080 lddl.ab r0r1,\[r1,r2\] +0x[0-9a-f]+ 22f3 8f06 0000 0100 lddl.ab r6r7,\[r2,256@s32\] +0x[0-9a-f]+ 22f3 8f02 ffff feff lddl.ab r2r3,\[r2,-257@s32\] +0x[0-9a-f]+ 1000 0ec2 lddl.ab r2r3,\[r0\] +0x[0-9a-f]+ 17ff 0ec6 lddl.ab r6r7,\[r7,255\] +0x[0-9a-f]+ 1700 8ec6 lddl.ab r6r7,\[r7,-256\] +0x[0-9a-f]+ 21f2 8080 lddl.as r0r1,\[r1,r2\] +0x[0-9a-f]+ 22f2 8f06 0000 0100 lddl.as r6r7,\[r2,256@s32\] +0x[0-9a-f]+ 22f2 8f02 ffff feff lddl.as r2r3,\[r2,-257@s32\] +0x[0-9a-f]+ 26f2 f144 8000 0000 lddl.as r4r5,\[0x80000000,r5\] +0x[0-9a-f]+ 24f2 f144 ffff ff9c lddl.as r4r5,\[-100@s32,r5\] +0x[0-9a-f]+ 1000 0e82 lddl.as r2r3,\[r0\] +0x[0-9a-f]+ 17ff 0e86 lddl.as r6r7,\[r7,255\] +0x[0-9a-f]+ 1700 8e86 lddl.as r6r7,\[r7,-256\] +0x[0-9a-f]+ 24f2 f144 ffff ff00 lddl.as r4r5,\[-256@s32,r5\] +0x[0-9a-f]+ 1400 7e80 1337 1338 lddl.as r0r1,\[322376504@s32] +0x[0-9a-f]+ 1600 7e82 8000 0000 lddl.as r2r3,\[0x80000000] +0x[0-9a-f]+ 1400 7e82 8000 0000 lddl.as r2r3,\[-2147483648@s32] diff --git a/gas/testsuite/gas/arc64/lddl.s b/gas/testsuite/gas/arc64/lddl.s new file mode 100644 index 00000000000..77d6c58b6d1 --- /dev/null +++ b/gas/testsuite/gas/arc64/lddl.s @@ -0,0 +1,54 @@ +; 128-bit double loads + + lddl r0, [r1,r2] ; lddl a, [b, c] + lddl r6, [r2,256] ; lddl a, [b, limm] (limm > s9) + lddl r2, [r2,-257] ; lddl a, [b, ximm] + lddl r4, [0x80000000,r5] ; lddl a, [limm, c] + lddl r4, [-100,r5] ; lddl a, [ximm, c] + + lddl r2, [r0] ; lddl a, [b, s9=0] + lddl r6, [r7,255] ; lddl a, [b, s9] biggest s9 + lddl r6, [r7,-256] ; lddl a, [b, s9] smallest s9 + lddl r0, [0x13371338] ; lddl a, [limm,s9=0] + lddl r2, [0x80000000] ; lddl a, [limm,s9=0] + lddl r2, [-2147483648] ; lddl a, [ximm,s9=0] + + ; Now, repetition of instructions above with suffices (*.a/aw/ab/as) + + lddl.a r0, [r1,r2] + lddl.a r6, [r2,256] + lddl.a r2, [r2,-257] + + lddl.a r2, [r0] + lddl.a r6, [r7,255] + lddl.a r6, [r7,-256] + + lddl.aw r0, [r1,r2] + lddl.aw r6, [r2,256] + lddl.aw r2, [r2,-257] + + lddl.aw r2, [r0] + lddl.aw r6, [r7,255] + lddl.aw r6, [r7,-256] + + lddl.ab r0, [r1,r2] + lddl.ab r6, [r2,256] + lddl.ab r2, [r2,-257] + + lddl.ab r2, [r0] + lddl.ab r6, [r7,255] + lddl.ab r6, [r7,-256] + + lddl.as r0, [r1,r2] + lddl.as r6, [r2,256] + lddl.as r2, [r2,-257] + lddl.as r4, [0x80000000,r5] + lddl.as r4, [-100,r5] + + lddl.as r2, [r0] + lddl.as r6, [r7,255] + lddl.as r6, [r7,-256] + lddl.as r4, [-256,r5] + lddl.as r0, [0x13371338] + lddl.as r2, [0x80000000] + lddl.as r2, [-2147483648] diff --git a/gas/testsuite/gas/arc64/load.d b/gas/testsuite/gas/arc64/load.d new file mode 100644 index 00000000000..a387f923c8a --- /dev/null +++ b/gas/testsuite/gas/arc64/load.d @@ -0,0 +1,70 @@ +#as: -mcpu=hs6x +#source: load.s +#objdump: -d --prefix-addresses --show-raw-insn + +.*: +file format elf64-.*arc64 + + +Disassembly of section .text: +0x[0-9a-f]+ 2031 8f01 ffff f020 ldl r1,\[r0,-4064@s32\] +0x[0-9a-f]+ 2030 0f01 ffff f020 ld r1,\[r0,-4064@s32\] +0x[0-9a-f]+ 2032 0f01 ffff f020 ldb r1,\[r0,-4064@s32\] +0x[0-9a-f]+ 20f2 0f02 ffff f020 lddl r2r3,\[r0,-4064@s32\] +0x[0-9a-f]+ 2034 0f01 ffff f020 ldh r1,\[r0,-4064@s32\] +0x[0-9a-f]+ 2431 f001 ffff f020 ldl r1,\[-4064@s32,r0\] +0x[0-9a-f]+ 2430 7001 ffff f020 ld r1,\[-4064@s32,r0\] +0x[0-9a-f]+ 2432 7001 ffff f020 ldb r1,\[-4064@s32,r0\] +0x[0-9a-f]+ 24f2 7002 ffff f020 lddl r2r3,\[-4064@s32,r0\] +0x[0-9a-f]+ 2434 7001 ffff f020 ldh r1,\[-4064@s32,r0\] +0x[0-9a-f]+ 2631 f001 ffff f020 ldl r1,\[0xfffff020,r0\] +0x[0-9a-f]+ 2630 7001 ffff f020 ld r1,\[0xfffff020,r0\] +0x[0-9a-f]+ 2632 7001 ffff f020 ldb r1,\[0xfffff020,r0\] +0x[0-9a-f]+ 26f2 7002 ffff f020 lddl r2r3,\[0xfffff020,r0\] +0x[0-9a-f]+ 2634 7001 ffff f020 ldh r1,\[0xfffff020,r0\] +0x[0-9a-f]+ 2031 8f81 ffff f020 ldl r1,\[r0,0xfffff020\] +0x[0-9a-f]+ 2030 0f81 ffff f020 ld r1,\[r0,0xfffff020\] +0x[0-9a-f]+ 2032 0f81 ffff f020 ldb r1,\[r0,0xfffff020\] +0x[0-9a-f]+ 20f2 0f82 ffff f020 lddl r2r3,\[r0,0xfffff020\] +0x[0-9a-f]+ 2034 0f81 ffff f020 ldh r1,\[r0,0xfffff020\] +0x[0-9a-f]+ 2071 8f01 ffff f020 ldl.aw r1,\[r0,-4064@s32\] +0x[0-9a-f]+ 2070 0f01 ffff f020 ld.aw r1,\[r0,-4064@s32\] +0x[0-9a-f]+ 2072 0f01 ffff f020 ldb.aw r1,\[r0,-4064@s32\] +0x[0-9a-f]+ 20f3 0f02 ffff f020 lddl.aw r2r3,\[r0,-4064@s32\] +0x[0-9a-f]+ 2074 0f01 ffff f020 ldh.aw r1,\[r0,-4064@s32\] +0x[0-9a-f]+ 2471 f001 ffff f020 ldl.aw r1,\[-4064@s32,r0\] +0x[0-9a-f]+ 2470 7001 ffff f020 ld.aw r1,\[-4064@s32,r0\] +0x[0-9a-f]+ 2472 7001 ffff f020 ldb.aw r1,\[-4064@s32,r0\] +0x[0-9a-f]+ 2474 7001 ffff f020 ldh.aw r1,\[-4064@s32,r0\] +0x[0-9a-f]+ 2671 f001 ffff f020 ldl.aw r1,\[0xfffff020,r0\] +0x[0-9a-f]+ 2670 7001 ffff f020 ld.aw r1,\[0xfffff020,r0\] +0x[0-9a-f]+ 2672 7001 ffff f020 ldb.aw r1,\[0xfffff020,r0\] +0x[0-9a-f]+ 2674 7001 ffff f020 ldh.aw r1,\[0xfffff020,r0\] +0x[0-9a-f]+ 2071 8f81 ffff f020 ldl.aw r1,\[r0,0xfffff020\] +0x[0-9a-f]+ 2070 0f81 ffff f020 ld.aw r1,\[r0,0xfffff020\] +0x[0-9a-f]+ 2072 0f81 ffff f020 ldb.aw r1,\[r0,0xfffff020\] +0x[0-9a-f]+ 20f3 0f82 ffff f020 lddl.aw r2r3,\[r0,0xfffff020\] +0x[0-9a-f]+ 2074 0f81 ffff f020 ldh.aw r1,\[r0,0xfffff020\] +0x[0-9a-f]+ 2030 8f01 ffff f020 ld.di r1,\[r0,-4064@s32\] +0x[0-9a-f]+ 2032 8f01 ffff f020 ldb.di r1,\[r0,-4064@s32\] +0x[0-9a-f]+ 2034 8f01 ffff f020 ldh.di r1,\[r0,-4064@s32\] +0x[0-9a-f]+ 2430 f001 ffff f020 ld.di r1,\[-4064@s32,r0\] +0x[0-9a-f]+ 2432 f001 ffff f020 ldb.di r1,\[-4064@s32,r0\] +0x[0-9a-f]+ 2434 f001 ffff f020 ldh.di r1,\[-4064@s32,r0\] +0x[0-9a-f]+ 2630 f001 ffff f020 ld.di r1,\[0xfffff020,r0\] +0x[0-9a-f]+ 2632 f001 ffff f020 ldb.di r1,\[0xfffff020,r0\] +0x[0-9a-f]+ 2634 f001 ffff f020 ldh.di r1,\[0xfffff020,r0\] +0x[0-9a-f]+ 2030 8f81 ffff f020 ld.di r1,\[r0,0xfffff020\] +0x[0-9a-f]+ 2032 8f81 ffff f020 ldb.di r1,\[r0,0xfffff020\] +0x[0-9a-f]+ 2034 8f81 ffff f020 ldh.di r1,\[r0,0xfffff020\] +0x[0-9a-f]+ 2031 0f01 ffff f020 ld.x r1,\[r0,-4064@s32\] +0x[0-9a-f]+ 2033 0f01 ffff f020 ldb.x r1,\[r0,-4064@s32\] +0x[0-9a-f]+ 2035 0f01 ffff f020 ldh.x r1,\[r0,-4064@s32\] +0x[0-9a-f]+ 2431 7001 ffff f020 ld.x r1,\[-4064@s32,r0\] +0x[0-9a-f]+ 2433 7001 ffff f020 ldb.x r1,\[-4064@s32,r0\] +0x[0-9a-f]+ 2435 7001 ffff f020 ldh.x r1,\[-4064@s32,r0\] +0x[0-9a-f]+ 2631 7001 ffff f020 ld.x r1,\[0xfffff020,r0\] +0x[0-9a-f]+ 2633 7001 ffff f020 ldb.x r1,\[0xfffff020,r0\] +0x[0-9a-f]+ 2635 7001 ffff f020 ldh.x r1,\[0xfffff020,r0\] +0x[0-9a-f]+ 2031 0f81 ffff f020 ld.x r1,\[r0,0xfffff020\] +0x[0-9a-f]+ 2033 0f81 ffff f020 ldb.x r1,\[r0,0xfffff020\] +0x[0-9a-f]+ 2035 0f81 ffff f020 ldh.x r1,\[r0,0xfffff020\] diff --git a/gas/testsuite/gas/arc64/load.s b/gas/testsuite/gas/arc64/load.s new file mode 100644 index 00000000000..f142f8a6f41 --- /dev/null +++ b/gas/testsuite/gas/arc64/load.s @@ -0,0 +1,82 @@ + ldl r1,[r0,-4064] + ld r1,[r0,-4064] + ldb r1,[r0,-4064] + lddl r2,[r0,-4064] + ldh r1,[r0,-4064] + + ldl r1,[-4064,r0] + ld r1,[-4064,r0] + ldb r1,[-4064,r0] + lddl r2,[-4064,r0] + ldh r1,[-4064,r0] + + ldl r1,[0xfffff020,r0] + ld r1,[0xfffff020,r0] + ldb r1,[0xfffff020,r0] + lddl r2,[0xfffff020,r0] + ldh r1,[0xfffff020,r0] + + ldl r1,[r0,0xfffff020] + ld r1,[r0,0xfffff020] + ldb r1,[r0,0xfffff020] + lddl r2,[r0,0xfffff020] + ldh r1,[r0,0xfffff020] + + + ldl.aw r1,[r0,-4064] + ld.aw r1,[r0,-4064] + ldb.aw r1,[r0,-4064] + lddl.aw r2,[r0,-4064] + ldh.aw r1,[r0,-4064] + + ldl.aw r1,[-4064,r0] + ld.aw r1,[-4064,r0] + ldb.aw r1,[-4064,r0] + ;; lddl.aw r2,[-4064,r0] + ldh.aw r1,[-4064,r0] + + ldl.aw r1,[0xfffff020,r0] + ld.aw r1,[0xfffff020,r0] + ldb.aw r1,[0xfffff020,r0] + ;; lddl.aw r2,[0xfffff020,r0] + ldh.aw r1,[0xfffff020,r0] + + ldl.aw r1,[r0,0xfffff020] + ld.aw r1,[r0,0xfffff020] + ldb.aw r1,[r0,0xfffff020] + lddl.aw r2,[r0,0xfffff020] + ldh.aw r1,[r0,0xfffff020] + + + ld.di r1,[r0,-4064] + ldb.di r1,[r0,-4064] + ldh.di r1,[r0,-4064] + + ld.di r1,[-4064,r0] + ldb.di r1,[-4064,r0] + ldh.di r1,[-4064,r0] + + ld.di r1,[0xfffff020,r0] + ldb.di r1,[0xfffff020,r0] + ldh.di r1,[0xfffff020,r0] + + ld.di r1,[r0,0xfffff020] + ldb.di r1,[r0,0xfffff020] + ldh.di r1,[r0,0xfffff020] + + + ld.x r1,[r0,-4064] + ldb.x r1,[r0,-4064] + ldh.x r1,[r0,-4064] + + ld.x r1,[-4064,r0] + ldb.x r1,[-4064,r0] + ldh.x r1,[-4064,r0] + + ld.x r1,[0xfffff020,r0] + ldb.x r1,[0xfffff020,r0] + ldh.x r1,[0xfffff020,r0] + + ld.x r1,[r0,0xfffff020] + ldb.x r1,[r0,0xfffff020] + ldh.x r1,[r0,0xfffff020] diff --git a/gas/testsuite/gas/arc64/st.d b/gas/testsuite/gas/arc64/st.d new file mode 100644 index 00000000000..66cbbb76b92 --- /dev/null +++ b/gas/testsuite/gas/arc64/st.d @@ -0,0 +1,61 @@ +#source: st.s +#objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format elf.*-.*arc64 + +Disassembly of section .text: +0x[0-9a-f]+ 1900 0100 st r4,\[r1,0\] +0x[0-9a-f]+ 1e00 7100 0000 1338 st r4,\[0x1338,0\] +0x[0-9a-f]+ 1e00 7180 7fff ffff st r6,\[0x7fffffff,0\] +0x[0-9a-f]+ 1b00 0f80 0800 0000 st 0x8000000,\[r3,0\] +0x[0-9a-f]+ 1e00 7f80 0000 1234 st 0x1234,\[0x1234,0\] +0x[0-9a-f]+ 19ff 0000 st r0,\[r1,255\] +0x[0-9a-f]+ 1c00 8080 st r2,\[r4,-256\] +0x[0-9a-f]+ 1e0c 7180 7fff ffff st r6,\[0x7fffffff,12\] +0x[0-9a-f]+ 1e0d 7f80 0000 4321 st 0x4321,\[0x4321,13\] +0x[0-9a-f]+ 1e00 7200 ffff fc00 st r8,\[0xfffffc00,0\] +0x[0-9a-f]+ 1a14 8f80 0000 0020 st 0x20,\[r2,-236\] +0x[0-9a-f]+ 1a0a 8f80 ffff ffdf st 0xffffffdf,\[r2,-246\] +0x[0-9a-f]+ 1a00 8f80 1234 5678 st 0x12345678,\[r2,-256\] +0x[0-9a-f]+ 19ff 0f80 ffff 5bf0 st 0xffff5bf0,\[r1,255\] +0x[0-9a-f]+ 19ff 0008 st.aw r0,\[r1,255\] +0x[0-9a-f]+ 1c00 8088 st.aw r2,\[r4,-256\] +0x[0-9a-f]+ 1a00 8f88 1234 5678 st.aw 0x12345678,\[r2,-256\] +0x[0-9a-f]+ 19ff 0f88 ffff 5bf0 st.aw 0xffff5bf0,\[r1,255\] +0x[0-9a-f]+ 19ff 0008 st.aw r0,\[r1,255\] +0x[0-9a-f]+ 1c00 8088 st.aw r2,\[r4,-256\] +0x[0-9a-f]+ 1a00 8f88 1234 5678 st.aw 0x12345678,\[r2,-256\] +0x[0-9a-f]+ 19ff 0f88 ffff 5bf0 st.aw 0xffff5bf0,\[r1,255\] +0x[0-9a-f]+ 19ff 0010 st.ab r0,\[r1,255\] +0x[0-9a-f]+ 1c00 8090 st.ab r2,\[r4,-256\] +0x[0-9a-f]+ 1a00 8f90 1234 5678 st.ab 0x12345678,\[r2,-256\] +0x[0-9a-f]+ 19ff 0f90 ffff 5bf0 st.ab 0xffff5bf0,\[r1,255\] +0x[0-9a-f]+ 19ff 0018 st.as r0,\[r1,255\] +0x[0-9a-f]+ 1c00 8098 st.as r2,\[r4,-256\] +0x[0-9a-f]+ 1e00 7100 0000 1338 st r4,\[0x1338,0\] +0x[0-9a-f]+ 1e00 7180 7fff ffff st r6,\[0x7fffffff,0\] +0x[0-9a-f]+ 1e00 7200 ffff fc00 st r8,\[0xfffffc00,0\] +0x[0-9a-f]+ 1a00 8f98 1234 5678 st.as 0x12345678,\[r2,-256\] +0x[0-9a-f]+ 19ff 0f98 ffff 5bf0 st.as 0xffff5bf0,\[r1,255\] +0x[0-9a-f]+ 1900 07c1 st 31,\[r1,0\] +0x[0-9a-f]+ 1900 0801 st -32,\[r1,0\] +0x[0-9a-f]+ 19ff 0801 st -32,\[r1,255\] +0x[0-9a-f]+ 1c00 8141 st 5,\[r4,-256\] +0x[0-9a-f]+ 1e00 7001 0000 1338 st 0,\[0x1338,0\] +0x[0-9a-f]+ 1e00 7041 7fff ffff st 1,\[0x7fffffff,0\] +0x[0-9a-f]+ 1e00 7fc1 ffff fc00 st -1,\[0xfffffc00,0\] +0x[0-9a-f]+ 1900 07e1 st.di 31,\[r1,0\] +0x[0-9a-f]+ 19ff 0839 st.di.as -32,\[r1,255\] +0x[0-9a-f]+ 1c00 8169 st.di.aw 5,\[r4,-256\] +0x[0-9a-f]+ 1b9b 0db1 st.di.ab -10,\[r3,155\] +0x[0-9a-f]+ 1c9c 0289 st.aw 10,\[r4,156\] +0x[0-9a-f]+ 1e00 7001 0000 1338 st 0,\[0x1338,0\] +0x[0-9a-f]+ 1e00 7061 7fff ffff st.di 1,\[0x7fffffff,0\] +0x[0-9a-f]+ 1c00 0fa4 0000 0004\s+sth.di\s+0x4,\[r4,0\] +0x[0-9a-f]+ 1d09 0fbc 0000 0005\s+sth.di.as\s+0x5,\[r5,9\] +0x[0-9a-f]+ 1e00 0001\s+st\s+0,\[r6,0\] +0x[0-9a-f]+ 1900 0043\s+stb\s+1,\[r1,0\] +0x[0-9a-f]+ 1e02 0009\s+st.aw\s+0,\[r6,2\] +0x[0-9a-f]+ 1901 0053\s+stb.ab\s+1,\[r1,1\] +0x[0-9a-f]+ 1e00 7105 0000 0000\s+sth\s+4,\[0,0\] +\s+[0-9a-f]+: R_ARC_32_ME\s+symb diff --git a/gas/testsuite/gas/arc64/st.s b/gas/testsuite/gas/arc64/st.s new file mode 100644 index 00000000000..2089de3ff03 --- /dev/null +++ b/gas/testsuite/gas/arc64/st.s @@ -0,0 +1,68 @@ +; common stores + + st r4, [r1] ; st c, [b] + st r4, [0x1338] ; st c, [limm] limm: small + st r6, [0x7fffffff] ; st c, [limm] limm: big + st 0x8000000, [r3] ; st limm, [b] limm: big + st 0x1234, [0x1234] ; st limm, [limm] limm: equal + + st r0, [r1,255] ; st c, [b, s9] s9: biggest + st r2, [r4,-256] ; st c, [b, s9] s9: smallest + st r6, [0x7fffffff,12] ; st c, [limm,s9] limm: positive + st 0x4321, [0x4321,13] ; st limm, [limm,s9] limm: equal + st r8, [-1024] ; st c, [limm] limm: negative + st 32, [r2, -236] ; st limm, [b, s9] limm: smallest positive + st -33, [r2, -246] ; st limm, [b, s9] limm: biggest negative + st 0x12345678, [r2, -256] ; st limm, [b, s9] limm: positive + st -42000, [r1, 255] ; st limm, [b, s9] limm: negative + + ; Now, repetition of instructions above with suffices (*.a/aw/ab/as) + + st.a r0, [r1,255] + st.a r2, [r4,-256] + st.a 0x12345678, [r2, -256] + st.a -42000, [r1, 255] + + st.aw r0, [r1,255] + st.aw r2, [r4,-256] + st.aw 0x12345678, [r2, -256] + st.aw -42000, [r1, 255] + + st.ab r0, [r1,255] + st.ab r2, [r4,-256] + st.ab 0x12345678, [r2, -256] + st.ab -42000, [r1, 255] + + st.as r0, [r1,255] + st.as r2, [r4,-256] + st r4, [0x1338] + st r6, [0x7fffffff] + st r8, [-1024] + st.as 0x12345678, [r2, -256] + st.as -42000, [r1, 255] + + ; st w6, ... + st 31, [r1] ; st w6, [b, s9=0] w6: biggest + st -32, [r1] ; st w6, [b, s9=0] w6: smallest + st -32, [r1,255] ; st w6, [b, s9] s9: biggest + st 5, [r4,-256] ; st w6, [b, s9] s9: smallest + st 0, [0x1338] ; st w6, [limm] limm: small positive + st 1, [0x7fffffff] ; st w6, [limm] limm: positive + st -1, [-1024] ; st w6, [limm] limm: negative + + st.di 31, [r1] ; st w6, [b, s9=0] w6: biggest + st.as.di -32, [r1,255] ; st w6, [b, s9] s9: biggest + st.aw.di 5, [r4,-256] ; st w6, [b, s9] s9: smallest + st.ab.di -10, [r3,155] ; st w6, [b, s9] + st.aw 10, [r4,156] ; st w6, [b, s9] + st 0, [0x1338] ; st w6, [limm] limm: small positive + st.di 1, [0x7fffffff] ; st w6, [limm] limm: positive + + ;; sth w6 ... + sth.di 4,[r4] + sth.di.as 5,[r5,9] + st 0,[r6] + stb 1,[r1,0] + st.aw 0,[r6,2] + stb.ab 1,[r1,1] + sth 4,[@symb] diff --git a/gas/testsuite/gas/arc64/std.d b/gas/testsuite/gas/arc64/std.d new file mode 100644 index 00000000000..9958b59f01c --- /dev/null +++ b/gas/testsuite/gas/arc64/std.d @@ -0,0 +1,55 @@ +#as: -mcpu=hs5x +#source: std.s +#objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format elf32-.*arc64 + +Disassembly of section .text: +0x[0-9a-f]+ 1900 0106 std r4r5,\[r1\] +0x[0-9a-f]+ 1e00 7106 0000 1338 std r4r5,\[0x1338\] +0x[0-9a-f]+ 1e00 7186 7fff ffff std r6r7,\[0x7fffffff\] +0x[0-9a-f]+ 1b00 0f86 0800 0000 std 0x8000000,\[r3\] +0x[0-9a-f]+ 1e00 7f86 0000 1234 std 0x1234,\[0x1234\] +0x[0-9a-f]+ 19ff 0006 std r0r1,\[r1,255\] +0x[0-9a-f]+ 1c00 8086 std r2r3,\[r4,-256\] +0x[0-9a-f]+ 1e0c 7186 7fff ffff std r6r7,\[0x7fffffff,12\] +0x[0-9a-f]+ 1e0d 7f86 0000 4321 std 0x4321,\[0x4321,13\] +0x[0-9a-f]+ 1e00 7206 ffff fc00 std r8r9,\[0xfffffc00\] +0x[0-9a-f]+ 1a14 8f86 0000 0020 std 0x20,\[r2,-236\] +0x[0-9a-f]+ 1a0a 8f86 ffff ffdf std 0xffffffdf,\[r2,-246\] +0x[0-9a-f]+ 1a00 8f86 1234 5678 std 0x12345678,\[r2,-256\] +0x[0-9a-f]+ 19ff 0f86 ffff 5bf0 std 0xffff5bf0,\[r1,255\] +0x[0-9a-f]+ 19ff 000e std.aw r0r1,\[r1,255\] +0x[0-9a-f]+ 1c00 808e std.aw r2r3,\[r4,-256\] +0x[0-9a-f]+ 1a00 8f8e 1234 5678 std.aw 0x12345678,\[r2,-256\] +0x[0-9a-f]+ 19ff 0f8e ffff 5bf0 std.aw 0xffff5bf0,\[r1,255\] +0x[0-9a-f]+ 19ff 000e std.aw r0r1,\[r1,255\] +0x[0-9a-f]+ 1c00 808e std.aw r2r3,\[r4,-256\] +0x[0-9a-f]+ 1a00 8f8e 1234 5678 std.aw 0x12345678,\[r2,-256\] +0x[0-9a-f]+ 19ff 0f8e ffff 5bf0 std.aw 0xffff5bf0,\[r1,255\] +0x[0-9a-f]+ 19ff 0016 std.ab r0r1,\[r1,255\] +0x[0-9a-f]+ 1c00 8096 std.ab r2r3,\[r4,-256\] +0x[0-9a-f]+ 1a00 8f96 1234 5678 std.ab 0x12345678,\[r2,-256\] +0x[0-9a-f]+ 19ff 0f96 ffff 5bf0 std.ab 0xffff5bf0,\[r1,255\] +0x[0-9a-f]+ 19ff 001e std.as r0r1,\[r1,255\] +0x[0-9a-f]+ 1c00 809e std.as r2r3,\[r4,-256\] +0x[0-9a-f]+ 1e00 711e 0000 1338 std.as r4r5,\[0x1338\] +0x[0-9a-f]+ 1e00 719e 7fff ffff std.as r6r7,\[0x7fffffff] +0x[0-9a-f]+ 1e00 721e ffff fc00 std.as r8r9,\[0xfffffc00] +0x[0-9a-f]+ 1a00 8f9e 1234 5678 std.as 0x12345678,\[r2,-256\] +0x[0-9a-f]+ 19ff 0f9e ffff 5bf0 std.as 0xffff5bf0,\[r1,255\] +0x[0-9a-f]+ 1e0f 7fbe 0000 4321 std.di.as 0x4321,\[0x4321,15\] +0x[0-9a-f]+ 1900 07c7 std 31,\[r1\] +0x[0-9a-f]+ 1900 0807 std -32,\[r1\] +0x[0-9a-f]+ 19ff 0807 std -32,\[r1,255\] +0x[0-9a-f]+ 1c00 8147 std 5,\[r4,-256\] +0x[0-9a-f]+ 1e00 7007 0000 1338 std 0,\[0x1338\] +0x[0-9a-f]+ 1e00 7047 7fff ffff std 1,\[0x7fffffff\] +0x[0-9a-f]+ 1e00 7fc7 ffff fc00 std -1,\[0xfffffc00\] +0x[0-9a-f]+ 1900 07e7 std.di 31,\[r1\] +0x[0-9a-f]+ 19ff 083f std.di.as -32,\[r1,255\] +0x[0-9a-f]+ 1c00 816f std.di.aw 5,\[r4,-256\] +0x[0-9a-f]+ 1b9b 0db7 std.di.ab -10,\[r3,155\] +0x[0-9a-f]+ 1c9c 028f std.aw 10,\[r4,156\] +0x[0-9a-f]+ 1e00 7007 0000 1338 std 0,\[0x1338\] +0x[0-9a-f]+ 1e00 7067 7fff ffff std.di 1,\[0x7fffffff\] diff --git a/gas/testsuite/gas/arc64/std.s b/gas/testsuite/gas/arc64/std.s new file mode 100644 index 00000000000..75c5a7cb4f3 --- /dev/null +++ b/gas/testsuite/gas/arc64/std.s @@ -0,0 +1,60 @@ +; 64-bit double stores + + std r4, [r1] ; std c, [b] + std r4, [0x1338] ; std c, [limm] limm: small + std r6, [0x7fffffff] ; std c, [limm] limm: big + std 0x8000000, [r3] ; std limm, [b] limm: big + std 0x1234, [0x1234] ; std limm, [limm] limm: equal + + std r0, [r1,255] ; std c, [b, s9] s9: biggest + std r2, [r4,-256] ; std c, [b, s9] s9: smallest + std r6, [0x7fffffff,12] ; std c, [limm,s9] limm: positive + std 0x4321, [0x4321,13] ; std limm, [limm,s9] limm: equal + std r8, [-1024] ; std c, [limm] limm: negative + std 32, [r2, -236] ; std limm, [b, s9] limm: smallest positive + std -33, [r2, -246] ; std limm, [b, s9] limm: biggest negative + std 0x12345678, [r2, -256] ; std limm, [b, s9] limm: positive + std -42000, [r1, 255] ; std limm, [b, s9] limm: negative + + ; Now, repetition of instructions above with suffices (*.a/aw/ab/as) + + std.a r0, [r1,255] + std.a r2, [r4,-256] + std.a 0x12345678, [r2, -256] + std.a -42000, [r1, 255] + + std.aw r0, [r1,255] + std.aw r2, [r4,-256] + std.aw 0x12345678, [r2, -256] + std.aw -42000, [r1, 255] + + std.ab r0, [r1,255] + std.ab r2, [r4,-256] + std.ab 0x12345678, [r2, -256] + std.ab -42000, [r1, 255] + + std.as r0, [r1,255] + std.as r2, [r4,-256] + std.as r4, [0x1338] + std.as r6, [0x7fffffff] + std.as r8, [-1024] + std.as 0x12345678, [r2, -256] + std.as -42000, [r1, 255] + std.as.di 0x4321, [0x4321, 15] + + ; std w6, ... + std 31, [r1] ; std w6, [b, s9=0] w6: biggest + std -32, [r1] ; std w6, [b, s9=0] w6: smallest + std -32, [r1,255] ; std w6, [b, s9] s9: biggest + std 5, [r4,-256] ; std w6, [b, s9] s9: smallest + std 0, [0x1338] ; std w6, [limm] limm: small positive + std 1, [0x7fffffff] ; std w6, [limm] limm: positive + std -1, [-1024] ; std w6, [limm] limm: negative + + std.di 31, [r1] ; std w6, [b, s9=0] w6: biggest + std.as.di -32, [r1,255] ; std w6, [b, s9] s9: biggest + std.aw.di 5, [r4,-256] ; std w6, [b, s9] s9: smallest + std.ab.di -10, [r3,155] ; std w6, [b, s9] + std.aw 10, [r4,156] ; std w6, [b, s9] + std 0, [0x1338] ; std w6, [limm] limm: small positive + std.di 1, [0x7fffffff] ; std w6, [limm] limm: positive diff --git a/gas/testsuite/gas/arc64/stdl.d b/gas/testsuite/gas/arc64/stdl.d new file mode 100644 index 00000000000..0917802e68a --- /dev/null +++ b/gas/testsuite/gas/arc64/stdl.d @@ -0,0 +1,35 @@ +#as: -mcpu=hs6x +#source: stdl.s +#objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format elf64-.*arc64 + +Disassembly of section .text: +0x[0-9a-f]+ 1900 0126 stdl r4r5,\[r1,0\] +0x[0-9a-f]+ 1c00 70a6 0000 1338 stdl r2r3,\[4920@s32\] +0x[0-9a-f]+ 1c00 71a6 7fff ffff stdl r6r7,\[2147483647@s32\] +0x[0-9a-f]+ 1e00 70a6 8000 0000 stdl r2r3,\[0x80000000\] +0x[0-9a-f]+ 1c00 7026 ffff fb2e stdl r0r1,\[-1234@s32\] +0x[0-9a-f]+ 1b00 0fa6 8000 0000 stdl 0x80000000,\[r3,0\] +0x[0-9a-f]+ 1b00 0f26 7fff ffff stdl 2147483647@s32,\[r3,0\] +0x[0-9a-f]+ 19ff 0026 stdl r0r1,\[r1,255\] +0x[0-9a-f]+ 1c00 80a6 stdl r2r3,\[r4,-256\] +0x[0-9a-f]+ 19ff 0f26 ffff 5bf0 stdl -42000@s32,\[r1,255\] +0x[0-9a-f]+ 1a00 8fa6 8234 5678 stdl 0x82345678,\[r2,-256\] +0x[0-9a-f]+ 19ff 002e stdl.aw r0r1,\[r1,255\] +0x[0-9a-f]+ 1c00 812e stdl.aw r4r5,\[r4,-256\] +0x[0-9a-f]+ 1a00 8fae 8234 5678 stdl.aw 0x82345678,\[r2,-256\] +0x[0-9a-f]+ 19ff 0f2e ffff 5bf0 stdl.aw -42000@s32,\[r1,255\] +0x[0-9a-f]+ 19ff 002e stdl.aw r0r1,\[r1,255\] +0x[0-9a-f]+ 1c00 80ae stdl.aw r2r3,\[r4,-256\] +0x[0-9a-f]+ 1a00 8fae 8234 5678 stdl.aw 0x82345678,\[r2,-256\] +0x[0-9a-f]+ 19ff 0f2e ffff 5bf0 stdl.aw -42000@s32,\[r1,255\] +0x[0-9a-f]+ 19ff 0036 stdl.ab r0r1,\[r1,255\] +0x[0-9a-f]+ 1c00 81b6 stdl.ab r6r7,\[r4,-256\] +0x[0-9a-f]+ 1a00 8fb6 8234 5678 stdl.ab 0x82345678,\[r2,-256\] +0x[0-9a-f]+ 19ff 0f36 ffff 5bf0 stdl.ab -42000@s32,\[r1,255\] +0x[0-9a-f]+ 19ff 003e stdl.as r0r1,\[r1,255\] +0x[0-9a-f]+ 1c00 813e stdl.as r4r5,\[r4,-256\] +0x[0-9a-f]+ 1a00 8fbe 8234 5678 stdl.as 0x82345678,\[r2,-256\] +0x[0-9a-f]+ 19ff 0f3e ffff 5bf0 stdl.as -42000@s32,\[r1,255\] +0x[0-9a-f]+ 1a00 8fbe 8234 5678 stdl.as 0x82345678,\[r2,-256\] diff --git a/gas/testsuite/gas/arc64/stdl.s b/gas/testsuite/gas/arc64/stdl.s new file mode 100644 index 00000000000..bafdeea363a --- /dev/null +++ b/gas/testsuite/gas/arc64/stdl.s @@ -0,0 +1,37 @@ +; 128-bit double stores + + stdl r4, [r1] ; stdl c, [b] + stdl r2, [0x1338] ; stdl c, [ximm] ximm: default + stdl r6, [0x7fffffff] ; stdl c, [ximm] ximm: big + stdl r2, [0x80000000] ; stdl c, [limm] limm: positive + stdl r0, [-1234] ; stdl c, [ximm] ximm: negative + stdl 0x80000000, [r3] ; stdl limm, [b] limm: smallest + stdl 0x7fffffff, [r3] ; stdl ximm, [b] ximm: biggest + + stdl r0, [r1, 255] ; stdl c, [b, s9] s9: biggest + stdl r2, [r4,-256] ; stdl c, [b, s9] s9: smallest + stdl -42000, [r1, 255] ; stdl ximm, [b, s9] ximm: negative + stdl 0x82345678, [r2, -256] ; stdl limm, [b, s9] limm: positive + + ; Now, repetition of instructions above with suffices (*.a/aw/ab/as) + + stdl.a r0, [r1,255] + stdl.a r4, [r4,-256] + stdl.a 0x82345678, [r2, -256] + stdl.a -42000, [r1, 255] + + stdl.aw r0, [r1,255] + stdl.aw r2, [r4,-256] + stdl.aw 0x82345678, [r2, -256] + stdl.aw -42000, [r1, 255] + + stdl.ab r0, [r1,255] + stdl.ab r6, [r4,-256] + stdl.ab 0x82345678, [r2, -256] + stdl.ab -42000, [r1, 255] + + stdl.as r0, [r1,255] + stdl.as r4, [r4,-256] + stdl.as 0x82345678, [r2, -256] + stdl.as -42000, [r1, 255] + stdl.as 0x82345678, [r2, -256] diff --git a/gas/testsuite/gas/arc64/stl.d b/gas/testsuite/gas/arc64/stl.d new file mode 100644 index 00000000000..f2925c6a516 --- /dev/null +++ b/gas/testsuite/gas/arc64/stl.d @@ -0,0 +1,46 @@ +#as: -mcpu=hs6x +#source: stl.s +#objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format elf64-.*arc64 + +Disassembly of section .text: +0x[0-9a-f]+ 1900 0107 stl r4,\[r1,0\] +0x[0-9a-f]+ 1c00 70c7 0000 1338 stl r3,\[4920@s32\] +0x[0-9a-f]+ 1c00 7147 7fff ffff stl r5,\[2147483647@s32\] +0x[0-9a-f]+ 1e00 7087 8000 0000 stl r2,\[0x80000000\] +0x[0-9a-f]+ 1c00 71c7 ffff fb2e stl r7,\[-1234@s32\] +0x[0-9a-f]+ 1b00 0f87 8000 0000 stl 0x80000000,\[r3,0\] +0x[0-9a-f]+ 1b00 0f07 7fff ffff stl 2147483647@s32,\[r3,0\] +0x[0-9a-f]+ 19ff 0047 stl r1,\[r1,255\] +0x[0-9a-f]+ 1c00 8087 stl r2,\[r4,-256\] +0x[0-9a-f]+ 19ff 0f07 ffff 5bf0 stl -42000@s32,\[r1,255\] +0x[0-9a-f]+ 1a00 8f87 8234 5678 stl 0x82345678,\[r2,-256\] +0x[0-9a-f]+ 19ff 000f stl.aw r0,\[r1,255\] +0x[0-9a-f]+ 1c00 804f stl.aw r1,\[r4,-256\] +0x[0-9a-f]+ 1a00 8f8f 8234 5678 stl.aw 0x82345678,\[r2,-256\] +0x[0-9a-f]+ 19ff 0f0f ffff 5bf0 stl.aw -42000@s32,\[r1,255\] +0x[0-9a-f]+ 19ff 000f stl.aw r0,\[r1,255\] +0x[0-9a-f]+ 1c00 808f stl.aw r2,\[r4,-256\] +0x[0-9a-f]+ 1a00 8f8f 8234 5678 stl.aw 0x82345678,\[r2,-256\] +0x[0-9a-f]+ 19ff 0f0f ffff 5bf0 stl.aw -42000@s32,\[r1,255\] +0x[0-9a-f]+ 19ff 0017 stl.ab r0,\[r1,255\] +0x[0-9a-f]+ 1c00 80d7 stl.ab r3,\[r4,-256\] +0x[0-9a-f]+ 1a00 8f97 8234 5678 stl.ab 0x82345678,\[r2,-256\] +0x[0-9a-f]+ 19ff 0f17 ffff 5bf0 stl.ab -42000@s32,\[r1,255\] +0x[0-9a-f]+ 19ff 001f stl.as r0,\[r1,255\] +0x[0-9a-f]+ 1c00 805f stl.as r1,\[r4,-256\] +0x[0-9a-f]+ 1a00 8f9f 8234 5678 stl.as 0x82345678,\[r2,-256\] +0x[0-9a-f]+ 19ff 0f1f ffff 5bf0 stl.as -42000@s32,\[r1,255\] +0x[0-9a-f]+ 1a00 8f9f 8234 5678\s+stl.as\s+0x82345678,\[r2,-256\] +0x[0-9a-f]+ 1900 07e7 stl 31,\[r1,0\] +0x[0-9a-f]+ 1900 0827 stl -32,\[r1,0\] +0x[0-9a-f]+ 19ff 0827 stl -32,\[r1,255\] +0x[0-9a-f]+ 1c00 8167 stl 5,\[r4,-256\] +0x[0-9a-f]+ 19ff 083f stl.as -32,\[r1,255\] +0x[0-9a-f]+ 1c00 816f stl.aw 5,\[r4,-256\] +0x[0-9a-f]+ 1b9b 0db7 stl.ab -10,\[r3,155\] +0x[0-9a-f]+ 1c9c 02af stl.aw 10,\[r4,156\] +0x[0-9a-f]+ 1c00 7027 0000 1338 stl 0,\[4920@s32\] +0x[0-9a-f]+ 1e00 7067 8fff ffff stl 1,\[0x8fffffff\] +0x[0-9a-f]+ 1c00 7fe7 ffff fc00 stl -1,\[-1024@s32\] diff --git a/gas/testsuite/gas/arc64/stl.s b/gas/testsuite/gas/arc64/stl.s new file mode 100644 index 00000000000..d4b5e95684a --- /dev/null +++ b/gas/testsuite/gas/arc64/stl.s @@ -0,0 +1,50 @@ +; 64-bit stores + + stl r4, [r1] ; stl c, [b] + stl r3, [0x1338] ; stl c, [ximm] ximm: default + stl r5, [0x7fffffff] ; stl c, [ximm] ximm: big + stl r2, [0x80000000] ; stl c, [limm] limm: positive + stl r7, [-1234] ; stl c, [ximm] ximm: negative + stl 0x80000000, [r3] ; stl limm, [b] limm: smallest + stl 0x7fffffff, [r3] ; stl ximm, [b] ximm: biggest + + stl r1, [r1, 255] ; stl c, [b, s9] s9: biggest + stl r2, [r4,-256] ; stl c, [b, s9] s9: smallest + stl -42000, [r1, 255] ; stl ximm, [b, s9] ximm: negative + stl 0x82345678, [r2, -256] ; stl limm, [b, s9] limm: positive + + ; Now, repetition of instructions above with suffices (*.a/aw/ab/as) + + stl.a r0, [r1,255] + stl.a r1, [r4,-256] + stl.a 0x82345678, [r2, -256] + stl.a -42000, [r1, 255] + + stl.aw r0, [r1,255] + stl.aw r2, [r4,-256] + stl.aw 0x82345678, [r2, -256] + stl.aw -42000, [r1, 255] + + stl.ab r0, [r1,255] + stl.ab r3, [r4,-256] + stl.ab 0x82345678, [r2, -256] + stl.ab -42000, [r1, 255] + + stl.as r0, [r1,255] + stl.as r1, [r4,-256] + stl.as 0x82345678, [r2, -256] + stl.as -42000, [r1, 255] + stl.as 0x82345678, [r2, -256] + + ; stl w6, ... + stl 31, [r1] ; stl w6, [b, s9=0] w6: biggest + stl -32, [r1] ; stl w6, [b, s9=0] w6: smallest + stl -32, [r1,255] ; stl w6, [b, s9] s9: biggest + stl 5, [r4,-256] ; stl w6, [b, s9] s9: smallest + stl.as -32, [r1,255] ; stl w6, [b, s9] s9: biggest + stl.aw 5, [r4,-256] ; stl w6, [b, s9] s9: smallest + stl.ab -10, [r3,155] ; stl w6, [b, s9] + stl.aw 10, [r4,156] ; stl w6, [b, s9] + stl 0, [0x1338] ; stl w6, [ximm] ximm: small positive + stl 1, [0x8fffffff] ; stl w6, [limm] limm: positive + stl -1, [-1024] ; stl w6, [ximm] ximm: negative -- 2.30.2 ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 2/7] arc: Add new LD tests for ARCv3. 2023-09-19 8:12 [PATCH 0/7] arc: Add new ARCv3 isa support to ARC's backend Claudiu Zissulescu 2023-09-19 8:12 ` [PATCH 1/7] arc: Add new GAS tests for ARCv3 Claudiu Zissulescu @ 2023-09-19 8:12 ` Claudiu Zissulescu 2023-09-19 8:12 ` [PATCH 3/7] arc: Add new ARCv3 ISA to BFD Claudiu Zissulescu ` (4 subsequent siblings) 6 siblings, 0 replies; 8+ messages in thread From: Claudiu Zissulescu @ 2023-09-19 8:12 UTC (permalink / raw) To: binutils; +Cc: Claudiu Zissulescu From: Claudiu Zissulescu <claziss@synopsys.com> Add new linker tests for ARCv3 ISA. All the new tests are added in a distinct new folder named arc64. ld/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * ld/testsuite/ld-arc64/arcv3_64-reloc-near-exe.dd: New file. * ld/testsuite/ld-arc64/arcv3_64-reloc-near-so.dd: Likewise. * ld/testsuite/ld-arc64/arcv3_64-reloc-near.s: Likewise. * ld/testsuite/ld-arc64/arcv3_64.exp: Likewise. * ld/testsuite/ld-arc64/bl34.dd: Likewise. * ld/testsuite/ld-arc64/bl34.s: Likewise. * ld/testsuite/ld-arc64/linkscript.ld: Likewise. * ld/testsuite/ld-arc64/plt34-got.dd: Likewise. * ld/testsuite/ld-arc64/plt34-got.s: Likewise. * ld/testsuite/ld-arc64/plt34-reloc.dd: Likewise. * ld/testsuite/ld-arc64/plt34-reloc.s: Likewise. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com> --- .../ld-arc64/arcv3_64-reloc-near-exe.dd | 29 +++++++++++ .../ld-arc64/arcv3_64-reloc-near-so.dd | 21 ++++++++ ld/testsuite/ld-arc64/arcv3_64-reloc-near.s | 11 +++++ ld/testsuite/ld-arc64/arcv3_64.exp | 48 +++++++++++++++++++ ld/testsuite/ld-arc64/bl34.dd | 12 +++++ ld/testsuite/ld-arc64/bl34.s | 13 +++++ ld/testsuite/ld-arc64/linkscript.ld | 5 ++ ld/testsuite/ld-arc64/plt34-got.dd | 9 ++++ ld/testsuite/ld-arc64/plt34-got.s | 9 ++++ ld/testsuite/ld-arc64/plt34-reloc.dd | 12 +++++ ld/testsuite/ld-arc64/plt34-reloc.s | 14 ++++++ 11 files changed, 183 insertions(+) create mode 100644 ld/testsuite/ld-arc64/arcv3_64-reloc-near-exe.dd create mode 100644 ld/testsuite/ld-arc64/arcv3_64-reloc-near-so.dd create mode 100644 ld/testsuite/ld-arc64/arcv3_64-reloc-near.s create mode 100644 ld/testsuite/ld-arc64/arcv3_64.exp create mode 100644 ld/testsuite/ld-arc64/bl34.dd create mode 100644 ld/testsuite/ld-arc64/bl34.s create mode 100644 ld/testsuite/ld-arc64/linkscript.ld create mode 100644 ld/testsuite/ld-arc64/plt34-got.dd create mode 100644 ld/testsuite/ld-arc64/plt34-got.s create mode 100644 ld/testsuite/ld-arc64/plt34-reloc.dd create mode 100644 ld/testsuite/ld-arc64/plt34-reloc.s diff --git a/ld/testsuite/ld-arc64/arcv3_64-reloc-near-exe.dd b/ld/testsuite/ld-arc64/arcv3_64-reloc-near-exe.dd new file mode 100644 index 00000000000..2c77c412719 --- /dev/null +++ b/ld/testsuite/ld-arc64/arcv3_64-reloc-near-exe.dd @@ -0,0 +1,29 @@ +# an exemplary output +# +# test_static.exe: file format elf64-littlearc64 +# +# +# Disassembly of section .text: +# +# 0000000000001000 <__start>: +# 1000: 78e0 nop_s +# 1002: 2731 ff0e 0000 7000 ldl r14,[pcl,28672@s32] ;8000 <.got> +# 1006: R_ARC_GOTPC32 foo +# 100a: 2731 ff0f 0000 7000 ldl r15,[pcl,28672@s32] ;8008 <.got+0x8> +# 100e: R_ARC_GOTPC32 bar +# 1012: 78e0 nop_s +# 1014: 0000 0000 b 0 ;1014 <__start+0x14> + +[^:]+:\s+file format elf.*-.*arc64 + + +Disassembly of section .text: + +^[0-9a-f]+.*: +\s*[0-9a-f]+:\s+[0-9a-f\s]+nop_s +\s*[0-9a-f]+:\s+[0-9a-f\s]+ldl\s+r14,.* +\s*[0-9a-f]+:\s+R_ARC_GOTPC32\s+foo +\s*[0-9a-f]+:\s+[0-9a-f\s]+ldl\s+r15,.* +\s*[0-9a-f]+:\s+R_ARC_GOTPC32\s+bar +\s*[0-9a-f]+:\s+[0-9a-f\s]+nop_s +\s*[0-9a-f]+:.* diff --git a/ld/testsuite/ld-arc64/arcv3_64-reloc-near-so.dd b/ld/testsuite/ld-arc64/arcv3_64-reloc-near-so.dd new file mode 100644 index 00000000000..2b3cef9418e --- /dev/null +++ b/ld/testsuite/ld-arc64/arcv3_64-reloc-near-so.dd @@ -0,0 +1,21 @@ +# an exemplary output +# +# test_dynamic.so: file format elf64-littlearc64 +# +# +# Disassembly of section .got: +# +# 0000000000002440 <.got>: +# ... +# 2440: R_ARC_GLOB_DAT foo +# 2448: R_ARC_GLOB_DAT bar + +[^:]+:\s+file format elf.*-.*arc64 + + +Disassembly of section .got: + +^[0-9a-f]+.*: +\s*\.\.\. +\s*[0-9a-f]+:\s+R_ARC_GLOB_DAT\s+foo +\s*[0-9a-f]+:\s+R_ARC_GLOB_DAT\s+bar diff --git a/ld/testsuite/ld-arc64/arcv3_64-reloc-near.s b/ld/testsuite/ld-arc64/arcv3_64-reloc-near.s new file mode 100644 index 00000000000..1423f924414 --- /dev/null +++ b/ld/testsuite/ld-arc64/arcv3_64-reloc-near.s @@ -0,0 +1,11 @@ + .comm foo,4 + .comm bar,4 + + .text + .align 8 + + .global __start +__start: + nop_s # messing with the alignment a bit + ldl r14, [pcl, @foo@gotpc] + ldl r15, [pcl, @bar@gotpc] diff --git a/ld/testsuite/ld-arc64/arcv3_64.exp b/ld/testsuite/ld-arc64/arcv3_64.exp new file mode 100644 index 00000000000..d39483cd6dd --- /dev/null +++ b/ld/testsuite/ld-arc64/arcv3_64.exp @@ -0,0 +1,48 @@ +# Copyright (C) 2020 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, +# MA 02110-1301, USA. +# + +if { ![istarget arc64-*-*] } { + return +} + +set arcv3_64_tests { + { "Near relocations (executable)" + "-q" "" "" {arcv3_64-reloc-near.s} + { { objdump { -Dr -j .text } arcv3_64-reloc-near-exe.dd } } + "arcv3_64-reloc.exe" } + { "Near relocations (shared object)" + "-shared -q -m arc64linux64" "" "" {arcv3_64-reloc-near.s} + { { objdump -DRj.got arcv3_64-reloc-near-so.dd } } + "arcv3_64-reloc-near.so" } + { "Solve fixed PLT34 reloc" + "-q -T linkscript.ld" "" "" {plt34-reloc.s} + { { objdump -drj.text plt34-reloc.dd } } + "plt34-reloc.x" } + { "Generate PLT entry using PLT34 reloc" + "-shared -m arc64linux64" "" "" {plt34-got.s} + { { objdump -dj.text plt34-got.dd } } + "plt34-got.so" } + { "Solve PCLO32_ME_2 reloc" + "-q -T linkscript.ld" "" "" {bl34.s} + { { objdump -drj.text bl34.dd } } + "bl34.x" } +} + +run_ld_link_tests $arcv3_64_tests diff --git a/ld/testsuite/ld-arc64/bl34.dd b/ld/testsuite/ld-arc64/bl34.dd new file mode 100644 index 00000000000..4f983ecae33 --- /dev/null +++ b/ld/testsuite/ld-arc64/bl34.dd @@ -0,0 +1,12 @@ +[^:]+:\s+file format elf64-.*arc64 + + +Disassembly of section .text: + +^[0-9a-f]+ <__start>: +^\s*[0-9a-f]+:\s+78e0\s+nop_s$ +^\s*[0-9a-f]+:\s+7be0\s4000\s0000\s+bl_s\s\d+@s32\s;100000000\s<foo>$ +^\s*[0-9a-f]+:\s+R_ARC_PCLO32_ME_2\s+\.text2$ +^\s*[0-9a-f]+:\s+7be0\s3fff\sfffe\s+bl_s\s\d+@s32\s;100000000\s<foo>$ +^\s*[0-9a-f]+:\s+R_ARC_PCLO32_ME_2\s+\.text2$ +^\s*[0-9a-f]+:\s+78e0\s+nop_s$ diff --git a/ld/testsuite/ld-arc64/bl34.s b/ld/testsuite/ld-arc64/bl34.s new file mode 100644 index 00000000000..dfda09133ca --- /dev/null +++ b/ld/testsuite/ld-arc64/bl34.s @@ -0,0 +1,13 @@ + .text + .align 4 + .global __start +__start: + nop_s + bl_s @foo@s32 + bl_s @foo@s32 + +;;; Have a symbol beyond 4G boundary. + .section ".foo.text" + .align 4 +foo: + add r0,r0,r0 diff --git a/ld/testsuite/ld-arc64/linkscript.ld b/ld/testsuite/ld-arc64/linkscript.ld new file mode 100644 index 00000000000..bddc653e29b --- /dev/null +++ b/ld/testsuite/ld-arc64/linkscript.ld @@ -0,0 +1,5 @@ +SECTIONS +{ + .text 0x00 : { *(.text) } + .text2 0x100000000 : { *(.foo.text) } +} diff --git a/ld/testsuite/ld-arc64/plt34-got.dd b/ld/testsuite/ld-arc64/plt34-got.dd new file mode 100644 index 00000000000..3f57f6a00ca --- /dev/null +++ b/ld/testsuite/ld-arc64/plt34-got.dd @@ -0,0 +1,9 @@ +[^:]+:\s+file format elf64-.*arc64 + + +Disassembly of section .text: + +^[0-9a-f]+ <__start>: +^\s*[0-9a-f]+:\s+78e0\s+nop_s$ +^\s*[0-9a-f]+:\s+[0-9a-f]+\s[0-9a-f]+\s+bl\s+[\-0-9]+\s+;[0-9a-f]+\s+<\.plt\+0x[0-9a-f]+>$ +^\s*[0-9a-f]+:\s+7be0\s[0-9a-f]+\s[0-9a-f]+\s+bl_s\s+[\-\d]+@s32\s+;[0-9a-f]+\s+<\.plt\+0x[0-9a-f]+>$ \ No newline at end of file diff --git a/ld/testsuite/ld-arc64/plt34-got.s b/ld/testsuite/ld-arc64/plt34-got.s new file mode 100644 index 00000000000..a74c3213dbb --- /dev/null +++ b/ld/testsuite/ld-arc64/plt34-got.s @@ -0,0 +1,9 @@ +;;; Check if 34bit reloc is correctly solved by the linker. + .text + .align 4 + .global __start +__start: + nop_s + bl @foo@plt + bl_s @foo@plt34 + diff --git a/ld/testsuite/ld-arc64/plt34-reloc.dd b/ld/testsuite/ld-arc64/plt34-reloc.dd new file mode 100644 index 00000000000..36427a5394f --- /dev/null +++ b/ld/testsuite/ld-arc64/plt34-reloc.dd @@ -0,0 +1,12 @@ +[^:]+:\s+file format elf64-.*arc64 + + +Disassembly of section .text: + +^[0-9a-f]+ <__start>: +^\s*[0-9a-f]+:\s+78e0\s+nop_s$ +^\s*[0-9a-f]+:\s+7be0\s4000\s0000\s+bl_s\s\d+@s32\s;100000000\s<foo>$ +^\s*[0-9a-f]+:\s+R_ARC_PLT34\s+foo$ +^\s*[0-9a-f]+:\s+7be0\s3fff\sfffe\s+bl_s\s\d+@s32\s;100000000\s<foo>$ +^\s*[0-9a-f]+:\s+R_ARC_PLT34\s+foo$ +^\s*[0-9a-f]+:\s+78e0\s+nop_s$ diff --git a/ld/testsuite/ld-arc64/plt34-reloc.s b/ld/testsuite/ld-arc64/plt34-reloc.s new file mode 100644 index 00000000000..2be4aaf51b6 --- /dev/null +++ b/ld/testsuite/ld-arc64/plt34-reloc.s @@ -0,0 +1,14 @@ +;;; Check if 34bit reloc is correctly solved by the linker. + .text + .align 4 + .global __start +__start: + nop_s + bl_s @foo@plt34 + bl_s @foo@plt34 + +;;; Have a symbol beyond 4G boundary. + .section ".foo.text" + .align 4 +foo: + add r0,r0,r0 -- 2.30.2 ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 3/7] arc: Add new ARCv3 ISA to BFD. 2023-09-19 8:12 [PATCH 0/7] arc: Add new ARCv3 isa support to ARC's backend Claudiu Zissulescu 2023-09-19 8:12 ` [PATCH 1/7] arc: Add new GAS tests for ARCv3 Claudiu Zissulescu 2023-09-19 8:12 ` [PATCH 2/7] arc: Add new LD " Claudiu Zissulescu @ 2023-09-19 8:12 ` Claudiu Zissulescu 2023-09-19 8:12 ` [PATCH 4/7] arc: Add new linker emulation and scripts for ARCv3 ISA Claudiu Zissulescu ` (3 subsequent siblings) 6 siblings, 0 replies; 8+ messages in thread From: Claudiu Zissulescu @ 2023-09-19 8:12 UTC (permalink / raw) To: binutils; +Cc: Claudiu Zissulescu From: Claudiu Zissulescu <claziss@synopsys.com> The new Synopsys's ARCv3 ISA is capable to run either 64-bit or 32-bit ISA. The new 32-bit ISA is not compatible with the old Synopsys ARCv1/ARCv2 ISA, however, it retains a lot of common concepts. Thus, this patch is reusing the old ARC BFD backend and adds the necessary bits for the new architecture in a similar way as it is done for RISCV backend. bfd/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * bfd/Makefile.am: Add ARC64 files. * bfd/Makefile.in: Regerate. * bfd/arc-got.h (TCB_SIZE): Depends on the target architecture. (GOT_ENTRY_SIZE): New define. (write_in_got): Likewise. (read_from_got): Likewise. (align_power): Likewise. (arc_got_entry_type_for_reloc): Use RELA_SIZE and GOT_ENTRY_SIZE. (arc_fill_got_info_for_reloc): Update formating. (relocate_fix_got_relocs_for_got_info): Likewise. (arc_static_sym_data): Deleted structure. (get_static_sym_data): Deleted function. (relocate_fix_got_relocs_for_got_info): Use symbol static data. (create_got_dynrelocs_for_single_entry): Update formating. (create_got_dynrelocs_for_got_info): Likewise. * bfd/arc-plt.c: New file. * bfd/arc-plt.def: Add ARC64 PLT entry. * bfd/arc-plt.h: Clean it up, move functionality to arc-plt.c file. * bfd/archures.c: Add ARC64 target. * bfd/config.bfd: Likewise. * bfd/configure.ac: Likewise. * bfd/bfd-in2.h: Regenerate. * bfd/configure: Likewise. * bfd/libbfd.h: Likewise. * bfd/cpu-arc.c: Clean it up. * bfd/cpu-arc64.c: New file. * bfd/elf32-arc.c: Renamed to elfnn-arc.c. * bfd/elfnn-arc.c: New file. * bfd/reloc.c: Add new ARC64 relocs. * bfd/targets.c: Add ARC64 target. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com> --- bfd/Makefile.am | 23 +- bfd/Makefile.in | 27 +- bfd/arc-got.h | 253 +++-- bfd/arc-plt.c | 121 +++ bfd/arc-plt.def | 127 ++- bfd/arc-plt.h | 93 +- bfd/archures.c | 5 + bfd/bfd-in2.h | 25 + bfd/config.bfd | 20 +- bfd/configure | 6 +- bfd/configure.ac | 6 +- bfd/cpu-arc.c | 79 +- bfd/cpu-arc64.c | 75 ++ bfd/{elf32-arc.c => elfnn-arc.c} | 1486 +++++++++++++++++++----------- bfd/libbfd.h | 22 + bfd/reloc.c | 44 + bfd/targets.c | 6 + 17 files changed, 1593 insertions(+), 825 deletions(-) create mode 100644 bfd/arc-plt.c create mode 100644 bfd/cpu-arc64.c rename bfd/{elf32-arc.c => elfnn-arc.c} (68%) diff --git a/bfd/Makefile.am b/bfd/Makefile.am index 378c13198d6..d8b1cdfeb19 100644 --- a/bfd/Makefile.am +++ b/bfd/Makefile.am @@ -99,6 +99,7 @@ ALL_MACHINES = \ cpu-alpha.lo \ cpu-amdgcn.lo \ cpu-arc.lo \ + cpu-arc64.lo \ cpu-arm.lo \ cpu-avr.lo \ cpu-bfin.lo \ @@ -183,6 +184,7 @@ ALL_MACHINES_CFILES = \ cpu-alpha.c \ cpu-amdgcn.c \ cpu-arc.c \ + cpu-arc64.c \ cpu-arm.c \ cpu-avr.c \ cpu-bfin.c \ @@ -265,6 +267,7 @@ ALL_MACHINES_CFILES = \ # The .o files needed by all of the 32 bit vectors that are configured into # target_vector in targets.c if configured with --enable-targets=all. BFD32_BACKENDS = \ + arc-plt.lo \ aout-cris.lo \ aout-ns32k.lo \ aout32.lo \ @@ -400,6 +403,7 @@ BFD32_BACKENDS = \ xtensa-modules.lo BFD32_BACKENDS_CFILES = \ + arc-plt.c \ aout-cris.c \ aout-ns32k.c \ aout32.c \ @@ -432,7 +436,6 @@ BFD32_BACKENDS_CFILES = \ elf-vxworks.c \ elf.c \ elf32-am33lin.c \ - elf32-arc.c \ elf32-arm.c \ elf32-avr.c \ elf32-bfin.c \ @@ -545,6 +548,7 @@ BFD64_BACKENDS = \ coff-x86_64.lo \ coff64-rs6000.lo \ elf32-aarch64.lo \ + elf32-arc64.lo \ elf32-ia64.lo \ elf32-kvx.lo \ elf32-loongarch.lo \ @@ -553,6 +557,7 @@ BFD64_BACKENDS = \ elf32-score.lo \ elf32-score7.lo \ elf64-aarch64.lo \ + elf64-arc64.lo \ elf64-alpha.lo \ elf64-amdgcn.lo \ elf64-bpf.lo \ @@ -687,6 +692,7 @@ SOURCE_CFILES = \ BUILD_CFILES = \ elf32-aarch64.c elf64-aarch64.c \ + elf32-arc.c elf64-arc64.c elf32-arc64.c\ elf32-kvx.c elf64-kvx.c \ elf32-ia64.c elf64-ia64.c \ elf32-loongarch.c elf64-loongarch.c \ @@ -849,6 +855,21 @@ elf64-aarch64.c : elfnn-aarch64.c $(AM_V_at)echo "#line 1 \"$<\"" > $@ $(AM_V_GEN)$(SED) -e s/NN/64/g < $< >> $@ +elf32-arc.c : elfnn-arc.c + rm -f elf32-arc.c + $(AM_V_at)echo "#line 1 \"$(srcdir)/elfnn-arc.c\"" > $@ + $(AM_V_GEN)$(SED) -e s/NN/32/g -e s/AA//g < $< >> $@ + +elf64-arc64.c : elfnn-arc.c + rm -f elf64-arc64.c + $(AM_V_at)echo "#line 1 \"$(srcdir)/elfnn-arc.c\"" > $@ + $(AM_V_GEN)$(SED) -e s/NN/64/g -e s/AA/64/g < $< >> $@ + +elf32-arc64.c : elfnn-arc.c + rm -f elf32-arc64.c + $(AM_V_at)echo "#line 1 \"$(srcdir)/elfnn-arc.c\"" > $@ + $(AM_V_GEN)$(SED) -e s/NN/32/g -e s/AA/64/g < $< >> $@ + elf32-ia64.c : elfnn-ia64.c $(AM_V_at)echo "#line 1 \"$<\"" > $@ $(AM_V_GEN)$(SED) -e s/NN/32/g < $< >> $@ diff --git a/bfd/Makefile.in b/bfd/Makefile.in index 8d09f6fa4af..4c396334a0e 100644 --- a/bfd/Makefile.in +++ b/bfd/Makefile.in @@ -554,6 +554,7 @@ ALL_MACHINES = \ cpu-alpha.lo \ cpu-amdgcn.lo \ cpu-arc.lo \ + cpu-arc64.lo \ cpu-arm.lo \ cpu-avr.lo \ cpu-bfin.lo \ @@ -638,6 +639,7 @@ ALL_MACHINES_CFILES = \ cpu-alpha.c \ cpu-amdgcn.c \ cpu-arc.c \ + cpu-arc64.c \ cpu-arm.c \ cpu-avr.c \ cpu-bfin.c \ @@ -721,6 +723,7 @@ ALL_MACHINES_CFILES = \ # The .o files needed by all of the 32 bit vectors that are configured into # target_vector in targets.c if configured with --enable-targets=all. BFD32_BACKENDS = \ + arc-plt.lo \ aout-cris.lo \ aout-ns32k.lo \ aout32.lo \ @@ -856,6 +859,7 @@ BFD32_BACKENDS = \ xtensa-modules.lo BFD32_BACKENDS_CFILES = \ + arc-plt.c \ aout-cris.c \ aout-ns32k.c \ aout32.c \ @@ -888,7 +892,6 @@ BFD32_BACKENDS_CFILES = \ elf-vxworks.c \ elf.c \ elf32-am33lin.c \ - elf32-arc.c \ elf32-arm.c \ elf32-avr.c \ elf32-bfin.c \ @@ -1002,6 +1005,7 @@ BFD64_BACKENDS = \ coff-x86_64.lo \ coff64-rs6000.lo \ elf32-aarch64.lo \ + elf32-arc64.lo \ elf32-ia64.lo \ elf32-kvx.lo \ elf32-loongarch.lo \ @@ -1010,6 +1014,7 @@ BFD64_BACKENDS = \ elf32-score.lo \ elf32-score7.lo \ elf64-aarch64.lo \ + elf64-arc64.lo \ elf64-alpha.lo \ elf64-amdgcn.lo \ elf64-bpf.lo \ @@ -1143,6 +1148,7 @@ SOURCE_CFILES = \ BUILD_CFILES = \ elf32-aarch64.c elf64-aarch64.c \ + elf32-arc.c elf32-arc64.c elf64-arc64.c \ elf32-kvx.c elf64-kvx.c \ elf32-ia64.c elf64-ia64.c \ elf32-loongarch.c elf64-loongarch.c \ @@ -1435,6 +1441,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/aout-ns32k.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/aout32.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/aout64.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/arc-plt.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/archive.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/archive64.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/archures.Plo@am__quote@ @@ -1468,6 +1475,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-alpha.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-amdgcn.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-arc.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-arc64.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-arm.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-avr.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-bfin.Plo@am__quote@ @@ -1564,6 +1572,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-aarch64.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-am33lin.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-arc.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-arc64.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-arm.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-avr.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-bfin.Plo@am__quote@ @@ -1633,6 +1642,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-aarch64.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-alpha.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-amdgcn.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-arc64.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-bpf.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-gen.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-hppa.Plo@am__quote@ @@ -2351,6 +2361,21 @@ elf64-aarch64.c : elfnn-aarch64.c $(AM_V_at)echo "#line 1 \"$<\"" > $@ $(AM_V_GEN)$(SED) -e s/NN/64/g < $< >> $@ +elf32-arc.c : elfnn-arc.c + rm -f elf32-arc.c + $(AM_V_at)echo "#line 1 \"$(srcdir)/elfnn-arc.c\"" > $@ + $(AM_V_GEN)$(SED) -e s/NN/32/g -e s/AA//g < $< >> $@ + +elf64-arc64.c : elfnn-arc.c + rm -f elf64-arc64.c + $(AM_V_at)echo "#line 1 \"$(srcdir)/elfnn-arc.c\"" > $@ + $(AM_V_GEN)$(SED) -e s/NN/64/g -e s/AA/64/g < $< >> $@ + +elf32-arc64.c : elfnn-arc.c + rm -f elf32-arc64.c + $(AM_V_at)echo "#line 1 \"$(srcdir)/elfnn-arc.c\"" > $@ + $(AM_V_GEN)$(SED) -e s/NN/32/g -e s/AA/64/g < $< >> $@ + elf32-ia64.c : elfnn-ia64.c $(AM_V_at)echo "#line 1 \"$<\"" > $@ $(AM_V_GEN)$(SED) -e s/NN/32/g < $< >> $@ diff --git a/bfd/arc-got.h b/bfd/arc-got.h index dfa3f5b4fe0..456a2be7d29 100644 --- a/bfd/arc-got.h +++ b/bfd/arc-got.h @@ -22,9 +22,25 @@ #ifndef ARC_GOT_H #define ARC_GOT_H +/* Thread Control Block (TCB) contains at offset zero a pointer to the + dynamic thread vector dtvt for the thread. */ +#if ARCH_SIZE == 32 #define TCB_SIZE (8) - -#define align_power(addr, align) \ +#else +#define TCB_SIZE (16) +#endif + +#if ARCH_SIZE == 32 +#define GOT_ENTRY_SIZE 4 +#define write_in_got(A, B, C) bfd_put_32 (A, B, C) +#define read_from_got(A, B) bfd_get_32 (A, B) +#else +#define GOT_ENTRY_SIZE 8 +#define write_in_got(A, B, C) bfd_put_64 (A, B, C) +#define read_from_got(A, B) bfd_get_64 (A, B) +#endif + +#define align_power(addr, align) \ (((addr) + ((bfd_vma) 1 << (align)) - 1) & (-((bfd_vma) 1 << (align)))) enum tls_type_e @@ -201,7 +217,7 @@ arc_got_entry_type_for_reloc (reloc_howto_type *howto) { \ if (COND_FOR_RELOC) \ { \ - htab->srel##SECNAME->size += sizeof (Elf32_External_Rela); \ + htab->srel##SECNAME->size += RELA_SIZE; \ ARC_DEBUG ("arc_info: Added reloc space in " \ #SECNAME " section at " __FILE__ \ ":%d for symbol %s\n", \ @@ -211,7 +227,7 @@ arc_got_entry_type_for_reloc (reloc_howto_type *howto) if (H->dynindx == -1 && !H->forced_local) \ if (! bfd_elf_link_record_dynamic_symbol (info, H)) \ return false; \ - htab->s##SECNAME->size += 4; \ + htab->s##SECNAME->size += GOT_ENTRY_SIZE; \ } \ static bool @@ -230,13 +246,13 @@ arc_fill_got_info_for_reloc (enum tls_type_e type, case GOT_NORMAL: { bfd_vma offset - = ADD_SYMBOL_REF_SEC_AND_RELOC (got, bfd_link_pic (info) - || h != NULL, h); + = ADD_SYMBOL_REF_SEC_AND_RELOC (got, + bfd_link_pic (info) || h != NULL, + h); new_got_entry_to_list (list, type, offset, TLS_GOT_NONE); } break; - case GOT_TLS_GD: { bfd_vma offset @@ -262,59 +278,16 @@ arc_fill_got_info_for_reloc (enum tls_type_e type, return true; } -struct arc_static_sym_data { - bfd_vma sym_value; - const char *symbol_name; -}; - -static struct arc_static_sym_data -get_static_sym_data (unsigned long r_symndx, - Elf_Internal_Sym *local_syms, - asection **local_sections, - struct elf_link_hash_entry *h, - struct arc_relocation_data *reloc_data) -{ - static const char local_name[] = "(local)"; - struct arc_static_sym_data ret = { 0, NULL }; - - if (h != NULL) - { - BFD_ASSERT (h->root.type != bfd_link_hash_undefweak - && h->root.type != bfd_link_hash_undefined); - /* TODO: This should not be here. */ - reloc_data->sym_value = h->root.u.def.value; - reloc_data->sym_section = h->root.u.def.section; - - ret.sym_value = h->root.u.def.value - + h->root.u.def.section->output_section->vma - + h->root.u.def.section->output_offset; - - ret.symbol_name = h->root.root.string; - } - else - { - Elf_Internal_Sym *sym = local_syms + r_symndx; - asection *sec = local_sections[r_symndx]; - - ret.sym_value = sym->st_value - + sec->output_section->vma - + sec->output_offset; - - ret.symbol_name = local_name; - } - return ret; -} - static bfd_vma -relocate_fix_got_relocs_for_got_info (struct got_entry ** list_p, - enum tls_type_e type, - struct bfd_link_info * info, - bfd * output_bfd, - unsigned long r_symndx, - Elf_Internal_Sym * local_syms, - asection ** local_sections, - struct elf_link_hash_entry * h, - struct arc_relocation_data * reloc_data) +relocate_fix_got_relocs_for_got_info (struct got_entry **list_p, + enum tls_type_e type, + struct bfd_link_info *info, + bfd *output_bfd, + unsigned long r_symndx, + Elf_Internal_Sym * local_syms, + asection **local_sections, + struct elf_link_hash_entry *h, + struct arc_relocation_data *reloc_data) { struct elf_link_hash_table *htab = elf_hash_table (info); struct got_entry *entry = NULL; @@ -332,91 +305,84 @@ relocate_fix_got_relocs_for_got_info (struct got_entry ** list_p, && SYMBOL_REFERENCES_LOCAL (info, h)))) { const char ATTRIBUTE_UNUSED *symbol_name; - asection *tls_sec = elf_hash_table (info)->tls_sec; + static const char *local_name = "(local)"; + bfd_vma sym_value = 0; + asection *sec = NULL; + + if (h != NULL) + { + reloc_data->sym_value = h->root.u.def.value; + reloc_data->sym_section = h->root.u.def.section; + + sec = h->root.u.def.section; + sym_value = h->root.u.def.value; + symbol_name = h->root.root.string; + } + else + { + Elf_Internal_Sym *sym = local_syms + r_symndx; + + sec = local_sections[r_symndx]; + sym_value = sym->st_value; + symbol_name = local_name; + } if (entry && !entry->processed) { + int tcb_size = 0; + switch (entry->type) { + case GOT_TLS_IE: + tcb_size = TCB_SIZE; + /* Fall through. */ case GOT_TLS_GD: { + asection *tls_sec = elf_hash_table (info)->tls_sec; + BFD_ASSERT (tls_sec && tls_sec->output_section); - bfd_vma sec_vma = tls_sec->output_section->vma; + bfd_vma tls_vma = tls_sec->output_section->vma; + + BFD_ASSERT (sec->output_section); + sym_value += sec->output_section->vma + sec->output_offset; - if (h == NULL || h->forced_local - || !elf_hash_table (info)->dynamic_sections_created) + if (h == NULL + || h->forced_local + || !elf_hash_table (info)->dynamic_sections_created) { - struct arc_static_sym_data tmp = - get_static_sym_data (r_symndx, local_syms, local_sections, - h, reloc_data); - - bfd_put_32 (output_bfd, - tmp.sym_value - sec_vma - + (elf_hash_table (info)->dynamic_sections_created - ? 0 - : (align_power (0, - tls_sec->alignment_power))), - htab->sgot->contents + entry->offset - + (entry->existing_entries == TLS_GOT_MOD_AND_OFF - ? 4 : 0)); - - ARC_DEBUG ("arc_info: FIXED -> %s value = %#lx " - "@ %lx, for symbol %s\n", - (entry->type == GOT_TLS_GD ? "GOT_TLS_GD" : - "GOT_TLS_IE"), - (long) (sym_value - sec_vma), - (long) (htab->sgot->output_section->vma - + htab->sgot->output_offset - + entry->offset - + (entry->existing_entries == TLS_GOT_MOD_AND_OFF - ? 4 : 0)), - tmp.symbol_name); + write_in_got + (output_bfd, + /* S - TLS_REL + { round (TCB_SIZE, align), 0 } */ + sym_value - tls_vma + + (elf_hash_table (info)->dynamic_sections_created + ? 0 : (align_power (tcb_size, + tls_sec->alignment_power))), + htab->sgot->contents + entry->offset + + (entry->existing_entries == TLS_GOT_MOD_AND_OFF + ? GOT_ENTRY_SIZE : 0)); + + ARC_DEBUG + ("arc_info: FIXED -> %s value = %#lx " + "@ %lx, for symbol %s\n", + (entry->type == GOT_TLS_GD ? "GOT_TLS_GD" : + "GOT_TLS_IE"), + (long) (sym_value - tls_vma), + (long) (htab->sgot->output_section->vma + + htab->sgot->output_offset + + entry->offset + + (entry->existing_entries == TLS_GOT_MOD_AND_OFF + ? GOT_ENTRY_SIZE : 0)), + symbol_name); } } break; - case GOT_TLS_IE: - { - BFD_ASSERT (tls_sec && tls_sec->output_section); - bfd_vma ATTRIBUTE_UNUSED sec_vma - = tls_sec->output_section->vma; - - struct arc_static_sym_data tmp = - get_static_sym_data (r_symndx, local_syms, local_sections, - h, reloc_data); - - bfd_put_32 (output_bfd, - tmp.sym_value - sec_vma - + (elf_hash_table (info)->dynamic_sections_created - ? 0 - : (align_power (TCB_SIZE, - tls_sec->alignment_power))), - htab->sgot->contents + entry->offset - + (entry->existing_entries == TLS_GOT_MOD_AND_OFF - ? 4 : 0)); - - ARC_DEBUG ("arc_info: FIXED -> %s value = %#lx " - "@ %p, for symbol %s\n", - (entry->type == GOT_TLS_GD ? "GOT_TLS_GD" : - "GOT_TLS_IE"), - (long) (sym_value - sec_vma), - (long) (htab->sgot->output_section->vma - + htab->sgot->output_offset - + entry->offset - + (entry->existing_entries == TLS_GOT_MOD_AND_OFF - ? 4 : 0)), - tmp.symbol_name); - } - break; - case GOT_NORMAL: { - bfd_vma sec_vma - = reloc_data->sym_section->output_section->vma - + reloc_data->sym_section->output_offset; - - if (h != NULL - && h->root.type == bfd_link_hash_undefweak) + if (h != NULL && + (h->root.type == bfd_link_hash_undefweak + /* FIXME! catch the undefined situation in a test. */ + || h->root.type == bfd_link_hash_undefined)) ARC_DEBUG ("arc_info: PATCHED: NOT_PATCHED " "@ %#08lx for sym %s in got offset %#lx " "(is undefweak)\n", @@ -427,12 +393,16 @@ relocate_fix_got_relocs_for_got_info (struct got_entry ** list_p, (long) entry->offset); else { - bfd_put_32 (output_bfd, - reloc_data->sym_value + sec_vma, - htab->sgot->contents + entry->offset); + BFD_ASSERT (sec->output_section); + + sym_value += sec->output_section->vma + sec->output_offset; + + write_in_got (output_bfd, + sym_value, + htab->sgot->contents + entry->offset); ARC_DEBUG ("arc_info: PATCHED: %#08lx " "@ %#08lx for sym %s in got offset %#lx\n", - (long) (reloc_data->sym_value + sec_vma), + (long) sym_value, (long) (htab->sgot->output_section->vma + htab->sgot->output_offset + entry->offset), @@ -455,7 +425,7 @@ relocate_fix_got_relocs_for_got_info (struct got_entry ** list_p, static void create_got_dynrelocs_for_single_entry (struct got_entry *list, bfd *output_bfd, - struct bfd_link_info * info, + struct bfd_link_info *info, struct elf_link_hash_entry *h) { if (list == NULL) @@ -474,8 +444,8 @@ create_got_dynrelocs_for_single_entry (struct got_entry *list, ADD_RELA (output_bfd, got, got_offset, 0, R_ARC_RELATIVE, 0); } /* Do not fully understand the side effects of this condition. - The relocation space might still being reserved. Perhaps - I should clear its value. */ + The relocation space might still being reserved. Perhaps I + should clear its value. */ else if (h != NULL && h->dynindx != -1) { ADD_RELA (output_bfd, got, got_offset, h->dynindx, R_ARC_GLOB_DAT, 0); @@ -516,12 +486,12 @@ GOT_OFFSET = %#lx, GOT_VMA = %#lx, INDEX = %ld, ADDEND = 0x0\n", bfd_vma addend = 0; if (list->type == GOT_TLS_IE) { - addend = bfd_get_32 (output_bfd, - htab->sgot->contents + got_offset); + addend = read_from_got (output_bfd, + htab->sgot->contents + got_offset); } - ADD_RELA (output_bfd, got, - got_offset + (e == TLS_GOT_MOD_AND_OFF ? 4 : 0), + ADD_RELA (output_bfd, got, got_offset + + (e == TLS_GOT_MOD_AND_OFF ? GOT_ENTRY_SIZE : 0), dynindx, (list->type == GOT_TLS_IE ? R_ARC_TLS_TPOFF : R_ARC_TLS_DTPOFF), @@ -542,13 +512,14 @@ GOT_OFFSET = %#lx, GOT_VMA = %#lx, INDEX = %ld, ADDEND = %#lx\n", static void create_got_dynrelocs_for_got_info (struct got_entry **list_p, bfd *output_bfd, - struct bfd_link_info * info, + struct bfd_link_info *info, struct elf_link_hash_entry *h) { + struct got_entry *list = *list_p; + if (list_p == NULL) return; - struct got_entry *list = *list_p; /* Traverse the list of got entries for this symbol. */ while (list) { diff --git a/bfd/arc-plt.c b/bfd/arc-plt.c new file mode 100644 index 00000000000..8dd778b58d2 --- /dev/null +++ b/bfd/arc-plt.c @@ -0,0 +1,121 @@ +/* ARC-specific support for PLT relocations. + Copyright (C) 2023 Free Software Foundation, Inc. + Contributed by Cupertino Miranda (cmiranda@synopsys.com). + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "arc-plt.h" + +#define PLT_TYPE_START(NAME) \ + const insn_hword NAME##_plt_entry[] = { +#define PLT_TYPE_END(NAME) }; +#define PLT_ENTRY(...) __VA_ARGS__, +#define PLT_ELEM(...) +#define ENTRY_RELOC(...) +#define ELEM_RELOC(...) + +#include "arc-plt.def" + +#undef PLT_TYPE_START +#undef PLT_TYPE_END +#undef PLT_ENTRY +#undef PLT_ELEM +#undef ENTRY_RELOC +#undef ELEM_RELOC + +#define PLT_TYPE_START(NAME) \ + const struct plt_reloc NAME##_plt_entry_relocs[] = { +#define PLT_TYPE_END(NAME) \ + {0, 0, 0, LAST_RELOC, 0} \ + }; +#define PLT_ENTRY(...) +#define PLT_ELEM(...) +#define ENTRY_RELOC(...) { __VA_ARGS__ }, +#define ELEM_RELOC(...) + +#include "arc-plt.def" + +#undef PLT_TYPE_START +#undef PLT_TYPE_END +#undef PLT_ENTRY +#undef PLT_ELEM +#undef ENTRY_RELOC +#undef ELEM_RELOC + + +#define PLT_TYPE_START(NAME) \ + const insn_hword NAME##_plt_elem[] = { +#define PLT_TYPE_END(NAME) }; +#define PLT_ENTRY(...) +#define PLT_ELEM(...) __VA_ARGS__, +#define ENTRY_RELOC(...) +#define ELEM_RELOC(...) + +#include "arc-plt.def" + +#undef PLT_TYPE_START +#undef PLT_TYPE_END +#undef PLT_ENTRY +#undef PLT_ELEM +#undef ENTRY_RELOC +#undef ELEM_RELOC + +#define PLT_TYPE_START(NAME) \ + const struct plt_reloc NAME##_plt_elem_relocs[] = { +#define PLT_TYPE_END(NAME) \ + {0, 0, 0, LAST_RELOC, 0} \ + }; +#define PLT_ENTRY(...) +#define PLT_ELEM(...) +#define ENTRY_RELOC(...) +#define ELEM_RELOC(...) { __VA_ARGS__ }, + +#include "arc-plt.def" + +#undef PLT_TYPE_START +#undef PLT_TYPE_END +#undef PLT_ENTRY +#undef PLT_ELEM +#undef ENTRY_RELOC +#undef ELEM_RELOC + + +#define PLT_TYPE_START(NAME) \ + { \ + .entry = &NAME##_plt_entry, \ + .entry_size = sizeof (NAME##_plt_entry), \ + .elem = &NAME##_plt_elem, \ + .elem_size = sizeof (NAME##_plt_elem), \ + .entry_relocs = NAME##_plt_entry_relocs, \ + .elem_relocs = NAME##_plt_elem_relocs +#define PLT_TYPE_END(NAME) }, +#define PLT_ENTRY(...) +#define PLT_ELEM(...) +#define ENTRY_RELOC(...) +#define ELEM_RELOC(...) +struct plt_version_t plt_versions[PLT_MAX] = + { +#include "arc-plt.def" + }; + +#undef PLT_TYPE_START +#undef PLT_TYPE_END +#undef PLT_ENTRY +#undef PLT_ELEM +#undef ENTRY_RELOC +#undef ELEM_RELOC diff --git a/bfd/arc-plt.def b/bfd/arc-plt.def index 2b602c47639..a3b32f379f0 100644 --- a/bfd/arc-plt.def +++ b/bfd/arc-plt.def @@ -1,4 +1,4 @@ -/* Arc V2 Related PLT entries. +/* Arc V2/V3 Related PLT entries. Copyright (C) 2016-2023 Free Software Foundation, Inc. Contributed by Cupertino Miranda (cmiranda@synopsys.com). @@ -19,15 +19,72 @@ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ -PLT_TYPE_START (ELF_ARCV2_PIC) - PLT_ENTRY (0x2730, 0x7f8b, 0x0000, 0x0000) /* ld %r11, [pcl,0] : 0 to be replaced by _DYNAMIC@GOTPC+4 */ - PLT_ENTRY (0x2730, 0x7f8a, 0x0000, 0x0000) /* ld %r10, [pcl,0] : 0 to be replaced by _DYNAMIC@GOTPC+8 */ - PLT_ENTRY (0x2020, 0x0280) /* j [%r10] */ - PLT_ENTRY (0x0,0x0,0x0,0x0,0x0,0x0) /* padding */ - PLT_ELEM (0x2730, 0x7f8c, 0x0000, 0x0000) /* ld %r12, [%pc,func@got] */ - PLT_ELEM (0x2021, 0x0300) /* j.d [%r12] */ - PLT_ELEM (0x240a, 0x1fc0) /* mov %r12, %pcl */ +PLT_TYPE_START (ELF_ARCV3_PIC) +/* + -- at .got.plt + 0 should be the address of .dynamic + ldl r11, [pcl, 0] .got.plt + 8 + ldl r10, [pcl, 0] .got.plt + 16 + j [r10] + padding + + 2e: 2731 ff0b 0000 0000 ldl r11,[pcl,0@s32] ;2c <main+0x2c> + 32: R_ARC_GOTPC32 f_var + 36: 2731 ff0a 0000 0000 ldl r10,[pcl,0@s32] ;34 <main+0x34> + 3a: R_ARC_GOTPC32 f_var + 3e: 2020 0280 j [r10] +*/ + +/* ldl %r11, [pcl,0] : 0 to be replaced by _DYNAMIC@GOTPC+4. */ + PLT_ENTRY (0x2731, 0xff0b, 0x0000, 0x0000) +/* ldl %r10, [pcl,0] : 0 to be replaced by _DYNAMIC@GOTPC+8. */ + PLT_ENTRY (0x2731, 0xff0a, 0x0000, 0x0000) +/* j [%r10]. */ + PLT_ENTRY (0x2020, 0x0280) +/* padding. */ + PLT_ENTRY (0x0, 0x0, 0x0, 0x0, 0x0,0x0) + +/* + ldl r12, [pcl, 0] -- at .got.plt + 0 should be the address of .dynamic + + 46: 2731 ff0c 0000 0000 ldl r12,[pcl,0@s32] ;44 <main+0x44> + 4a: R_ARC_GOTPC32 f_var + 4e: 2021 0300 j.d [r12] + 52: 5c0a 1fc0 movl r12,pcl +*/ + +/* ld %r12, [%pc,func@got]. */ + PLT_ELEM (0x2731, 0xff0c, 0x0000, 0x0000) +/* j.d [%r12]. */ + PLT_ELEM (0x2021, 0x0300) +/* movl %r12, %pcl. */ + PLT_ELEM (0x5c0a, 0x1fc0) + + ENTRY_RELOC (4, 32, 0xFFFFFFFF, SGOT | RELATIVE_INSN_32 | MIDDLE_ENDIAN, 8) + ENTRY_RELOC (12, 32, 0xFFFFFFFF, SGOT | RELATIVE_INSN_32 | MIDDLE_ENDIAN, 16) + ENTRY_RELOC (20, 32, 0xFFFFFFFF, SGOT, 0) + + ELEM_RELOC (4, 32, 0xFFFFFFFF, SGOT | RELATIVE_INSN_32 | MIDDLE_ENDIAN, 0) + +PLT_TYPE_END (ELF_ARCV3_PIC) + + +PLT_TYPE_START (ELF_ARCV2_PIC) +/* ld %r11, [pcl,0] : 0 to be replaced by _DYNAMIC@GOTPC+4. */ + PLT_ENTRY (0x2730, 0x7f8b, 0x0000, 0x0000) +/* ld %r10, [pcl,0] : 0 to be replaced by _DYNAMIC@GOTPC+8. */ + PLT_ENTRY (0x2730, 0x7f8a, 0x0000, 0x0000) +/* j [%r10]. */ + PLT_ENTRY (0x2020, 0x0280) +/* padding. */ + PLT_ENTRY (0x0,0x0,0x0,0x0,0x0,0x0) + + /* ld %r12, [%pc,func@got]. */ + PLT_ELEM (0x2730, 0x7f8c, 0x0000, 0x0000) +/* j.d [%r12]. */ + PLT_ELEM (0x2021, 0x0300) +/* mov %r12, %pcl. */ + PLT_ELEM (0x240a, 0x1fc0) ENTRY_RELOC (4, 32, 0xFFFFFFFF, SGOT | RELATIVE_INSN_32 | MIDDLE_ENDIAN, 4) ENTRY_RELOC (12, 32, 0xFFFFFFFF, SGOT | RELATIVE_INSN_32 | MIDDLE_ENDIAN, 8) @@ -38,14 +95,18 @@ PLT_TYPE_START (ELF_ARCV2_PIC) PLT_TYPE_END (ELF_ARCV2_PIC) PLT_TYPE_START (ELF_ARCV2_ABS) - PLT_ENTRY (0x1600,0x700b,0x0000,0x0000) /* ld %r11, [0] */ - PLT_ENTRY (0x1600,0x700a,0x0000,0x0000) /* ld %r10, [0] */ - PLT_ENTRY (0x2020,0x0280) /* j [%r10] */ - PLT_ENTRY (0x0,0x0,0x0,0x0,0x0,0x0) /* padding */ - - PLT_ELEM (0x2730, 0x7f8c, 0x0000, 0x0000) /* ld %r12, [%pcl,func@gotpc] */ - PLT_ELEM (0x2021,0x0300) /* j.d [%r12] */ - PLT_ELEM (0x240a,0x1fc0) /* mov %r12, %pcl */ +/* ld %r11, [0]. */ + PLT_ENTRY (0x1600,0x700b,0x0000,0x0000) +/* ld %r10, [0]. */ + PLT_ENTRY (0x1600,0x700a,0x0000,0x0000) +/* j [%r10]. */ + PLT_ENTRY (0x2020,0x0280) +/* padding. */ + PLT_ENTRY (0x0,0x0,0x0,0x0,0x0,0x0) + + PLT_ELEM (0x2730, 0x7f8c, 0x0000, 0x0000) /* ld %r12, [%pcl,func@gotpc]. */ + PLT_ELEM (0x2021,0x0300) /* j.d [%r12]. */ + PLT_ELEM (0x240a,0x1fc0) /* mov %r12, %pcl. */ ENTRY_RELOC (4, 32, 0xFFFFFFFF, SGOT | MIDDLE_ENDIAN, 4) ENTRY_RELOC (12, 32, 0xFFFFFFFF, SGOT | MIDDLE_ENDIAN, 8) @@ -59,14 +120,18 @@ PLT_TYPE_END (ELF_ARCV2_ABS) /* Non Arc V2 Related PLT entries. */ PLT_TYPE_START (ELF_ARC_PIC) - PLT_ENTRY (0x2730,0x7f8b,0x0000,0x0000) /* ld %r11, [pcl,0] : 0 to be replaced by _DYNAMIC@GOTPC+4 */ - PLT_ENTRY (0x2730,0x7f8a,0x0000,0x0000) /* ld %r10, [pcl,0] : 0 to be replaced by -DYNAMIC@GOTPC+8 */ - PLT_ENTRY (0x2020,0x0280) /* j [%r10] */ - PLT_ENTRY (0x0,0x0) /* padding */ - - PLT_ELEM (0x2730,0x7f8c,0x0000,0x0000) /* ld %r12, [%pc,func@got] */ - PLT_ELEM (0x7c20) /* j_s.d [%r12] */ - PLT_ELEM (0x74ef) /* mov_s %r12, %pcl */ +/* ld %r11, [pcl,0] : 0 to be replaced by _DYNAMIC@GOTPC+4. */ + PLT_ENTRY (0x2730,0x7f8b,0x0000,0x0000) +/* ld %r10, [pcl,0] : 0 to be replaced by -DYNAMIC@GOTPC+8. */ + PLT_ENTRY (0x2730,0x7f8a,0x0000,0x0000) +/* j [%r10]. */ + PLT_ENTRY (0x2020,0x0280) +/* padding. */ + PLT_ENTRY (0x0,0x0) + + PLT_ELEM (0x2730,0x7f8c,0x0000,0x0000) /* ld %r12, [%pc,func@got]. */ + PLT_ELEM (0x7c20) /* j_s.d [%r12]. */ + PLT_ELEM (0x74ef) /* mov_s %r12, %pcl. */ ENTRY_RELOC (4, 32, 0xFFFFFFFF, SGOT | RELATIVE_INSN_32 | MIDDLE_ENDIAN, 4) ENTRY_RELOC (12, 32, 0xFFFFFFFF, SGOT | RELATIVE_INSN_32 | MIDDLE_ENDIAN, 8) @@ -77,13 +142,13 @@ PLT_TYPE_START (ELF_ARC_PIC) PLT_TYPE_END (ELF_ARC_PIC) PLT_TYPE_START (ELF_ARC_ABS) - PLT_ENTRY (0x1600,0x700b,0x0000,0x0000) /* ld %r11, [0] */ - PLT_ENTRY (0x1600,0x700a,0x0000,0x0000) /* ld %r10, [0] */ - PLT_ENTRY (0x2020,0x0280) /* j [%r10] */ - PLT_ENTRY (0x0,0x0) /* padding */ + PLT_ENTRY (0x1600,0x700b,0x0000,0x0000) /* ld %r11, [0]. */ + PLT_ENTRY (0x1600,0x700a,0x0000,0x0000) /* ld %r10, [0]. */ + PLT_ENTRY (0x2020,0x0280) /* j [%r10]. */ + PLT_ENTRY (0x0,0x0) /* padding. */ - PLT_ELEM (0x2730,0x7f8c,0x0000,0x0000) /* ld %r12, [%pc,func@gotpc] */ - PLT_ELEM (0x7c20,0x74ef) /* mov_s %r12, %pcl */ + PLT_ELEM (0x2730,0x7f8c,0x0000,0x0000) /* ld %r12, [%pc,func@gotpc]. */ + PLT_ELEM (0x7c20,0x74ef) /* mov_s %r12, %pcl. */ ENTRY_RELOC (4, 32, 0xFFFFFFFF, SGOT | MIDDLE_ENDIAN, 4) ENTRY_RELOC (12, 32, 0xFFFFFFFF, SGOT | MIDDLE_ENDIAN, 8) diff --git a/bfd/arc-plt.h b/bfd/arc-plt.h index e11b72eeadd..ad1b86fc9f8 100644 --- a/bfd/arc-plt.h +++ b/bfd/arc-plt.h @@ -22,6 +22,9 @@ #ifndef ARC_PLT_H #define ARC_PLT_H +#include "sysdep.h" +#include "bfd.h" + /* Instructions appear in memory as a sequence of half-words (16 bit); individual half-words are represented on the target in target byte order. We use 'unsigned short' on the host to represent the PLT templates, @@ -92,97 +95,20 @@ struct plt_version_t }; #define PLT_TYPE_START(NAME) \ - const insn_hword NAME##_plt_entry[] = { -#define PLT_TYPE_END(NAME) }; -#define PLT_ENTRY(...) __VA_ARGS__, -#define PLT_ELEM(...) -#define ENTRY_RELOC(...) -#define ELEM_RELOC(...) - -#include "arc-plt.def" - -#undef PLT_TYPE_START -#undef PLT_TYPE_END -#undef PLT_ENTRY -#undef PLT_ELEM -#undef ENTRY_RELOC -#undef ELEM_RELOC - -#define PLT_TYPE_START(NAME) \ - const struct plt_reloc NAME##_plt_entry_relocs[] = { -#define PLT_TYPE_END(NAME) \ - {0, 0, 0, LAST_RELOC, 0} \ - }; -#define PLT_ENTRY(...) -#define PLT_ELEM(...) -#define ENTRY_RELOC(...) { __VA_ARGS__ }, -#define ELEM_RELOC(...) + extern const insn_hword NAME##_plt_entry[]; \ + extern const struct plt_reloc NAME##_plt_entry_relocs[]; \ + extern const insn_hword NAME##_plt_elem[]; \ + extern const struct plt_reloc NAME##_plt_elem_relocs[]; -#include "arc-plt.def" -#undef PLT_TYPE_START -#undef PLT_TYPE_END -#undef PLT_ENTRY -#undef PLT_ELEM -#undef ENTRY_RELOC -#undef ELEM_RELOC - - -#define PLT_TYPE_START(NAME) \ - const insn_hword NAME##_plt_elem[] = { -#define PLT_TYPE_END(NAME) }; -#define PLT_ENTRY(...) -#define PLT_ELEM(...) __VA_ARGS__, -#define ENTRY_RELOC(...) -#define ELEM_RELOC(...) - -#include "arc-plt.def" - -#undef PLT_TYPE_START -#undef PLT_TYPE_END -#undef PLT_ENTRY -#undef PLT_ELEM -#undef ENTRY_RELOC -#undef ELEM_RELOC - -#define PLT_TYPE_START(NAME) \ - const struct plt_reloc NAME##_plt_elem_relocs[] = { -#define PLT_TYPE_END(NAME) \ - {0, 0, 0, LAST_RELOC, 0} \ - }; -#define PLT_ENTRY(...) -#define PLT_ELEM(...) -#define ENTRY_RELOC(...) -#define ELEM_RELOC(...) { __VA_ARGS__ }, - -#include "arc-plt.def" - -#undef PLT_TYPE_START -#undef PLT_TYPE_END -#undef PLT_ENTRY -#undef PLT_ELEM -#undef ENTRY_RELOC -#undef ELEM_RELOC - - -#define PLT_TYPE_START(NAME) \ - { \ - .entry = &NAME##_plt_entry, \ - .entry_size = sizeof (NAME##_plt_entry), \ - .elem = &NAME##_plt_elem, \ - .elem_size = sizeof (NAME##_plt_elem), \ - .entry_relocs = NAME##_plt_entry_relocs, \ - .elem_relocs = NAME##_plt_elem_relocs -#define PLT_TYPE_END(NAME) }, +#define PLT_TYPE_END(NAME) #define PLT_ENTRY(...) #define PLT_ELEM(...) #define ENTRY_RELOC(...) #define ELEM_RELOC(...) -const struct plt_version_t plt_versions[PLT_MAX] = { #include "arc-plt.def" -}; #undef PLT_TYPE_START #undef PLT_TYPE_END #undef PLT_ENTRY @@ -190,5 +116,6 @@ const struct plt_version_t plt_versions[PLT_MAX] = { #undef ENTRY_RELOC #undef ELEM_RELOC +extern struct plt_version_t plt_versions[PLT_MAX]; -#endif /* ARC_PLT_H */ +#endif diff --git a/bfd/archures.c b/bfd/archures.c index b59979e60ac..b0c1e3e70bd 100644 --- a/bfd/archures.c +++ b/bfd/archures.c @@ -361,6 +361,9 @@ DESCRIPTION .#define bfd_mach_arc_arc601 4 .#define bfd_mach_arc_arc700 3 .#define bfd_mach_arc_arcv2 5 +. bfd_arch_arc64, {* ARCv3 32/64 Cores. *} +.#define bfd_mach_arcv3_64 1 +.#define bfd_mach_arcv3_32 2 . bfd_arch_m32c, {* Renesas M16C/M32C. *} .#define bfd_mach_m16c 0x75 .#define bfd_mach_m32c 0x78 @@ -632,6 +635,7 @@ extern const bfd_arch_info_type bfd_aarch64_arch; extern const bfd_arch_info_type bfd_alpha_arch; extern const bfd_arch_info_type bfd_amdgcn_arch; extern const bfd_arch_info_type bfd_arc_arch; +extern const bfd_arch_info_type bfd_arc64_arch; extern const bfd_arch_info_type bfd_arm_arch; extern const bfd_arch_info_type bfd_avr_arch; extern const bfd_arch_info_type bfd_bfin_arch; @@ -721,6 +725,7 @@ static const bfd_arch_info_type * const bfd_archures_list[] = &bfd_alpha_arch, &bfd_amdgcn_arch, &bfd_arc_arch, + &bfd_arc64_arch, &bfd_arm_arch, &bfd_avr_arch, &bfd_bfin_arch, diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index 1c4f75ae244..991344adf5c 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -1617,6 +1617,9 @@ enum bfd_architecture #define bfd_mach_arc_arc601 4 #define bfd_mach_arc_arc700 3 #define bfd_mach_arc_arcv2 5 + bfd_arch_arc64, /* ARCv3 32/64 Cores. */ +#define bfd_mach_arcv3_64 1 +#define bfd_mach_arcv3_32 2 bfd_arch_m32c, /* Renesas M16C/M32C. */ #define bfd_mach_m16c 0x75 #define bfd_mach_m32c 0x78 @@ -4383,6 +4386,7 @@ pc-relative or some form of GOT-indirect relocation. */ BFD_RELOC_ARC_16, BFD_RELOC_ARC_24, BFD_RELOC_ARC_32, + BFD_RELOC_ARC_64, BFD_RELOC_ARC_N8, BFD_RELOC_ARC_N16, BFD_RELOC_ARC_N24, @@ -4447,6 +4451,27 @@ pc-relative or some form of GOT-indirect relocation. */ BFD_RELOC_ARC_S21H_PCREL_PLT, BFD_RELOC_ARC_NPS_CMEM16, BFD_RELOC_ARC_JLI_SECTOFF, + BFD_RELOC_ARC_S7H_PCREL, + BFD_RELOC_ARC_S8H_PCREL, + BFD_RELOC_ARC_S9H_PCREL, + BFD_RELOC_ARC_S10H_PCREL, + BFD_RELOC_ARC_S13H_PCREL, + BFD_RELOC_ARC_ALIGN, + BFD_RELOC_ARC_ADD8, + BFD_RELOC_ARC_ADD16, + BFD_RELOC_ARC_SUB8, + BFD_RELOC_ARC_SUB16, + BFD_RELOC_ARC_SUB32, + BFD_RELOC_ARC_LO32, + BFD_RELOC_ARC_HI32, + BFD_RELOC_ARC_LO32_ME, + BFD_RELOC_ARC_HI32_ME, + BFD_RELOC_ARC_N64, + BFD_RELOC_ARC_SDA_LDST3, + BFD_RELOC_ARC_NLO32, + BFD_RELOC_ARC_NLO32_ME, + BFD_RELOC_ARC_PCLO32_ME_2, + BFD_RELOC_ARC_PLT34, /* ADI Blackfin 16 bit immediate absolute reloc. */ BFD_RELOC_BFIN_16_IMM, diff --git a/bfd/config.bfd b/bfd/config.bfd index 08129e6a8cb..861a520a752 100644 --- a/bfd/config.bfd +++ b/bfd/config.bfd @@ -180,7 +180,8 @@ case "${targ_cpu}" in aarch64*) targ_archs="bfd_aarch64_arch bfd_arm_arch";; alpha*) targ_archs=bfd_alpha_arch ;; am33_2.0*) targ_archs=bfd_mn10300_arch ;; -arc*) targ_archs=bfd_arc_arch ;; +arc|arceb) targ_archs=bfd_arc_arch ;; +arc64|arc32) targ_archs=bfd_arc64_arch ;; arm*) targ_archs=bfd_arm_arch ;; amdgcn*) targ_archs=bfd_amdgcn_arch ;; bfin*) targ_archs=bfd_bfin_arch ;; @@ -353,16 +354,29 @@ case "${targ}" in targ_defvec=am33_elf32_linux_vec ;; - arc*eb-*-elf* | arc*eb-*-linux*) + arceb-*-elf* | arceb-*-linux*) targ_defvec=arc_elf32_be_vec targ_selvecs=arc_elf32_le_vec ;; - arc*-*-elf* | arc*-*-linux*) + arc-*-elf* | arc-*-linux*) targ_defvec=arc_elf32_le_vec targ_selvecs=arc_elf32_be_vec ;; +#ifdef BFD64 + arc64-*-*) + targ_defvec=arc64_elf64_le_vec + targ_selvecs=arc64_elf32_le_vec + want64=true + ;; + arc32-*-*) + targ_defvec=arc64_elf32_le_vec + targ_selvecs=arc64_elf64_le_vec + want64=true + ;; +#endif + arm-*-darwin*) targ_defvec=arm_mach_o_vec targ_selvecs="mach_o_le_vec mach_o_be_vec mach_o_fat_vec" diff --git a/bfd/configure b/bfd/configure index f0a07ff675f..f30ac5b25f4 100755 --- a/bfd/configure +++ b/bfd/configure @@ -13883,8 +13883,10 @@ do aout0_be_vec) tb="$tb aout0.lo aout32.lo" ;; aout64_vec) tb="$tb demo64.lo aout64.lo"; target_size=64 ;; aout_vec) tb="$tb host-aout.lo aout32.lo" ;; - arc_elf32_be_vec) tb="$tb elf32-arc.lo elf32.lo $elf" ;; - arc_elf32_le_vec) tb="$tb elf32-arc.lo elf32.lo $elf" ;; + arc_elf32_be_vec) tb="$tb arc-plt.lo elf32-arc.lo elf32.lo $elf" ;; + arc_elf32_le_vec) tb="$tb arc-plt.lo elf32-arc.lo elf32.lo $elf" ;; + arc64_elf64_le_vec) tb="$tb arc-plt.lo elf64-arc64.lo elf64.lo $elf"; target_size=64 ;; + arc64_elf32_le_vec) tb="$tb arc-plt.lo elf32-arc64.lo elf32.lo $elf"; target_size=64 ;; arm_elf32_be_vec) tb="$tb elf32-arm.lo elf32.lo elf-nacl.lo elf-vxworks.lo $elf" ;; arm_elf32_le_vec) tb="$tb elf32-arm.lo elf32.lo elf-nacl.lo elf-vxworks.lo $elf" ;; arm_elf32_fdpic_be_vec) tb="$tb elf32-arm.lo elf32.lo elf-nacl.lo elf-vxworks.lo $elf" ;; diff --git a/bfd/configure.ac b/bfd/configure.ac index d1e7e3a4bf3..64334743ce3 100644 --- a/bfd/configure.ac +++ b/bfd/configure.ac @@ -419,8 +419,10 @@ do aout0_be_vec) tb="$tb aout0.lo aout32.lo" ;; aout64_vec) tb="$tb demo64.lo aout64.lo"; target_size=64 ;; aout_vec) tb="$tb host-aout.lo aout32.lo" ;; - arc_elf32_be_vec) tb="$tb elf32-arc.lo elf32.lo $elf" ;; - arc_elf32_le_vec) tb="$tb elf32-arc.lo elf32.lo $elf" ;; + arc_elf32_be_vec) tb="$tb arc-plt.lo elf32-arc.lo elf32.lo $elf" ;; + arc_elf32_le_vec) tb="$tb arc-plt.lo elf32-arc.lo elf32.lo $elf" ;; + arc64_elf64_le_vec) tb="$tb arc-plt.lo elf64-arc64.lo elf64.lo $elf"; target_size=64 ;; + arc64_elf32_le_vec) tb="$tb arc-plt.lo elf32-arc64.lo elf32.lo $elf"; target_size=64 ;; arm_elf32_be_vec) tb="$tb elf32-arm.lo elf32.lo elf-nacl.lo elf-vxworks.lo $elf" ;; arm_elf32_le_vec) tb="$tb elf32-arm.lo elf32.lo elf-nacl.lo elf-vxworks.lo $elf" ;; arm_elf32_fdpic_be_vec) tb="$tb elf32-arm.lo elf32.lo elf-nacl.lo elf-vxworks.lo $elf" ;; diff --git a/bfd/cpu-arc.c b/bfd/cpu-arc.c index 390a69dc2a7..a5e0f80a0cc 100644 --- a/bfd/cpu-arc.c +++ b/bfd/cpu-arc.c @@ -26,51 +26,53 @@ static const bfd_arch_info_type * arc_compatible (const bfd_arch_info_type *a, const bfd_arch_info_type *b); -#define ARC(mach, print_name, default_p, next) \ - { \ - 32, /* Bits in a word. */ \ - 32, /* Bits in an address. */ \ - 8, /* Bits in a byte. */ \ - bfd_arch_arc, \ - mach, \ - "arc", \ - print_name, \ - 4, /* Section alignment power. */ \ - default_p, \ - arc_compatible, \ - bfd_default_scan, \ - bfd_arch_default_fill, \ - next, \ - 0 /* Maximum offset of a reloc from the start of an insn. */ \ - } +#define ARC(BITS_WORD, BITS_ADDR, MACH, PRINT_NAME, DEFAULT_P, NEXT) \ +{ \ + BITS_WORD, /* 32 bits in a word. */ \ + BITS_ADDR, /* 32 bits in an address. */ \ + 8, /* 8 bits in a byte. */ \ + bfd_arch_arc, \ + MACH, \ + "arc", \ + PRINT_NAME, \ + 4, /* section alignment power. */ \ + DEFAULT_P, \ + arc_compatible, \ + bfd_default_scan, \ + bfd_arch_default_fill, \ + NEXT, \ + 0 /* Maximum offset of a reloc from the start of an insn. */ \ +} static const bfd_arch_info_type arch_info_struct[] = { - ARC (bfd_mach_arc_arc600, "A6" , false, &arch_info_struct[1]), - ARC (bfd_mach_arc_arc601, "ARC601", false, &arch_info_struct[2]), - ARC (bfd_mach_arc_arc700, "ARC700", false, &arch_info_struct[3]), - ARC (bfd_mach_arc_arc700, "A7", false, &arch_info_struct[4]), - ARC (bfd_mach_arc_arcv2, "ARCv2", false, &arch_info_struct[5]), - ARC (bfd_mach_arc_arcv2, "EM", false, &arch_info_struct[6]), - ARC (bfd_mach_arc_arcv2, "HS", false, NULL), + ARC (32, 32, bfd_mach_arc_arc600, "A6" , false, &arch_info_struct[1]), + ARC (32, 32, bfd_mach_arc_arc601, "ARC601", false, &arch_info_struct[2]), + ARC (32, 32, bfd_mach_arc_arc700, "ARC700", false, &arch_info_struct[3]), + ARC (32, 32, bfd_mach_arc_arc700, "A7", false, &arch_info_struct[4]), + ARC (32, 32, bfd_mach_arc_arcv2, "ARCv2", false, &arch_info_struct[5]), + ARC (32, 32, bfd_mach_arc_arcv2, "EM", false, &arch_info_struct[6]), + ARC (32, 32, bfd_mach_arc_arcv2, "HS", false, NULL), }; const bfd_arch_info_type bfd_arc_arch = - ARC (bfd_mach_arc_arc600, "ARC600", true, &arch_info_struct[0]); - -/* ARC-specific "compatible" function. The general rule is that if A and B are - compatible, then this function should return architecture that is more - "feature-rich", that is, can run both A and B. ARCv2, EM and HS all has - same mach number, so bfd_default_compatible assumes they are the same, and - returns an A. That causes issues with GDB, because GDB assumes that if - machines are compatible, then "compatible ()" always returns same machine - regardless of argument order. As a result GDB gets confused because, for - example, compatible (ARCv2, EM) returns ARCv2, but compatible (EM, ARCv2) - returns EM, hence GDB is not sure if they are compatible and prints a - warning. */ + ARC (32, 32, bfd_mach_arc_arc600, "ARC600", true, &arch_info_struct[0]); + +/* ARC-specific "compatible" function. The general rule is that if A + and B are compatible, then this function should return architecture + that is more "feature-rich", that is, can run both A and B. ARCv2, + EM and HS all has same mach number, so bfd_default_compatible + assumes they are the same, and returns an A. That causes issues + with GDB, because GDB assumes that if machines are compatible, then + "compatible ()" always returns same machine regardless of argument + order. As a result GDB gets confused because, for example, + compatible (ARCv2, EM) returns ARCv2, but compatible (EM, ARCv2) + returns EM, hence GDB is not sure if they are compatible and prints + a warning. */ static const bfd_arch_info_type * -arc_compatible (const bfd_arch_info_type *a, const bfd_arch_info_type *b) +arc_compatible (const bfd_arch_info_type *a ATTRIBUTE_UNUSED, + const bfd_arch_info_type *b ATTRIBUTE_UNUSED) { const bfd_arch_info_type * const em = &arch_info_struct[5]; const bfd_arch_info_type * const hs = &arch_info_struct[6]; @@ -84,9 +86,6 @@ arc_compatible (const bfd_arch_info_type *a, const bfd_arch_info_type *b) if (a->arch != b->arch) return NULL; - if (a->bits_per_word != b->bits_per_word) - return NULL; - /* ARCv2|EM and EM. */ if ((a->mach == bfd_mach_arc_arcv2 && b == em) || (b->mach == bfd_mach_arc_arcv2 && a == em)) diff --git a/bfd/cpu-arc64.c b/bfd/cpu-arc64.c new file mode 100644 index 00000000000..a1c3a2e23b9 --- /dev/null +++ b/bfd/cpu-arc64.c @@ -0,0 +1,75 @@ +/* BFD support for the ARC64 processor + Copyright (C) 2023 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "sysdep.h" +#include "bfd.h" +#include "libbfd.h" + +/* ARC64-specific "compatible" function. The general rule is that if + A and B are compatible, then this function should return + architecture that is more "feature-rich", that is, can run both A + and B. */ + +static const bfd_arch_info_type * +compatible (const bfd_arch_info_type *a ATTRIBUTE_UNUSED, + const bfd_arch_info_type *b ATTRIBUTE_UNUSED) +{ + /* If a & b are for different architecture we can do nothing. */ + if (a->arch != b->arch) + return NULL; + + /* If a & b are for the same machine then all is well. */ + if (a->mach == b->mach) + return a; + + /* Otherwise if either a or b is the 'default' machine + then it can be polymorphed into the other. */ + if (a->the_default) + return b; + + if (b->the_default) + return a; + + return NULL; +} + +#define ARC64(WORDSIZE, MACH, PRINT_NAME, DEFAULT_P, NEXT) \ + { \ + WORDSIZE, /* 64/32 bits in a word. */ \ + WORDSIZE, /* 64/32 bits in an address. */ \ + 8, /* 8 bits in a byte. */ \ + bfd_arch_arc64, \ + MACH, \ + "arc64", \ + PRINT_NAME, \ + 4, /* section alignment power. */ \ + DEFAULT_P, \ + compatible, \ + bfd_default_scan, \ + bfd_arch_default_fill, \ + NEXT, \ + 0 /* Maximum offset of a reloc from the start of an insn. */ \ + } + +static const bfd_arch_info_type bfd_arc64_arch_32 = + ARC64 (32, bfd_mach_arcv3_32, "arc64:32", false, NULL); + +const bfd_arch_info_type bfd_arc64_arch = + ARC64 (64, bfd_mach_arcv3_64, "arc64:64", true, &bfd_arc64_arch_32); diff --git a/bfd/elf32-arc.c b/bfd/elfnn-arc.c similarity index 68% rename from bfd/elf32-arc.c rename to bfd/elfnn-arc.c index ac9970545c3..04fce7eb6e0 100644 --- a/bfd/elf32-arc.c +++ b/bfd/elfnn-arc.c @@ -27,13 +27,43 @@ #include "libiberty.h" #include "opcode/arc-func.h" #include "opcode/arc.h" + +#define RELA_SIZE sizeof(ElfNN_External_Rela) + #include "arc-plt.h" -#define FEATURE_LIST_NAME bfd_feature_list -#define CONFLICT_LIST bfd_conflict_list +#define FEATURE_LIST_NAME bfdNN_feature_list +#define CONFLICT_LIST bfdNN_conflict_list #include "opcode/arc-attrs.h" -/* #define ARC_ENABLE_DEBUG 1 */ +/* Possible ARC architectures. */ +#define ARC 0 +#define ARC32 1 +#define ARC64 2 + +/* Arc's architecture size. */ +#define ARCH_SIZE NN + +/* Arc's architecture type. */ +#define ARCH_TYPE ARCAA + +/* Arc's BFD backend. There are two different backends, one for + ARCv1/v2 and the second for the ARCv3/64/32. They are + incompatible. */ +#define ARC_BFD_ARCH bfd_arch_arcAA + +/* The name of the dynamic interpreter. This is put in the .interp + section. */ + +#define ELF64_DYNAMIC_INTERPRETER "/lib/ld.so.1" +#define ELF32_DYNAMIC_INTERPRETER "/sbin/ld-uClibc.so" + +#define LOG_FILE_ALIGN (ARCH_SIZE == 32 ? 2 : 3) + +/* Do not enable this unless you know what you are doing. + Code under this macro is not safe for production. + #define ARC_ENABLE_DEBUG 1 */ + #ifdef ARC_ENABLE_DEBUG static const char * name_for_global_symbol (struct elf_link_hash_entry *h) @@ -48,26 +78,27 @@ name_for_global_symbol (struct elf_link_hash_entry *h) #define ARC_DEBUG(...) #endif - #define ADD_RELA(BFD, SECTION, OFFSET, SYM_IDX, TYPE, ADDEND) \ { \ struct elf_link_hash_table *_htab = elf_hash_table (info); \ Elf_Internal_Rela _rel; \ bfd_byte * _loc; \ + const struct elf_backend_data *bed; \ + bed = get_elf_backend_data (BFD); \ \ if (_htab->dynamic_sections_created) \ { \ BFD_ASSERT (_htab->srel##SECTION &&_htab->srel##SECTION->contents); \ _loc = _htab->srel##SECTION->contents \ + ((_htab->srel##SECTION->reloc_count) \ - * sizeof (Elf32_External_Rela)); \ + * sizeof (ElfNN_External_Rela)); \ _htab->srel##SECTION->reloc_count++; \ _rel.r_addend = ADDEND; \ _rel.r_offset = (_htab->s##SECTION)->output_section->vma \ + (_htab->s##SECTION)->output_offset + OFFSET; \ BFD_ASSERT ((long) SYM_IDX != -1); \ - _rel.r_info = ELF32_R_INFO (SYM_IDX, TYPE); \ - bfd_elf32_swap_reloca_out (BFD, &_rel, _loc); \ + _rel.r_info = ELFNN_R_INFO (SYM_IDX, TYPE); \ + bed->s->swap_reloca_out (BFD, &_rel, _loc); \ } \ } @@ -195,9 +226,11 @@ struct elf_arc_link_hash_entry #define arc_bfd_get_8(A,B,C) bfd_get_8(A,B) #define arc_bfd_get_16(A,B,C) bfd_get_16(A,B) #define arc_bfd_get_32(A,B,C) bfd_get_32(A,B) +#define arc_bfd_get_64(A,B,C) bfd_get_64(A,B) #define arc_bfd_put_8(A,B,C,D) bfd_put_8(A,B,C) #define arc_bfd_put_16(A,B,C,D) bfd_put_16(A,B,C) #define arc_bfd_put_32(A,B,C,D) bfd_put_32(A,B,C) +#define arc_bfd_put_64(A,B,C,D) bfd_put_64(A,B,C) static bfd_reloc_status_type @@ -230,10 +263,10 @@ arc_elf_reloc (bfd *abfd ATTRIBUTE_UNUSED, TYPE = VALUE, enum howto_list -{ + { #include "elf/arc-reloc.def" - HOWTO_LIST_LAST -}; + HOWTO_LIST_LAST + }; #undef ARC_RELOC_HOWTO @@ -243,7 +276,7 @@ enum howto_list "R_" #TYPE, false, 0, 0, false), static struct reloc_howto_struct elf_arc_howto_table[] = -{ + { #include "elf/arc-reloc.def" /* Example of what is generated by the preprocessor. Currently kept as an example. @@ -282,17 +315,6 @@ arc_elf_howto_init (void) } #undef ARC_RELOC_HOWTO - -#define ARC_RELOC_HOWTO(TYPE, VALUE, SIZE, BITSIZE, RELOC_FUNCTION, OVERFLOW, FORMULA) \ - [TYPE] = VALUE, - -const int howto_table_lookup[] = -{ -#include "elf/arc-reloc.def" -}; - -#undef ARC_RELOC_HOWTO - static reloc_howto_type * arc_elf_howto (unsigned int r_type) { @@ -327,7 +349,7 @@ elf_arc_link_hash_newfunc (struct bfd_hash_entry *entry, subclass. */ if (ret == NULL) ret = (struct elf_arc_link_hash_entry *) - bfd_hash_allocate (table, sizeof (struct elf_arc_link_hash_entry)); + bfd_hash_allocate (table, sizeof (struct elf_arc_link_hash_entry)); if (ret == NULL) return (struct bfd_hash_entry *) ret; @@ -356,8 +378,9 @@ static struct bfd_link_hash_table * arc_elf_link_hash_table_create (bfd *abfd) { struct elf_arc_link_hash_table *ret; + bfd_size_type amt = sizeof (struct elf_arc_link_hash_table); - ret = (struct elf_arc_link_hash_table *) bfd_zmalloc (sizeof (*ret)); + ret = (struct elf_arc_link_hash_table *) bfd_zmalloc (amt); if (ret == NULL) return NULL; @@ -379,24 +402,27 @@ arc_elf_link_hash_table_create (bfd *abfd) { BFD_RELOC_##TYPE, R_##TYPE }, static const struct arc_reloc_map arc_reloc_map[] = -{ + { #include "elf/arc-reloc.def" - {BFD_RELOC_NONE, R_ARC_NONE}, - {BFD_RELOC_8, R_ARC_8}, - {BFD_RELOC_16, R_ARC_16}, - {BFD_RELOC_24, R_ARC_24}, - {BFD_RELOC_32, R_ARC_32}, -}; + {BFD_RELOC_NONE, R_ARC_NONE}, + {BFD_RELOC_8, R_ARC_8}, + {BFD_RELOC_16, R_ARC_16}, + {BFD_RELOC_24, R_ARC_24}, + {BFD_RELOC_32, R_ARC_32}, + {BFD_RELOC_64, R_ARC_64}, + }; #undef ARC_RELOC_HOWTO -typedef ATTRIBUTE_UNUSED unsigned (*replace_func) (unsigned, int ATTRIBUTE_UNUSED); +typedef ATTRIBUTE_UNUSED +bfd_vma (*replace_func) (bfd_vma, bfd_vma ATTRIBUTE_UNUSED); -#define ARC_RELOC_HOWTO(TYPE, VALUE, SIZE, BITSIZE, RELOC_FUNCTION, OVERFLOW, FORMULA) \ - case TYPE: \ - func = RELOC_FUNCTION; \ - break; +#define ARC_RELOC_HOWTO(TYPE, VALUE, SIZE, BITSIZE, \ + RELOC_FUNCTION, OVERFLOW, FORMULA) \ + case TYPE: \ + func = (void *) RELOC_FUNCTION; \ + break; static replace_func get_replace_function (bfd *abfd, unsigned int r_type) @@ -405,7 +431,7 @@ get_replace_function (bfd *abfd, unsigned int r_type) switch (r_type) { - #include "elf/arc-reloc.def" +#include "elf/arc-reloc.def" } if (func == replace_bits24 && bfd_big_endian (abfd)) @@ -416,7 +442,7 @@ get_replace_function (bfd *abfd, unsigned int r_type) #undef ARC_RELOC_HOWTO static reloc_howto_type * -arc_elf32_bfd_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED, +arc_elfNN_bfd_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED, bfd_reloc_code_real_type code) { unsigned int i; @@ -503,7 +529,7 @@ arc_elf_copy_private_bfd_data (bfd *ibfd, bfd *obfd) } static reloc_howto_type * -bfd_elf32_bfd_reloc_name_lookup (bfd * abfd ATTRIBUTE_UNUSED, +bfd_elfNN_bfd_reloc_name_lookup (bfd * abfd ATTRIBUTE_UNUSED, const char *r_name) { unsigned int i; @@ -525,7 +551,7 @@ arc_info_to_howto_rel (bfd * abfd, { unsigned int r_type; - r_type = ELF32_R_TYPE (dst->r_info); + r_type = ELFNN_R_TYPE (dst->r_info); if (r_type >= (unsigned int) R_ARC_max) { /* xgettext:c-format */ @@ -536,7 +562,7 @@ arc_info_to_howto_rel (bfd * abfd, } cache_ptr->howto = arc_elf_howto (r_type); - return true; + return cache_ptr->howto != NULL; } /* Extract CPU features from an NTBS. */ @@ -549,14 +575,14 @@ arc_extract_features (const char *p) if (!p) return 0; - for (i = 0; i < ARRAY_SIZE (bfd_feature_list); i++) + for (i = 0; i < ARRAY_SIZE (FEATURE_LIST_NAME); i++) { - char *t = strstr (p, bfd_feature_list[i].attr); - unsigned l = strlen (bfd_feature_list[i].attr); + char *t = strstr (p, FEATURE_LIST_NAME[i].attr); + unsigned l = strlen (FEATURE_LIST_NAME[i].attr); if ((t != NULL) && (t[l] == ',' || t[l] == '\0')) - r |= bfd_feature_list[i].feature; + r |= FEATURE_LIST_NAME[i].feature; } return r; @@ -629,20 +655,21 @@ arc_elf_merge_attributes (bfd *ibfd, struct bfd_link_info *info) case Tag_ARC_PCS_config: if (out_attr[i].i == 0) out_attr[i].i = in_attr[i].i; - else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i) + else if ((in_attr[i].i & 0xff) != 0 + && ((out_attr[i].i & 0xff) != (in_attr[i].i & 0xff))) { const char *tagval[] = { "Absent", "Bare-metal/mwdt", - "Bare-metal/newlib", "Linux/uclibc", - "Linux/glibc" }; - BFD_ASSERT (in_attr[i].i < 5); - BFD_ASSERT (out_attr[i].i < 5); + "Bare-metal/newlib", "Linux/uclibc", + "Linux/glibc" }; + BFD_ASSERT ((in_attr[i].i & 0xff) < 5); + BFD_ASSERT ((out_attr[i].i & 0xff) < 5); /* It's sometimes ok to mix different configs, so this is only a warning. */ _bfd_error_handler (_("warning: %pB: conflicting platform configuration " "%s with %s"), ibfd, - tagval[in_attr[i].i], - tagval[out_attr[i].i]); + tagval[in_attr[i].i & 0xff], + tagval[out_attr[i].i & 0xff]); } break; @@ -653,7 +680,7 @@ arc_elf_merge_attributes (bfd *ibfd, struct bfd_link_info *info) && ((out_attr[i].i + in_attr[i].i) < 6)) { const char *tagval[] = { "Absent", "ARC6xx", "ARC7xx", - "ARCEM", "ARCHS" }; + "ARCEM", "ARCHS" }; BFD_ASSERT (in_attr[i].i < 5); BFD_ASSERT (out_attr[i].i < 5); /* We cannot mix code for different CPUs. */ @@ -690,33 +717,33 @@ arc_elf_merge_attributes (bfd *ibfd, struct bfd_link_info *info) /* First, check if a feature is compatible with the output object chosen CPU. */ - for (j = 0; j < ARRAY_SIZE (bfd_feature_list); j++) - if (((in_feature | out_feature) & bfd_feature_list[j].feature) - && (!(cpu_out & bfd_feature_list[j].cpus))) + for (j = 0; j < ARRAY_SIZE (FEATURE_LIST_NAME); j++) + if (((in_feature | out_feature) & FEATURE_LIST_NAME[j].feature) + && (!(cpu_out & FEATURE_LIST_NAME[j].cpus))) { _bfd_error_handler (_("error: %pB: unable to merge ISA extension attributes " "%s"), - obfd, bfd_feature_list[j].name); + obfd, FEATURE_LIST_NAME[j].name); result = false; break; } /* Second, if we have compatible features with the chosen CPU, check if they are compatible among them. */ - for (j = 0; j < ARRAY_SIZE (bfd_conflict_list); j++) - if (((in_feature | out_feature) & bfd_conflict_list[j]) - == bfd_conflict_list[j]) + for (j = 0; j < ARRAY_SIZE (CONFLICT_LIST); j++) + if (((in_feature | out_feature) & CONFLICT_LIST[j]) + == CONFLICT_LIST[j]) { unsigned k; - for (k = 0; k < ARRAY_SIZE (bfd_feature_list); k++) + for (k = 0; k < ARRAY_SIZE (FEATURE_LIST_NAME); k++) { - if (in_feature & bfd_feature_list[k].feature - & bfd_conflict_list[j]) - p1 = (char *) bfd_feature_list[k].name; - if (out_feature & bfd_feature_list[k].feature - & bfd_conflict_list[j]) - p2 = (char *) bfd_feature_list[k].name; + if (in_feature & FEATURE_LIST_NAME[k].feature + & CONFLICT_LIST[j]) + p1 = (char *) FEATURE_LIST_NAME[k].name; + if (out_feature & FEATURE_LIST_NAME[k].feature + & CONFLICT_LIST[j]) + p2 = (char *) FEATURE_LIST_NAME[k].name; } _bfd_error_handler (_("error: %pB: conflicting ISA extension attributes " @@ -728,9 +755,9 @@ arc_elf_merge_attributes (bfd *ibfd, struct bfd_link_info *info) /* Everithing is alright. */ out_feature |= in_feature; p1 = NULL; - for (j = 0; j < ARRAY_SIZE (bfd_feature_list); j++) - if (out_feature & bfd_feature_list[j].feature) - p1 = arc_stralloc (p1, bfd_feature_list[j].attr); + for (j = 0; j < ARRAY_SIZE (FEATURE_LIST_NAME); j++) + if (out_feature & FEATURE_LIST_NAME[j].feature) + p1 = arc_stralloc (p1, FEATURE_LIST_NAME[j].attr); if (p1) out_attr[Tag_ARC_ISA_config].s = _bfd_elf_attr_strdup (obfd, p1); @@ -784,7 +811,7 @@ arc_elf_merge_attributes (bfd *ibfd, struct bfd_link_info *info) if (out_attr[i].i == 0) out_attr[i].i = in_attr[i].i; else if (out_attr[i].i != 0 && in_attr[i].i != 0 - && out_attr[i].i != in_attr[i].i) + && out_attr[i].i != in_attr[i].i) { _bfd_error_handler (_("error: %pB: conflicting attributes %s: %s with %s"), @@ -811,7 +838,7 @@ arc_elf_merge_attributes (bfd *ibfd, struct bfd_link_info *info) if (out_attr[i].i == 0) out_attr[i].i = in_attr[i].i; else if (out_attr[i].i != 0 && in_attr[i].i != 0 - && out_attr[i].i != in_attr[i].i) + && out_attr[i].i != in_attr[i].i) { _bfd_error_handler (_("error: %pB: conflicting attributes %s"), @@ -865,10 +892,19 @@ arc_elf_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info) flagword in_flags; asection *sec; - /* Check if we have the same endianess. */ + /* Check if we have the same endianess. */ if (! _bfd_generic_verify_endian_match (ibfd, info)) return false; + if (strcmp (bfd_get_target (ibfd), bfd_get_target (obfd)) != 0) + { + _bfd_error_handler + (_("%pB: ABI is incompatible with the selected emulation:\n" + " target emulation '%s' does not match '%s'"), + ibfd, bfd_get_target (ibfd), bfd_get_target (obfd)); + return false; + } + if (bfd_get_flavour (ibfd) != bfd_target_elf_flavour || bfd_get_flavour (obfd) != bfd_target_elf_flavour) return true; @@ -956,7 +992,7 @@ arc_elf_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info) if (bfd_get_mach (obfd) < bfd_get_mach (ibfd)) { - return bfd_set_arch_mach (obfd, bfd_arch_arc, bfd_get_mach (ibfd)); + return bfd_set_arch_mach (obfd, ARC_BFD_ARCH, bfd_get_mach (ibfd)); } return true; @@ -964,7 +1000,7 @@ arc_elf_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info) /* Return a best guess for the machine number based on the attributes. */ -static unsigned int +static ATTRIBUTE_UNUSED unsigned int bfd_arc_get_mach_from_attributes (bfd * abfd) { int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ARC_CPU_base); @@ -986,19 +1022,24 @@ bfd_arc_get_mach_from_attributes (bfd * abfd) ? bfd_mach_arc_arc700 : bfd_mach_arc_arcv2; } -/* Set the right machine number for an ARC ELF file. */ +/* Set the right machine number for an ARC ELF file. Make sure this + is initialised, or you'll have the potential of passing + garbage---or misleading values---into the call to + bfd_default_set_arch_mach (). */ + static bool arc_elf_object_p (bfd * abfd) { - /* Make sure this is initialised, or you'll have the potential of passing - garbage---or misleading values---into the call to - bfd_default_set_arch_mach (). */ - unsigned int mach = bfd_mach_arc_arc700; - unsigned long arch = elf_elfheader (abfd)->e_flags & EF_ARC_MACH_MSK; - unsigned e_machine = elf_elfheader (abfd)->e_machine; + unsigned int mach; + unsigned long ATTRIBUTE_UNUSED arch = elf_elfheader (abfd)->e_flags + & EF_ARC_MACH_MSK; + unsigned e_machine = elf_elfheader (abfd)->e_machine; - if (e_machine == EM_ARC_COMPACT || e_machine == EM_ARC_COMPACT2) + switch (e_machine) { +#if (ARCH_TYPE == ARC) && (ARCH_SIZE == 32) + case EM_ARC_COMPACT: + case EM_ARC_COMPACT2: switch (arch) { case E_ARC_MACH_ARC600: @@ -1018,24 +1059,29 @@ arc_elf_object_p (bfd * abfd) mach = bfd_arc_get_mach_from_attributes (abfd); break; } - } - else - { - if (e_machine == EM_ARC) - { - _bfd_error_handler - (_("error: the ARC4 architecture is no longer supported")); - return false; - } - else - { - _bfd_error_handler - (_("warning: unset or old architecture flags; " - "use default machine")); - } + break; + + case EM_ARC: + _bfd_error_handler + (_("error: the ARC4 architecture is no longer supported")); + return false; + +#else /* New ARCv3 arches. */ + case EM_ARC_COMPACT3_64: + mach = bfd_mach_arcv3_64; + break; + + case EM_ARC_COMPACT3: + mach = bfd_mach_arcv3_32; + break; +#endif + + default: + _bfd_error_handler (_("error: unset or old architecture flags.")); + return false; } - return bfd_default_set_arch_mach (abfd, bfd_arch_arc, mach); + return bfd_default_set_arch_mach (abfd, ARC_BFD_ARCH, mach); } /* The final processing done just before writing out an ARC ELF object file. @@ -1049,6 +1095,7 @@ arc_elf_final_write_processing (bfd *abfd) Tag_ARC_ABI_osver); flagword e_flags = elf_elfheader (abfd)->e_flags & ~EF_ARC_OSABI_MSK; +#if (ARCH_TYPE == ARC) && (ARCH_SIZE == 32) switch (bfd_get_mach (abfd)) { case bfd_mach_arc_arcv2: @@ -1058,7 +1105,21 @@ arc_elf_final_write_processing (bfd *abfd) emf = EM_ARC_COMPACT; break; } - +#else + switch (bfd_get_mach (abfd)) + { + case bfd_mach_arcv3_64: + emf = EM_ARC_COMPACT3_64; + break; + case bfd_mach_arcv3_32: + emf = EM_ARC_COMPACT3; + break; + default: + _bfd_error_handler (_("Unknown ARC architecture")); + bfd_set_error (bfd_error_sorry); + return false; + } +#endif elf_elfheader (abfd)->e_machine = emf; /* Record whatever is the current syscall ABI version. */ @@ -1108,7 +1169,8 @@ debug_arc_reloc (struct arc_relocation_data reloc_data) ARC_DEBUG (" Input_section:\n"); if (reloc_data.input_section != NULL) { - ARC_DEBUG (" section name = %s, output_offset 0x%08x, output_section->vma = 0x%08x\n", + ARC_DEBUG (" section name = %s, output_offset 0x%08x, " \ + "output_section->vma = 0x%08x\n", reloc_data.input_section->name, (unsigned int) reloc_data.input_section->output_offset, (unsigned int) reloc_data.input_section->output_section->vma); @@ -1120,7 +1182,7 @@ debug_arc_reloc (struct arc_relocation_data reloc_data) } else { - ARC_DEBUG (" input section is NULL\n"); + ARC_DEBUG ("\tinput section is NULL\n"); } } #else @@ -1134,14 +1196,14 @@ middle_endian_convert (bfd_vma insn, bool do_it) { insn = ((insn & 0xffff0000) >> 16) - | ((insn & 0xffff) << 16); + | ((insn & 0xffff) << 16); } return insn; } -/* This function is called for relocations that are otherwise marked as NOT - requiring overflow checks. In here we perform non-standard checks of - the relocation value. */ +/* This function is called for relocations that are otherwise marked + as NOT requiring overflow checks. In here we perform non-standard + checks of the relocation value. */ static inline bfd_reloc_status_type arc_special_overflow_checks (const struct arc_relocation_data reloc_data, @@ -1189,17 +1251,19 @@ arc_special_overflow_checks (const struct arc_relocation_data reloc_data, #define ME(reloc) (reloc) -#define IS_ME(FORMULA,BFD) ((strstr (FORMULA, "ME") != NULL) \ +#define IS_ME(FORMULA,BFD) ((strstr (FORMULA, "ME") != NULL) \ && (!bfd_big_endian (BFD))) -#define S ((bfd_signed_vma) (reloc_data.sym_value \ - + (reloc_data.sym_section->output_section != NULL ? \ - (reloc_data.sym_section->output_offset \ - + reloc_data.sym_section->output_section->vma) : 0))) -#define L ((bfd_signed_vma) (reloc_data.sym_value \ - + (reloc_data.sym_section->output_section != NULL ? \ - (reloc_data.sym_section->output_offset \ - + reloc_data.sym_section->output_section->vma) : 0))) +#define S \ + ((bfd_signed_vma) (reloc_data.sym_value \ + + (reloc_data.sym_section->output_section != NULL ? \ + (reloc_data.sym_section->output_offset \ + + reloc_data.sym_section->output_section->vma) : 0))) +#define L \ + ((bfd_signed_vma) (reloc_data.sym_value \ + + (reloc_data.sym_section->output_section != NULL ? \ + (reloc_data.sym_section->output_offset \ + + reloc_data.sym_section->output_section->vma) : 0))) #define A (reloc_data.reloc_addend) #define B (0) #define G (reloc_data.got_offset_value) @@ -1207,27 +1271,30 @@ arc_special_overflow_checks (const struct arc_relocation_data reloc_data, #define GOT_BEGIN (htab->sgot->output_section->vma) #define MES (0) - /* P: relative offset to PCL The offset should be to the - current location aligned to 32 bits. */ -#define P ((bfd_signed_vma) ( \ - ( \ - (reloc_data.input_section->output_section != NULL ? \ - reloc_data.input_section->output_section->vma : 0) \ - + reloc_data.input_section->output_offset \ - + (reloc_data.reloc_offset - (bitsize >= 32 ? 4 : 0))) \ - & ~0x3)) -#define PDATA ((bfd_signed_vma) ( \ - (reloc_data.input_section->output_section->vma \ - + reloc_data.input_section->output_offset \ - + (reloc_data.reloc_offset)))) -#define SECTSTART (bfd_signed_vma) (reloc_data.sym_section->output_section->vma \ - + reloc_data.sym_section->output_offset) -#define FINAL_SECTSTART \ +/* P: relative offset to PCL The offset should be to the + current location aligned to 32 bits. */ +#define P ((bfd_signed_vma) \ + (((reloc_data.input_section->output_section != NULL ? \ + reloc_data.input_section->output_section->vma : 0) \ + + reloc_data.input_section->output_offset \ + + (reloc_data.reloc_offset - (bitsize == 32 ? 4 : \ + (bitsize == 34 ? 2 : 0)))) \ + & ~0x3)) +#define PDATA \ + ((bfd_signed_vma) ((reloc_data.input_section->output_section->vma \ + + reloc_data.input_section->output_offset \ + + (reloc_data.reloc_offset)))) +#define SECTSTART \ + (bfd_signed_vma) (reloc_data.sym_section->output_section->vma \ + + reloc_data.sym_section->output_offset) +#define FINAL_SECTSTART \ (bfd_signed_vma) (reloc_data.sym_section->output_section->vma) #define JLI (bfd_signed_vma) (reloc_data.sym_section->output_section->vma) #define _SDA_BASE_ (bfd_signed_vma) (reloc_data.sdata_begin_symbol_vma) #define TLS_REL (bfd_signed_vma)(tls_sec->output_section->vma) #define TLS_TBSS (align_power (TCB_SIZE, tls_sec->alignment_power)) +#define ICARRY insn +#define DEREFP (insn) #define none (0) @@ -1279,20 +1346,21 @@ arc_special_overflow_checks (const struct arc_relocation_data reloc_data, #define PRINT_DEBUG_RELOC_INFO_BEFORE(...) #define PRINT_DEBUG_RELOC_INFO_AFTER -#endif /* ARC_ENABLE_DEBUG */ +#endif /* ARC_ENABLE_DEBUG. */ -#define ARC_RELOC_HOWTO(TYPE, VALUE, SIZE, BITSIZE, RELOC_FUNCTION, OVERFLOW, FORMULA) \ +#define ARC_RELOC_HOWTO(TYPE, VALUE, SIZE, BITSIZE, \ + RELOC_FUNCTION, OVERFLOW, FORMULA) \ case R_##TYPE: \ - { \ - bfd_signed_vma bitsize ATTRIBUTE_UNUSED = BITSIZE; \ - relocation = FORMULA ; \ - PRINT_DEBUG_RELOC_INFO_BEFORE (#FORMULA, #TYPE); \ - insn = middle_endian_convert (insn, IS_ME (#FORMULA, abfd)); \ - insn = (* get_replace_function (abfd, TYPE)) (insn, relocation); \ - insn = middle_endian_convert (insn, IS_ME (#FORMULA, abfd)); \ - PRINT_DEBUG_RELOC_INFO_AFTER; \ - } \ - break; + { \ + bfd_signed_vma bitsize ATTRIBUTE_UNUSED = BITSIZE; \ + relocation = FORMULA ; \ + PRINT_DEBUG_RELOC_INFO_BEFORE (#FORMULA, #TYPE); \ + insn = middle_endian_convert (insn, IS_ME (#FORMULA, abfd)); \ + insn = (* get_replace_function (abfd, TYPE)) (insn, relocation); \ + insn = middle_endian_convert (insn, IS_ME (#FORMULA, abfd)); \ + PRINT_DEBUG_RELOC_INFO_AFTER; \ + } \ + break; static bfd_reloc_status_type arc_do_relocation (bfd_byte * contents, @@ -1312,6 +1380,11 @@ arc_do_relocation (bfd_byte * contents, switch (bfd_get_reloc_size (reloc_data.howto)) { + case 8: + insn = arc_bfd_get_64 (abfd, + contents + reloc_data.reloc_offset, + reloc_data.input_section); + break; case 4: insn = arc_bfd_get_32 (abfd, contents + reloc_data.reloc_offset, @@ -1374,7 +1447,7 @@ arc_do_relocation (bfd_byte * contents, DEBUG_ARC_RELOC (reloc_data); ARC_DEBUG ("Relocation value = signed -> %d, unsigned -> %u" ", hex -> (0x%08x)\n", - (int) relocation, (unsigned) relocation, (int) relocation); + (int) relocation, (unsigned) relocation, (int) relocation); return flag; } @@ -1382,6 +1455,11 @@ arc_do_relocation (bfd_byte * contents, /* Write updated instruction back to memory. */ switch (bfd_get_reloc_size (reloc_data.howto)) { + case 8: + arc_bfd_put_64 (abfd, insn, + contents + reloc_data.reloc_offset, + reloc_data.input_section); + break; case 4: arc_bfd_put_32 (abfd, insn, contents + reloc_data.reloc_offset, @@ -1417,6 +1495,7 @@ arc_do_relocation (bfd_byte * contents, #undef SECTSTART #undef JLI #undef _SDA_BASE_ +#undef ICARRY #undef none #undef ARC_RELOC_HOWTO @@ -1437,14 +1516,14 @@ arc_do_relocation (bfd_byte * contents, corresponding to the st_shndx field of each local symbol. */ static int -elf_arc_relocate_section (bfd * output_bfd, - struct bfd_link_info * info, - bfd * input_bfd, - asection * input_section, - bfd_byte * contents, - Elf_Internal_Rela * relocs, - Elf_Internal_Sym * local_syms, - asection ** local_sections) +elf_arc_relocate_section (bfd *output_bfd, + struct bfd_link_info *info, + bfd *input_bfd, + asection *input_section, + bfd_byte *contents, + Elf_Internal_Rela *relocs, + Elf_Internal_Sym *local_syms, + asection **local_sections) { Elf_Internal_Shdr * symtab_hdr; struct elf_link_hash_entry ** sym_hashes; @@ -1452,7 +1531,9 @@ elf_arc_relocate_section (bfd * output_bfd, Elf_Internal_Rela * wrel; Elf_Internal_Rela * relend; struct elf_link_hash_table * htab = elf_hash_table (info); + const struct elf_backend_data *bed; + bed = get_elf_backend_data (output_bfd); symtab_hdr = &((elf_tdata (input_bfd))->symtab_hdr); sym_hashes = elf_sym_hashes (input_bfd); @@ -1460,32 +1541,33 @@ elf_arc_relocate_section (bfd * output_bfd, relend = relocs + input_section->reloc_count; for (; rel < relend; wrel++, rel++) { - enum elf_arc_reloc_type r_type; - reloc_howto_type *howto; - unsigned long r_symndx; - struct elf_link_hash_entry *h; - Elf_Internal_Sym *sym; - asection *sec; - struct elf_link_hash_entry *h2; - const char *msg; - bool unresolved_reloc = false; + enum elf_arc_reloc_type r_type; + reloc_howto_type * howto; + unsigned long r_symndx; + struct elf_link_hash_entry * h; + Elf_Internal_Sym * sym; + asection * sec; + struct elf_link_hash_entry * h2; + const char * msg; + bool unresolved_reloc = false; + bool resolved_to_zero; struct arc_relocation_data reloc_data = - { - .reloc_offset = 0, - .reloc_addend = 0, - .got_offset_value = 0, - .sym_value = 0, - .sym_section = NULL, - .howto = NULL, - .input_section = NULL, - .sdata_begin_symbol_vma = 0, - .sdata_begin_symbol_vma_set = false, - .got_symbol_vma = 0, - .should_relocate = false - }; - - r_type = ELF32_R_TYPE (rel->r_info); + { + .reloc_offset = 0, + .reloc_addend = 0, + .got_offset_value = 0, + .sym_value = 0, + .sym_section = NULL, + .howto = NULL, + .input_section = NULL, + .sdata_begin_symbol_vma = 0, + .sdata_begin_symbol_vma_set = false, + .got_symbol_vma = 0, + .should_relocate = false + }; + + r_type = ELFNN_R_TYPE (rel->r_info); if (r_type >= (int) R_ARC_max) { @@ -1494,7 +1576,7 @@ elf_arc_relocate_section (bfd * output_bfd, } howto = arc_elf_howto (r_type); - r_symndx = ELF32_R_SYM (rel->r_info); + r_symndx = ELFNN_R_SYM (rel->r_info); /* If we are generating another .o file and the symbol in not local, skip this relocation. */ @@ -1596,9 +1678,9 @@ elf_arc_relocate_section (bfd * output_bfd, /* For ld -r, remove relocations in debug sections against sections defined in discarded sections. Not done for eh_frame editing code expects to be present. */ - if (bfd_link_relocatable (info) - && (input_section->flags & SEC_DEBUGGING)) - wrel--; + if (bfd_link_relocatable (info) + && (input_section->flags & SEC_DEBUGGING)) + wrel--; continue; } @@ -1610,6 +1692,8 @@ elf_arc_relocate_section (bfd * output_bfd, continue; } + resolved_to_zero = (h != NULL && UNDEFWEAK_NO_DYNAMIC_RELOC (info, h)); + if (r_symndx < symtab_hdr->sh_info) /* A local symbol. */ { reloc_data.sym_value = sym->st_value; @@ -1638,7 +1722,7 @@ elf_arc_relocate_section (bfd * output_bfd, BFD_ASSERT (htab->sgot != NULL || !is_reloc_for_GOT (howto)); if (htab->sgot != NULL) reloc_data.got_symbol_vma = htab->sgot->output_section->vma - + htab->sgot->output_offset; + + htab->sgot->output_offset; reloc_data.should_relocate = true; } @@ -1652,19 +1736,18 @@ elf_arc_relocate_section (bfd * output_bfd, while (h->root.type == bfd_link_hash_indirect || h->root.type == bfd_link_hash_warning) - { - struct elf_arc_link_hash_entry *ah_old = - (struct elf_arc_link_hash_entry *) h; - h = (struct elf_link_hash_entry *) h->root.u.i.link; - struct elf_arc_link_hash_entry *ah = - (struct elf_arc_link_hash_entry *) h; - - if (ah->got_ents == 0 && ah_old->got_ents != ah->got_ents) - ah->got_ents = ah_old->got_ents; - } + { + struct elf_arc_link_hash_entry *ah_old + = (struct elf_arc_link_hash_entry *) h; + h = (struct elf_link_hash_entry *) h->root.u.i.link; + struct elf_arc_link_hash_entry *ah + = (struct elf_arc_link_hash_entry *) h; + + if (ah->got_ents == 0 && ah_old->got_ents != ah->got_ents) + ah->got_ents = ah_old->got_ents; + } /* TODO: Need to validate what was the intention. */ - /* BFD_ASSERT ((h->dynindx == -1) || (h->forced_local != 0)); */ reloc_data.symbol_name = h->root.root.string; /* If we have encountered a definition for this symbol. */ @@ -1681,13 +1764,13 @@ elf_arc_relocate_section (bfd * output_bfd, struct elf_arc_link_hash_entry *ah = (struct elf_arc_link_hash_entry *) h; /* TODO: Change it to use arc_do_relocation with - ARC_32 reloc. Try to use ADD_RELA macro. */ + ARC_32 reloc. Try to use ADD_RELA macro. */ bfd_vma relocation = reloc_data.sym_value + reloc_data.reloc_addend + (reloc_data.sym_section->output_section != NULL ? - (reloc_data.sym_section->output_offset - + reloc_data.sym_section->output_section->vma) - : 0); + (reloc_data.sym_section->output_offset + + reloc_data.sym_section->output_section->vma) + : 0); BFD_ASSERT (ah->got_ents); bfd_vma got_offset = ah->got_ents->offset; @@ -1718,7 +1801,8 @@ elf_arc_relocate_section (bfd * output_bfd, reloc_data.sym_section = htab->splt; reloc_data.should_relocate = true; } - else + /* See pr22269. */ + else if (!resolved_to_zero) continue; } else @@ -1752,11 +1836,12 @@ elf_arc_relocate_section (bfd * output_bfd, BFD_ASSERT (htab->sgot != NULL || !is_reloc_for_GOT (howto)); if (htab->sgot != NULL) reloc_data.got_symbol_vma = htab->sgot->output_section->vma - + htab->sgot->output_offset; + + htab->sgot->output_offset; } - if ((is_reloc_for_GOT (howto) - || is_reloc_for_TLS (howto))) + if (is_reloc_for_GOT (howto) + || (is_reloc_for_TLS (howto) + && !resolved_to_zero)) { reloc_data.should_relocate = true; @@ -1776,106 +1861,109 @@ elf_arc_relocate_section (bfd * output_bfd, if (h == NULL) { - create_got_dynrelocs_for_single_entry ( - got_entry_for_type (list, - arc_got_entry_type_for_reloc (howto)), - output_bfd, info, NULL); + create_got_dynrelocs_for_single_entry + (got_entry_for_type (list, + arc_got_entry_type_for_reloc (howto)), + output_bfd, info, NULL); } } -#define IS_ARC_PCREL_TYPE(TYPE) \ - ( (TYPE == R_ARC_PC32) \ - || (TYPE == R_ARC_32_PCREL)) +#define IS_ARC_PCREL_TYPE(TYPE) \ + ((TYPE == R_ARC_PC32) \ + || (TYPE == R_ARC_32_PCREL)) switch (r_type) { - case R_ARC_32: - case R_ARC_32_ME: - case R_ARC_PC32: - case R_ARC_32_PCREL: - if (bfd_link_pic (info) - && (input_section->flags & SEC_ALLOC) != 0 - && (!IS_ARC_PCREL_TYPE (r_type) - || (h != NULL - && h->dynindx != -1 - && !h->def_regular - && (!info->symbolic || !h->def_regular)))) - { - Elf_Internal_Rela outrel; - bfd_byte *loc; - bool skip = false; - bool relocate = false; - asection *sreloc = _bfd_elf_get_dynamic_reloc_section - (input_bfd, input_section, - /*RELA*/ true); + case R_ARC_64: + case R_ARC_32: + case R_ARC_32_ME: + case R_ARC_PC32: + case R_ARC_32_PCREL: + case R_ARC_HI32_ME: + case R_ARC_LO32_ME: + if (bfd_link_pic (info) + && !resolved_to_zero + && (input_section->flags & SEC_ALLOC) != 0 + && (!IS_ARC_PCREL_TYPE (r_type) + || (h != NULL + && h->dynindx != -1 + && (!SYMBOL_REFERENCES_LOCAL (info, h))))) + { + Elf_Internal_Rela outrel; + bfd_byte *loc; + bool skip = false; + bool relocate = false; + asection *sreloc = _bfd_elf_get_dynamic_reloc_section + (input_bfd, input_section, + /*RELA*/ true); - BFD_ASSERT (sreloc != NULL); + BFD_ASSERT (sreloc != NULL); - outrel.r_offset = _bfd_elf_section_offset (output_bfd, - info, - input_section, - rel->r_offset); + outrel.r_offset = _bfd_elf_section_offset (output_bfd, + info, + input_section, + rel->r_offset); if (outrel.r_offset == (bfd_vma) -1) skip = true; - outrel.r_addend = rel->r_addend; - outrel.r_offset += (input_section->output_section->vma - + input_section->output_offset); + outrel.r_addend = rel->r_addend; + outrel.r_offset += (input_section->output_section->vma + + input_section->output_offset); - if (skip) - { - memset (&outrel, 0, sizeof outrel); + if (skip) + { + memset (&outrel, 0, sizeof outrel); + relocate = false; + } + else if (h != NULL + && h->dynindx != -1 + && (IS_ARC_PCREL_TYPE (r_type) + || !(bfd_link_executable (info) + || SYMBOLIC_BIND (info, h)) + || ! h->def_regular)) + { + BFD_ASSERT (h != NULL); + if ((input_section->flags & SEC_ALLOC) != 0) relocate = false; - } - else if (h != NULL - && h->dynindx != -1 - && (IS_ARC_PCREL_TYPE (r_type) - || !(bfd_link_executable (info) - || SYMBOLIC_BIND (info, h)) - || ! h->def_regular)) - { - BFD_ASSERT (h != NULL); - if ((input_section->flags & SEC_ALLOC) != 0) - relocate = false; - else - relocate = true; - - BFD_ASSERT (h->dynindx != -1); - outrel.r_info = ELF32_R_INFO (h->dynindx, r_type); - } - else - { - /* Handle local symbols, they either do not have a - global hash table entry (h == NULL), or are - forced local due to a version script - (h->forced_local), or the third condition is - legacy, it appears to say something like, for - links where we are pre-binding the symbols, or - there's not an entry for this symbol in the - dynamic symbol table, and it's a regular symbol - not defined in a shared object, then treat the - symbol as local, resolve it now. */ + else relocate = true; - /* outrel.r_addend = 0; */ - outrel.r_info = ELF32_R_INFO (0, R_ARC_RELATIVE); - } - BFD_ASSERT (sreloc->contents != 0); + BFD_ASSERT (h->dynindx != -1); + outrel.r_info = ELFNN_R_INFO (h->dynindx, r_type); + } + else + { + /* Handle local symbols, they either do not have a + global hash table entry (h == NULL), or are + forced local due to a version script + (h->forced_local), or the third condition is + legacy, it appears to say something like, for + links where we are pre-binding the symbols, or + there's not an entry for this symbol in the + dynamic symbol table, and it's a regular symbol + not defined in a shared object, then treat the + symbol as local, resolve it now. */ + relocate = true; + /* outrel.r_addend = 0; */ + outrel.r_info = ELFNN_R_INFO (0, R_ARC_RELATIVE); + } - loc = sreloc->contents; - loc += sreloc->reloc_count * sizeof (Elf32_External_Rela); - sreloc->reloc_count += 1; + BFD_ASSERT (sreloc->contents != 0); - bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc); + loc = sreloc->contents; + loc += sreloc->reloc_count * sizeof (ElfNN_External_Rela); + sreloc->reloc_count += 1; - if (!relocate) - continue; - } - break; - default: - break; + bed->s->swap_reloca_out (output_bfd, &outrel, loc); + + if (!relocate) + continue; + } + break; + default: + break; } if (is_reloc_SDA_relative (howto) @@ -1892,10 +1980,12 @@ elf_arc_relocate_section (bfd * output_bfd, /* Make sure we have with a dynamic linker. In case of GOT and PLT the sym_section should point to .got or .plt respectively. */ if ((is_reloc_for_GOT (howto) || is_reloc_for_PLT (howto)) - && reloc_data.sym_section == NULL) + && reloc_data.sym_section == NULL + && !resolved_to_zero) { _bfd_error_handler - (_("GOT and PLT relocations cannot be fixed with a non dynamic linker")); + (_("GOT and PLT relocations cannot be fixed with a non dynamic" \ + " linker")); bfd_set_error (bfd_error_bad_value); return false; } @@ -1908,18 +1998,20 @@ elf_arc_relocate_section (bfd * output_bfd, case bfd_reloc_overflow: (*info->callbacks->reloc_overflow) - (info, (h ? &h->root : NULL), reloc_data.symbol_name, howto->name, (bfd_vma) 0, - input_bfd, input_section, rel->r_offset); + (info, (h ? &h->root : NULL), reloc_data.symbol_name, howto->name, + (bfd_vma) 0, input_bfd, input_section, rel->r_offset); break; case bfd_reloc_undefined: (*info->callbacks->undefined_symbol) - (info, reloc_data.symbol_name, input_bfd, input_section, rel->r_offset, true); + (info, reloc_data.symbol_name, input_bfd, input_section, + rel->r_offset, true); break; case bfd_reloc_other: /* xgettext:c-format */ - msg = _("%pB(%pA): warning: unaligned access to symbol '%s' in the small data area"); + msg = _("%pB(%pA): warning: unaligned access to symbol '%s' in the" \ + " small data area"); break; case bfd_reloc_outofrange: @@ -1944,7 +2036,8 @@ elf_arc_relocate_section (bfd * output_bfd, } if (msg) - _bfd_error_handler (msg, input_bfd, input_section, reloc_data.symbol_name); + _bfd_error_handler (msg, input_bfd, input_section, + reloc_data.symbol_name); return false; } @@ -1988,7 +2081,7 @@ elf_arc_check_relocs (bfd * abfd, unsigned long r_symndx; struct elf_link_hash_entry *h; - r_type = ELF32_R_TYPE (rel->r_info); + r_type = ELFNN_R_TYPE (rel->r_info); if (r_type >= (int) R_ARC_max) { @@ -1998,7 +2091,7 @@ elf_arc_check_relocs (bfd * abfd, howto = arc_elf_howto (r_type); /* Load symbol information. */ - r_symndx = ELF32_R_SYM (rel->r_info); + r_symndx = ELFNN_R_SYM (rel->r_info); if (r_symndx < symtab_hdr->sh_info) /* Is a local symbol. */ h = NULL; else /* Global one. */ @@ -2012,8 +2105,13 @@ elf_arc_check_relocs (bfd * abfd, switch (r_type) { + case R_ARC_8: + case R_ARC_16: case R_ARC_32: + case R_ARC_64: case R_ARC_32_ME: + case R_ARC_HI32_ME: + case R_ARC_LO32_ME: /* During shared library creation, these relocs should not appear in a shared library (as memory will be read only and the dynamic linker can not resolve these. However @@ -2042,39 +2140,52 @@ elf_arc_check_relocs (bfd * abfd, return false; } - /* In some cases we are not setting the 'non_got_ref' - flag, even though the relocations don't require a GOT - access. We should extend the testing in this area to - ensure that no significant cases are being missed. */ - if (h) - h->non_got_ref = 1; - /* FALLTHROUGH */ - case R_ARC_PC32: - case R_ARC_32_PCREL: - if ((bfd_link_pic (info)) - && ((r_type != R_ARC_PC32 && r_type != R_ARC_32_PCREL) - || (h != NULL - && (!info->symbolic || !h->def_regular)))) - { - if (sreloc == NULL) - { - if (info->dynamic - && ! htab->dynamic_sections_created - && ! _bfd_elf_link_create_dynamic_sections (abfd, info)) - return false; - sreloc = _bfd_elf_make_dynamic_reloc_section (sec, dynobj, - 2, abfd, - /*rela*/ - true); - - if (sreloc == NULL) - return false; - } - sreloc->size += sizeof (Elf32_External_Rela); + /* In some cases we are not setting the 'non_got_ref' flag, + even though the relocations don't require a GOT access. + We should extend the testing in this area to ensure that + no significant cases are being missed. */ + if (h) + h->non_got_ref = 1; - } - default: + /* We don't need to handle relocs into sections not going + into the "real" output. */ + if ((sec->flags & SEC_ALLOC) == 0) break; + + /* No need to do anything if we're not creating a shared + object. */ + if (!bfd_link_pic (info) + || (h != NULL + && UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))) + break; + + /* fall through */ + case R_ARC_PC32: + case R_ARC_32_PCREL: + if (!bfd_link_pic (info)) + break; + + if (((r_type != R_ARC_PC32 && r_type != R_ARC_32_PCREL) + || (!SYMBOL_REFERENCES_LOCAL (info, h)))) + { + if (sreloc == NULL) + { + if (info->dynamic + && ! htab->dynamic_sections_created + && ! _bfd_elf_link_create_dynamic_sections (abfd, info)) + return false; + sreloc = _bfd_elf_make_dynamic_reloc_section (sec, dynobj, + 2, abfd, + /* rela */ + true); + + if (sreloc == NULL) + return false; + } + sreloc->size += sizeof (ElfNN_External_Rela); + } + default: + break; } if (is_reloc_for_PLT (howto)) @@ -2112,20 +2223,18 @@ elf_arc_check_relocs (bfd * abfd, if (! _bfd_elf_create_got_section (dynobj, info)) return false; - arc_fill_got_info_for_reloc ( - arc_got_entry_type_for_reloc (howto), - get_got_entry_list_for_symbol (abfd, r_symndx, h), - info, - h); + arc_fill_got_info_for_reloc + (arc_got_entry_type_for_reloc (howto), + get_got_entry_list_for_symbol (abfd, r_symndx, h), + info, + h); } } return true; } -#define ELF_DYNAMIC_INTERPRETER "/sbin/ld-uClibc.so" - -static const struct plt_version_t * +static struct plt_version_t * arc_get_plt_version (struct bfd_link_info *info) { int i; @@ -2137,7 +2246,12 @@ arc_get_plt_version (struct bfd_link_info *info) (int) plt_versions[i].elem_size); } - if (bfd_get_mach (info->output_bfd) == bfd_mach_arc_arcv2) + if (bfd_get_mach (info->output_bfd) == bfd_mach_arcv3_64) + { + return &(plt_versions[ELF_ARCV3_PIC]); + } + else if (bfd_get_mach (info->output_bfd) == bfd_mach_arc_arcv2 + || bfd_get_mach (info->output_bfd) == bfd_mach_arcv3_32) { if (bfd_link_pic (info)) return &(plt_versions[ELF_ARCV2_PIC]); @@ -2151,6 +2265,8 @@ arc_get_plt_version (struct bfd_link_info *info) else return &(plt_versions[ELF_ARC_ABS]); } + BFD_ASSERT (0); + return NULL; } static bfd_vma @@ -2171,9 +2287,8 @@ add_symbol_to_plt (struct bfd_link_info *info) htab->splt->size += plt_data->elem_size; ARC_DEBUG ("PLT_SIZE = %d\n", (int) htab->splt->size); - htab->sgotplt->size += 4; - htab->srelplt->size += sizeof (Elf32_External_Rela); - + htab->sgotplt->size += GOT_ENTRY_SIZE; + htab->srelplt->size += sizeof (ElfNN_External_Rela); return ret; } @@ -2193,11 +2308,11 @@ plt_do_relocs_for_symbol (bfd *abfd, switch (SYM_ONLY (reloc->symbol)) { - case SGOT: - relocation - = htab->sgotplt->output_section->vma - + htab->sgotplt->output_offset + symbol_got_offset; - break; + case SGOT: + relocation + = htab->sgotplt->output_section->vma + + htab->sgotplt->output_offset + symbol_got_offset; + break; } relocation += reloc->addend; @@ -2208,26 +2323,26 @@ plt_do_relocs_for_symbol (bfd *abfd, reloc_offset -= (IS_INSN_24 (reloc->symbol)) ? 2 : 0; relocation -= htab->splt->output_section->vma - + htab->splt->output_offset - + plt_offset + reloc_offset; + + htab->splt->output_offset + + plt_offset + reloc_offset; } /* TODO: being ME is not a property of the relocation but of the - section of which is applying the relocation. */ + section of which is applying the relocation. */ if (IS_MIDDLE_ENDIAN (reloc->symbol) && !bfd_big_endian (abfd)) { relocation = ((relocation & 0xffff0000) >> 16) - | ((relocation & 0xffff) << 16); + | ((relocation & 0xffff) << 16); } switch (reloc->size) { - case 32: - bfd_put_32 (htab->splt->output_section->owner, - relocation, - htab->splt->contents + plt_offset + reloc->offset); - break; + case 32: + bfd_put_32 (htab->splt->output_section->owner, + relocation, + htab->splt->contents + plt_offset + reloc->offset); + break; } reloc = &(reloc[1]); /* Jump to next relocation. */ @@ -2241,10 +2356,12 @@ relocate_plt_for_symbol (bfd *output_bfd, { const struct plt_version_t *plt_data = arc_get_plt_version (info); struct elf_link_hash_table *htab = elf_hash_table (info); + const struct elf_backend_data *bed; bfd_vma plt_index = (h->plt.offset - plt_data->entry_size) - / plt_data->elem_size; - bfd_vma got_offset = (plt_index + 3) * 4; + / plt_data->elem_size; + bfd_vma got_offset = (plt_index + 3) * GOT_ENTRY_SIZE; + bed = get_elf_backend_data (output_bfd); ARC_DEBUG ("arc_info: PLT_OFFSET = %#lx, PLT_ENTRY_VMA = %#lx, \ GOT_ENTRY_OFFSET = %#lx, GOT_ENTRY_VMA = %#lx, for symbol %s\n", @@ -2293,32 +2410,30 @@ GOT_ENTRY_OFFSET = %#lx, GOT_ENTRY_VMA = %#lx, for symbol %s\n", rel.r_addend = 0; BFD_ASSERT (h->dynindx != -1); - rel.r_info = ELF32_R_INFO (h->dynindx, R_ARC_JMP_SLOT); + rel.r_info = ELFNN_R_INFO (h->dynindx, R_ARC_JMP_SLOT); loc = htab->srelplt->contents; - loc += plt_index * sizeof (Elf32_External_Rela); /* relA */ - bfd_elf32_swap_reloca_out (output_bfd, &rel, loc); + loc += plt_index * sizeof (ElfNN_External_Rela); /* relA */ + bed->s->swap_reloca_out (output_bfd, &rel, loc); } } +/* Initialize the PLT with ARC specific PLT header. See arc-plt.def. + Use middle-endian to fill in the data as it is executable code. */ + static void relocate_plt_for_entry (bfd *abfd, struct bfd_link_info *info) { const struct plt_version_t *plt_data = arc_get_plt_version (info); struct elf_link_hash_table *htab = elf_hash_table (info); + bfd_vma i = 0; + uint16_t *ptr = (uint16_t *) plt_data->entry; - { - bfd_vma i = 0; - uint16_t *ptr = (uint16_t *) plt_data->entry; - for (i = 0; i < plt_data->entry_size/2; i++) - { - uint16_t data = ptr[i]; - bfd_put_16 (abfd, - (bfd_vma) data, - htab->splt->contents + (i*2)); - } - } + for (i = 0; i < plt_data->entry_size/2; i++) + { + bfd_put_16 (abfd, (bfd_vma) ptr[i], htab->splt->contents + (i*2)); + } PLT_DO_RELOCS_FOR_ENTRY (abfd, htab, plt_data->entry_relocs); } @@ -2330,7 +2445,7 @@ relocate_plt_for_entry (bfd *abfd, static bool elf_arc_adjust_dynamic_symbol (struct bfd_link_info *info, - struct elf_link_hash_entry *h) + struct elf_link_hash_entry *h) { asection *s; bfd *dynobj = (elf_hash_table (info))->dynobj; @@ -2432,7 +2547,7 @@ elf_arc_adjust_dynamic_symbol (struct bfd_link_info *info, struct elf_arc_link_hash_table *arc_htab = elf_arc_hash_table (info); BFD_ASSERT (arc_htab->elf.srelbss != NULL); - arc_htab->elf.srelbss->size += sizeof (Elf32_External_Rela); + arc_htab->elf.srelbss->size += sizeof (ElfNN_External_Rela); h->needs_copy = 1; } @@ -2445,7 +2560,7 @@ elf_arc_adjust_dynamic_symbol (struct bfd_link_info *info, /* Function : elf_arc_finish_dynamic_symbol Brief : Finish up dynamic symbol handling. We set the - contents of various dynamic sections here. + contents of various dynamic sections here. Args : output_bfd : info : h : @@ -2458,6 +2573,10 @@ elf_arc_finish_dynamic_symbol (bfd * output_bfd, struct elf_link_hash_entry *h, Elf_Internal_Sym * sym) { + const struct elf_backend_data *bed; + + bed = get_elf_backend_data (output_bfd); + if (h->plt.offset != (bfd_vma) -1) { relocate_plt_for_symbol (output_bfd, info, h); @@ -2475,12 +2594,8 @@ elf_arc_finish_dynamic_symbol (bfd * output_bfd, create respective dynamic relocs. */ /* TODO: Make function to get list and not access the list directly. */ /* TODO: Move function to relocate_section create this relocs eagerly. */ - struct elf_arc_link_hash_entry *ah = - (struct elf_arc_link_hash_entry *) h; - create_got_dynrelocs_for_got_info (&ah->got_ents, - output_bfd, - info, - h); + struct elf_arc_link_hash_entry *ah = (struct elf_arc_link_hash_entry *) h; + create_got_dynrelocs_for_got_info (&ah->got_ents, output_bfd, info, h); if (h->needs_copy) { @@ -2500,7 +2615,7 @@ elf_arc_finish_dynamic_symbol (bfd * output_bfd, + h->root.u.def.section->output_offset); bfd_byte * loc = arc_htab->elf.srelbss->contents - + (arc_htab->elf.srelbss->reloc_count * sizeof (Elf32_External_Rela)); + + (arc_htab->elf.srelbss->reloc_count * sizeof (ElfNN_External_Rela)); arc_htab->elf.srelbss->reloc_count++; Elf_Internal_Rela rel; @@ -2508,9 +2623,9 @@ elf_arc_finish_dynamic_symbol (bfd * output_bfd, rel.r_offset = rel_offset; BFD_ASSERT (h->dynindx != -1); - rel.r_info = ELF32_R_INFO (h->dynindx, R_ARC_COPY); + rel.r_info = ELFNN_R_INFO (h->dynindx, R_ARC_COPY); - bfd_elf32_swap_reloca_out (output_bfd, &rel, loc); + bed->s->swap_reloca_out (output_bfd, &rel, loc); } /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. */ @@ -2554,8 +2669,7 @@ arc_create_forced_local_got_entries_for_tls (struct bfd_hash_entry *bh, while (list != NULL) { create_got_dynrelocs_for_single_entry (list, tmp->output_bfd, - tmp->info, - (struct elf_link_hash_entry *) h); + tmp->info, (struct elf_link_hash_entry *) h); list = list->next; } } @@ -2579,14 +2693,17 @@ elf_arc_finish_dynamic_sections (bfd * output_bfd, struct elf_link_hash_table *htab = elf_hash_table (info); bfd *dynobj = (elf_hash_table (info))->dynobj; asection *sdyn = bfd_get_linker_section (dynobj, ".dynamic"); + const struct elf_backend_data *bed = get_elf_backend_data (output_bfd); + /* TODO: instead of checking for sdyn, we can use elf_hash_table + (info)->dynamic_sections_created to see if we have dynamic + sections creared. */ if (sdyn) { - Elf32_External_Dyn *dyncon, *dynconend; + ElfNN_External_Dyn *dyncon, *dynconend; - dyncon = (Elf32_External_Dyn *) sdyn->contents; - dynconend - = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size); + dyncon = (ElfNN_External_Dyn *) sdyn->contents; + dynconend = (ElfNN_External_Dyn *) (sdyn->contents + sdyn->size); for (; dyncon < dynconend; dyncon++) { Elf_Internal_Dyn internal_dyn; @@ -2595,20 +2712,20 @@ elf_arc_finish_dynamic_sections (bfd * output_bfd, struct elf_link_hash_entry *h = NULL; asection *s = NULL; - bfd_elf32_swap_dyn_in (dynobj, dyncon, &internal_dyn); + bed->s->swap_dyn_in (dynobj, dyncon, &internal_dyn); switch (internal_dyn.d_tag) { GET_SYMBOL_OR_SECTION (DT_INIT, info->init_function, NULL) - GET_SYMBOL_OR_SECTION (DT_FINI, info->fini_function, NULL) - GET_SYMBOL_OR_SECTION (DT_PLTGOT, NULL, ".plt") - GET_SYMBOL_OR_SECTION (DT_JMPREL, NULL, ".rela.plt") - GET_SYMBOL_OR_SECTION (DT_PLTRELSZ, NULL, ".rela.plt") - GET_SYMBOL_OR_SECTION (DT_VERSYM, NULL, ".gnu.version") - GET_SYMBOL_OR_SECTION (DT_VERDEF, NULL, ".gnu.version_d") - GET_SYMBOL_OR_SECTION (DT_VERNEED, NULL, ".gnu.version_r") - default: - break; + GET_SYMBOL_OR_SECTION (DT_FINI, info->fini_function, NULL) + GET_SYMBOL_OR_SECTION (DT_PLTGOT, NULL, ".plt") + GET_SYMBOL_OR_SECTION (DT_JMPREL, NULL, ".rela.plt") + GET_SYMBOL_OR_SECTION (DT_PLTRELSZ, NULL, ".rela.plt") + GET_SYMBOL_OR_SECTION (DT_VERSYM, NULL, ".gnu.version") + GET_SYMBOL_OR_SECTION (DT_VERDEF, NULL, ".gnu.version_d") + GET_SYMBOL_OR_SECTION (DT_VERNEED, NULL, ".gnu.version_r") + default: + break; } /* In case the dynamic symbols should be updated with a symbol. */ @@ -2659,9 +2776,10 @@ elf_arc_finish_dynamic_sections (bfd * output_bfd, } if (do_it) - bfd_elf32_swap_dyn_out (output_bfd, &internal_dyn, dyncon); + bed->s->swap_dyn_out (output_bfd, &internal_dyn, dyncon); } + /* Fill in the first entry in the procedure linkage table. */ if (htab->splt->size > 0) { relocate_plt_for_entry (output_bfd, info); @@ -2670,30 +2788,40 @@ elf_arc_finish_dynamic_sections (bfd * output_bfd, /* TODO: Validate this. */ if (htab->srelplt->output_section != bfd_abs_section_ptr) elf_section_data (htab->srelplt->output_section) - ->this_hdr.sh_entsize = 12; + ->this_hdr.sh_entsize = GOT_ENTRY_SIZE * 3; } /* Fill in the first three entries in the global offset table. */ if (htab->sgot) { - struct elf_link_hash_entry *h; - h = elf_link_hash_lookup (elf_hash_table (info), "_GLOBAL_OFFSET_TABLE_", - false, false, true); - - if (h != NULL && h->root.type != bfd_link_hash_undefined - && h->root.u.def.section != NULL) + struct elf_link_hash_entry *got; + /* Get the hash entry of the first GOT entry. */ + got = elf_link_hash_lookup (elf_hash_table (info), + "_GLOBAL_OFFSET_TABLE_", false, false, true); + + if (got != NULL + && got->root.type != bfd_link_hash_undefined + && got->root.u.def.section != NULL) { - asection *sec = h->root.u.def.section; + asection *sec = got->root.u.def.section; + bfd_vma dyn_vma = 0; - if (sdyn == NULL) - bfd_put_32 (output_bfd, (bfd_vma) 0, - sec->contents); - else - bfd_put_32 (output_bfd, - sdyn->output_section->vma + sdyn->output_offset, - sec->contents); - bfd_put_32 (output_bfd, (bfd_vma) 0, sec->contents + 4); - bfd_put_32 (output_bfd, (bfd_vma) 0, sec->contents + 8); + /* Check if we participate in a dynamic linking. */ + if (sdyn) + { + /* Get the unrelocated address of the _DYNAMIC, which is + the start of the start of the dynamic sction. */ + dyn_vma = sdyn->output_section->vma + sdyn->output_offset; + } + + /* _GLOBAL_OFFSET_TABLE_[0] = VMA (.dynamic) */ + write_in_got (output_bfd, dyn_vma, sec->contents); + /* _GLOBAL_OFFSET_TABLE_[1] = 0. Reserved for dynamic linker. */ + write_in_got (output_bfd, (bfd_vma) 0, + sec->contents + (GOT_ENTRY_SIZE)); + /* _GLOBAL_OFFSET_TABLE_[2] = 0. Reserved for dynamic linker. */ + write_in_got (output_bfd, (bfd_vma) 0, + sec->contents + (GOT_ENTRY_SIZE * 2)); } } @@ -2721,6 +2849,7 @@ elf_arc_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED, bfd *dynobj; asection *s; bool relocs_exist = false; + bool reltext_exist = false; struct elf_link_hash_table *htab = elf_hash_table (info); dynobj = htab->dynobj; @@ -2736,8 +2865,8 @@ elf_arc_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED, { s = bfd_get_section_by_name (dynobj, ".interp"); BFD_ASSERT (s != NULL); - s->size = sizeof (ELF_DYNAMIC_INTERPRETER); - s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER; + s->size = sizeof (ELFNN_DYNAMIC_INTERPRETER); + s->contents = (unsigned char *) ELFNN_DYNAMIC_INTERPRETER; } /* Add some entries to the .dynamic section. We fill in some of @@ -2775,7 +2904,29 @@ elf_arc_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED, else if (startswith (s->name, ".rela")) { if (s->size != 0 && s != htab->srelplt) - relocs_exist = true; + { + if (!reltext_exist) + { + const char *name = s->name + 5; + bfd *ibfd; + for (ibfd = info->input_bfds; ibfd; ibfd = ibfd->link.next) + if (bfd_get_flavour (ibfd) == bfd_target_elf_flavour + && ibfd->flags & DYNAMIC) + { + asection *target = bfd_get_section_by_name (ibfd, name); + if (target != NULL + && elf_section_data (target)->sreloc == s + && ((target->output_section->flags + & (SEC_READONLY | SEC_ALLOC)) + == (SEC_READONLY | SEC_ALLOC))) + { + reltext_exist = true; + break; + } + } + } + relocs_exist = true; + } /* We use the reloc_count field as a counter if we need to copy relocs into the output file. */ @@ -2802,18 +2953,44 @@ elf_arc_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED, return false; } - return _bfd_elf_add_dynamic_tags (output_bfd, info, relocs_exist); + if (htab->dynamic_sections_created) + { + /* TODO: Check if this is needed. */ + if (!bfd_link_pic (info)) + if (!_bfd_elf_add_dynamic_entry (info, DT_DEBUG, 0)) + return false; + + if (htab->splt && (htab->splt->flags & SEC_EXCLUDE) == 0) + if (!_bfd_elf_add_dynamic_entry (info, DT_PLTGOT, 0) + || !_bfd_elf_add_dynamic_entry (info, DT_PLTRELSZ, 0) + || !_bfd_elf_add_dynamic_entry (info, DT_PLTREL, DT_RELA) + || !_bfd_elf_add_dynamic_entry (info, DT_JMPREL, 0)) + return false; + + if (relocs_exist) + if (!_bfd_elf_add_dynamic_entry (info, DT_RELA, 0) + || !_bfd_elf_add_dynamic_entry (info, DT_RELASZ, 0) + || !_bfd_elf_add_dynamic_entry (info, DT_RELAENT, + sizeof (ElfNN_External_Rela))) + return false; + + if (reltext_exist) + if (!_bfd_elf_add_dynamic_entry (info, DT_TEXTREL, 0)) + return false; + } + + return true; } -/* Classify dynamic relocs such that -z combreloc can reorder and combine - them. */ +/* Classify dynamic relocs such that -z combreloc can reorder and + combine them. */ static enum elf_reloc_type_class -elf32_arc_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED, - const asection *rel_sec ATTRIBUTE_UNUSED, - const Elf_Internal_Rela *rela) +arc_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED, + const asection *rel_sec ATTRIBUTE_UNUSED, + const Elf_Internal_Rela *rela) { - switch ((int) ELF32_R_TYPE (rela->r_info)) + switch ((int) ELFNN_R_TYPE (rela->r_info)) { case R_ARC_RELATIVE: return reloc_class_relative; @@ -2821,47 +2998,44 @@ elf32_arc_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED, return reloc_class_plt; case R_ARC_COPY: return reloc_class_copy; - /* TODO: Needed in future to support ifunc. */ - /* - case R_ARC_IRELATIVE: - return reloc_class_ifunc; - */ default: return reloc_class_normal; } } -const struct elf_size_info arc_elf32_size_info = -{ - sizeof (Elf32_External_Ehdr), - sizeof (Elf32_External_Phdr), - sizeof (Elf32_External_Shdr), - sizeof (Elf32_External_Rel), - sizeof (Elf32_External_Rela), - sizeof (Elf32_External_Sym), - sizeof (Elf32_External_Dyn), - sizeof (Elf_External_Note), - 4, - 1, - 32, 2, - ELFCLASS32, EV_CURRENT, - bfd_elf32_write_out_phdrs, - bfd_elf32_write_shdrs_and_ehdr, - bfd_elf32_checksum_contents, - bfd_elf32_write_relocs, - bfd_elf32_swap_symbol_in, - bfd_elf32_swap_symbol_out, - bfd_elf32_slurp_reloc_table, - bfd_elf32_slurp_symbol_table, - bfd_elf32_swap_dyn_in, - bfd_elf32_swap_dyn_out, - bfd_elf32_swap_reloc_in, - bfd_elf32_swap_reloc_out, - bfd_elf32_swap_reloca_in, - bfd_elf32_swap_reloca_out -}; +/* We use this so we can override certain functions + (though currently we don't). */ -#define elf_backend_size_info arc_elf32_size_info +const struct elf_size_info arc_elfNN_size_info = + { + sizeof (ElfNN_External_Ehdr), + sizeof (ElfNN_External_Phdr), + sizeof (ElfNN_External_Shdr), + sizeof (ElfNN_External_Rel), + sizeof (ElfNN_External_Rela), + sizeof (ElfNN_External_Sym), + sizeof (ElfNN_External_Dyn), + sizeof (Elf_External_Note), + 4, + 1, + ARCH_SIZE, + LOG_FILE_ALIGN, + ELFCLASSNN, EV_CURRENT, + bfd_elfNN_write_out_phdrs, + bfd_elfNN_write_shdrs_and_ehdr, + bfd_elfNN_checksum_contents, + bfd_elfNN_write_relocs, + bfd_elfNN_swap_symbol_in, + bfd_elfNN_swap_symbol_out, + bfd_elfNN_slurp_reloc_table, + bfd_elfNN_slurp_symbol_table, + bfd_elfNN_swap_dyn_in, + bfd_elfNN_swap_dyn_out, + bfd_elfNN_swap_reloc_in, + bfd_elfNN_swap_reloc_out, + bfd_elfNN_swap_reloca_in, + bfd_elfNN_swap_reloca_out + }; /* GDB expects general purpose registers to be in section .reg. However Linux kernel doesn't create this section and instead writes registers to NOTE @@ -2871,7 +3045,7 @@ const struct elf_size_info arc_elf32_size_info = stable. */ static bool -elf32_arc_grok_prstatus (bfd *abfd, Elf_Internal_Note *note) +elfNN_arc_grok_prstatus (bfd *abfd, Elf_Internal_Note *note) { int offset; size_t size; @@ -2882,11 +3056,11 @@ elf32_arc_grok_prstatus (bfd *abfd, Elf_Internal_Note *note) return false; case 236: /* sizeof (struct elf_prstatus) on Linux/arc. */ - /* pr_cursig */ + /* pr_cursig. */ elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12); - /* pr_pid */ + /* pr_pid. */ elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24); - /* pr_regs */ + /* pr_regs. */ offset = 72; size = (40 * 4); /* There are 40 registers in user_regs_struct. */ break; @@ -2900,11 +3074,11 @@ elf32_arc_grok_prstatus (bfd *abfd, Elf_Internal_Note *note) string or both. */ static int -elf32_arc_obj_attrs_arg_type (int tag) +elfNN_arc_obj_attrs_arg_type (int tag) { if (tag == Tag_ARC_CPU_name - || tag == Tag_ARC_ISA_config - || tag == Tag_ARC_ISA_apex) + || tag == Tag_ARC_ISA_config + || tag == Tag_ARC_ISA_apex) return ATTR_TYPE_FLAG_STR_VAL; else if (tag < (Tag_ARC_ISA_mpy_option + 1)) return ATTR_TYPE_FLAG_INT_VAL; @@ -2915,7 +3089,7 @@ elf32_arc_obj_attrs_arg_type (int tag) /* Attribute numbers >=14 can be safely ignored. */ static bool -elf32_arc_obj_attrs_handle_unknown (bfd *abfd, int tag) +elfNN_arc_obj_attrs_handle_unknown (bfd *abfd, int tag) { if ((tag & 127) < (Tag_ARC_ISA_mpy_option + 1)) { @@ -2934,12 +3108,12 @@ elf32_arc_obj_attrs_handle_unknown (bfd *abfd, int tag) } } -/* Handle an ARC specific section when reading an object file. This is - called when bfd_section_from_shdr finds a section with an unknown - type. */ +/* Handle an ARC specific section when reading an object file. This + is called when bfd_section_from_shdr finds a section with an + unknown type. */ static bool -elf32_arc_section_from_shdr (bfd *abfd, +elfNN_arc_section_from_shdr (bfd *abfd, Elf_Internal_Shdr * hdr, const char *name, int shindex) @@ -2960,13 +3134,138 @@ elf32_arc_section_from_shdr (bfd *abfd, return true; } +/* Delete a number of bytes from a given section while relaxing. */ + +static bool +arc_relax_delete_bytes (struct bfd_link_info *link_info, bfd *abfd, + asection *sec, bfd_vma addr, int count) +{ + Elf_Internal_Shdr *symtab_hdr; + unsigned int sec_shndx; + bfd_byte *contents; + Elf_Internal_Rela *irel, *irelend; + bfd_vma toaddr; + Elf_Internal_Sym *isym; + Elf_Internal_Sym *isymend; + struct elf_link_hash_entry **sym_hashes; + struct elf_link_hash_entry **end_hashes; + struct elf_link_hash_entry **start_hashes; + unsigned int symcount; + + sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec); + + contents = elf_section_data (sec)->this_hdr.contents; + + toaddr = sec->size; + + irel = elf_section_data (sec)->relocs; + irelend = irel + sec->reloc_count; + + /* Actually delete the bytes. */ + memmove (contents + addr, contents + addr + count, + (size_t) (toaddr - addr - count)); + sec->size -= count; + + /* Adjust all the relocs. */ + for (irel = elf_section_data (sec)->relocs; irel < irelend; irel++) + /* Get the new reloc address. */ + if ((irel->r_offset > addr && irel->r_offset < toaddr)) + irel->r_offset -= count; + + /* Adjust the local symbols defined in this section. */ + symtab_hdr = &elf_tdata (abfd)->symtab_hdr; + isym = (Elf_Internal_Sym *) symtab_hdr->contents; + for (isymend = isym + symtab_hdr->sh_info; isym < isymend; isym++) + { + if (isym->st_shndx == sec_shndx + && isym->st_value > addr + && isym->st_value <= toaddr) + { + /* Adjust the addend of SWITCH relocations in this section, + which reference this local symbol. */ + isym->st_value -= count; + } + } + + /* Now adjust the global symbols defined in this section. */ + symcount = (symtab_hdr->sh_size / sizeof (ElfNN_External_Sym) + - symtab_hdr->sh_info); + sym_hashes = start_hashes = elf_sym_hashes (abfd); + end_hashes = sym_hashes + symcount; + + for (; sym_hashes < end_hashes; sym_hashes++) + { + struct elf_link_hash_entry *sym_hash = *sym_hashes; + + /* The '--wrap SYMBOL' option is causing a pain when the object + file, containing the definition of __wrap_SYMBOL, includes a + direct call to SYMBOL as well. Since both __wrap_SYMBOL and + SYMBOL reference the same symbol (which is __wrap_SYMBOL), + but still exist as two different symbols in 'sym_hashes', we + don't want to adjust the global symbol __wrap_SYMBOL twice. + This check is only relevant when symbols are being + wrapped. */ + if (link_info->wrap_hash != NULL) + { + struct elf_link_hash_entry **cur_sym_hashes; + + /* Loop only over the symbols whom been already checked. */ + for (cur_sym_hashes = start_hashes; cur_sym_hashes < sym_hashes; + cur_sym_hashes++) + /* If the current symbol is identical to 'sym_hash', that means + the symbol was already adjusted (or at least checked). */ + if (*cur_sym_hashes == sym_hash) + break; + + /* Don't adjust the symbol again. */ + if (cur_sym_hashes < sym_hashes) + continue; + } + + if ((sym_hash->root.type == bfd_link_hash_defined + || sym_hash->root.type == bfd_link_hash_defweak) + && sym_hash->root.u.def.section == sec) + { + /* As above, adjust the value if needed. */ + if (sym_hash->root.u.def.value > addr + && sym_hash->root.u.def.value <= toaddr) + sym_hash->root.u.def.value -= count; + + /* As above, adjust the size if needed. */ + if (sym_hash->root.u.def.value <= addr + && sym_hash->root.u.def.value + sym_hash->size > addr + && sym_hash->root.u.def.value + sym_hash->size <= toaddr) + sym_hash->size -= count; + } + } + + return true; +} + +/* Check Tag_ARC_PCS_config if we can relax. */ +static bool +arc_can_relax_p (bfd *abfd) +{ + obj_attribute *attr = elf_known_obj_attributes_proc (abfd); + + if (attr[Tag_ARC_PCS_config].i & 0x100) + return true; + return false; +} + /* Relaxation hook. These are the current relaxing opportunities available: * R_ARC_GOTPC32 => R_ARC_PCREL. + * R_ARC_S25W_PCREL => R_ARC_S13_PCREL. -*/ + This is a two step relaxation procedure, in the first round, we + relax all the above opportunities. In the second round, we deal + with function align by removing unnecessary NOP_S placed by the + assembler. + + Inspired from CRX and RISCV backends. */ static bool arc_elf_relax_section (bfd *abfd, asection *sec, @@ -2977,10 +3276,14 @@ arc_elf_relax_section (bfd *abfd, asection *sec, Elf_Internal_Rela *irel, *irelend; bfd_byte *contents = NULL; Elf_Internal_Sym *isymbuf = NULL; + bool do_relax = false; /* Assume nothing changes. */ *again = false; + /* Check if we can do size related relaxation. */ + do_relax = arc_can_relax_p (abfd); + /* We don't have to do anything for a relocatable link, if this section does not have relocs, or if this is not a code section. */ @@ -2988,6 +3291,7 @@ arc_elf_relax_section (bfd *abfd, asection *sec, || sec->reloc_count == 0 || (sec->flags & SEC_RELOC) == 0 || (sec->flags & SEC_HAS_CONTENTS) == 0 + || sec->sec_flg0 || (sec->flags & SEC_CODE) == 0) return true; @@ -3003,45 +3307,78 @@ arc_elf_relax_section (bfd *abfd, asection *sec, irelend = internal_relocs + sec->reloc_count; for (irel = internal_relocs; irel < irelend; irel++) { - /* If this isn't something that can be relaxed, then ignore - this reloc. */ - if (ELF32_R_TYPE (irel->r_info) != (int) R_ARC_GOTPC32) - continue; + asection *sym_sec; + struct elf_link_hash_entry *htop = NULL; + bfd_vma symval; + + /* If this isn't something that can be relaxed, then ignore this + reloc. */ + if (ELFNN_R_TYPE (irel->r_info) != (int) R_ARC_GOTPC32 + && ELFNN_R_TYPE (irel->r_info) != (int) R_ARC_S25W_PCREL + && ELFNN_R_TYPE (irel->r_info) != (int) R_ARC_ALIGN) + continue; /* Get the section contents if we haven't done so already. */ if (contents == NULL) - { - /* Get cached copy if it exists. */ - if (elf_section_data (sec)->this_hdr.contents != NULL) - contents = elf_section_data (sec)->this_hdr.contents; - /* Go get them off disk. */ - else if (!bfd_malloc_and_get_section (abfd, sec, &contents)) - goto error_return; - } + { + /* Get cached copy if it exists. */ + if (elf_section_data (sec)->this_hdr.contents != NULL) + contents = elf_section_data (sec)->this_hdr.contents; + /* Go get them off disk. */ + else if (!bfd_malloc_and_get_section (abfd, sec, &contents)) + goto error_return; + } /* Read this BFD's local symbols if we haven't done so already. */ if (isymbuf == NULL && symtab_hdr->sh_info != 0) - { - isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents; - if (isymbuf == NULL) - isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr, - symtab_hdr->sh_info, 0, - NULL, NULL, NULL); - if (isymbuf == NULL) - goto error_return; - } - - struct elf_link_hash_entry *htop = NULL; + { + isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents; + if (isymbuf == NULL) + isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr, + symtab_hdr->sh_info, 0, + NULL, NULL, NULL); + if (isymbuf == NULL) + goto error_return; + } - if (ELF32_R_SYM (irel->r_info) >= symtab_hdr->sh_info) + /* Get the value of the symbol referred to by the reloc. */ + if (ELFNN_R_SYM (irel->r_info) < symtab_hdr->sh_info) + { + /* A local symbol. */ + Elf_Internal_Sym *isym; + + isym = isymbuf + ELFNN_R_SYM (irel->r_info); + sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx); + symval = isym->st_value; + /* If the reloc is absolute, it will not have + a symbol or section associated with it. */ + if (sym_sec) + symval += sym_sec->output_section->vma + + sym_sec->output_offset; + } + else { /* An external symbol. */ - unsigned int indx = ELF32_R_SYM (irel->r_info) - symtab_hdr->sh_info; + unsigned int indx = ELFNN_R_SYM (irel->r_info) - symtab_hdr->sh_info; htop = elf_sym_hashes (abfd)[indx]; + + BFD_ASSERT (htop != NULL); + if (htop->root.type != bfd_link_hash_defined + && htop->root.type != bfd_link_hash_defweak) + /* This appears to be a reference to an undefined + symbol. Just ignore it--it will be caught by the + regular reloc processing. */ + continue; + + symval = (htop->root.u.def.value + + htop->root.u.def.section->output_section->vma + + htop->root.u.def.section->output_offset); + sym_sec = htop->root.u.def.section; } - if (ELF32_R_TYPE (irel->r_info) == (int) R_ARC_GOTPC32 - && SYMBOL_REFERENCES_LOCAL (link_info, htop)) + if (ELFNN_R_TYPE (irel->r_info) == (int) R_ARC_GOTPC32 + && SYMBOL_REFERENCES_LOCAL (link_info, htop) + && link_info->relax_pass == 0) { unsigned int code; @@ -3054,7 +3391,7 @@ arc_elf_relax_section (bfd *abfd, asection *sec, symtab_hdr->contents = (unsigned char *) isymbuf; /* Fix the relocation's type. */ - irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info), R_ARC_PC32); + irel->r_info = ELFNN_R_INFO (ELFNN_R_SYM (irel->r_info), R_ARC_PC32); /* ld rA,[pcl,symbol@tgot] -> add rA,pcl,symbol@pcl. */ /* 0010 0bbb aa11 0ZZX DBBB 1111 10AA AAAA. @@ -3069,26 +3406,121 @@ arc_elf_relax_section (bfd *abfd, asection *sec, /* The size isn't changed, don't redo. */ *again = false; } + + /* Any of the next relax rules are changing the size, allow them + is assembler was informed. */ + if (!do_relax) + continue; + + if (ELFNN_R_TYPE (irel->r_info) == (int) R_ARC_S25W_PCREL + && link_info->relax_pass == 0) + { + unsigned int code; + bfd_vma value = symval + irel->r_addend; + bfd_vma dot, gap; + + /* Get the address (PCL) of this instruction. */ + dot = (sec->output_section->vma + + sec->output_offset + irel->r_offset) & ~0x03; + + /* Compute the distance from this insn to the branch target. */ + gap = value - dot; + + /* Check if the gap falls in the range that can be + accomodated in 13bit signed range (32-bit aligned). */ + if ((int) gap < -4094 || (int) gap > 4097 || ((int) gap & 0x3) != 0) + continue; + + /* Get the opcode. */ + code = bfd_get_32_me (abfd, contents + irel->r_offset); + /* bl @symb@pcl -> bl_s @symb@pcl. */ + /* 0000 1sss ssss ss10 SSSS SSSS SSNR tttt. */ + BFD_ASSERT ((code & 0xF8030000) == 0x08020000); + + /* Check for delay slot bit. */ + if (code & 0x20) + continue; + + /* Note that we've changed the relocs, section contents, etc. */ + elf_section_data (sec)->relocs = internal_relocs; + elf_section_data (sec)->this_hdr.contents = contents; + symtab_hdr->contents = (unsigned char *) isymbuf; + + /* Fix the relocation's type. */ + irel->r_info = ELFNN_R_INFO (ELFNN_R_SYM (irel->r_info), + R_ARC_S13_PCREL); + + /* Write back bl_s instruction. */ + bfd_put_16 (abfd, 0xF800, contents + irel->r_offset); + /* Delete two bytes of data. */ + if (!arc_relax_delete_bytes (link_info, abfd, sec, + irel->r_offset + 2, 2)) + goto error_return; + + *again = true; + } + + if (ELFNN_R_TYPE (irel->r_info) == (int) R_ARC_ALIGN + && link_info->relax_pass == 1) + { + bfd_vma aligned_addr; + bfd_vma nop_bytes; + bfd_vma alignment = 4; + + if (irel->r_addend == 2) + alignment = 2; + aligned_addr = ((irel->r_offset - 1) & ~(alignment - 1)) + alignment; + nop_bytes = aligned_addr - irel->r_offset; + + /* Cannot remove more than we have left. */ + BFD_ASSERT (irel->r_addend >= nop_bytes); + /* I should be always 16bit multiple quantum. */ + BFD_ASSERT (nop_bytes == 0 || nop_bytes == 2); + + /* Once we aligned we cannot relax anything else. */ + sec->sec_flg0 = true; + + /* Note that we've changed the relocs, section contents, etc. */ + elf_section_data (sec)->relocs = internal_relocs; + elf_section_data (sec)->this_hdr.contents = contents; + symtab_hdr->contents = (unsigned char *) isymbuf; + + /* Delete the relocation's type. */ + irel->r_info = ELFNN_R_INFO (ELFNN_R_SYM (irel->r_info), + R_ARC_NONE); + + /* Add an NOP_S if needed. */ + if (nop_bytes != 0) + bfd_put_16 (abfd, 0x78E0, contents + irel->r_offset); + + /* Delete nop_bytes bytes of data. */ + if (!arc_relax_delete_bytes (link_info, abfd, sec, + irel->r_offset + nop_bytes, + irel->r_addend - nop_bytes)) + goto error_return; + + *again = true; + } } if (isymbuf != NULL && symtab_hdr->contents != (unsigned char *) isymbuf) { if (!link_info->keep_memory) - free (isymbuf); + free (isymbuf); else - /* Cache the symbols for elf_link_input_bfd. */ - symtab_hdr->contents = (unsigned char *) isymbuf; + /* Cache the symbols for elf_link_input_bfd. */ + symtab_hdr->contents = (unsigned char *) isymbuf; } if (contents != NULL && elf_section_data (sec)->this_hdr.contents != contents) { if (!link_info->keep_memory) - free (contents); + free (contents); else - /* Cache the section contents for elf_link_input_bfd. */ - elf_section_data (sec)->this_hdr.contents = contents; + /* Cache the section contents for elf_link_input_bfd. */ + elf_section_data (sec)->this_hdr.contents = contents; } if (elf_section_data (sec)->relocs != internal_relocs) @@ -3107,24 +3539,35 @@ arc_elf_relax_section (bfd *abfd, asection *sec, return false; } -#define TARGET_LITTLE_SYM arc_elf32_le_vec -#define TARGET_LITTLE_NAME "elf32-littlearc" -#define TARGET_BIG_SYM arc_elf32_be_vec -#define TARGET_BIG_NAME "elf32-bigarc" -#define ELF_ARCH bfd_arch_arc +#define TARGET_LITTLE_SYM arcAA_elfNN_le_vec +#define TARGET_LITTLE_NAME "elfNN-littlearcAA" +#define TARGET_BIG_SYM arc_elfNN_be_vec +#define TARGET_BIG_NAME "elfNN-bigarc" +#define ELF_ARCH ARC_BFD_ARCH #define ELF_TARGET_ID ARC_ELF_DATA -#define ELF_MACHINE_CODE EM_ARC_COMPACT -#define ELF_MACHINE_ALT1 EM_ARC_COMPACT2 + +#if (ARCH_TYPE == ARC) && (ARCH_SIZE == 32) +# define ELF_MACHINE_CODE EM_ARC_COMPACT2 +# define ELF_MACHINE_ALT1 EM_ARC_COMPACT +#elif (ARCH_TYPE == ARC32) || (ARCH_TYPE == ARC64) +# define ELF_MACHINE_CODE EM_ARC_COMPACT3_64 +# define ELF_MACHINE_ALT1 EM_ARC_COMPACT3 +#else +# error "Unsupported ARC architecture" +#endif + #define ELF_MAXPAGESIZE 0x2000 -#define bfd_elf32_bfd_link_hash_table_create arc_elf_link_hash_table_create +#define bfd_elfNN_bfd_link_hash_table_create arc_elf_link_hash_table_create + +#define bfd_elfNN_bfd_merge_private_bfd_data arc_elf_merge_private_bfd_data +#define bfd_elfNN_bfd_reloc_type_lookup arc_elfNN_bfd_reloc_type_lookup +#define bfd_elfNN_bfd_set_private_flags arc_elf_set_private_flags +#define bfd_elfNN_bfd_print_private_bfd_data arc_elf_print_private_bfd_data +#define bfd_elfNN_bfd_copy_private_bfd_data arc_elf_copy_private_bfd_data +#define bfd_elfNN_bfd_relax_section arc_elf_relax_section -#define bfd_elf32_bfd_merge_private_bfd_data arc_elf_merge_private_bfd_data -#define bfd_elf32_bfd_reloc_type_lookup arc_elf32_bfd_reloc_type_lookup -#define bfd_elf32_bfd_set_private_flags arc_elf_set_private_flags -#define bfd_elf32_bfd_print_private_bfd_data arc_elf_print_private_bfd_data -#define bfd_elf32_bfd_copy_private_bfd_data arc_elf_copy_private_bfd_data -#define bfd_elf32_bfd_relax_section arc_elf_relax_section +#define elf_backend_size_info arc_elfNN_size_info #define elf_info_to_howto_rel arc_info_to_howto_rel #define elf_backend_object_p arc_elf_object_p @@ -3134,7 +3577,7 @@ arc_elf_relax_section (bfd *abfd, asection *sec, #define elf_backend_check_relocs elf_arc_check_relocs #define elf_backend_create_dynamic_sections _bfd_elf_create_dynamic_sections -#define elf_backend_reloc_type_class elf32_arc_reloc_type_class +#define elf_backend_reloc_type_class arc_reloc_type_class #define elf_backend_adjust_dynamic_symbol elf_arc_adjust_dynamic_symbol #define elf_backend_finish_dynamic_symbol elf_arc_finish_dynamic_symbol @@ -3147,14 +3590,14 @@ arc_elf_relax_section (bfd *abfd, asection *sec, #define elf_backend_plt_readonly 1 #define elf_backend_rela_plts_and_copies_p 1 #define elf_backend_want_plt_sym 0 -#define elf_backend_got_header_size 12 +#define elf_backend_got_header_size (GOT_ENTRY_SIZE * 3) #define elf_backend_dtrel_excludes_plt 1 #define elf_backend_may_use_rel_p 0 #define elf_backend_may_use_rela_p 1 #define elf_backend_default_use_rela_p 1 -#define elf_backend_grok_prstatus elf32_arc_grok_prstatus +#define elf_backend_grok_prstatus elfNN_arc_grok_prstatus #define elf_backend_default_execstack 0 @@ -3163,11 +3606,12 @@ arc_elf_relax_section (bfd *abfd, asection *sec, #undef elf_backend_obj_attrs_section #define elf_backend_obj_attrs_section ".ARC.attributes" #undef elf_backend_obj_attrs_arg_type -#define elf_backend_obj_attrs_arg_type elf32_arc_obj_attrs_arg_type +#define elf_backend_obj_attrs_arg_type elfNN_arc_obj_attrs_arg_type #undef elf_backend_obj_attrs_section_type #define elf_backend_obj_attrs_section_type SHT_ARC_ATTRIBUTES -#define elf_backend_obj_attrs_handle_unknown elf32_arc_obj_attrs_handle_unknown +#define elf_backend_obj_attrs_handle_unknown \ + elfNN_arc_obj_attrs_handle_unknown -#define elf_backend_section_from_shdr elf32_arc_section_from_shdr +#define elf_backend_section_from_shdr elfNN_arc_section_from_shdr -#include "elf32-target.h" +#include "elfNN-target.h" diff --git a/bfd/libbfd.h b/bfd/libbfd.h index d5f42f22c08..b97d0f7910d 100644 --- a/bfd/libbfd.h +++ b/bfd/libbfd.h @@ -1876,6 +1876,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", "BFD_RELOC_ARC_16", "BFD_RELOC_ARC_24", "BFD_RELOC_ARC_32", + "BFD_RELOC_ARC_64", "BFD_RELOC_ARC_N8", "BFD_RELOC_ARC_N16", "BFD_RELOC_ARC_N24", @@ -1940,6 +1941,27 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", "BFD_RELOC_ARC_S21H_PCREL_PLT", "BFD_RELOC_ARC_NPS_CMEM16", "BFD_RELOC_ARC_JLI_SECTOFF", + "BFD_RELOC_ARC_S7H_PCREL", + "BFD_RELOC_ARC_S8H_PCREL", + "BFD_RELOC_ARC_S9H_PCREL", + "BFD_RELOC_ARC_S10H_PCREL", + "BFD_RELOC_ARC_S13H_PCREL", + "BFD_RELOC_ARC_ALIGN", + "BFD_RELOC_ARC_ADD8", + "BFD_RELOC_ARC_ADD16", + "BFD_RELOC_ARC_SUB8", + "BFD_RELOC_ARC_SUB16", + "BFD_RELOC_ARC_SUB32", + "BFD_RELOC_ARC_LO32", + "BFD_RELOC_ARC_HI32", + "BFD_RELOC_ARC_LO32_ME", + "BFD_RELOC_ARC_HI32_ME", + "BFD_RELOC_ARC_N64", + "BFD_RELOC_ARC_SDA_LDST3", + "BFD_RELOC_ARC_NLO32", + "BFD_RELOC_ARC_NLO32_ME", + "BFD_RELOC_ARC_PCLO32_ME_2", + "BFD_RELOC_ARC_PLT34", "BFD_RELOC_BFIN_16_IMM", "BFD_RELOC_BFIN_16_HIGH", "BFD_RELOC_BFIN_4_PCREL", diff --git a/bfd/reloc.c b/bfd/reloc.c index 2ac883d0eac..bba269a9b74 100644 --- a/bfd/reloc.c +++ b/bfd/reloc.c @@ -3424,6 +3424,8 @@ ENUMX BFD_RELOC_ARC_24 ENUMX BFD_RELOC_ARC_32 +ENUMX + BFD_RELOC_ARC_64 ENUMX BFD_RELOC_ARC_N8 ENUMX @@ -3552,6 +3554,48 @@ ENUMX BFD_RELOC_ARC_NPS_CMEM16 ENUMX BFD_RELOC_ARC_JLI_SECTOFF +ENUMX + BFD_RELOC_ARC_S7H_PCREL +ENUMX + BFD_RELOC_ARC_S8H_PCREL +ENUMX + BFD_RELOC_ARC_S9H_PCREL +ENUMX + BFD_RELOC_ARC_S10H_PCREL +ENUMX + BFD_RELOC_ARC_S13H_PCREL +ENUMX + BFD_RELOC_ARC_ALIGN +ENUMX + BFD_RELOC_ARC_ADD8 +ENUMX + BFD_RELOC_ARC_ADD16 +ENUMX + BFD_RELOC_ARC_SUB8 +ENUMX + BFD_RELOC_ARC_SUB16 +ENUMX + BFD_RELOC_ARC_SUB32 +ENUMX + BFD_RELOC_ARC_LO32 +ENUMX + BFD_RELOC_ARC_HI32 +ENUMX + BFD_RELOC_ARC_LO32_ME +ENUMX + BFD_RELOC_ARC_HI32_ME +ENUMX + BFD_RELOC_ARC_N64 +ENUMX + BFD_RELOC_ARC_SDA_LDST3 +ENUMX + BFD_RELOC_ARC_NLO32 +ENUMX + BFD_RELOC_ARC_NLO32_ME +ENUMX + BFD_RELOC_ARC_PCLO32_ME_2 +ENUMX + BFD_RELOC_ARC_PLT34 ENUMDOC ARC relocs. diff --git a/bfd/targets.c b/bfd/targets.c index 63b3abbd287..e9d608d9918 100644 --- a/bfd/targets.c +++ b/bfd/targets.c @@ -695,6 +695,8 @@ extern const bfd_target amdgcn_elf64_le_vec; extern const bfd_target aout_vec; extern const bfd_target arc_elf32_be_vec; extern const bfd_target arc_elf32_le_vec; +extern const bfd_target arc64_elf32_le_vec; +extern const bfd_target arc64_elf64_le_vec; extern const bfd_target arm_elf32_be_vec; extern const bfd_target arm_elf32_le_vec; extern const bfd_target arm_elf32_fdpic_be_vec; @@ -999,6 +1001,10 @@ static const bfd_target * const _bfd_target_vector[] = &aarch64_mach_o_vec, &aarch64_pe_le_vec, &aarch64_pei_le_vec, + &arc_elf32_be_vec, + &arc_elf32_le_vec, + &arc64_elf32_le_vec, + &arc64_elf64_le_vec, #endif #ifdef BFD64 -- 2.30.2 ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 4/7] arc: Add new linker emulation and scripts for ARCv3 ISA. 2023-09-19 8:12 [PATCH 0/7] arc: Add new ARCv3 isa support to ARC's backend Claudiu Zissulescu ` (2 preceding siblings ...) 2023-09-19 8:12 ` [PATCH 3/7] arc: Add new ARCv3 ISA to BFD Claudiu Zissulescu @ 2023-09-19 8:12 ` Claudiu Zissulescu 2023-09-19 8:12 ` [PATCH 5/7] arc: Update opcode related include files for ARCv3 Claudiu Zissulescu ` (2 subsequent siblings) 6 siblings, 0 replies; 8+ messages in thread From: Claudiu Zissulescu @ 2023-09-19 8:12 UTC (permalink / raw) To: binutils; +Cc: Claudiu Zissulescu From: Claudiu Zissulescu <claziss@synopsys.com> Add ARCv3's linker bits. Remove obsolete tests. ld/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * ld/Makefile.am: Add ARC64 targets. * ld/configure.tgt: Likewise. * ld/Makefile.in: Regenerate. * ld/emulparams/arc64elf32.sh: New file. * ld/emulparams/arc64elf64.sh: Likewise. * ld/emulparams/arc64linux32.sh: Likewise. * ld/emulparams/arc64linux64.sh: Likewise. * ld/scripttempl/elfarc.sc: Update stack and heap definitions. * ld/testsuite/ld-arc/got-weak.d: Deleted file. * ld/testsuite/ld-arc/got-weak.s: Likewise. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com> --- ld/Makefile.am | 4 ++++ ld/Makefile.in | 8 ++++++++ ld/configure.tgt | 21 +++++++++++++++++++-- ld/emulparams/arc64elf32.sh | 12 ++++++++++++ ld/emulparams/arc64elf64.sh | 12 ++++++++++++ ld/emulparams/arc64linux32.sh | 22 ++++++++++++++++++++++ ld/emulparams/arc64linux64.sh | 22 ++++++++++++++++++++++ ld/scripttempl/elfarc.sc | 18 ++++-------------- ld/testsuite/ld-arc/got-weak.d | 12 ------------ ld/testsuite/ld-arc/got-weak.s | 7 ------- 10 files changed, 103 insertions(+), 35 deletions(-) create mode 100644 ld/emulparams/arc64elf32.sh create mode 100644 ld/emulparams/arc64elf64.sh create mode 100644 ld/emulparams/arc64linux32.sh create mode 100644 ld/emulparams/arc64linux64.sh delete mode 100644 ld/testsuite/ld-arc/got-weak.d delete mode 100644 ld/testsuite/ld-arc/got-weak.s diff --git a/ld/Makefile.am b/ld/Makefile.am index 9664d4c7709..1efb1726f65 100644 --- a/ld/Makefile.am +++ b/ld/Makefile.am @@ -391,6 +391,10 @@ ALL_64_EMULATION_SOURCES = \ eaarch64nto.c \ eaarch64pe.c \ earm64pe.c \ + earc64elf32.c \ + earc64elf64.c \ + earc64linux32.c \ + earc64linux64.c \ eelf32_x86_64.c \ eelf32b4300.c \ eelf32bmip.c \ diff --git a/ld/Makefile.in b/ld/Makefile.in index afd22d479ec..ce2fb16ec83 100644 --- a/ld/Makefile.in +++ b/ld/Makefile.in @@ -890,6 +890,10 @@ ALL_64_EMULATION_SOURCES = \ eaarch64nto.c \ eaarch64pe.c \ earm64pe.c \ + earc64elf32.c \ + earc64elf64.c \ + earc64linux32.c \ + earc64linux64.c \ eelf32_x86_64.c \ eelf32b4300.c \ eelf32bmip.c \ @@ -1279,6 +1283,10 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eaixrs6.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ealpha.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ealphavms.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earc64elf32.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earc64elf64.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earc64linux32.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earc64linux64.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earcelf.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earclinux.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earclinux_nps.Po@am__quote@ diff --git a/ld/configure.tgt b/ld/configure.tgt index ff0aaaae257..d69dee8c355 100644 --- a/ld/configure.tgt +++ b/ld/configure.tgt @@ -153,10 +153,27 @@ alpha*-*-*vms*) targ_emul=alphavms ;; am33_2.0-*-linux*) targ_emul=elf32am33lin # mn10300 variant ;; -arc*-*-elf*) targ_emul=arcelf +arc-*-elf* | arc[be]*-*-elf*) targ_emul=arcelf targ_extra_emuls="arclinux arclinux_nps arcv2elf arcv2elfx" ;; -arc*-*-linux*) case "${with_cpu}" in +arc64-*-elf*) targ_emul=arc64elf64 + targ_extra_emuls="arc64elf32 arc64linux64 arc64linux32" + targ_extra_libpath=$targ_extra_emuls + ;; +arc32-*-elf*) targ_emul=arc64elf32 + targ_extra_emuls="arc64linux32 arc64elf64 arc64linux64" + targ_extra_libpath=$targ_extra_emuls + ;; +arc64-*-linux*) targ_emul=arc64linux64 + targ_extra_emuls="arc64elf64 arc64elf32 arc64linux32" + targ_extra_libpath=$targ_extra_emuls + ;; +arc32-*-linux*) targ_emul=arc64linux32 + targ_extra_emuls="arc64elf32 arc64elf64 arc64linux64" + targ_extra_libpath=$targ_extra_emuls + ;; +arc-*-linux* | arc[eb]*-linux*) + case "${with_cpu}" in nps400) targ_emul=arclinux_nps targ_extra_emuls=arclinux ;; diff --git a/ld/emulparams/arc64elf32.sh b/ld/emulparams/arc64elf32.sh new file mode 100644 index 00000000000..0f8389a0a6f --- /dev/null +++ b/ld/emulparams/arc64elf32.sh @@ -0,0 +1,12 @@ +SCRIPT_NAME=elf +ELFSIZE=32 +SCRIPT_NAME=elfarc +TEMPLATE_NAME=elf +OUTPUT_FORMAT="elf32-littlearc64" + +TEXT_START_ADDR=0x00 + +MAXPAGESIZE="CONSTANT (MAXPAGESIZE)" +ARCH="arc64:32" +ENTRY=__start +EMBEDDED=yes diff --git a/ld/emulparams/arc64elf64.sh b/ld/emulparams/arc64elf64.sh new file mode 100644 index 00000000000..d4291345206 --- /dev/null +++ b/ld/emulparams/arc64elf64.sh @@ -0,0 +1,12 @@ +SCRIPT_NAME=elf +ELFSIZE=64 +SCRIPT_NAME=elfarc +TEMPLATE_NAME=elf +OUTPUT_FORMAT="elf64-littlearc64" + +TEXT_START_ADDR=0x00 + +MAXPAGESIZE="CONSTANT (MAXPAGESIZE)" +ARCH="arc64:64" +ENTRY=__start +EMBEDDED=yes diff --git a/ld/emulparams/arc64linux32.sh b/ld/emulparams/arc64linux32.sh new file mode 100644 index 00000000000..1ad8f3de41e --- /dev/null +++ b/ld/emulparams/arc64linux32.sh @@ -0,0 +1,22 @@ +ARCH="arc64:32" + +SCRIPT_NAME=elf +ELFSIZE=32 +OUTPUT_FORMAT="elf32-littlearc64" + +TEMPLATE_NAME=elf + +GENERATE_SHLIB_SCRIPT=yes +GENERATE_PIE_SCRIPT=yes + +MAXPAGESIZE="CONSTANT (MAXPAGESIZE)" +COMMONPAGESIZE="CONSTANT (COMMONPAGESIZE)" + +TEXT_START_ADDR=0x10000 + +ENTRY=__start + +# To support RELRO security feature. +NO_SMALL_DATA=yes +SEPARATE_GOTPLT="SIZEOF (.got.plt) >= 12 ? 12 : 0" +GENERATE_COMBRELOC_SCRIPT=yes diff --git a/ld/emulparams/arc64linux64.sh b/ld/emulparams/arc64linux64.sh new file mode 100644 index 00000000000..89ff73dc4f2 --- /dev/null +++ b/ld/emulparams/arc64linux64.sh @@ -0,0 +1,22 @@ +ARCH="arc64:64" + +SCRIPT_NAME=elf +ELFSIZE=64 +OUTPUT_FORMAT="elf64-littlearc64" + +TEMPLATE_NAME=elf + +GENERATE_SHLIB_SCRIPT=yes +GENERATE_PIE_SCRIPT=yes + +MAXPAGESIZE="CONSTANT (MAXPAGESIZE)" +COMMONPAGESIZE="CONSTANT (COMMONPAGESIZE)" + +TEXT_START_ADDR=0x10000 + +ENTRY=__start + +# To support RELRO security feature. +NO_SMALL_DATA=yes +SEPARATE_GOTPLT=8 #FIXME! what is the true value here? +GENERATE_COMBRELOC_SCRIPT=yes diff --git a/ld/scripttempl/elfarc.sc b/ld/scripttempl/elfarc.sc index 1ae0248a900..78cb0fa9540 100644 --- a/ld/scripttempl/elfarc.sc +++ b/ld/scripttempl/elfarc.sc @@ -394,20 +394,10 @@ test -n "${RELOCATING}" && cat <<EOF The options appear in the wrong order to do this with a single symbol - ldflags comes after flags injected with per-file stanzas, and thus the setting from ldflags prevails. */ - .heap : - { - __start_heap = . ; - . = . + (DEFINED(__HEAP_SIZE) ? __HEAP_SIZE : (DEFINED(__DEFAULT_HEAP_SIZE) ? __DEFAULT_HEAP_SIZE : 20k)) ; - __end_heap = . ; - } - - . = ALIGN(0x8); - .stack : - { - __stack = . ; - . = . + (DEFINED(__STACK_SIZE) ? __STACK_SIZE : (DEFINED(__DEFAULT_STACK_SIZE) ? __DEFAULT_STACK_SIZE : 64k)) ; - __stack_top = . ; - } + ${RELOCATING+. = ALIGN(${ALIGNMENT});} + ${RELOCATING+ PROVIDE (__start_heap = .) ; } + ${RELOCATING+ PROVIDE (__stack_top = . + (DEFINED(__HEAP_SIZE) ? __HEAP_SIZE : (DEFINED(__DEFAULT_HEAP_SIZE) ? __DEFAULT_HEAP_SIZE : 20k)) + (DEFINED(__STACK_SIZE) ? __STACK_SIZE : 64k));} + ${RELOCATING+ PROVIDE (__end_heap = . + (DEFINED(__HEAP_SIZE) ? __HEAP_SIZE : (DEFINED(__DEFAULT_STACK_SIZE) ? __DEFAULT_STACK_SIZE : 20k)));} EOF source_sh $srcdir/scripttempl/misc-sections.sc diff --git a/ld/testsuite/ld-arc/got-weak.d b/ld/testsuite/ld-arc/got-weak.d deleted file mode 100644 index a7f5b2fa119..00000000000 --- a/ld/testsuite/ld-arc/got-weak.d +++ /dev/null @@ -1,12 +0,0 @@ -#source: got-weak.s -#as: -#ld: -Bstatic -#objdump: -d - -[^:]*:\s+file format elf32-.*arc - - -Disassembly of section \.text: - -[0-9a-f]+ <.*>: -^\s+[0-9a-f]+:\s+2730\s7f80\s[0-9a-f]+\s[0-9a-f]+\s+ld\s+r\d+,\[pcl,.* diff --git a/ld/testsuite/ld-arc/got-weak.s b/ld/testsuite/ld-arc/got-weak.s deleted file mode 100644 index 8ea18be3780..00000000000 --- a/ld/testsuite/ld-arc/got-weak.s +++ /dev/null @@ -1,7 +0,0 @@ - .cpu archs - - .weak symb - .global __start - .text -__start: - ld r0,[pcl,@symb@gotpc] -- 2.30.2 ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 5/7] arc: Update opcode related include files for ARCv3. 2023-09-19 8:12 [PATCH 0/7] arc: Add new ARCv3 isa support to ARC's backend Claudiu Zissulescu ` (3 preceding siblings ...) 2023-09-19 8:12 ` [PATCH 4/7] arc: Add new linker emulation and scripts for ARCv3 ISA Claudiu Zissulescu @ 2023-09-19 8:12 ` Claudiu Zissulescu 2023-09-19 8:12 ` [PATCH 6/7] arc: Update ARC's Gnu Assembler backend with ARCv3 ISA Claudiu Zissulescu 2023-09-19 8:12 ` [PATCH 7/7] arc: Add new opcode functions for " Claudiu Zissulescu 6 siblings, 0 replies; 8+ messages in thread From: Claudiu Zissulescu @ 2023-09-19 8:12 UTC (permalink / raw) To: binutils; +Cc: Claudiu Zissulescu, Bruno Mauricio From: Claudiu Zissulescu <claziss@synopsys.com> Add new ARCv3 CPUs and required bits to decode/encode ARCv3 ISA opcodes. include/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * include/elf/arc-cpu.def: Add new HS5x and HS6x CPUs. * include/elf/arc-reloc.def: Add new ARC64 relocations. * include/elf/arc.h (EF_ARC_CPU_ARC64): New define. * include/opcode/arc-attrs.h (FEATURE_LIST_NAME): Update predicate. * include/opcode/arc-func.h: Update formating. (replace_disp8ls): New function. (replace_disp9s): Likewise. (replace_disp6s): Likewise. (replace_disp7s): Likewise. (replace_disp12s): Likewise. * include/opcode/arc.h (ARC_OPCODE_ARC64): New define. (ARC_OPCODE_ARC32): Likewise. (ARC_OPERAND_FP): Likewise. (HARD_FIELDF): Likewise. (ARC_OPCODE_ARCVx): New macro. (arc_flag_class): Update structure to hold new extract/insert functions for flags. (INSN3OP): Update macro. (FP_SIZE, TPOF, DPOF, SOPF, COPF, CONVOPS): New enums. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com> Relocations: Fix some 32 bit relocations Fix for issue #564 The following 32 bit relocations were set as signed but should be bitfield: ARC_32_ME, ARC_GLOB_DAT, ARC_JMP_SLOT, ARC_RELATIVE Signed-off-by: Bruno Mauricio <brunoasmauricio@gmail.com> Relocations: Remove unused relocation ARC_32_ME_S Fix for issue #565 Signed-off-by: Bruno Mauricio <brunoasmauricio@gmail.com> --- include/elf/arc-cpu.def | 63 +++++++------ include/elf/arc-reloc.def | 171 ++++++++++++++++++++++++++++++--- include/elf/arc.h | 1 + include/opcode/arc-attrs.h | 4 +- include/opcode/arc-func.h | 188 +++++++++++++++++++++++++++---------- include/opcode/arc.h | 121 +++++++++++++++++++++++- 6 files changed, 452 insertions(+), 96 deletions(-) diff --git a/include/elf/arc-cpu.def b/include/elf/arc-cpu.def index 8b039a1b426..49a35ab711a 100644 --- a/include/elf/arc-cpu.def +++ b/include/elf/arc-cpu.def @@ -19,35 +19,40 @@ 02110-1301, USA. */ -ARC_CPU_TYPE_A7xx (arc700, 0x00), -ARC_CPU_TYPE_A7xx (nps400, NPS400), - -ARC_CPU_TYPE_AV2EM (arcem, 0x00), -ARC_CPU_TYPE_AV2EM (em, 0x00), -ARC_CPU_TYPE_AV2EM (em_mini, 0x00), -ARC_CPU_TYPE_AV2EM (em4, CD), -ARC_CPU_TYPE_AV2EM (em4_dmips, CD), -ARC_CPU_TYPE_AV2EM (em4_fpus, CD), -ARC_CPU_TYPE_AV2EM (em4_fpuda, CD | DPA), -ARC_CPU_TYPE_AV2EM (quarkse_em, CD | SPX | DPX), - -ARC_CPU_TYPE_AV2HS (archs, CD), -ARC_CPU_TYPE_AV2HS (hs, CD), -ARC_CPU_TYPE_AV2HS (hs34, CD), -ARC_CPU_TYPE_AV2HS (hs38, CD), -ARC_CPU_TYPE_AV2HS (hs38_linux, CD), -ARC_CPU_TYPE_AV2HS (hs4x, CD), -ARC_CPU_TYPE_AV2HS (hs4xd, CD), -ARC_CPU_TYPE_AV2HS (hs4x_rel31, CD), - -ARC_CPU_TYPE_A6xx (arc600, 0x00), -ARC_CPU_TYPE_A6xx (arc600_norm, 0x00), -ARC_CPU_TYPE_A6xx (arc600_mul64, 0x00), -ARC_CPU_TYPE_A6xx (arc600_mul32x16, 0x00), -ARC_CPU_TYPE_A6xx (arc601, 0x00), -ARC_CPU_TYPE_A6xx (arc601_norm, 0x00), -ARC_CPU_TYPE_A6xx (arc601_mul64, 0x00), -ARC_CPU_TYPE_A6xx (arc601_mul32x16, 0x00), +ARC_CPU_TYPE_A64x (hs6x, CD | DIV) +ARC_CPU_TYPE_A32x (hs5x, CD | DIV) +ARC_CPU_TYPE_A64x (hs68, CD | DIV) +ARC_CPU_TYPE_A32x (hs58, CD | DIV) + +ARC_CPU_TYPE_A7xx (arc700, 0x00) +ARC_CPU_TYPE_A7xx (nps400, NPS400) + +ARC_CPU_TYPE_AV2EM (arcem, 0x00) +ARC_CPU_TYPE_AV2EM (em, 0x00) +ARC_CPU_TYPE_AV2EM (em_mini, 0x00) +ARC_CPU_TYPE_AV2EM (em4, CD) +ARC_CPU_TYPE_AV2EM (em4_dmips, CD) +ARC_CPU_TYPE_AV2EM (em4_fpus, CD) +ARC_CPU_TYPE_AV2EM (em4_fpuda, CD | DPA) +ARC_CPU_TYPE_AV2EM (quarkse_em, CD | SPX | DPX) + +ARC_CPU_TYPE_AV2HS (archs, CD) +ARC_CPU_TYPE_AV2HS (hs, CD) +ARC_CPU_TYPE_AV2HS (hs34, CD) +ARC_CPU_TYPE_AV2HS (hs38, CD) +ARC_CPU_TYPE_AV2HS (hs38_linux, CD) +ARC_CPU_TYPE_AV2HS (hs4x, CD) +ARC_CPU_TYPE_AV2HS (hs4xd, CD) +ARC_CPU_TYPE_AV2HS (hs4x_rel31, CD) + +ARC_CPU_TYPE_A6xx (arc600, 0x00) +ARC_CPU_TYPE_A6xx (arc600_norm, 0x00) +ARC_CPU_TYPE_A6xx (arc600_mul64, 0x00) +ARC_CPU_TYPE_A6xx (arc600_mul32x16, 0x00) +ARC_CPU_TYPE_A6xx (arc601, 0x00) +ARC_CPU_TYPE_A6xx (arc601_norm, 0x00) +ARC_CPU_TYPE_A6xx (arc601_mul64, 0x00) +ARC_CPU_TYPE_A6xx (arc601_mul32x16, 0x00) ARC_CPU_TYPE_NONE diff --git a/include/elf/arc-reloc.def b/include/elf/arc-reloc.def index 9d0e42e4447..fd04a55b1bf 100644 --- a/include/elf/arc-reloc.def +++ b/include/elf/arc-reloc.def @@ -64,6 +64,13 @@ ARC_RELOC_HOWTO(ARC_32, 4, \ bitfield, \ ( S + A )) +ARC_RELOC_HOWTO(ARC_64, 5, \ + 8, \ + 64, \ + replace_word64, \ + bitfield, \ + ( S + A )) + ARC_RELOC_HOWTO(ARC_N8, 8, \ 1, \ 8, \ @@ -201,14 +208,7 @@ ARC_RELOC_HOWTO(ARC_32_ME, 27, \ 4, \ 32, \ replace_limm, \ - signed, \ - ( ME ( ( S + A ) ) )) - -ARC_RELOC_HOWTO(ARC_32_ME_S, 105, \ - 4, \ - 32, \ - replace_limms, \ - signed, \ + bitfield, \ ( ME ( ( S + A ) ) )) ARC_RELOC_HOWTO(ARC_N32_ME, 28, \ @@ -369,21 +369,21 @@ ARC_RELOC_HOWTO(ARC_GLOB_DAT, 54, \ 4, \ 32, \ replace_word32, \ - signed, \ + bitfield, \ S) ARC_RELOC_HOWTO(ARC_JMP_SLOT, 55, \ 4, \ 32, \ replace_word32, \ - signed, \ + bitfield, \ ( ME ( S ) )) ARC_RELOC_HOWTO(ARC_RELATIVE, 56, \ 4, \ 32, \ replace_word32, \ - signed, \ + bitfield, \ ( ME ( ( B + A ) ) )) ARC_RELOC_HOWTO(ARC_GOTOFF, 57, \ @@ -511,3 +511,152 @@ ARC_RELOC_HOWTO(ARC_NPS_CMEM16, 78, \ replace_bits16, \ dont, \ ( ME ( S + A ))) + +ARC_RELOC_HOWTO(ARC_S9H_PCREL, 79, \ + 4, \ + 8, \ + replace_disp8ls, \ + signed, \ + ( ME ( ( ( ( S + A ) - P ) >> 1 ) ) ) ) + +ARC_RELOC_HOWTO(ARC_S7H_PCREL, 80, \ + 2, \ + 6, \ + replace_disp6s, \ + signed, \ + ( ( ( ( S + A ) - P ) >> 1 ) ) ) + +ARC_RELOC_HOWTO(ARC_S8H_PCREL, 81, \ + 2, \ + 7, \ + replace_disp7s, \ + signed, \ + ( ( ( ( S + A ) - P ) >> 1 ) ) ) + +ARC_RELOC_HOWTO(ARC_S10H_PCREL, 82, \ + 2, \ + 9, \ + replace_disp9s, \ + signed, \ + ( ( ( ( S + A ) - P ) >> 1 ) ) ) + +ARC_RELOC_HOWTO(ARC_S13H_PCREL, 83, \ + 4, \ + 12, \ + replace_disp12s, \ + signed, \ + ( ME ( ( ( ( S + A ) - P ) >> 1 ) ) ) ) + +ARC_RELOC_HOWTO(ARC_ALIGN, 84, \ + 4, \ + 0, \ + replace_none, \ + dont, \ + 0 ) + +ARC_RELOC_HOWTO(ARC_ADD8, 85, \ + 1, \ + 8, \ + replace_bits8, \ + dont, \ + ( S + A )) + +ARC_RELOC_HOWTO(ARC_ADD16, 86, \ + 2, \ + 16, \ + replace_bits16, \ + dont, \ + ( S + A )) + +ARC_RELOC_HOWTO(ARC_SUB8, 87, \ + 1, \ + 8, \ + replace_bits8, \ + dont, \ + ( A - S + ICARRY )) + +ARC_RELOC_HOWTO(ARC_SUB16, 88, \ + 2, \ + 16, \ + replace_bits16, \ + dont, \ + ( A - S + ICARRY )) + +ARC_RELOC_HOWTO(ARC_SUB32, 89, \ + 4, \ + 32, \ + replace_word32, \ + dont, \ + ( A - S + ICARRY)) + +ARC_RELOC_HOWTO(ARC_LO32, 90, \ + 4, \ + 32, \ + replace_word32, \ + dont, \ + ( ( S + A ) & 4294967295 )) + +ARC_RELOC_HOWTO(ARC_HI32, 91, \ + 4, \ + 32, \ + replace_word32, \ + dont, \ + ( ( S + A ) >> 32 )) + +ARC_RELOC_HOWTO(ARC_LO32_ME, 92, \ + 4, \ + 32, \ + replace_word32, \ + dont, \ + ( ME ( ( ( S + A ) & 4294967295 ) ) )) + +ARC_RELOC_HOWTO(ARC_HI32_ME, 93, \ + 4, \ + 32, \ + replace_word32, \ + dont, \ + ( ME ( ( ( S + A ) >> 32 ) ) )) + +ARC_RELOC_HOWTO(ARC_N64, 94, \ + 4, \ + 32, \ + replace_word32, \ + dont, \ + ( DEREFP - ( S + A ) )) + +ARC_RELOC_HOWTO(ARC_SDA_LDST3, 95, \ + 4, \ + 9, \ + replace_disp9ls, \ + signed, \ + ( ( ( S + A ) - _SDA_BASE_ ) >> 3 )) + +ARC_RELOC_HOWTO(ARC_NLO32, 96, \ + 4, \ + 32, \ + replace_word32, \ + dont, \ + ( DEREFP - ( ( S + A ) & 4294967295 ) )) + +ARC_RELOC_HOWTO(ARC_NLO32_ME, 97, \ + 4, \ + 32, \ + replace_word32, \ + dont, \ + ( ME ( ( DEREFP - ( ( S + A ) & 4294967295 ) ) ) )) + +ARC_RELOC_HOWTO(ARC_PCLO32_ME_2, 98, \ + 4, \ + 34, \ + replace_word32, \ + signed, \ + ( ME ( ( ( ( S + A ) - P ) >> 2 ) & 0xFFFFFFFF ) ) ) + + +ARC_RELOC_HOWTO(ARC_PLT34, 99, \ + 4, \ + 34, \ + replace_word32, \ + signed, \ + ( ME ( ( ( ( L + A ) - P ) >> 2 ) & 0xFFFFFFFF ) ) ) + diff --git a/include/elf/arc.h b/include/elf/arc.h index 57800e024cd..a6a84cc75b4 100644 --- a/include/elf/arc.h +++ b/include/elf/arc.h @@ -50,6 +50,7 @@ END_RELOC_NUMBERS (R_ARC_max) #define E_ARC_MACH_ARC700 0x00000003 #define EF_ARC_CPU_ARCV2EM 0x00000005 #define EF_ARC_CPU_ARCV2HS 0x00000006 +#define EF_ARC_CPU_ARC64 0x00000007 /* ARC Linux specific ABIs. */ #define E_ARC_OSABI_ORIG 0x00000000 /* MUST be 0 for back-compat. */ diff --git a/include/opcode/arc-attrs.h b/include/opcode/arc-attrs.h index f0478dc7dd4..01276a60fc1 100644 --- a/include/opcode/arc-attrs.h +++ b/include/opcode/arc-attrs.h @@ -37,8 +37,8 @@ const struct feature_type } FEATURE_LIST_NAME [] = { { BTSCN, ARC_OPCODE_ARCALL, "BITSCAN", "bit-scan" }, - { CD, ARC_OPCODE_ARCV2, "CD", "code-density" }, - { DIV, ARC_OPCODE_ARCV2, "DIV_REM", "div/rem" }, + { CD, ARC_OPCODE_ARCVx, "CD", "code-density" }, + { DIV, ARC_OPCODE_ARCVx, "DIV_REM", "div/rem" }, { DP, ARC_OPCODE_ARCv2HS, "FPUD", "double-precision FPU" }, { DPA, ARC_OPCODE_ARCv2EM, "FPUDA", "double assist FP" }, { DPX, ARC_OPCODE_ARCFPX, "DPFP", "double-precision FPX" }, diff --git a/include/opcode/arc-func.h b/include/opcode/arc-func.h index 65d21e38d96..78356101d04 100644 --- a/include/opcode/arc-func.h +++ b/include/opcode/arc-func.h @@ -22,8 +22,8 @@ /* mask = 00000000000000000000000000000000. */ #ifndef REPLACE_none #define REPLACE_none -ATTRIBUTE_UNUSED static unsigned -replace_none (unsigned insn, int value ATTRIBUTE_UNUSED) +ATTRIBUTE_UNUSED static bfd_vma +replace_none (bfd_vma insn, bfd_vma value ATTRIBUTE_UNUSED) { insn = insn & ~0x00; @@ -35,8 +35,8 @@ replace_none (unsigned insn, int value ATTRIBUTE_UNUSED) /* mask = 11111111. */ #ifndef REPLACE_bits8 #define REPLACE_bits8 -ATTRIBUTE_UNUSED static unsigned -replace_bits8 (unsigned insn, int value ATTRIBUTE_UNUSED) +ATTRIBUTE_UNUSED static bfd_vma +replace_bits8 (bfd_vma insn, bfd_vma value ATTRIBUTE_UNUSED) { insn = insn & ~0xff; insn |= ((value >> 0) & 0x00ff) << 0; @@ -49,8 +49,8 @@ replace_bits8 (unsigned insn, int value ATTRIBUTE_UNUSED) /* mask = 1111111111111111. */ #ifndef REPLACE_bits16 #define REPLACE_bits16 -ATTRIBUTE_UNUSED static unsigned -replace_bits16 (unsigned insn, int value ATTRIBUTE_UNUSED) +ATTRIBUTE_UNUSED static bfd_vma +replace_bits16 (bfd_vma insn, bfd_vma value ATTRIBUTE_UNUSED) { insn = insn & ~0xffff; insn |= ((value >> 0) & 0xffff) << 0; @@ -63,8 +63,8 @@ replace_bits16 (unsigned insn, int value ATTRIBUTE_UNUSED) /* mask = 111111111111111111111111. */ #ifndef REPLACE_bits24 #define REPLACE_bits24 -ATTRIBUTE_UNUSED static unsigned -replace_bits24 (unsigned insn, int value ATTRIBUTE_UNUSED) +ATTRIBUTE_UNUSED static bfd_vma +replace_bits24 (bfd_vma insn, bfd_vma value ATTRIBUTE_UNUSED) { insn = insn & ~0xffffff; insn |= ((value >> 0) & 0xffffff) << 0; @@ -78,8 +78,8 @@ replace_bits24 (unsigned insn, int value ATTRIBUTE_UNUSED) /* mask = 111111111111111111111111. */ #ifndef REPLACE_bits24_be #define REPLACE_bits24_be -ATTRIBUTE_UNUSED static unsigned -replace_bits24_be (unsigned insn, int value ATTRIBUTE_UNUSED) +ATTRIBUTE_UNUSED static bfd_vma +replace_bits24_be (bfd_vma insn, bfd_vma value ATTRIBUTE_UNUSED) { insn = insn & ~0xffffff00; insn |= ((value >> 0) & 0xffffff) << 8; @@ -87,27 +87,39 @@ replace_bits24_be (unsigned insn, int value ATTRIBUTE_UNUSED) return insn; } -#endif /* REPLACE_bits24_be */ +#endif /* REPLACE_bits24_be. */ /* mask = 11111111111111111111111111111111. */ #ifndef REPLACE_word32 #define REPLACE_word32 -ATTRIBUTE_UNUSED static unsigned -replace_word32 (unsigned insn, int value ATTRIBUTE_UNUSED) +ATTRIBUTE_UNUSED static bfd_vma +replace_word32 (bfd_vma insn, bfd_vma value ATTRIBUTE_UNUSED) { insn = insn & ~0xffffffff; insn |= ((value >> 0) & 0xffffffff) << 0; return insn; } +#endif /* REPLACE_word32. */ + +/* mask = 1111111111111111111111111111111111111111111111111111111111111111. */ +#ifndef REPLACE_word64 +#define REPLACE_word64 +ATTRIBUTE_UNUSED static bfd_vma +replace_word64 (bfd_vma insn, bfd_vma value) +{ + insn |= value; + + return insn; +} +#endif /* REPLACE_word64. */ -#endif /* REPLACE_word32 */ /* mask = 0000000000000000000000000000000011111111111111111111111111111111. */ #ifndef REPLACE_limm #define REPLACE_limm -ATTRIBUTE_UNUSED static unsigned -replace_limm (unsigned insn, int value ATTRIBUTE_UNUSED) +ATTRIBUTE_UNUSED static bfd_vma +replace_limm (bfd_vma insn, bfd_vma value ATTRIBUTE_UNUSED) { insn = insn & ~0xffffffff; insn |= ((value >> 0) & 0xffffffff) << 0; @@ -115,13 +127,13 @@ replace_limm (unsigned insn, int value ATTRIBUTE_UNUSED) return insn; } -#endif /* REPLACE_limm */ +#endif /* REPLACE_limm. */ /* mask = 000000000000000011111111111111111111111111111111. */ #ifndef REPLACE_limms #define REPLACE_limms -ATTRIBUTE_UNUSED static unsigned -replace_limms (unsigned insn, int value ATTRIBUTE_UNUSED) +ATTRIBUTE_UNUSED static bfd_vma +replace_limms (bfd_vma insn, bfd_vma value ATTRIBUTE_UNUSED) { insn = insn & ~0xffffffff; insn |= ((value >> 0) & 0xffffffff) << 0; @@ -129,13 +141,13 @@ replace_limms (unsigned insn, int value ATTRIBUTE_UNUSED) return insn; } -#endif /* REPLACE_limms */ +#endif /* REPLACE_limms. */ /* mask = 00000111111111102222222222000000. */ #ifndef REPLACE_disp21h #define REPLACE_disp21h -ATTRIBUTE_UNUSED static unsigned -replace_disp21h (unsigned insn, int value ATTRIBUTE_UNUSED) +ATTRIBUTE_UNUSED static bfd_vma +replace_disp21h (bfd_vma insn, bfd_vma value ATTRIBUTE_UNUSED) { insn = insn & ~0x7feffc0; insn |= ((value >> 0) & 0x03ff) << 17; @@ -144,13 +156,13 @@ replace_disp21h (unsigned insn, int value ATTRIBUTE_UNUSED) return insn; } -#endif /* REPLACE_disp21h */ +#endif /* REPLACE_disp21h. */ /* mask = 00000111111111002222222222000000. */ #ifndef REPLACE_disp21w #define REPLACE_disp21w -ATTRIBUTE_UNUSED static unsigned -replace_disp21w (unsigned insn, int value ATTRIBUTE_UNUSED) +ATTRIBUTE_UNUSED static bfd_vma +replace_disp21w (bfd_vma insn, bfd_vma value ATTRIBUTE_UNUSED) { insn = insn & ~0x7fcffc0; insn |= ((value >> 0) & 0x01ff) << 18; @@ -159,13 +171,13 @@ replace_disp21w (unsigned insn, int value ATTRIBUTE_UNUSED) return insn; } -#endif /* REPLACE_disp21w */ +#endif /* REPLACE_disp21w. */ /* mask = 00000111111111102222222222003333. */ #ifndef REPLACE_disp25h #define REPLACE_disp25h -ATTRIBUTE_UNUSED static unsigned -replace_disp25h (unsigned insn, int value ATTRIBUTE_UNUSED) +ATTRIBUTE_UNUSED static bfd_vma +replace_disp25h (bfd_vma insn, bfd_vma value ATTRIBUTE_UNUSED) { insn = insn & ~0x7feffcf; insn |= ((value >> 0) & 0x03ff) << 17; @@ -175,13 +187,13 @@ replace_disp25h (unsigned insn, int value ATTRIBUTE_UNUSED) return insn; } -#endif /* REPLACE_disp25h */ +#endif /* REPLACE_disp25h. */ /* mask = 00000111111111002222222222003333. */ #ifndef REPLACE_disp25w #define REPLACE_disp25w -ATTRIBUTE_UNUSED static unsigned -replace_disp25w (unsigned insn, int value ATTRIBUTE_UNUSED) +ATTRIBUTE_UNUSED static bfd_vma +replace_disp25w (bfd_vma insn, bfd_vma value ATTRIBUTE_UNUSED) { insn = insn & ~0x7fcffcf; insn |= ((value >> 0) & 0x01ff) << 18; @@ -191,13 +203,13 @@ replace_disp25w (unsigned insn, int value ATTRIBUTE_UNUSED) return insn; } -#endif /* REPLACE_disp25w */ +#endif /* REPLACE_disp25w. */ /* mask = 00000000000000000000000111111111. */ #ifndef REPLACE_disp9 #define REPLACE_disp9 -ATTRIBUTE_UNUSED static unsigned -replace_disp9 (unsigned insn, int value ATTRIBUTE_UNUSED) +ATTRIBUTE_UNUSED static bfd_vma +replace_disp9 (bfd_vma insn, bfd_vma value ATTRIBUTE_UNUSED) { insn = insn & ~0x1ff; insn |= ((value >> 0) & 0x01ff) << 0; @@ -205,13 +217,13 @@ replace_disp9 (unsigned insn, int value ATTRIBUTE_UNUSED) return insn; } -#endif /* REPLACE_disp9 */ +#endif /* REPLACE_disp9. */ /* mask = 00000000111111112000000000000000. */ #ifndef REPLACE_disp9ls #define REPLACE_disp9ls -ATTRIBUTE_UNUSED static unsigned -replace_disp9ls (unsigned insn, int value ATTRIBUTE_UNUSED) +ATTRIBUTE_UNUSED static bfd_vma +replace_disp9ls (bfd_vma insn, bfd_vma value ATTRIBUTE_UNUSED) { insn = insn & ~0xff8000; insn |= ((value >> 0) & 0x00ff) << 16; @@ -225,8 +237,8 @@ replace_disp9ls (unsigned insn, int value ATTRIBUTE_UNUSED) /* mask = 0000000111111111. */ #ifndef REPLACE_disp9s #define REPLACE_disp9s -ATTRIBUTE_UNUSED static unsigned -replace_disp9s (unsigned insn, int value ATTRIBUTE_UNUSED) +ATTRIBUTE_UNUSED static bfd_vma +replace_disp9s (bfd_vma insn, bfd_vma value ATTRIBUTE_UNUSED) { insn = insn & ~0x1ff; insn |= ((value >> 0) & 0x01ff) << 0; @@ -234,13 +246,13 @@ replace_disp9s (unsigned insn, int value ATTRIBUTE_UNUSED) return insn; } -#endif /* REPLACE_disp9s */ +#endif /* REPLACE_disp9s. */ /* mask = 0000011111111111. */ #ifndef REPLACE_disp13s #define REPLACE_disp13s -ATTRIBUTE_UNUSED static unsigned -replace_disp13s (unsigned insn, int value ATTRIBUTE_UNUSED) +ATTRIBUTE_UNUSED static bfd_vma +replace_disp13s (bfd_vma insn, bfd_vma value ATTRIBUTE_UNUSED) { insn = insn & ~0x7ff; insn |= ((value >> 0) & 0x07ff) << 0; @@ -248,13 +260,13 @@ replace_disp13s (unsigned insn, int value ATTRIBUTE_UNUSED) return insn; } -#endif /* REPLACE_disp13s */ +#endif /* REPLACE_disp13s. */ /* mask = 0000022222200111. */ #ifndef REPLACE_disp9s1 #define REPLACE_disp9s1 -ATTRIBUTE_UNUSED static unsigned -replace_disp9s1 (unsigned insn, int value ATTRIBUTE_UNUSED) +ATTRIBUTE_UNUSED static bfd_vma +replace_disp9s1 (bfd_vma insn, bfd_vma value ATTRIBUTE_UNUSED) { insn = insn & ~0x7e7; insn |= ((value >> 0) & 0x0007) << 0; @@ -263,13 +275,13 @@ replace_disp9s1 (unsigned insn, int value ATTRIBUTE_UNUSED) return insn; } -#endif /* REPLACE_disp9s1 */ +#endif /* REPLACE_disp9s1. */ /* mask = 00000000000000000000111111222222. */ #ifndef REPLACE_disp12s #define REPLACE_disp12s -ATTRIBUTE_UNUSED static unsigned -replace_disp12s (unsigned insn, int value ATTRIBUTE_UNUSED) +ATTRIBUTE_UNUSED static bfd_vma +replace_disp12s (bfd_vma insn, bfd_vma value ATTRIBUTE_UNUSED) { insn = insn & ~0xfff; insn |= ((value >> 0) & 0x003f) << 6; @@ -277,13 +289,13 @@ replace_disp12s (unsigned insn, int value ATTRIBUTE_UNUSED) return insn; } -#endif /* REPLACE_disp12s */ +#endif /* REPLACE_disp12s. */ /* mask = 0000001111111111. */ #ifndef REPLACE_jli #define REPLACE_jli -ATTRIBUTE_UNUSED static unsigned -replace_jli (unsigned insn, int value) +ATTRIBUTE_UNUSED static bfd_vma +replace_jli (bfd_vma insn, bfd_vma value) { insn = insn & ~0x3ff; insn |= ((value >> 0) & 0x03ff) << 0; @@ -291,4 +303,76 @@ replace_jli (unsigned insn, int value) return insn; } -#endif /* REPLACE_jli */ +#endif /* REPLACE_jli. */ + +#ifndef REPLACE_disp8ls +#define REPLACE_disp8ls +/* mask = 0000 0000 1111 1110 2000 0000 0000 0000. */ +ATTRIBUTE_UNUSED static bfd_vma +replace_disp8ls (bfd_vma insn, bfd_vma value ATTRIBUTE_UNUSED) +{ + insn = insn & ~0xfe8000; + insn |= ((value >> 0) & 0x007f) << 17; + insn |= ((value >> 7) & 0x0001) << 15; + + return insn; +} +#endif /* REPLACE_disp8ls. */ + +#ifndef REPLACE_disp9s +#define REPLACE_disp9s +/* mask = 0000000111111111 + insn = 1111001sssssssss. */ +static bfd_vma +replace_disp9s (bfd_vma insn, bfd_vma value ATTRIBUTE_UNUSED) +{ + insn = insn & ~0x1ff; + insn |= ((value >> 0) & 0x01ff) << 0; + + return insn; +} +#endif /* REPLACE_disp9s. */ + +#ifndef REPLACE_disp6s +#define REPLACE_disp6s +/* mask = 0000000000111111 + insn = 1111011000ssssss. */ +ATTRIBUTE_UNUSED static bfd_vma +replace_disp6s (bfd_vma insn, bfd_vma value ATTRIBUTE_UNUSED) +{ + insn = insn & ~0x3f; + insn |= ((value >> 0) & 0x003f) << 0; + + return insn; +} + +#endif /* REPLACE_disp6s. */ + +#ifndef REPLACE_disp7s +#define REPLACE_disp7s +/* mask = 0000000001111111 + insn = 11101bbb1sssssss. */ +ATTRIBUTE_UNUSED static bfd_vma +replace_disp7s (bfd_vma insn, bfd_vma value ATTRIBUTE_UNUSED) +{ + insn = insn & ~0x7f; + insn |= ((value >> 0) & 0x007f) << 0; + + return insn; +} +#endif /* REPLACE_disp7s. */ + +#ifndef REPLACE_disp12s +#define REPLACE_disp12s +/* mask = 00000000000000000000111111222222 + insn = 00100RRR101010000RRRssssssSSSSSS. */ +ATTRIBUTE_UNUSED static bfd_vma +replace_disp12s (bfd_vma insn, bfd_vma value ATTRIBUTE_UNUSED) +{ + insn = insn & ~0xfff; + insn |= ((value >> 0) & 0x003f) << 6; + insn |= ((value >> 6) & 0x003f) << 0; + + return insn; +} +#endif /* REPLACE_disp12s. */ diff --git a/include/opcode/arc.h b/include/opcode/arc.h index 0fae8740722..fe3278ab706 100644 --- a/include/opcode/arc.h +++ b/include/opcode/arc.h @@ -199,13 +199,19 @@ extern int arc_opcode_len (const struct arc_opcode *opcode); #define ARC_OPCODE_ARC700 0x0002 /* ARC 700 specific insns. */ #define ARC_OPCODE_ARCv2EM 0x0004 /* ARCv2 EM specific insns. */ #define ARC_OPCODE_ARCv2HS 0x0008 /* ARCv2 HS specific insns. */ +#define ARC_OPCODE_ARC64 0x0010 /* ARC64 specific insns. */ +#define ARC_OPCODE_ARC32 0x0020 /* ARC32 specific insns. */ /* CPU combi. */ #define ARC_OPCODE_ARCALL (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 \ - | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS) + | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS \ + | ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32) #define ARC_OPCODE_ARCFPX (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM) #define ARC_OPCODE_ARCV1 (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700) #define ARC_OPCODE_ARCV2 (ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS) +#define ARC_OPCODE_ARCVx \ + (ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64 \ + | ARC_OPCODE_ARC32) #define ARC_OPCODE_ARCMPY6E (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCV2) /* The operands table is an array of struct arc_operand. */ @@ -325,6 +331,9 @@ extern const unsigned arc_NToperand; /* Mark the colon position. */ #define ARC_OPERAND_COLON 0x4000 +/* Mark a floating point register. */ +#define ARC_OPERAND_FP 0x8000 + /* Mask for selecting the type for typecheck purposes. */ #define ARC_OPERAND_TYPECHECK_MASK \ (ARC_OPERAND_IR \ @@ -369,6 +378,16 @@ struct arc_flag_class /* List of valid flags (codes). */ unsigned flags[256]; + + /* Some special cases needs to use insert/extract functions for + flags as well. The function prototypes are identically like the + one used for insertion/extraction of an operand. The reason + beeing the ability of reusing these functions. */ + unsigned long long (*insert) (unsigned long long instruction, + long long int op, + const char **errmsg); + long long int (*extract) (unsigned long long instruction, + bool *invalid); }; extern const struct arc_flag_class arc_flag_classes[]; @@ -441,6 +460,8 @@ struct arc_pseudo_insn extern const struct arc_pseudo_insn arc_pseudo_insns[]; extern const unsigned arc_num_pseudo_insn; +extern const struct arc_pseudo_insn arc64_pseudo_insns[]; +extern const unsigned arc64_num_pseudo_insn; /* Structure for AUXILIARY registers. */ struct arc_aux_reg @@ -478,8 +499,10 @@ extern const unsigned arc_num_relax_opcodes; #define FIELDC(word) ((word & 0x3F) << 6) #define FIELDF (0x01 << 15) #define FIELDQ (0x1F) +#define HARD_FIELDF (0x00) -#define INSN3OP(MOP,SOP) (((MOP & 0x1F) << 27) | ((SOP & 0x3F) << 16)) +#define INSN3OP(MOP,SOP) \ + (((MOP & 0x1F) << 27) | ((SOP & 0x3F) << 16) | HARD_FIELDF) #define INSN2OPX(MOP,SOP1,SOP2) (INSN3OP (MOP,SOP1) | (SOP2 & 0x3F)) #define INSN2OP(MOP,SOP) (INSN2OPX (MOP,0x2F,SOP)) @@ -667,6 +690,100 @@ typedef enum #define ARC_NUM_ADDRTYPES 16 +/*ARC64 floating point enums. */ +#define P_HALF 0 +#define P_SINGLE 1 +#define P_DOUBLE 2 + +#define TOPF_FMADD 0 +#define TOPF_FMSUB 1 +#define TOPF_FNMADD 2 +#define TOPF_FNMSUB 3 +#define TOPF_VFMADD 4 +#define TOPF_VFMSUB 5 +#define TOPF_VFNMADD 6 +#define TOPF_VFNMSUB 7 +#define TOPF_VFMADDS 0xC +#define TOPF_VFMSUBS 0xD +#define TOPF_VFNMADDS 0xE +#define TOPF_VFNMSUBS 0xF + +#define DOPF_FADD 0 +#define DOPF_FSUB 1 +#define DOPF_FMUL 2 +#define DOPF_FDIV 3 +#define DOPF_FCMP 4 +#define DOPF_FCMPF 5 +#define DOPF_FMIN 6 +#define DOPF_FMAX 7 +#define DOPF_FSGNJ 8 +#define DOPF_FSGNJN 10 +#define DOPF_FSGNJX 11 +#define DOPF_VFADD 0x10 +#define DOPF_VFSUB 0x11 +#define DOPF_VFMUL 0x12 +#define DOPF_VFDIV 0x13 +#define DOPF_VFADDS 0x14 +#define DOPF_VFSUBS 0x15 +#define DOPF_VFMULS 0x16 +#define DOPF_VFDIVS 0x17 +#define DOPF_VFUNPKL 0x18 +#define DOPF_VFUNPKM 0x19 +#define DOPF_VFPACKL 0x1a +#define DOPF_VFPACKM 0x1b +#define DOPF_VFBFLYL 0x1c +#define DOPF_VFBFLYM 0x1d +#define DOPF_VFADDSUB 0x1e +#define DOPF_VFSUBADD 0x1f + +#define SOPF_FSQRT 0 +#define SOPF_VFSQRT 1 +#define SOPF_VFEXCH 2 + +#define COPF_FMOV 0 +#define COPF_VFMOV 1 + +#define FUINT2S 0 +#define FS2UINT 0 +#define FINT2S 0 +#define FS2INT 0 +#define FSRND 0 +#define F2UINT_RZ 0 +#define FSINT_RZ 0 +#define FSRND_RZ 0 +#define FMVI2S 0 +#define FMVS2I 0 +#define FS2H 0 +#define FH2S 0 +#define FS2H_RZ 0 + +#define FUINT2D 1 +#define FS2UL 1 +#define FINT2D 1 +#define FS2L 1 +#define FS2D 1 +#define FS2UL_RZ 1 +#define FS2L_RZ 1 + +#define FUL2S 2 +#define FD2UINT 2 +#define FL2S 2 +#define FD2INT 2 +#define FD2S 2 +#define FD2UINT_RZ 2 +#define FD2INT_RZ 2 + +#define FUL2D 3 +#define FD2UL 3 +#define FL2D 3 +#define FD2L 3 +#define FDRND 3 +#define FD2UL_RZ 3 +#define FD2L_RZ 3 +#define FDRND_RZ 3 +#define FMVL2D 3 +#define FMVD2L 3 + #ifdef __cplusplus } #endif -- 2.30.2 ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 6/7] arc: Update ARC's Gnu Assembler backend with ARCv3 ISA. 2023-09-19 8:12 [PATCH 0/7] arc: Add new ARCv3 isa support to ARC's backend Claudiu Zissulescu ` (4 preceding siblings ...) 2023-09-19 8:12 ` [PATCH 5/7] arc: Update opcode related include files for ARCv3 Claudiu Zissulescu @ 2023-09-19 8:12 ` Claudiu Zissulescu 2023-09-19 8:12 ` [PATCH 7/7] arc: Add new opcode functions for " Claudiu Zissulescu 6 siblings, 0 replies; 8+ messages in thread From: Claudiu Zissulescu @ 2023-09-19 8:12 UTC (permalink / raw) To: binutils; +Cc: Claudiu Zissulescu From: Claudiu Zissulescu <claziss@synopsys.com> The new Synopsys ARCv3 ISA has a similar instruction format like the old ARCv1 and ARCv2 ISA. Thus, the ARCv3 addition is using whatever we have for old ARC processors plus some ARCv3 spcific mods. To distinguish between various ARC variants, we introduced two new configure defines named TARGET_ARCv3_32 and TARGET_ARCv3_64 which are set when we choose either an ARC32 (ARCv3/32) ISA toolchain or an ARC64 (ARCv3/64) ISA toolchain. gas/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * gas/config/tc-arc.h: Selectively define default target macros. * gas/configure.ac: Add ARC64 target. * gas/configure.tgt: Likewise. * gas/configure: Regenerate * gas/config.in: Regenerate. * gas/config/tc-arc.c (DEFAULT_ARCH): New macro. (default_arch): New variable. (md_pseudo_table): Add xword. (md_shortopts): Only a few options are recognized by the new ARC64 assembler. (md_longopts): Likewise. (ARC_CPU_TYPE_A64x): New define. (ARC_CPU_TYPE_A32x): Likewise. (cpu_type): New arch field. (selected_cpu): Update fields. (arc_opcode_hash_entry_iterator_init): Formating. (arc_opcode_hash_entry_iterator_next): Likewise. (arc_select_cpu): Likewise. (arc_option): Likewise. (check_cpu_feature): Likewise. (debug_exp): Recognize new expression operands. (parse_reloc_symbol): Parse new signed/unsigend cases. (parse_opcode_flags): Update for the case when the flags needs insert/extract functions. (find_opcode_match): Match new signed/unsigned 32-bit immediates. (autodetect_attributes): PLT34 only available for ARC64. (md_assemble): Extend match characters. (declare_fp_set): New function. (init_default_arch): Likewise. (md_begin): Detect and initialize the correct CPU and coresponding registers. (md_pcrel_from_section): Add new relocs. (arc_target_format): New function. (md_apply_fix): Add new relocs. (md_parse_option): Update options. (arc_show_cpu_list): Update with ARC64 cpus. (md_show_usage): Update messages. (may_relax_expr): Add PLT34 case. (assemble_insn): Update for ARC64. (arc_make_nops): New function. (arc_handle_align): Refurbish this function, use arc_make_nops. (tc_arc_fix_adjustable): Update messages. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com> add patch 11 --- gas/config.in | 6 + gas/config/tc-arc.c | 723 ++++++++++++++++++++++++++++++-------------- gas/config/tc-arc.h | 46 +-- gas/configure | 14 +- gas/configure.ac | 10 +- gas/configure.tgt | 5 +- 6 files changed, 563 insertions(+), 241 deletions(-) diff --git a/gas/config.in b/gas/config.in index 232bc350759..ec6d08bd123 100644 --- a/gas/config.in +++ b/gas/config.in @@ -237,6 +237,12 @@ /* Target alias. */ #undef TARGET_ALIAS +/* Using ARCv3/32 architecture. */ +#undef TARGET_ARCv3_32 + +/* Using ARCv3/64 architecture. */ +#undef TARGET_ARCv3_64 + /* Define as 1 if big endian. */ #undef TARGET_BYTES_BIG_ENDIAN diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c index d9b13a0388e..186966ef91c 100644 --- a/gas/config/tc-arc.c +++ b/gas/config/tc-arc.c @@ -48,6 +48,11 @@ #define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) \ && (SUB_OPCODE (x) == 0x28)) + +#ifndef DEFAULT_ARCH +#define DEFAULT_ARCH "arc" +#endif /* DEFAULT_ARCH. */ + #ifndef TARGET_WITH_CPU #define TARGET_WITH_CPU "hs38_linux" #endif /* TARGET_WITH_CPU */ @@ -121,6 +126,9 @@ enum arc_rlx_types /* Generic assembler global variables which must be defined by all targets. */ +/* Default architecture. */ +static const char default_arch[] = DEFAULT_ARCH; + /* Characters which always start a comment. */ const char comment_chars[] = "#;"; @@ -141,7 +149,6 @@ const char FLT_CHARS[] = "rRsSfFdD"; /* Byte order. */ extern int target_big_endian; -const char *arc_target_format = DEFAULT_TARGET_FORMAT; static int byte_order = DEFAULT_BYTE_ORDER; /* Arc extension section. */ @@ -164,6 +171,9 @@ const pseudo_typeS md_pseudo_table[] = { /* Make sure that .word is 32 bits. */ { "word", cons, 4 }, +#if defined (TARGET_ARCv3_64) || defined (TARGET_ARCv3_32) + { "xword", cons, 8}, +#endif { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */ { "lcomm", arc_lcomm, 0 }, @@ -186,18 +196,21 @@ const char *md_shortopts = ""; enum options { - OPTION_EB = OPTION_MD_BASE, - OPTION_EL, + OPTION_MCPU = OPTION_MD_BASE, + + OPTION_CD, + OPTION_RELAX, + OPTION_LINKER_RELAX, +#if !defined (TARGET_ARCv3_64) && !defined (TARGET_ARCv3_32) + OPTION_EB, + OPTION_EL, OPTION_ARC600, OPTION_ARC601, OPTION_ARC700, OPTION_ARCEM, OPTION_ARCHS, - OPTION_MCPU, - OPTION_CD, - OPTION_RELAX, OPTION_NPS400, OPTION_SPFP, @@ -226,13 +239,19 @@ enum options OPTION_LOCK, OPTION_SWAPE, OPTION_RTSC +#endif }; struct option md_longopts[] = { + { "mcpu", required_argument, NULL, OPTION_MCPU }, + { "mcode-density", no_argument, NULL, OPTION_CD }, + { "mrelax", no_argument, NULL, OPTION_RELAX }, + { "mlinker-relax", no_argument, NULL, OPTION_LINKER_RELAX }, + +#if !defined (TARGET_ARCv3_64) && !defined (TARGET_ARCv3_32) { "EB", no_argument, NULL, OPTION_EB }, { "EL", no_argument, NULL, OPTION_EL }, - { "mcpu", required_argument, NULL, OPTION_MCPU }, { "mA6", no_argument, NULL, OPTION_ARC600 }, { "mARC600", no_argument, NULL, OPTION_ARC600 }, { "mARC601", no_argument, NULL, OPTION_ARC601 }, @@ -240,9 +259,7 @@ struct option md_longopts[] = { "mA7", no_argument, NULL, OPTION_ARC700 }, { "mEM", no_argument, NULL, OPTION_ARCEM }, { "mHS", no_argument, NULL, OPTION_ARCHS }, - { "mcode-density", no_argument, NULL, OPTION_CD }, - { "mrelax", no_argument, NULL, OPTION_RELAX }, - { "mnps400", no_argument, NULL, OPTION_NPS400 }, + { "mnps400", no_argument, NULL, OPTION_NPS400 }, /* Floating point options */ { "mspfp", no_argument, NULL, OPTION_SPFP}, @@ -287,8 +304,9 @@ struct option md_longopts[] = { "mlock", no_argument, NULL, OPTION_LOCK}, { "mswape", no_argument, NULL, OPTION_SWAPE}, { "mrtsc", no_argument, NULL, OPTION_RTSC}, +#endif - { NULL, no_argument, NULL, 0 } + { NULL, no_argument, NULL, 0 } }; size_t md_longopts_size = sizeof (md_longopts); @@ -437,25 +455,41 @@ static htab_t arc_aux_hash; /* The hash table of address types. */ static htab_t arc_addrtype_hash; -#define ARC_CPU_TYPE_A6xx(NAME,EXTRA) \ - { #NAME, ARC_OPCODE_ARC600, bfd_mach_arc_arc600, \ - E_ARC_MACH_ARC600, EXTRA} -#define ARC_CPU_TYPE_A7xx(NAME,EXTRA) \ - { #NAME, ARC_OPCODE_ARC700, bfd_mach_arc_arc700, \ - E_ARC_MACH_ARC700, EXTRA} -#define ARC_CPU_TYPE_AV2EM(NAME,EXTRA) \ - { #NAME, ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2, \ - EF_ARC_CPU_ARCV2EM, EXTRA} -#define ARC_CPU_TYPE_AV2HS(NAME,EXTRA) \ - { #NAME, ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2, \ - EF_ARC_CPU_ARCV2HS, EXTRA} -#define ARC_CPU_TYPE_NONE \ - { 0, 0, 0, 0, 0 } +#if !defined (TARGET_ARCv3_64) && !defined (TARGET_ARCv3_32) +# define ARC_CPU_TYPE_A6xx(NAME,EXTRA) \ + { #NAME, "arc", ARC_OPCODE_ARC600, bfd_mach_arc_arc600, \ + E_ARC_MACH_ARC600, EXTRA}, +# define ARC_CPU_TYPE_A7xx(NAME,EXTRA) \ + { #NAME, "arc", ARC_OPCODE_ARC700, bfd_mach_arc_arc700, \ + E_ARC_MACH_ARC700, EXTRA}, +# define ARC_CPU_TYPE_AV2EM(NAME,EXTRA) \ + { #NAME, "arc", ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2, \ + EF_ARC_CPU_ARCV2EM, EXTRA}, +# define ARC_CPU_TYPE_AV2HS(NAME,EXTRA) \ + { #NAME, "arc", ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2, \ + EF_ARC_CPU_ARCV2HS, EXTRA}, +# define ARC_CPU_TYPE_A64x(NAME,EXTRA) +# define ARC_CPU_TYPE_A32x(NAME,EXTRA) +#else +# define ARC_CPU_TYPE_A6xx(NAME,EXTRA) +# define ARC_CPU_TYPE_A7xx(NAME,EXTRA) +# define ARC_CPU_TYPE_AV2EM(NAME,EXTRA) +# define ARC_CPU_TYPE_AV2HS(NAME,EXTRA) +# define ARC_CPU_TYPE_A64x(NAME,EXTRA) \ + { #NAME, "arc64", ARC_OPCODE_ARC64, bfd_mach_arcv3_64, \ + EF_ARC_CPU_ARC64, EXTRA}, +# define ARC_CPU_TYPE_A32x(NAME,EXTRA) \ + { #NAME, "arc64", ARC_OPCODE_ARC32, bfd_mach_arcv3_32, \ + 0x00, EXTRA}, +#endif +#define ARC_CPU_TYPE_NONE \ + { 0, 0, 0, 0, 0, 0 } /* A table of CPU names and opcode sets. */ static const struct cpu_type { const char *name; + const char *arch; unsigned flags; int mach; unsigned eflags; @@ -467,7 +501,7 @@ static const struct cpu_type }; /* Information about the cpu/variant we're assembling for. */ -static struct cpu_type selected_cpu = { 0, 0, 0, E_ARC_OSABI_CURRENT, 0 }; +static struct cpu_type selected_cpu = { 0, 0, 0, 0, E_ARC_OSABI_CURRENT, 0 }; /* TRUE if current assembly code uses RF16 only registers. */ static bool rf16_only = true; @@ -475,7 +509,7 @@ static bool rf16_only = true; /* MPY option. */ static unsigned mpy_option = 0; -/* Use PIC. */ +/* Use PIC. */ static unsigned pic_option = 0; /* Use small data. */ @@ -499,7 +533,14 @@ static unsigned cl_features = 0; #define O_tpoff O_md9 /* @tpoff relocation. */ #define O_dtpoff9 O_md10 /* @dtpoff9 relocation. */ #define O_dtpoff O_md11 /* @dtpoff relocation. */ -#define O_last O_dtpoff +#if defined (TARGET_ARCv3_64) || defined (TARGET_ARCv3_32) +# define O_u32 O_md12 /* @u32 modifier. */ +# define O_s32 O_md13 /* @s32 modifier. */ +# define O_plt34 O_md14 /* @plt34 relocation. */ +# define O_last O_md14 +#else +# define O_last O_md11 +#endif /* Used to define a bracket as operand in tokens. */ #define O_bracket O_md32 @@ -552,6 +593,11 @@ static const struct arc_reloc_op_tag DEF (tpoff, BFD_RELOC_ARC_TLS_LE_32, 1), DEF (dtpoff9, BFD_RELOC_ARC_TLS_DTPOFF_S9, 0), DEF (dtpoff, BFD_RELOC_ARC_TLS_DTPOFF, 1), +#if defined (TARGET_ARCv3_64) || defined (TARGET_ARCv3_32) + DEF (u32, BFD_RELOC_ARC_LO32_ME, 1), + DEF (s32, BFD_RELOC_ARC_32_ME, 1), + DEF (plt34, BFD_RELOC_ARC_PLT34, 0), +#endif }; static const int arc_num_reloc_op @@ -709,7 +755,8 @@ arc_find_opcode (const char *name) /* Initialise the iterator ITER. */ static void -arc_opcode_hash_entry_iterator_init (struct arc_opcode_hash_entry_iterator *iter) +arc_opcode_hash_entry_iterator_init +(struct arc_opcode_hash_entry_iterator *iter) { iter->index = 0; iter->opcode = NULL; @@ -720,8 +767,9 @@ arc_opcode_hash_entry_iterator_init (struct arc_opcode_hash_entry_iterator *iter been returned. */ static const struct arc_opcode * -arc_opcode_hash_entry_iterator_next (const struct arc_opcode_hash_entry *entry, - struct arc_opcode_hash_entry_iterator *iter) +arc_opcode_hash_entry_iterator_next +(const struct arc_opcode_hash_entry *entry, + struct arc_opcode_hash_entry_iterator *iter) { if (iter->opcode == NULL && iter->index == 0) { @@ -843,12 +891,12 @@ static void arc_select_cpu (const char *arg, enum mach_selection_type sel) { int i; - static struct cpu_type old_cpu = { 0, 0, 0, E_ARC_OSABI_CURRENT, 0 }; + static struct cpu_type old_cpu = { 0, 0, 0, 0, E_ARC_OSABI_CURRENT, 0 }; - /* We should only set a default if we've not made a selection from some - other source. */ + /* We should only set a default if we've not made a selection from + some other source. */ gas_assert (sel != MACH_SELECTION_FROM_DEFAULT - || mach_selection_mode == MACH_SELECTION_NONE); + || mach_selection_mode == MACH_SELECTION_NONE); if ((mach_selection_mode == MACH_SELECTION_FROM_CPU_DIRECTIVE) && (sel == MACH_SELECTION_FROM_CPU_DIRECTIVE)) @@ -858,19 +906,21 @@ arc_select_cpu (const char *arg, enum mach_selection_type sel) for (i = 0; cpu_types[i].name; ++i) { if (!strcasecmp (cpu_types[i].name, arg)) - { - /* If a previous selection was made on the command line, then we - allow later selections on the command line to override earlier - ones. However, a selection from a '.cpu NAME' directive must - match the command line selection, or we give a warning. */ - if (mach_selection_mode == MACH_SELECTION_FROM_COMMAND_LINE) - { - gas_assert (sel == MACH_SELECTION_FROM_COMMAND_LINE - || sel == MACH_SELECTION_FROM_CPU_DIRECTIVE); - if (sel == MACH_SELECTION_FROM_CPU_DIRECTIVE - && selected_cpu.mach != cpu_types[i].mach) - { - as_warn (_("Command-line value overrides \".cpu\" directive")); + { + /* If a previous selection was made on the command line, + then we allow later selections on the command line to + override earlier ones. However, a selection from a '.cpu + NAME' directive must match the command line selection, or + we give a warning. */ + if (mach_selection_mode == MACH_SELECTION_FROM_COMMAND_LINE) + { + gas_assert (sel == MACH_SELECTION_FROM_COMMAND_LINE + || sel == MACH_SELECTION_FROM_CPU_DIRECTIVE); + if (sel == MACH_SELECTION_FROM_CPU_DIRECTIVE + && selected_cpu.mach != cpu_types[i].mach) + { + as_warn (_("Command-line value overrides \".cpu\" " + "directive")); } return; } @@ -895,8 +945,8 @@ arc_select_cpu (const char *arg, enum mach_selection_type sel) if (mach_selection_mode != MACH_SELECTION_NONE && (old_cpu.mach != selected_cpu.mach)) { - bfd_find_target (arc_target_format, stdoutput); - if (! bfd_set_arch_mach (stdoutput, bfd_arch_arc, selected_cpu.mach)) + bfd_find_target (arc_target_format (), stdoutput); + if (! bfd_set_arch_mach (stdoutput, TARGET_ARCH, selected_cpu.mach)) as_warn (_("Could not set architecture and machine")); } @@ -1016,7 +1066,7 @@ arc_option (int ignore ATTRIBUTE_UNUSED) || (!strcmp ("A6", cpu))) cpu_name = "arc600"; else if ((!strcmp ("ARC700", cpu)) - || (!strcmp ("A7", cpu))) + || (!strcmp ("A7", cpu))) cpu_name = "arc700"; else if (!strcmp ("EM", cpu)) cpu_name = "arcem"; @@ -1093,6 +1143,11 @@ debug_exp (expressionS *t) case O_tpoff: namemd = "O_tpoff"; break; case O_dtpoff9: namemd = "O_dtpoff9"; break; case O_dtpoff: namemd = "O_dtpoff"; break; +#if defined (TARGET_ARCv3_64) || defined (TARGET_ARCv3_32) + case O_u32: namemd = "O_u32"; break; + case O_s32: namemd = "O_s32"; break; + case O_plt34: namemd = "O_plt34"; break; +#endif } pr_debug ("%s (%s, %s, %d, %s)", name, @@ -1117,10 +1172,13 @@ parse_reloc_symbol (expressionS *resultP) expressionS right; symbolS *base; + /* We want to use @u32 and @s32 to force immediates into long + field. */ /* A relocation operand has the following form @identifier@relocation_type. The identifier is already in tok! */ - if (resultP->X_op != O_symbol) + if (resultP->X_op != O_constant + && resultP->X_op != O_symbol) { as_bad (_("No valid label relocation operand")); resultP->X_op = O_illegal; @@ -1151,6 +1209,12 @@ parse_reloc_symbol (expressionS *resultP) return; } + if (resultP->X_op == O_constant) + { + resultP->X_md = r->op; + return; + } + *input_line_pointer = c; SKIP_WHITESPACE_AFTER_NAME (); /* Extra check for TLS: base. */ @@ -1245,8 +1309,11 @@ tokenize_arguments (char *str, ++num_args; break; - case '{': case '[': + /* Silence the error detection. */ + saw_comma = TRUE; + /* Fall through. */ + case '{': input_line_pointer++; if (brk_lvl || num_args == ntok) goto err; @@ -1284,8 +1351,8 @@ tokenize_arguments (char *str, debug_exp (tok); if (tok->X_op == O_illegal - || tok->X_op == O_absent - || num_args == ntok) + || tok->X_op == O_absent + || num_args == ntok) goto err; saw_comma = false; @@ -1318,8 +1385,8 @@ tokenize_arguments (char *str, debug_exp (tok); if (tok->X_op == O_illegal - || tok->X_op == O_absent - || num_args == ntok) + || tok->X_op == O_absent + || num_args == ntok) goto err; saw_comma = false; @@ -1658,10 +1725,10 @@ check_cpu_feature (insn_subclass_t sc) } /* Parse the flags described by FIRST_PFLAG and NFLGS against the flag - operands in OPCODE. Stores the matching OPCODES into the FIRST_PFLAG - array and returns TRUE if the flag operands all match, otherwise, - returns FALSE, in which case the FIRST_PFLAG array may have been - modified. */ + operands in OPCODE. Stores the matching OPCODES into the + FIRST_PFLAG array and returns TRUE if the flag operands all match, + otherwise, returns FALSE, in which case the FIRST_PFLAG array may + have been modified. */ static bool parse_opcode_flags (const struct arc_opcode *opcode, @@ -1688,56 +1755,58 @@ parse_opcode_flags (const struct arc_opcode *opcode, if (cl_flags->flag_class & F_CLASS_IMPLICIT) continue; - /* Check for extension conditional codes. */ + /* Check for extension conditional codes. */ if (ext_condcode.arc_ext_condcode - && cl_flags->flag_class & F_CLASS_EXTEND) - { - struct arc_flag_operand *pf = ext_condcode.arc_ext_condcode; - while (pf->name) - { - pflag = first_pflag; - for (i = 0; i < nflgs; i++, pflag++) - { - if (!strcmp (pf->name, pflag->name)) - { - if (pflag->flgp != NULL) - return false; - /* Found it. */ - cl_matches++; - pflag->flgp = pf; - lnflg--; - break; - } - } - pf++; - } - } + && cl_flags->flag_class & F_CLASS_EXTEND) + { + struct arc_flag_operand *pf = ext_condcode.arc_ext_condcode; + while (pf->name) + { + pflag = first_pflag; + for (i = 0; i < nflgs; i++, pflag++) + { + if (!strcmp (pf->name, pflag->name)) + { + if (pflag->flgp != NULL) + return false; + /* Found it. */ + cl_matches++; + pflag->flgp = pf; + pflag->insert = cl_flags->insert; + lnflg--; + break; + } + } + pf++; + } + } for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx) - { - const struct arc_flag_operand *flg_operand; - - pflag = first_pflag; - flg_operand = &arc_flag_operands[*flgopridx]; - for (i = 0; i < nflgs; i++, pflag++) - { - /* Match against the parsed flags. */ - if (!strcmp (flg_operand->name, pflag->name)) - { - if (pflag->flgp != NULL) - return false; - cl_matches++; - pflag->flgp = flg_operand; - lnflg--; - break; /* goto next flag class and parsed flag. */ - } - } - } + { + const struct arc_flag_operand *flg_operand; + + pflag = first_pflag; + flg_operand = &arc_flag_operands[*flgopridx]; + for (i = 0; i < nflgs; i++, pflag++) + { + /* Match against the parsed flags. */ + if (!strcmp (flg_operand->name, pflag->name)) + { + if (pflag->flgp != NULL) + return false; + cl_matches++; + pflag->flgp = flg_operand; + pflag->insert = cl_flags->insert; + lnflg--; + break; /* goto next flag class and parsed flag. */ + } + } + } if ((cl_flags->flag_class & F_CLASS_REQUIRED) && cl_matches == 0) - return false; + return false; if ((cl_flags->flag_class & F_CLASS_OPTIONAL) && cl_matches > 1) - return false; + return false; } /* Did I check all the parsed flags? */ @@ -1765,6 +1834,7 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry, int bkntok, maxerridx = 0; expressionS emptyE; const char *tmpmsg = NULL; + unsigned int tmp ATTRIBUTE_UNUSED = 0; arc_opcode_hash_entry_iterator_init (&iter); memset (&emptyE, 0, sizeof (emptyE)); @@ -1879,12 +1949,30 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry, goto match_failed; break; - case ARC_OPERAND_COLON: + case ARC_OPERAND_COLON: /* Check if colon is also in opcode table as operand. */ - if (tok[tokidx].X_op != O_colon) - goto match_failed; - break; + if (tok[tokidx].X_op != O_colon) + goto match_failed; + break; + + case (ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED): + /* Signed extended 32 bit, only available for ARC64. */ + if (tok[tokidx].X_op == O_constant) + { + offsetT val = tok[tokidx].X_add_number; + const offsetT min = -(1LL << 31); + const offsetT max = (1LL << 31) - 1; + if (val > max || val < min) + goto match_failed; + break; + } + /* By default a symbol is zero extended. */ + else if (tok[tokidx].X_op == O_symbol + && tok[tokidx].X_md == O_absent) + goto match_failed; + + /* Fall through. */ case ARC_OPERAND_LIMM: case ARC_OPERAND_SIGNED: case ARC_OPERAND_UNSIGNED: @@ -1917,8 +2005,8 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry, if (opcode->insn_class != AUXREG) goto de_fault; - p = S_GET_NAME (tok[tokidx].X_add_symbol); + p = S_GET_NAME (tok[tokidx].X_add_symbol); /* For compatibility reasons, an aux register can be spelled with upper or lower case letters. */ @@ -1943,6 +2031,12 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry, } /* Fall through. */ case O_constant: +#if defined (TARGET_ARCv3_64) || defined (TARGET_ARCv3_32) + /* Check if we want limm. */ + if (tok[tokidx].X_md == O_u32 + && !(operand->flags & ARC_OPERAND_LIMM)) + goto match_failed; +#endif /* Check the range. */ if (operand->bits != 32 && !(operand->flags & ARC_OPERAND_NCHK)) @@ -2012,9 +2106,7 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry, if (operand->insert) { tmpmsg = NULL; - (*operand->insert)(0, - regs, - &tmpmsg); + (*operand->insert) (0, regs, &tmpmsg); if (tmpmsg) goto match_failed; } @@ -2030,15 +2122,30 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry, /* Relocs requiring long immediate. FIXME! make it generic and move it to a function. */ + tmp = ARC_OPERAND_SIGNED; switch (tok[tokidx].X_md) { - case O_gotoff: + /* All offsets needs to be mapped into a signed + limm. */ case O_gotpc: - case O_pcl: case O_tpoff: - case O_dtpoff: - case O_tlsgd: case O_tlsie: + case O_tlsgd: + case O_pcl: +#if defined (TARGET_ARCv3_64) || defined (TARGET_ARCv3_32) + case O_plt34: + case O_s32: + /* Fail if is not signed (ARC64 only). */ + tmp = (selected_cpu.mach == bfd_mach_arcv3_64) ? 0 : tmp; + /* Fall through. */ + case O_u32: + if ((operand->flags & ARC_OPERAND_SIGNED) == tmp) + goto match_failed; + /* Fall through. */ +#else + case O_gotoff: /* Not generated by ARC64. */ + case O_dtpoff: /* Not generated by ARC64. */ +#endif if (!(operand->flags & ARC_OPERAND_LIMM)) goto match_failed; /* Fall through. */ @@ -2152,7 +2259,8 @@ pseudo_operand_match (const expressionS *tok, switch (tok->X_op) { case O_constant: - if (operand_real->bits == 32 && (operand_real->flags & ARC_OPERAND_LIMM)) + if (operand_real->bits == 32 + && (operand_real->flags & ARC_OPERAND_LIMM)) ret = 1; else if (!(operand_real->flags & ARC_OPERAND_IR)) { @@ -2224,6 +2332,25 @@ find_pseudo_insn (const char *opname, return pseudo_insn; } } + +#if defined (TARGET_ARCv3_64) || defined (TARGET_ARCv3_32) + /* ARC64 pseudo instructions. */ + for (i = 0; i < arc64_num_pseudo_insn; i++) + { + pseudo_insn = &arc64_pseudo_insns[i]; + if (strcmp (pseudo_insn->mnemonic_p, opname) == 0) + { + op = pseudo_insn->operand; + for (j = 0; j < ntok; ++j) + if (!pseudo_operand_match (&tok[j], &op[j])) + break; + + /* Found the right instruction. */ + if (j == ntok) + return pseudo_insn; + } + } +#endif return NULL; } @@ -2420,6 +2547,9 @@ autodetect_attributes (const struct arc_opcode *opcode, case O_gotoff: case O_gotpc: case O_plt: +#if defined (TARGET_ARCv3_64) || defined (TARGET_ARCv3_32) + case O_plt34: +#endif pic_option = 2; break; case O_sda: @@ -2583,6 +2713,27 @@ declare_register_set (void) } } +#if defined (TARGET_ARCv3_64) || defined (TARGET_ARCv3_32) +/* Helper use for declaration of fp refisters. */ +static void +declare_fp_set (void) +{ + int i; + for (i = 0; i < 32; ++i) + { + char name[32]; + + sprintf (name, "f%d", i); + declare_register (name, i); + if ((i & 0x01) == 0) + { + sprintf (name, "f%df%d", i, i+1); + declare_register (name, i); + } + } +} +#endif + /* Construct a symbol for an address type. */ static void @@ -2595,21 +2746,38 @@ declare_addrtype (const char *name, int number) as_fatal (_("duplicate %s"), name); } +/* Initialize the default cpu. */ + +static void +init_default_arch (void) +{ + if (strcmp (default_arch, "arc64") == 0) +#ifdef TARGET_ARCv3_32 + arc_select_cpu ("hs5x", MACH_SELECTION_FROM_DEFAULT); +#else + arc_select_cpu ("hs6x", MACH_SELECTION_FROM_DEFAULT); +#endif + else + arc_select_cpu (TARGET_WITH_CPU, MACH_SELECTION_FROM_DEFAULT); +} + /* Port-specific assembler initialization. This function is called once, at assembler startup time. */ void md_begin (void) { - const struct arc_opcode *opcode = arc_opcodes; + const struct arc_opcode *opcode; + + opcode = arc_opcodes; if (mach_selection_mode == MACH_SELECTION_NONE) - arc_select_cpu (TARGET_WITH_CPU, MACH_SELECTION_FROM_DEFAULT); + init_default_arch (); /* The endianness can be chosen "at the factory". */ target_big_endian = byte_order == BIG_ENDIAN; - if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, selected_cpu.mach)) + if (!bfd_set_arch_mach (stdoutput, TARGET_ARCH, selected_cpu.mach)) as_warn (_("could not set architecture and machine")); /* Set elf header flags. */ @@ -2636,12 +2804,23 @@ md_begin (void) arc_reg_hash = str_htab_create (); declare_register_set (); +#if defined (TARGET_ARCv3_64) || defined (TARGET_ARCv3_32) + declare_register ("gp", 30); + declare_fp_set (); +#else declare_register ("gp", 26); +#endif declare_register ("fp", 27); declare_register ("sp", 28); declare_register ("ilink", 29); - declare_register ("ilink1", 29); - declare_register ("ilink2", 30); +#if !defined (TARGET_ARCv3_64) && !defined (TARGET_ARCv3_32) + if (selected_cpu.mach == bfd_mach_arc_arc600 + || selected_cpu.mach == bfd_mach_arc_arc700) + { + declare_register ("ilink1", 29); + declare_register ("ilink2", 30); + } +#endif declare_register ("blink", 31); /* XY memory registers. */ @@ -2807,8 +2986,14 @@ md_pcrel_from_section (fixS *fixP, case BFD_RELOC_ARC_S13_PCREL: case BFD_RELOC_ARC_S21W_PCREL: case BFD_RELOC_ARC_S25W_PCREL: + case BFD_RELOC_ARC_S10H_PCREL: + case BFD_RELOC_ARC_S13H_PCREL: + case BFD_RELOC_ARC_S9H_PCREL: + case BFD_RELOC_ARC_S8H_PCREL: + case BFD_RELOC_ARC_S7H_PCREL: base &= ~3; break; + default: as_bad_where (fixP->fx_file, fixP->fx_line, _("unhandled reloc %s in md_pcrel_from_section"), @@ -2905,6 +3090,36 @@ insert_operand (unsigned long long insn, return insn; } +/* Called by TARGET_FORMAT. */ + +const char * +arc_target_format (void) +{ + + /* We don't get a chance to initialize anything before we're called, + so handle that now. */ + if (mach_selection_mode == MACH_SELECTION_NONE) + init_default_arch (); + + if (selected_cpu.name == NULL) + return DEFAULT_TARGET_FORMAT; + +#if defined(TARGET_ARCv3_64) || defined(TARGET_ARCv3_32) + if (selected_cpu.mach == bfd_mach_arcv3_64) + return "elf64-littlearc64"; + + if (selected_cpu.mach == bfd_mach_arcv3_32) + return "elf32-littlearc64"; + + return DEFAULT_TARGET_FORMAT; +#else + if (byte_order == LITTLE_ENDIAN) + return "elf32-littlearc"; + + return "elf32-bigarc"; +#endif +} + /* Apply a fixup to the object code. At this point all symbol values should be fully resolved, and we attempt to completely resolve the reloc. If we can not do that, we determine the correct reloc code @@ -2922,7 +3137,6 @@ md_apply_fix (fixS *fixP, symbolS *fx_addsy, *fx_subsy; offsetT fx_offset; segT add_symbol_segment = absolute_section; - segT sub_symbol_segment = absolute_section; const struct arc_operand *operand = NULL; extended_bfd_reloc_code_real_type reloc; @@ -2941,29 +3155,9 @@ md_apply_fix (fixS *fixP, add_symbol_segment = S_GET_SEGMENT (fx_addsy); } - if (fx_subsy - && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF - && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF_S9 - && fixP->fx_r_type != BFD_RELOC_ARC_TLS_GD_LD) - { - resolve_symbol_value (fx_subsy); - sub_symbol_segment = S_GET_SEGMENT (fx_subsy); - - if (sub_symbol_segment == absolute_section) - { - /* The symbol is really a constant. */ - fx_offset -= S_GET_VALUE (fx_subsy); - fx_subsy = NULL; - } - else - { - as_bad_subtract (fixP); - return; - } - } - if (fx_addsy - && !S_IS_WEAK (fx_addsy)) + && !S_IS_WEAK (fx_addsy) + && !fx_subsy) { if (add_symbol_segment == seg && fixP->fx_pcrel) @@ -3133,6 +3327,11 @@ md_apply_fix (fixS *fixP, case BFD_RELOC_ARC_S21H_PCREL: case BFD_RELOC_ARC_S25H_PCREL: case BFD_RELOC_ARC_S13_PCREL: + case BFD_RELOC_ARC_S10H_PCREL: + case BFD_RELOC_ARC_S13H_PCREL: + case BFD_RELOC_ARC_S9H_PCREL: + case BFD_RELOC_ARC_S8H_PCREL: + case BFD_RELOC_ARC_S7H_PCREL: solve_plt: operand = find_operand_for_reloc (reloc); gas_assert (operand); @@ -3261,8 +3460,7 @@ tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, code = fixP->fx_r_type; - /* if we have something like add gp, pcl, - _GLOBAL_OFFSET_TABLE_@gotpc. */ + /* if we have something like add gp, pcl, _GLOBAL_OFFSET_TABLE_@gotpc. */ if (code == BFD_RELOC_ARC_GOTPC32 && GOT_symbol && fixP->fx_addsy == GOT_symbol) @@ -3448,6 +3646,25 @@ md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED) { switch (c) { + case OPTION_MCPU: + arc_select_cpu (arg, MACH_SELECTION_FROM_COMMAND_LINE); + break; + + case OPTION_CD: + selected_cpu.features |= CD; + cl_features |= CD; + arc_check_feature (); + break; + + case OPTION_RELAX: + relaxation_state = TRUE; + break; + + case OPTION_LINKER_RELAX: + relaxation_state = FALSE; + break; + +#if !defined (TARGET_ARCv3_64) && !defined (TARGET_ARCv3_32) case OPTION_ARC600: case OPTION_ARC601: return md_parse_option (OPTION_MCPU, "arc600"); @@ -3461,32 +3678,14 @@ md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED) case OPTION_ARCHS: return md_parse_option (OPTION_MCPU, "archs"); - case OPTION_MCPU: - { - arc_select_cpu (arg, MACH_SELECTION_FROM_COMMAND_LINE); - break; - } - case OPTION_EB: - arc_target_format = "elf32-bigarc"; byte_order = BIG_ENDIAN; break; case OPTION_EL: - arc_target_format = "elf32-littlearc"; byte_order = LITTLE_ENDIAN; break; - case OPTION_CD: - selected_cpu.features |= CD; - cl_features |= CD; - arc_check_feature (); - break; - - case OPTION_RELAX: - relaxation_state = 1; - break; - case OPTION_NPS400: selected_cpu.features |= NPS400; cl_features |= NPS400; @@ -3533,6 +3732,7 @@ md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED) case OPTION_SWAPE: case OPTION_RTSC: break; +#endif default: return 0; @@ -3555,13 +3755,16 @@ arc_show_cpu_list (FILE *stream) { bool last = (cpu_types[i + 1].name == NULL); + if (strcmp (default_arch, cpu_types[i].arch) != 0) + continue; + /* If displaying the new cpu name string, and the ', ' (for all - but the last one) will take us past a target width of 80 - characters, then it's time for a new line. */ + but the last one) will take us past a target width of 80 + characters, then it's time for a new line. */ if (offset + strlen (cpu_types[i].name) + (last ? 0 : 2) > 80) { - fprintf (stream, "\n%s", space_buf); - offset = strlen (space_buf); + fprintf (stream, "\n%s", space_buf); + offset = strlen (space_buf); } fprintf (stream, "%s%s", cpu_types[i].name, (last ? "\n" : ", ")); @@ -3572,10 +3775,11 @@ arc_show_cpu_list (FILE *stream) void md_show_usage (FILE *stream) { +#if !defined(TARGET_ARCv3_64) && !defined(TARGET_ARCv3_32) fprintf (stream, _("ARC-specific assembler options:\n")); fprintf (stream, " -mcpu=<cpu name>\t (default: %s), assemble for" - " CPU <cpu name>, one of:\n", TARGET_WITH_CPU); + " CPU <cpu name>, one of:\n", TARGET_WITH_CPU); arc_show_cpu_list (stream); fprintf (stream, "\n"); fprintf (stream, " -mA6/-mARC600/-mARC601 same as -mcpu=arc600\n"); @@ -3589,7 +3793,7 @@ md_show_usage (FILE *stream) fprintf (stream, " -mdpfp\t\t enable double-precision floating point" " instructions\n"); fprintf (stream, " -mfpuda\t\t enable double-precision assist floating " - "point\n\t\t\t instructions for ARC EM\n"); + "point\n\t\t\t instructions for ARC EM\n"); fprintf (stream, " -mcode-density\t enable code density option for ARC EM\n"); @@ -3602,33 +3806,41 @@ md_show_usage (FILE *stream) -mrelax enable relaxation\n")); fprintf (stream, _("The following ARC-specific assembler options are " - "deprecated and are accepted\nfor compatibility only:\n")); + "deprecated and are accepted\nfor compatibility only:\n")); fprintf (stream, _(" -mEA\n" - " -mbarrel-shifter\n" - " -mbarrel_shifter\n" - " -mcrc\n" - " -mdsp-packa\n" - " -mdsp_packa\n" - " -mdvbf\n" - " -mld-extension-reg-mask\n" - " -mlock\n" - " -mmac-24\n" - " -mmac-d16\n" - " -mmac_24\n" - " -mmac_d16\n" - " -mmin-max\n" - " -mmin_max\n" - " -mmul64\n" - " -mno-mpy\n" - " -mnorm\n" - " -mrtsc\n" - " -msimd\n" - " -mswap\n" - " -mswape\n" - " -mtelephony\n" + " -mbarrel-shifter\n" + " -mbarrel_shifter\n" + " -mcrc\n" + " -mdsp-packa\n" + " -mdsp_packa\n" + " -mdvbf\n" + " -mld-extension-reg-mask\n" + " -mlock\n" + " -mmac-24\n" + " -mmac-d16\n" + " -mmac_24\n" + " -mmac_d16\n" + " -mmin-max\n" + " -mmin_max\n" + " -mmul64\n" + " -mno-mpy\n" + " -mnorm\n" + " -mrtsc\n" + " -msimd\n" + " -mswap\n" + " -mswape\n" + " -mtelephony\n" " -muser-mode-only\n" - " -mxy\n")); + " -mxy\n")); +#else + fprintf (stream, _("ARC64-specific assembler options:\n")); + + fprintf (stream, " -mcpu=<cpu name>\t assemble for CPU <cpu name>," + "one of:\n"); + arc_show_cpu_list (stream); + fprintf (stream, "\n"); +#endif } /* Find the proper relocation for the given opcode. */ @@ -3711,6 +3923,9 @@ may_relax_expr (expressionS tok) default: break; case O_plt: +#if defined (TARGET_ARCv3_64) || defined (TARGET_ARCv3_32) + case O_plt34: +#endif return false; } @@ -3956,8 +4171,8 @@ assemble_insn (const struct arc_opcode *opcode, break; case O_bracket: - case O_colon: - case O_addrtype: + case O_colon: + case O_addrtype: /* Ignore brackets, colons, and address types. */ break; @@ -3997,6 +4212,17 @@ assemble_insn (const struct arc_opcode *opcode, operand->default_reloc); break; +#if defined (TARGET_ARCv3_64) || defined (TARGET_ARCv3_32) + case O_s32: + if ((operand->flags & ARC_OPERAND_SIGNED) == 0) + as_bad (_("Unable to use @s32 relocation for insn %s"), + opcode->name); + /* Fall-through. */ + case O_u32: + reloc = operand->default_reloc; + break; + case O_plt34: +#endif case O_gotoff: case O_gotpc: needGOTSymbol = true; @@ -4154,8 +4380,22 @@ assemble_insn (const struct arc_opcode *opcode, } } else - image |= (flg_operand->code & ((1 << flg_operand->bits) - 1)) - << flg_operand->shift; + { + unsigned int flag_encoding; + flag_encoding = (flg_operand->code & ((1 << flg_operand->bits) - 1)); + + if (pflags[i].insert) + { + /* We can have a special flag which needs an insertion + function. */ + const char *errmsg = NULL; + image = (*pflags[i].insert) (image, flag_encoding, &errmsg); + } + else + { + image |= flag_encoding << flg_operand->shift; + } + } } insn->relax = relax_insn_p (opcode, tok, ntok, pflags, nflg); @@ -4184,26 +4424,64 @@ assemble_insn (const struct arc_opcode *opcode, arc_last_insns[0].opcode->name); } +static void +arc_make_nops (char *buf, bfd_vma bytes) +{ + bfd_vma i = 0; + + /* ARC instructions cannot begin or end on odd addresses, so this case + means we are not within a valid instruction sequence. It is thus safe + to use a zero byte, even though that is not a valid instruction. */ + if (bytes % 2 == 1) + buf[i++] = 0; + + /* Use 2-byte NOP. */ + for ( ; i < bytes; i += 2) + md_number_to_chars_midend (buf + i, NOP_OPCODE_S, 2); +} + +/* Implement HANDLE_ALIGN. */ + void arc_handle_align (fragS* fragP) { - if ((fragP)->fr_type == rs_align_code) + char *dest = (fragP)->fr_literal + (fragP)->fr_fix; + valueT count = ((fragP)->fr_next->fr_address + - (fragP)->fr_address - (fragP)->fr_fix); + bfd_signed_vma size = count & ~0x01; + bfd_signed_vma excess = count & 0x01; + expressionS ex; + + if (fragP->fr_type != rs_align_code) + return; + + if (count <= 0) + return; + + /* Insert zeros to get 2 byte alignment. */ + if (excess && fragP->fr_type == rs_align_code) { - char *dest = (fragP)->fr_literal + (fragP)->fr_fix; - valueT count = ((fragP)->fr_next->fr_address - - (fragP)->fr_address - (fragP)->fr_fix); + arc_make_nops (dest, excess); + fragP->fr_fix += excess; + dest += excess; + } - (fragP)->fr_var = 2; + /* Only emit this reloc when linker relaxation is required. */ + if (linkrelax && size) + { + ex.X_op = O_constant; + ex.X_add_number = size; + fix_new_exp (fragP, fragP->fr_fix, 0, &ex, FALSE, BFD_RELOC_ARC_ALIGN); + } + else + { + if (size > MAX_MEM_FOR_RS_ALIGN_CODE) + size &= MAX_MEM_FOR_RS_ALIGN_CODE; - if (count & 1)/* Padding in the gap till the next 2-byte - boundary with 0s. */ - { - (fragP)->fr_fix++; - *dest++ = 0; - } - /* Writing nop_s. */ - md_number_to_chars (dest, NOP_OPCODE_S, 2); + /* Insert variable number of 2 bytes NOPs. */ + arc_make_nops (dest, size); } + fragP->fr_fix += size; } /* Here we decide which fixups can be adjusted to make them relative @@ -4215,7 +4493,6 @@ arc_handle_align (fragS* fragP) int tc_arc_fix_adjustable (fixS *fixP) { - /* Prevent all adjustments to global symbols. */ if (S_IS_EXTERNAL (fixP->fx_addsy)) return 0; @@ -4227,6 +4504,9 @@ tc_arc_fix_adjustable (fixS *fixP) { case BFD_RELOC_ARC_GOTPC32: case BFD_RELOC_ARC_PLT32: +#if defined (TARGET_ARCv3_64) || defined (TARGET_ARCv3_32) + case BFD_RELOC_ARC_PLT34: +#endif case BFD_RELOC_ARC_S25H_PCREL_PLT: case BFD_RELOC_ARC_S21H_PCREL_PLT: case BFD_RELOC_ARC_S25W_PCREL_PLT: @@ -4309,14 +4589,16 @@ check_zol (symbolS *s) if (is_br_jmp_insn_p (arc_last_insns[0].opcode) || arc_last_insns[1].has_delay_slot) - as_bad (_("Jump/Branch instruction detected at the end of the ZOL label @%s"), + as_bad (_("Jump/Branch instruction detected at the end " + "of the ZOL label @%s"), S_GET_NAME (s)); break; case bfd_mach_arc_arc600: if (is_kernel_insn_p (arc_last_insns[0].opcode)) - as_bad (_("Kernel instruction detected at the end of the ZOL label @%s"), + as_bad (_("Kernel instruction detected at the end " + "of the ZOL label @%s"), S_GET_NAME (s)); if (arc_last_insns[0].has_limm @@ -4327,7 +4609,8 @@ end of the ZOL label @%s"), S_GET_NAME (s)); /* Fall through. */ case bfd_mach_arc_arc700: if (arc_last_insns[0].has_delay_slot) - as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"), + as_bad (_("An illegal use of delay slot detected at the end " + "of the ZOL label @%s"), S_GET_NAME (s)); break; @@ -4641,7 +4924,8 @@ arc_extinsn (int ignore ATTRIBUTE_UNUSED) | ARC_OPCODE_ARCv2HS)) ? 0x07 : 0x0a; if ((einsn.major > mophigh) || (einsn.major < moplow)) - as_fatal (_("major opcode not in range [0x%02x - 0x%02x]"), moplow, mophigh); + as_fatal (_("major opcode not in range [0x%02x - 0x%02x]"), moplow, + mophigh); if ((einsn.minor > 0x3f) && (einsn.major != 0x0a) && (einsn.major != 5) && (einsn.major != 9)) @@ -5080,9 +5364,6 @@ arc_md_finish (void) { arc_set_public_attributes (); - if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, selected_cpu.mach)) - as_fatal (_("could not set architecture and machine")); - bfd_set_private_flags (stdoutput, selected_cpu.eflags); } diff --git a/gas/config/tc-arc.h b/gas/config/tc-arc.h index 743e5362c30..4240ed47ba5 100644 --- a/gas/config/tc-arc.h +++ b/gas/config/tc-arc.h @@ -34,7 +34,11 @@ /* This macro is the BFD architecture to pass to `bfd_set_arch_mach'. */ -#define TARGET_ARCH bfd_arch_arc +#if defined (TARGET_ARCv3_64) || defined (TARGET_ARCv3_32) +# define TARGET_ARCH bfd_arch_arc64 +#else +# define TARGET_ARCH bfd_arch_arc +#endif /* The `extsym - .' expressions can be emitted using PC-relative relocs. */ @@ -48,28 +52,33 @@ #undef BIG_ENDIAN #define BIG_ENDIAN 4321 -#ifdef TARGET_BYTES_BIG_ENDIAN - -# define DEFAULT_TARGET_FORMAT "elf32-bigarc" -# define DEFAULT_BYTE_ORDER BIG_ENDIAN - -#else +#ifndef TARGET_BYTES_BIG_ENDIAN /* You should define this macro to be non-zero if the target is big endian, and zero if the target is little endian. */ -# define TARGET_BYTES_BIG_ENDIAN 0 +#define TARGET_BYTES_BIG_ENDIAN 0 +#endif -# define DEFAULT_TARGET_FORMAT "elf32-littlearc" +#ifdef TARGET_ARCv3_64 +# define DEFAULT_TARGET_FORMAT "elf64-littlearc64" # define DEFAULT_BYTE_ORDER LITTLE_ENDIAN - +#elif defined (TARGET_ARCv3_32) +# define DEFAULT_TARGET_FORMAT "elf64-littlearc32" +# define DEFAULT_BYTE_ORDER LITTLE_ENDIAN +#else +# if TARGET_BYTES_BIG_ENDIAN == 1 +# define DEFAULT_TARGET_FORMAT "elf32-bigarc" +# define DEFAULT_BYTE_ORDER BIG_ENDIAN +# else +# define DEFAULT_TARGET_FORMAT "elf32-littlearc" +# define DEFAULT_BYTE_ORDER LITTLE_ENDIAN #endif /* TARGET_BYTES_BIG_ENDIAN. */ -/* The endianness of the target format may change based on command - line arguments. */ -extern const char *arc_target_format; +#endif /* TARGET_ARCv3_64. */ /* This macro is the BFD target name to use when creating the output file. This will normally depend upon the `OBJ_FMT' macro. */ -#define TARGET_FORMAT arc_target_format +#define TARGET_FORMAT arc_target_format() +extern const char *arc_target_format (void); /* `md_short_jump_size' `md_long_jump_size' @@ -103,9 +112,6 @@ extern const char *arc_target_format; fixp->fx_frag->fr_address. */ #define MD_PCREL_FROM_SECTION(FIX, SEC) md_pcrel_from_section (FIX, SEC) -/* [ ] is index operator. */ -#define NEED_INDEX_OPERATOR - #define MAX_MEM_FOR_RS_ALIGN_CODE (1+2) /* HANDLE_ALIGN called after all the assembly has been done, @@ -131,6 +137,7 @@ extern const char *arc_target_format; #define TC_VALIDATE_FIX(FIXP,SEG,SKIP) \ if ((FIXP->fx_r_type == BFD_RELOC_ARC_GOTPC32 \ || FIXP->fx_r_type == BFD_RELOC_ARC_PLT32 \ + || FIXP->fx_r_type == BFD_RELOC_ARC_PLT34 \ || FIXP->fx_r_type == BFD_RELOC_ARC_S25W_PCREL_PLT \ || FIXP->fx_r_type == BFD_RELOC_ARC_S25H_PCREL_PLT \ || FIXP->fx_r_type == BFD_RELOC_ARC_S21W_PCREL_PLT \ @@ -236,6 +243,11 @@ struct arc_flags /* Pointer to arc flags. */ const struct arc_flag_operand *flgp; + + /* Pointer to insert function. */ + unsigned long long (*insert) (unsigned long long instruction, + long long int op, + const char **errmsg); }; extern const relax_typeS md_relax_table[]; diff --git a/gas/configure b/gas/configure index 3c80fe5741a..b1a06bb6199 100755 --- a/gas/configure +++ b/gas/configure @@ -12099,6 +12099,18 @@ cat >>confdefs.h <<_ACEOF #define DEFAULT_CRIS_ARCH $arch _ACEOF + ;; + arc64) + # Set for which architecture we compile + +$as_echo "#define TARGET_ARCv3_64 1" >>confdefs.h + + ;; + arc32) + # Set for which architecture we compile + +$as_echo "#define TARGET_ARCv3_32 1" >>confdefs.h + ;; esac @@ -12523,7 +12535,7 @@ $as_echo "#define NDS32_DEFAULT_ZOL_EXT 1" >>confdefs.h $as_echo "$enable_zol_ext" >&6; } ;; - aarch64 | i386 | s390 | sparc) + aarch64 | i386 | s390 | sparc | arc) if test $this_target = $target ; then cat >>confdefs.h <<_ACEOF diff --git a/gas/configure.ac b/gas/configure.ac index 3a04c39d344..2f6aa7e31ae 100644 --- a/gas/configure.ac +++ b/gas/configure.ac @@ -235,6 +235,14 @@ for this_target in $target $canon_targets ; do AC_DEFINE_UNQUOTED(DEFAULT_CRIS_ARCH, $arch, [Default CRIS architecture.]) ;; + arc64) + # Set for which architecture we compile + AC_DEFINE(TARGET_ARCv3_64, 1, [Using ARCv3/64 architecture.]) + ;; + arc32) + # Set for which architecture we compile + AC_DEFINE(TARGET_ARCv3_32, 1, [Using ARCv3/32 architecture.]) + ;; esac if test ${this_target} = $target ; then @@ -606,7 +614,7 @@ changequote([,])dnl AC_MSG_RESULT($enable_zol_ext) ;; - aarch64 | i386 | s390 | sparc) + aarch64 | i386 | s390 | sparc | arc) if test $this_target = $target ; then AC_DEFINE_UNQUOTED(DEFAULT_ARCH, "${arch}", [Default architecture.]) fi diff --git a/gas/configure.tgt b/gas/configure.tgt index 3a582ef41d4..d39db7d79d0 100644 --- a/gas/configure.tgt +++ b/gas/configure.tgt @@ -50,7 +50,9 @@ case ${cpu} in aarch64_be) cpu_type=aarch64 endian=big arch=aarch64;; alpha*) cpu_type=alpha ;; am33_2.0) cpu_type=mn10300 endian=little ;; - arc*eb) cpu_type=arc endian=big ;; + arc64|arc32) cpu_type=arc arch=arc64 endian=little ;; + arceb) cpu_type=arc arch=arc endian=big ;; + arc) cpu_type=arc arch=arc endian=little ;; arm*be|arm*b) cpu_type=arm endian=big ;; arm*) cpu_type=arm endian=little ;; bfin*) cpu_type=bfin endian=little ;; @@ -145,6 +147,7 @@ case ${generic_target} in alpha-*-netbsd* | alpha-*-openbsd*) fmt=elf em=nbsd ;; arc-*-elf*) fmt=elf ;; + arc64-*-* | arc32-*-*) fmt=elf ;; arc*-*-linux*) fmt=elf bfd_gas=yes ;; arm-*-phoenix*) fmt=elf ;; -- 2.30.2 ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 7/7] arc: Add new opcode functions for ARCv3 ISA. 2023-09-19 8:12 [PATCH 0/7] arc: Add new ARCv3 isa support to ARC's backend Claudiu Zissulescu ` (5 preceding siblings ...) 2023-09-19 8:12 ` [PATCH 6/7] arc: Update ARC's Gnu Assembler backend with ARCv3 ISA Claudiu Zissulescu @ 2023-09-19 8:12 ` Claudiu Zissulescu 6 siblings, 0 replies; 8+ messages in thread From: Claudiu Zissulescu @ 2023-09-19 8:12 UTC (permalink / raw) To: binutils opcodes/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> Cupertino Miranda <cmiranda@synopsys.com> * opcodes/Makefile.am: Add ARC64 opcode file. * opcodes/Makefile.in: Regenerate. * opcodes/arc-opc.c: Move the common functionality to arcxx-opc.inc. Keep only ARCv2 ARCv1 specifics. * opcodes/arc-ext-tbl.h: Deleted file. * opcodes/arcxx-opc.inc: New file. * opcodes/arc64-opc.c: Likewise. * opcodes/arc-fxi.h (insert_uimm9_a32_11_s): New function. (extract_uimm9_a32_11_s): Likewise. (insert_uimm10_13_s): Likewise. (extract_uimm10_13_s): Likewise. * opcodes/configure: Regenerate. * opcodes/configure.ac: Add ARC64 target. * opcodes/disassemble.c: Likewise. * opcodes/arc-dis.c (regmod_t): New type. (regmods): New structure. (fpnames): New strings with fp-regs name. (REG_PCL, REG_LIMM, REG_LIMM_S, REG_U32, REG_S32): New defines. (getregname): New function. (find_format_from_table): Discriminate between signed and unsigned 32bit immediates. (find_format): Handle extract function for flags. (arc_insn_length): Update insn lengths to various architectures. (print_insn_arc): Update printing for various ARC architectures. * opcodes/arc-flag-classes.def: New file. * opcodes/arc-flag.def: New file. * opcodes/arc-operands.def: New file. * opcodes/arc-regs.h: Changed. Signed-off-by: Claudiu Zissulescu <claziss@gmail.com> --- opcodes/Makefile.am | 1 + opcodes/Makefile.in | 2 + opcodes/arc-dis.c | 290 +++- opcodes/arc-ext-tbl.h | 124 -- opcodes/arc-flag-classes.def | 125 ++ opcodes/arc-flag.def | 179 ++ opcodes/arc-fxi.h | 60 + opcodes/arc-opc.c | 2990 ++-------------------------------- opcodes/arc-operands.def | 502 ++++++ opcodes/arc-regs.h | 8 +- opcodes/arc64-opc.c | 834 ++++++++++ opcodes/arcxx-opc.inc | 1840 +++++++++++++++++++++ opcodes/configure | 1 + opcodes/configure.ac | 1 + opcodes/disassemble.c | 6 + 15 files changed, 3872 insertions(+), 3091 deletions(-) delete mode 100644 opcodes/arc-ext-tbl.h create mode 100644 opcodes/arc-flag-classes.def create mode 100644 opcodes/arc-flag.def create mode 100644 opcodes/arc-operands.def create mode 100644 opcodes/arc64-opc.c create mode 100644 opcodes/arcxx-opc.inc diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am index 5804dd1ab38..effcd41b6ae 100644 --- a/opcodes/Makefile.am +++ b/opcodes/Makefile.am @@ -116,6 +116,7 @@ TARGET32_LIBOPCODES_CFILES = \ arc-dis.c \ arc-ext.c \ arc-opc.c \ + arc64-opc.c \ arm-dis.c \ avr-dis.c \ bfin-dis.c \ diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in index 29c26263061..f207cf57f44 100644 --- a/opcodes/Makefile.in +++ b/opcodes/Makefile.in @@ -508,6 +508,7 @@ TARGET32_LIBOPCODES_CFILES = \ arc-dis.c \ arc-ext.c \ arc-opc.c \ + arc64-opc.c \ arm-dis.c \ avr-dis.c \ bfin-dis.c \ @@ -876,6 +877,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/arc-dis.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/arc-ext.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/arc-opc.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/arc64-opc.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/arm-dis.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/avr-dis.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bfin-dis.Plo@am__quote@ diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c index 59b668ff64e..dbcd0dbd7f8 100644 --- a/opcodes/arc-dis.c +++ b/opcodes/arc-dis.c @@ -60,7 +60,7 @@ struct arc_disassemble_info /* Instruction length w/o limm field. */ unsigned insn_len; - /* TRUE if we have limm. */ + /* true if we have limm. */ bool limm_p; /* LIMM value, if exists. */ @@ -85,7 +85,7 @@ static const char * const regnames[64] = "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", - "r24", "r25", "gp", "fp", "sp", "ilink", "r30", "blink", + "r24", "r25", "r26", "fp", "sp", "ilink", "r30", "blink", "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", @@ -93,6 +93,29 @@ static const char * const regnames[64] = "r56", "r57", "r58", "r59", "lp_count", "reserved", "LIMM", "pcl" }; +typedef struct regmod +{ + const unsigned int index; + const unsigned int isa; + const char *rname; +} regmod_t; + +static regmod_t regmods[] = +{ + { 26, ARC_OPCODE_ARCV1 | ARC_OPCODE_ARCV2, "gp" }, + { 29, ARC_OPCODE_ARCV1, "ilink1" }, + { 30, ARC_OPCODE_ARCV1, "ilink2" }, + { 0, ARC_OPCODE_NONE, 0 } +}; + +static const char * const fpnames[32] = +{ + "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", + "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", + "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", + "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31" +}; + static const char * const addrtypenames[ARC_NUM_ADDRTYPES] = { "bd", "jid", "lbd", "mbd", "sd", "sm", "xa", "xd", @@ -126,7 +149,6 @@ static unsigned enforced_isa_mask = ARC_OPCODE_NONE; static bool print_hex = false; /* Macros section. */ - #ifdef DEBUG # define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args) #else @@ -140,8 +162,29 @@ static bool print_hex = false; #define BITS(word,s,e) (((word) >> (s)) & ((1ull << ((e) - (s)) << 1) - 1)) #define OPCODE_32BIT_INSN(word) (BITS ((word), 27, 31)) +#define REG_PCL 63 +#define REG_LIMM 62 +#define REG_LIMM_S 30 +#define REG_U32 62 +#define REG_S32 60 + /* Functions implementation. */ +static const char * +getregname (unsigned int index, unsigned int isa_mask) +{ + regmod_t *iregmods = regmods; + while (iregmods->rname) + { + if (index == iregmods->index + && (isa_mask & iregmods->isa)) + return iregmods->rname; + iregmods ++; + } + + return regnames[index % 64]; +} + /* Initialize private data. */ static bool init_arc_disasm_info (struct disassemble_info *info) @@ -170,7 +213,7 @@ add_to_decodelist (insn_class_t insn_class, decodelist = t; } -/* Return TRUE if we need to skip the opcode from being +/* Return true if we need to skip the opcode from being disassembled. */ static bool @@ -277,7 +320,7 @@ find_format_from_table (struct disassemble_info *info, if (arc_opcode_len (opcode) != (int) insn_len) continue; - if ((insn & opcode->mask) != opcode->opcode) + if ((insn & opcode->mask) != (opcode->mask & opcode->opcode)) continue; *has_limm = false; @@ -285,7 +328,7 @@ find_format_from_table (struct disassemble_info *info, /* Possible candidate, check the operands. */ for (opidx = opcode->operands; *opidx; opidx++) { - int value, limmind; + int value, slimmind; const struct arc_operand *operand = &arc_operands[*opidx]; if (operand->flags & ARC_OPERAND_FAKE) @@ -296,19 +339,19 @@ find_format_from_table (struct disassemble_info *info, else value = (insn >> operand->shift) & ((1ull << operand->bits) - 1); - /* Check for LIMM indicator. If it is there, then make sure - we pick the right format. */ - limmind = (isa_mask & ARC_OPCODE_ARCV2) ? 0x1E : 0x3E; + /* Check for (short) LIMM indicator. If it is there, then + make sure we pick the right format. */ + slimmind = (isa_mask & ARC_OPCODE_ARCVx) ? REG_LIMM_S : REG_LIMM; if (operand->flags & ARC_OPERAND_IR && !(operand->flags & ARC_OPERAND_LIMM)) - { - if ((value == 0x3E && insn_len == 4) - || (value == limmind && insn_len == 2)) - { - invalid = true; - break; - } - } + if ((value == REG_LIMM && insn_len == 4) + || (value == slimmind && insn_len == 2) + || (isa_mask & ARC_OPCODE_ARC64 + && (value == REG_S32) && (insn_len == 4))) + { + invalid = true; + break; + } if (operand->flags & ARC_OPERAND_LIMM && !(operand->flags & ARC_OPERAND_DUPLICATE)) @@ -338,11 +381,15 @@ find_format_from_table (struct disassemble_info *info, for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx) { + bool tmp = false; const struct arc_flag_operand *flg_operand = &arc_flag_operands[*flgopridx]; - value = (insn >> flg_operand->shift) - & ((1 << flg_operand->bits) - 1); + if (cl_flags->extract) + value = (*cl_flags->extract)(insn, &tmp); + else + value = (insn >> flg_operand->shift) + & ((1 << flg_operand->bits) - 1); if (value == flg_operand->code) foundA = 1; if (value) @@ -396,15 +443,15 @@ find_format_from_table (struct disassemble_info *info, the found opcode requires a LIMM then the LIMM value will be loaded into a field of ITER. - This function returns TRUE in almost all cases, FALSE is reserved to + This function returns true in almost all cases, false is reserved to indicate an error (failing to find an opcode is not an error) a returned - result of FALSE would indicate that the disassembler can't continue. + result of false would indicate that the disassembler can't continue. - If no matching opcode is found then the returned result will be TRUE, the + If no matching opcode is found then the returned result will be true, the value placed into OPCODE_RESULT will be NULL, ITER will be undefined, and INSN_LEN will be unchanged. - If a matching opcode is found, then the returned result will be TRUE, the + If a matching opcode is found, then the returned result will be true, the opcode pointer is placed into OPCODE_RESULT, INSN_LEN will be increased by 4 if the instruction requires a LIMM, and the LIMM value will have been loaded into a field of ITER. Finally, ITER will have been initialised so @@ -421,11 +468,14 @@ find_format (bfd_vma memaddr, struct arc_operand_iterator * iter) { const struct arc_opcode *opcode = NULL; + const struct arc_opcode *opcodeList = NULL; bool needs_limm = false; const extInstruction_t *einsn, *i; unsigned limm = 0; struct arc_disassemble_info *arc_infop = info->private_data; + opcodeList = arc_opcodes; + /* First, try the extension instructions. */ if (*insn_len == 4) { @@ -452,7 +502,7 @@ find_format (bfd_vma memaddr, /* Then, try finding the first match in the opcode table. */ if (opcode == NULL) - opcode = find_format_from_table (info, arc_opcodes, insn, *insn_len, + opcode = find_format_from_table (info, opcodeList, insn, *insn_len, isa_mask, &needs_limm, true); if (opcode != NULL && needs_limm) @@ -542,8 +592,14 @@ print_flags (const struct arc_opcode *opcode, if (!flg_operand->favail) continue; - value = (insn[0] >> flg_operand->shift) - & ((1 << flg_operand->bits) - 1); + if (cl_flags->extract) + { + bool tmp = false; + value = (*cl_flags->extract)(insn[0], &tmp); + } + else + value = (insn[0] >> flg_operand->shift) + & ((1 << flg_operand->bits) - 1); if (value == flg_operand->code) { /* FIXME!: print correctly nt/t flag. */ @@ -646,34 +702,59 @@ arc_insn_length (bfd_byte msb, bfd_byte lsb, struct disassemble_info *info) { bfd_byte major_opcode = msb >> 3; - switch (info->mach) + switch (info->arch) { - case bfd_mach_arc_arc700: - /* The nps400 extension set requires this special casing of the - instruction length calculation. Right now this is not causing any - problems as none of the known extensions overlap in opcode space, - but, if they ever do then we might need to start carrying - information around in the elf about which extensions are in use. */ - if (major_opcode == 0xb) - { - bfd_byte minor_opcode = lsb & 0x1f; + case bfd_arch_arc: + switch (info->mach) + { + case bfd_mach_arc_arc700: + /* The nps400 extension set requires this special casing of + the instruction length calculation. Right now this is + not causing any problems as none of the known extensions + overlap in opcode space, but, if they ever do then we + might need to start carrying information around in the + elf about which extensions are in use. */ + if (major_opcode == 0xb) + { + bfd_byte minor_opcode = lsb & 0x1f; - if (minor_opcode < 4) - return 6; - else if (minor_opcode == 0x10 || minor_opcode == 0x11) - return 8; - } - if (major_opcode == 0xa) - { - return 8; - } - /* Fall through. */ - case bfd_mach_arc_arc600: - return (major_opcode > 0xb) ? 2 : 4; + if (minor_opcode < 4) + return 6; + else if (minor_opcode == 0x10 || minor_opcode == 0x11) + return 8; + } + if (major_opcode == 0xa) + { + return 8; + } + /* Fall through. */ + case bfd_mach_arc_arc600: + return (major_opcode > 0xb) ? 2 : 4; + break; + + case bfd_mach_arc_arcv2: + return (major_opcode > 0x7) ? 2 : 4; + break; + + default: + return 0; + } break; - case bfd_mach_arc_arcv2: - return (major_opcode > 0x7) ? 2 : 4; + case bfd_arch_arc64: + switch (info->mach) + { + case bfd_mach_arcv3_32: + case bfd_mach_arcv3_64: + if (major_opcode == 0x0b + || major_opcode == 0x0d + || major_opcode == 0x1c) + return 4; + return (major_opcode > 0x7) ? 2 : 4; + + default: + return 0; + } break; default: @@ -723,8 +804,8 @@ extract_operand_value (const struct arc_operand *operand, return value; } -/* Find the next operand, and the operands value from ITER. Return TRUE if - there is another operand, otherwise return FALSE. If there is an +/* Find the next operand, and the operands value from ITER. Return true if + there is another operand, otherwise return false. If there is an operand returned then the operand is placed into OPERAND, and the value into VALUE. If there is no operand returned then OPERAND and VALUE are unchanged. */ @@ -808,14 +889,18 @@ parse_option (const char *option) } #define ARC_CPU_TYPE_A6xx(NAME,EXTRA) \ - { #NAME, ARC_OPCODE_ARC600, "ARC600" } + { #NAME, ARC_OPCODE_ARC600, "ARC600" }, #define ARC_CPU_TYPE_A7xx(NAME,EXTRA) \ - { #NAME, ARC_OPCODE_ARC700, "ARC700" } + { #NAME, ARC_OPCODE_ARC700, "ARC700" }, #define ARC_CPU_TYPE_AV2EM(NAME,EXTRA) \ - { #NAME, ARC_OPCODE_ARCv2EM, "ARC EM" } + { #NAME, ARC_OPCODE_ARCv2EM, "ARC EM" }, #define ARC_CPU_TYPE_AV2HS(NAME,EXTRA) \ - { #NAME, ARC_OPCODE_ARCv2HS, "ARC HS" } -#define ARC_CPU_TYPE_NONE \ + { #NAME, ARC_OPCODE_ARCv2HS, "ARC HS" }, +#define ARC_CPU_TYPE_A64x(NAME,EXTRA) \ + { #NAME, ARC_OPCODE_ARC64, "ARC64" }, +#define ARC_CPU_TYPE_A32x(NAME,EXTRA) \ + { #NAME, ARC_OPCODE_ARC64, "ARC32" }, +#define ARC_CPU_TYPE_NONE \ { 0, 0, 0 } /* A table of CPU names and opcode sets. */ @@ -950,7 +1035,8 @@ print_insn_arc (bfd_vma memaddr, bool open_braket; int size; const struct arc_operand *operand; - int value, vpcl; + int value; + bfd_vma vpcl; struct arc_operand_iterator iter; struct arc_disassemble_info *arc_infop; bool rpcl = false, rset = false; @@ -978,25 +1064,54 @@ print_insn_arc (bfd_vma memaddr, if (info->section && info->section->owner) header = elf_elfheader (info->section->owner); - switch (info->mach) + switch (info->arch) { - case bfd_mach_arc_arc700: - isa_mask = ARC_OPCODE_ARC700; + case bfd_arch_arc: + switch (info->mach) + { + case bfd_mach_arc_arc700: + isa_mask = ARC_OPCODE_ARC700; + break; + + case bfd_mach_arc_arc600: + isa_mask = ARC_OPCODE_ARC600; + break; + + case bfd_mach_arc_arcv2: + default: + isa_mask = ARC_OPCODE_ARCv2EM; + /* TODO: Perhaps remove definition of header since it is + only used at this location. */ + if (header != NULL + && (header->e_flags & EF_ARC_MACH_MSK) == EF_ARC_CPU_ARCV2HS) + isa_mask = ARC_OPCODE_ARCv2HS; + break; + } break; - case bfd_mach_arc_arc600: - isa_mask = ARC_OPCODE_ARC600; + case bfd_arch_arc64: + switch (info->mach) + { + case bfd_mach_arcv3_64: + isa_mask = ARC_OPCODE_ARC64; + break; + + case bfd_mach_arcv3_32: + isa_mask = ARC_OPCODE_ARC32; + break; + + default: + /* xgettext:c-format */ + opcodes_error_handler (_("unrecognised arc64 disassembler \ +variant")); + return -1; + } break; - case bfd_mach_arc_arcv2: default: - isa_mask = ARC_OPCODE_ARCv2EM; - /* TODO: Perhaps remove definition of header since it is only used at - this location. */ - if (header != NULL - && (header->e_flags & EF_ARC_MACH_MSK) == EF_ARC_CPU_ARCV2HS) - isa_mask = ARC_OPCODE_ARCv2HS; - break; + /* xgettext:c-format */ + opcodes_error_handler (_("unrecognised disassembler architecture")); + return -1; } } else @@ -1289,8 +1404,10 @@ print_insn_arc (bfd_vma memaddr, rpcl = true; vpcl = value; rset = true; - - info->target = (bfd_vma) (memaddr & ~3) + value; + if ((operand->flags & ARC_OPERAND_LIMM) + && (operand->flags & ARC_OPERAND_ALIGNED32)) + vpcl <<= 2; + info->target = (bfd_vma) (memaddr & ~3) + vpcl; } else if (!(operand->flags & ARC_OPERAND_IR)) { @@ -1303,10 +1420,15 @@ print_insn_arc (bfd_vma memaddr, { const char *rname; - assert (value >=0 && value < 64); + assert (value >= 0 && value < 64); rname = arcExtMap_coreRegName (value); if (!rname) - rname = regnames[value]; + { + if (operand->flags & ARC_OPERAND_FP) + rname = fpnames[value & 0x1f]; + else + rname = getregname (value, isa_mask); + } (*info->fprintf_styled_func) (info->stream, dis_style_register, "%s", rname); @@ -1316,8 +1438,10 @@ print_insn_arc (bfd_vma memaddr, if ((value & 0x01) == 0) { rname = arcExtMap_coreRegName (value + 1); - if (!rname) - rname = regnames[value + 1]; + if (operand->flags & ARC_OPERAND_FP) + rname = fpnames[(value + 1) & 0x1f]; + else + rname = getregname (value + 1, isa_mask); } else rname = _("\nWarning: illegal use of double register " @@ -1325,7 +1449,7 @@ print_insn_arc (bfd_vma memaddr, (*info->fprintf_styled_func) (info->stream, dis_style_register, "%s", rname); } - if (value == 63) + if (value == REG_PCL) rpcl = true; else rpcl = false; @@ -1339,8 +1463,12 @@ print_insn_arc (bfd_vma memaddr, "%s", rname); else { - (*info->fprintf_styled_func) (info->stream, dis_style_immediate, - "%#x", value); + if (operand->flags & ARC_OPERAND_SIGNED) + (*info->fprintf_styled_func) (info->stream, dis_style_immediate, + "%d@s32", value); + else + (*info->fprintf_styled_func) (info->stream, dis_style_immediate, + "%#x", value); if (info->insn_type == dis_branch || info->insn_type == dis_jsr) info->target = (bfd_vma) value; @@ -1418,7 +1546,7 @@ print_insn_arc (bfd_vma memaddr, = ARC_OPERAND_KIND_LIMM; /* It is not important to have exactly the LIMM indicator here. */ - arc_infop->operands[arc_infop->operands_count].value = 63; + arc_infop->operands[arc_infop->operands_count].value = REG_PCL; } else { diff --git a/opcodes/arc-ext-tbl.h b/opcodes/arc-ext-tbl.h deleted file mode 100644 index d230b610e8c..00000000000 --- a/opcodes/arc-ext-tbl.h +++ /dev/null @@ -1,124 +0,0 @@ -/* ARC instruction defintions. - Copyright (C) 2016-2023 Free Software Foundation, Inc. - - Contributed by Claudiu Zissulescu (claziss@synopsys.com) - - This file is part of libopcodes. - - This library is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - It is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software Foundation, - Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -/* Common combinations of FLAGS. */ -#define FLAGS_NONE { 0 } -#define FLAGS_F { C_F } -#define FLAGS_CC { C_CC } -#define FLAGS_CCF { C_CC, C_F } - -/* Common combination of arguments. */ -#define ARG_NONE { 0 } -#define ARG_32BIT_RARBRC { RA, RB, RC } -#define ARG_32BIT_ZARBRC { ZA, RB, RC } -#define ARG_32BIT_RBRBRC { RB, RBdup, RC } -#define ARG_32BIT_RARBU6 { RA, RB, UIMM6_20 } -#define ARG_32BIT_ZARBU6 { ZA, RB, UIMM6_20 } -#define ARG_32BIT_RBRBU6 { RB, RBdup, UIMM6_20 } -#define ARG_32BIT_RBRBS12 { RB, RBdup, SIMM12_20 } -#define ARG_32BIT_RALIMMRC { RA, LIMM, RC } -#define ARG_32BIT_RARBLIMM { RA, RB, LIMM } -#define ARG_32BIT_ZALIMMRC { ZA, LIMM, RC } -#define ARG_32BIT_ZARBLIMM { ZA, RB, LIMM } - -#define ARG_32BIT_RBRBLIMM { RB, RBdup, LIMM } -#define ARG_32BIT_RALIMMU6 { RA, LIMM, UIMM6_20 } -#define ARG_32BIT_ZALIMMU6 { ZA, LIMM, UIMM6_20 } - -#define ARG_32BIT_ZALIMMS12 { ZA, LIMM, SIMM12_20 } -#define ARG_32BIT_RALIMMLIMM { RA, LIMM, LIMMdup } -#define ARG_32BIT_ZALIMMLIMM { ZA, LIMM, LIMMdup } - -#define ARG_32BIT_RBRC { RB, RC } -#define ARG_32BIT_ZARC { ZA, RC } -#define ARG_32BIT_RBU6 { RB, UIMM6_20 } -#define ARG_32BIT_ZAU6 { ZA, UIMM6_20 } -#define ARG_32BIT_RBLIMM { RB, LIMM } -#define ARG_32BIT_ZALIMM { ZA, LIMM } - -/* Macro to generate 2 operand extension instruction. */ -#define EXTINSN2OPF(NAME, CPU, CLASS, SCLASS, MOP, SOP, FL) \ - { NAME, INSN2OP_BC (MOP,SOP), MINSN2OP_BC, CPU, CLASS, SCLASS, \ - ARG_32BIT_RBRC, FL }, \ - { NAME, INSN2OP_0C (MOP,SOP), MINSN2OP_0C, CPU, CLASS, SCLASS, \ - ARG_32BIT_ZARC, FL }, \ - { NAME, INSN2OP_BU (MOP,SOP), MINSN2OP_BU, CPU, CLASS, SCLASS, \ - ARG_32BIT_RBU6, FL }, \ - { NAME, INSN2OP_0U (MOP,SOP), MINSN2OP_0U, CPU, CLASS, SCLASS, \ - ARG_32BIT_ZAU6, FL }, \ - { NAME, INSN2OP_BL (MOP,SOP), MINSN2OP_BL, CPU, CLASS, SCLASS, \ - ARG_32BIT_RBLIMM, FL }, \ - { NAME, INSN2OP_0L (MOP,SOP), MINSN2OP_0L, CPU, CLASS, SCLASS, \ - ARG_32BIT_ZALIMM, FL }, - -#define EXTINSN2OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \ - EXTINSN2OPF(NAME, CPU, CLASS, SCLASS, MOP, SOP, FLAGS_F) - -/* Macro to generate 3 operand extesion instruction. */ -#define EXTINSN3OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \ - { NAME, INSN3OP_ABC (MOP,SOP), MINSN3OP_ABC, CPU, CLASS, SCLASS, \ - ARG_32BIT_RARBRC, FLAGS_F }, \ - { NAME, INSN3OP_0BC (MOP,SOP), MINSN3OP_0BC, CPU, CLASS, SCLASS, \ - ARG_32BIT_ZARBRC, FLAGS_F }, \ - { NAME, INSN3OP_CBBC (MOP,SOP), MINSN3OP_CBBC, CPU, CLASS, SCLASS, \ - ARG_32BIT_RBRBRC, FLAGS_CCF }, \ - { NAME, INSN3OP_ABU (MOP,SOP), MINSN3OP_ABU, CPU, CLASS, SCLASS, \ - ARG_32BIT_RARBU6, FLAGS_F }, \ - { NAME, INSN3OP_0BU (MOP,SOP), MINSN3OP_0BU, CPU, CLASS, SCLASS, \ - ARG_32BIT_ZARBU6, FLAGS_F }, \ - { NAME, INSN3OP_CBBU (MOP,SOP), MINSN3OP_CBBU, CPU, CLASS, SCLASS, \ - ARG_32BIT_RBRBU6, FLAGS_CCF }, \ - { NAME, INSN3OP_BBS (MOP,SOP), MINSN3OP_BBS, CPU, CLASS, SCLASS, \ - ARG_32BIT_RBRBS12, FLAGS_F }, \ - { NAME, INSN3OP_ALC (MOP,SOP), MINSN3OP_ALC, CPU, CLASS, SCLASS, \ - ARG_32BIT_RALIMMRC, FLAGS_F }, \ - { NAME, INSN3OP_ABL (MOP,SOP), MINSN3OP_ABL, CPU, CLASS, SCLASS, \ - ARG_32BIT_RARBLIMM, FLAGS_F }, \ - { NAME, INSN3OP_0LC (MOP,SOP), MINSN3OP_0LC, CPU, CLASS, SCLASS, \ - ARG_32BIT_ZALIMMRC, FLAGS_F }, \ - { NAME, INSN3OP_0BL (MOP,SOP), MINSN3OP_0BL, CPU, CLASS, SCLASS, \ - ARG_32BIT_ZARBLIMM, FLAGS_F }, \ - { NAME, INSN3OP_C0LC (MOP,SOP), MINSN3OP_C0LC, CPU, CLASS, SCLASS, \ - ARG_32BIT_ZALIMMRC, FLAGS_CCF }, \ - { NAME, INSN3OP_CBBL (MOP,SOP), MINSN3OP_CBBL, CPU, CLASS, SCLASS, \ - ARG_32BIT_RBRBLIMM, FLAGS_CCF }, \ - { NAME, INSN3OP_ALU (MOP,SOP), MINSN3OP_ALU, CPU, CLASS, SCLASS, \ - ARG_32BIT_RALIMMU6, FLAGS_F }, \ - { NAME, INSN3OP_0LU (MOP,SOP), MINSN3OP_0LU, CPU, CLASS, SCLASS, \ - ARG_32BIT_ZALIMMU6, FLAGS_F }, \ - { NAME, INSN3OP_C0LU (MOP,SOP), MINSN3OP_C0LU, CPU, CLASS, SCLASS, \ - ARG_32BIT_ZALIMMU6, FLAGS_CCF }, \ - { NAME, INSN3OP_0LS (MOP,SOP), MINSN3OP_0LS, CPU, CLASS, SCLASS, \ - ARG_32BIT_ZALIMMS12, FLAGS_F }, \ - { NAME, INSN3OP_ALL (MOP,SOP), MINSN3OP_ALL, CPU, CLASS, SCLASS, \ - ARG_32BIT_RALIMMLIMM, FLAGS_F }, \ - { NAME, INSN3OP_0LL (MOP,SOP), MINSN3OP_0LL, CPU, CLASS, SCLASS, \ - ARG_32BIT_ZALIMMLIMM, FLAGS_F }, \ - { NAME, INSN3OP_C0LL (MOP,SOP), MINSN3OP_C0LL, CPU, CLASS, SCLASS, \ - ARG_32BIT_ZALIMMLIMM, FLAGS_CCF }, - -/* Extension instruction declarations. */ -EXTINSN2OP ("dsp_fp_flt2i", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE1, 7, 43) -EXTINSN2OP ("dsp_fp_i2flt", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE1, 7, 44) -EXTINSN2OP ("dsp_fp_sqrt", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE2, 7, 45) - -EXTINSN3OP ("dsp_fp_div", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE2, 7, 42) -EXTINSN3OP ("dsp_fp_cmp", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE1, 7, 43) diff --git a/opcodes/arc-flag-classes.def b/opcodes/arc-flag-classes.def new file mode 100644 index 00000000000..bb33d033b58 --- /dev/null +++ b/opcodes/arc-flag-classes.def @@ -0,0 +1,125 @@ +/* ARC flag class defintions. + Copyright (C) 2023 Free Software Foundation, Inc. + + Contributed by Claudiu Zissulescu (claziss@synopsys.com) + Refactored by Cupertino Miranda (cmiranda@synopsys.com) + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +FLAG_CLASS(EMPTY, F_CLASS_NONE, 0, 0, F_NULL) +FLAG_CLASS(CC_EQ, F_CLASS_IMPLICIT | F_CLASS_COND, 0, 0 , F_EQUAL) +FLAG_CLASS(CC_GE, F_CLASS_IMPLICIT | F_CLASS_COND, 0, 0 , F_GE) +FLAG_CLASS(CC_GT, F_CLASS_IMPLICIT | F_CLASS_COND, 0, 0, F_GT) +FLAG_CLASS(CC_HI, F_CLASS_IMPLICIT | F_CLASS_COND, 0, 0, F_HI) +FLAG_CLASS(CC_HS, F_CLASS_IMPLICIT | F_CLASS_COND, 0, 0, F_NOTCARRY) +FLAG_CLASS(CC_LE, F_CLASS_IMPLICIT | F_CLASS_COND, 0, 0, F_LE) +FLAG_CLASS(CC_LO, F_CLASS_IMPLICIT | F_CLASS_COND, 0, 0, F_CARRY) +FLAG_CLASS(CC_LS, F_CLASS_IMPLICIT | F_CLASS_COND, 0, 0, F_LS) +FLAG_CLASS(CC_LT, F_CLASS_IMPLICIT | F_CLASS_COND, 0, 0, F_LT) +FLAG_CLASS(CC_NE, F_CLASS_IMPLICIT | F_CLASS_COND, 0, 0, F_NOTEQUAL) + +FLAG_CLASS(AA_AB, F_CLASS_IMPLICIT | F_CLASS_WB, 0, 0, F_AB3) +FLAG_CLASS(AA_AW, F_CLASS_IMPLICIT | F_CLASS_WB, 0, 0, F_AW3) + +FLAG_CLASS(ZZ_D, F_CLASS_IMPLICIT | F_CLASS_ZZ, 0, 0, F_SIZED) +FLAG_CLASS(ZZ_L, F_CLASS_IMPLICIT | F_CLASS_ZZ, 0, 0, F_SIZEL) +FLAG_CLASS(ZZ_W, F_CLASS_IMPLICIT | F_CLASS_ZZ, 0, 0, F_SIZEW) +FLAG_CLASS(ZZ_H, F_CLASS_IMPLICIT | F_CLASS_ZZ, 0, 0, F_H1) +FLAG_CLASS(ZZ_B, F_CLASS_IMPLICIT | F_CLASS_ZZ, 0, 0, F_SIZEB1) + +FLAG_CLASS(CC, F_CLASS_OPTIONAL | F_CLASS_EXTEND | F_CLASS_COND, 0, 0, F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NJ, F_NM, F_NO_T) + +FLAG_CLASS(AA_ADDR3, F_CLASS_OPTIONAL | F_CLASS_WB, 0, 0, F_A3, F_AW3, F_AB3, F_AS3) +FLAG_CLASS(AA27, F_CLASS_OPTIONAL | F_CLASS_WB, 0, 0, F_A3, F_AW3, F_AB3, F_AS3) +FLAG_CLASS(AS27, F_CLASS_OPTIONAL, 0, 0, F_AS3) +FLAG_CLASS(AA_ADDR9, F_CLASS_OPTIONAL | F_CLASS_WB, 0, 0, F_A9, F_AW9, F_AB9, F_AS9) +FLAG_CLASS(AA21, F_CLASS_OPTIONAL | F_CLASS_WB, 0, 0, F_A9, F_AW9, F_AB9, F_AS9) +FLAG_CLASS(AAB21, F_CLASS_OPTIONAL | F_CLASS_WB, 0, 0, F_A9, F_AW9, F_AB9) +FLAG_CLASS(AA_ADDR22, F_CLASS_OPTIONAL | F_CLASS_WB, 0, 0, F_A22, F_AW22, F_AB22, F_AS22) +FLAG_CLASS(AA8, F_CLASS_OPTIONAL | F_CLASS_WB, 0, 0, F_A22, F_AW22, F_AB22, F_AS22) +FLAG_CLASS(AAB8, F_CLASS_OPTIONAL | F_CLASS_WB, 0, 0, F_A22, F_AW22, F_AB22) + +FLAG_CLASS(F, F_CLASS_OPTIONAL, 0, 0, F_FLAG) +FLAG_CLASS(FHARD, F_CLASS_OPTIONAL, 0, 0, F_FFAKE) + +FLAG_CLASS(RL, F_CLASS_OPTIONAL, 0, 0, F_RL) +FLAG_CLASS(AQ, F_CLASS_OPTIONAL, 0, 0, F_AQ) + +FLAG_CLASS(ATOP, F_CLASS_REQUIRED, 0, 0, F_ATO_ADD, F_ATO_OR, F_ATO_AND, F_ATO_XOR, F_ATO_MINU, F_ATO_MAXU, F_ATO_MIN, F_ATO_MAX) + +FLAG_CLASS(T, F_CLASS_OPTIONAL, 0, 0, F_NT, F_T) +FLAG_CLASS(D, F_CLASS_OPTIONAL, 0, 0, F_ND, F_D) +FLAG_CLASS(DNZ_D, F_CLASS_OPTIONAL, 0, 0, F_DNZ_ND, F_DNZ_D) + +FLAG_CLASS(DHARD, F_CLASS_OPTIONAL, 0, 0, F_DFAKE) + +FLAG_CLASS(DI20, F_CLASS_OPTIONAL, 0, 0, F_DI11) +FLAG_CLASS(DI14, F_CLASS_OPTIONAL, 0, 0, F_DI14) +FLAG_CLASS(DI16, F_CLASS_OPTIONAL, 0, 0, F_DI15) +FLAG_CLASS(DI26, F_CLASS_OPTIONAL, 0, 0, F_DI5) + +FLAG_CLASS(X25, F_CLASS_OPTIONAL, 0, 0, F_SIGN6) +FLAG_CLASS(X15, F_CLASS_OPTIONAL, 0, 0, F_SIGN16) +FLAG_CLASS(XHARD, F_CLASS_OPTIONAL, 0, 0, F_SIGNX) +FLAG_CLASS(X, F_CLASS_OPTIONAL, 0, 0, F_SIGNX) + +FLAG_CLASS(ZZ13, F_CLASS_OPTIONAL, 0, 0, F_SIZEB17, F_SIZEW17, F_H17) +FLAG_CLASS(ZZ23, F_CLASS_OPTIONAL, 0, 0, F_SIZEB7, F_SIZEW7, F_H7) +FLAG_CLASS(ZZ29, F_CLASS_OPTIONAL, 0, 0, F_SIZEB1, F_SIZEW1, F_H1) +FLAG_CLASS(ZZW6, F_CLASS_OPTIONAL, 0, 0, F_SIZEB1) +FLAG_CLASS(ZZH1, F_CLASS_OPTIONAL, 0, 0, F_SIZEW1, F_H1) + +FLAG_CLASS(AS, F_CLASS_OPTIONAL, 0, 0, F_ASFAKE) +FLAG_CLASS(AAHARD13, F_CLASS_OPTIONAL, 0, 0, F_ASFAKE) +FLAG_CLASS(NE, F_CLASS_REQUIRED, 0, 0, F_NE) + +/* ARC NPS400 Support: See comment near head of file. */ +FLAG_CLASS(NPS_CL, F_CLASS_REQUIRED, 0, 0, F_NPS_CL) +FLAG_CLASS(NPS_NA, F_CLASS_OPTIONAL, 0, 0, F_NPS_NA) +FLAG_CLASS(NPS_SR, F_CLASS_OPTIONAL, 0, 0, F_NPS_SR) +FLAG_CLASS(NPS_M, F_CLASS_OPTIONAL, 0, 0, F_NPS_M) +FLAG_CLASS(NPS_F, F_CLASS_OPTIONAL, 0, 0, F_NPS_FLAG) +FLAG_CLASS(NPS_R, F_CLASS_OPTIONAL, 0, 0, F_NPS_R) +FLAG_CLASS(NPS_SCHD_RW, F_CLASS_REQUIRED, 0, 0, F_NPS_RW, F_NPS_RD) +FLAG_CLASS(NPS_SCHD_TRIG, F_CLASS_REQUIRED, 0, 0, F_NPS_WFT) +FLAG_CLASS(NPS_SCHD_IE, F_CLASS_OPTIONAL, 0, 0, F_NPS_IE1, F_NPS_IE2, F_NPS_IE12) +FLAG_CLASS(NPS_SYNC, F_CLASS_REQUIRED, 0, 0, F_NPS_SYNC_RD, F_NPS_SYNC_WR) +FLAG_CLASS(NPS_HWS_OFF, F_CLASS_REQUIRED, 0, 0, F_NPS_HWS_OFF) +FLAG_CLASS(NPS_HWS_RESTORE, F_CLASS_REQUIRED, 0, 0, F_NPS_HWS_RESTORE) +FLAG_CLASS(NPS_SX, F_CLASS_OPTIONAL, 0, 0, F_NPS_SX) +FLAG_CLASS(NPS_AR_AL, F_CLASS_REQUIRED, 0, 0, F_NPS_AR, F_NPS_AL) +FLAG_CLASS(NPS_S, F_CLASS_REQUIRED, 0, 0, F_NPS_S) +FLAG_CLASS(NPS_ZNCV, F_CLASS_REQUIRED, 0, 0, F_NPS_ZNCV_RD, F_NPS_ZNCV_WR) +FLAG_CLASS(NPS_P0, F_CLASS_REQUIRED, 0, 0, F_NPS_P0) +FLAG_CLASS(NPS_P1, F_CLASS_REQUIRED, 0, 0, F_NPS_P1) +FLAG_CLASS(NPS_P2, F_CLASS_REQUIRED, 0, 0, F_NPS_P2) +FLAG_CLASS(NPS_P3, F_CLASS_REQUIRED, 0, 0, F_NPS_P3) +FLAG_CLASS(NPS_LDBIT_DI, F_CLASS_REQUIRED, 0, 0, F_NPS_LDBIT_DI) +FLAG_CLASS(NPS_LDBIT_CL1, F_CLASS_OPTIONAL, 0, 0, F_NPS_LDBIT_CL1) +FLAG_CLASS(NPS_LDBIT_CL2, F_CLASS_OPTIONAL, 0, 0, F_NPS_LDBIT_CL2) +FLAG_CLASS(NPS_LDBIT_X_1, F_CLASS_OPTIONAL, 0, 0, F_NPS_LDBIT_X2_1, F_NPS_LDBIT_X4_1) +FLAG_CLASS(NPS_LDBIT_X_2, F_CLASS_OPTIONAL, 0, 0, F_NPS_LDBIT_X2_2, F_NPS_LDBIT_X4_2) +FLAG_CLASS(NPS_CORE, F_CLASS_REQUIRED, 0, 0, F_NPS_CORE) +FLAG_CLASS(NPS_CLSR, F_CLASS_REQUIRED, 0, 0, F_NPS_CLSR) +FLAG_CLASS(NPS_ALL, F_CLASS_REQUIRED, 0, 0, F_NPS_ALL) +FLAG_CLASS(NPS_GIC, F_CLASS_REQUIRED, 0, 0, F_NPS_GIC) +FLAG_CLASS(NPS_RSPI_GIC, F_CLASS_REQUIRED, 0, 0, F_NPS_RSPI_GIC) +FLAG_CLASS(FPCC, F_CLASS_OPTIONAL | F_CLASS_EXTEND | F_CLASS_COND, insert_fs2, extract_fs2, F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NJ, F_NM, F_NO_T) +FLAG_CLASS(AA_128, F_CLASS_OPTIONAL | F_CLASS_WB, 0, 0, F_AA128, F_AA128W, F_AA128B, F_AA128S) +FLAG_CLASS(AS_128, F_CLASS_OPTIONAL, 0, 0, F_AA128S) +FLAG_CLASS(AA_128S, F_CLASS_OPTIONAL | F_CLASS_WB, insert_qq, extract_qq, F_AA128, F_AA128W, F_AA128B, F_AA128S) +FLAG_CLASS(AS_128S, F_CLASS_OPTIONAL, insert_qq, extract_qq, F_AA128S) diff --git a/opcodes/arc-flag.def b/opcodes/arc-flag.def new file mode 100644 index 00000000000..1312c464a3c --- /dev/null +++ b/opcodes/arc-flag.def @@ -0,0 +1,179 @@ +/* ARC flag defintions. + Copyright (C) 2023 Free Software Foundation, Inc. + + Contributed by Claudiu Zissulescu (claziss@synopsys.com) + Refactored by Cupertino Miranda (cmiranda@synopsys.com) + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +FLAG(ALWAYS, "al", 0, 0, 0, 0) +FLAG(RA, "ra", 0, 0, 0, 0) +FLAG(EQUAL, "eq", 1, 5, 0, 1) +FLAG(ZERO, "z", 1, 5, 0, 0) +FLAG(NOTEQUAL, "ne", 2, 5, 0, 1) +FLAG(NOTZERO, "nz", 2, 5, 0, 0) +FLAG(POZITIVE, "p", 3, 5, 0, 1) +FLAG(PL, "pl", 3, 5, 0, 0) +FLAG(NEGATIVE, "n", 4, 5, 0, 1) +FLAG(MINUS, "mi", 4, 5, 0, 0) +FLAG(CARRY, "c", 5, 5, 0, 1) +FLAG(CARRYSET, "cs", 5, 5, 0, 0) +FLAG(LOWER, "lo", 5, 5, 0, 0) +FLAG(CARRYCLR, "cc", 6, 5, 0, 0) +FLAG(NOTCARRY, "nc", 6, 5, 0, 1) +FLAG(HIGHER, "hs", 6, 5, 0, 0) +FLAG(OVERFLOWSET, "vs", 7, 5, 0, 0) +FLAG(OVERFLOW, "v", 7, 5, 0, 1) +FLAG(NOTOVERFLOW, "nv", 8, 5, 0, 1) +FLAG(OVERFLOWCLR, "vc", 8, 5, 0, 0) +FLAG(GT, "gt", 9, 5, 0, 1) +FLAG(GE, "ge", 10, 5, 0, 1) +FLAG(LT, "lt", 11, 5, 0, 1) +FLAG(LE, "le", 12, 5, 0, 1) +FLAG(HI, "hi", 13, 5, 0, 1) +FLAG(LS, "ls", 14, 5, 0, 1) +FLAG(PNZ, "pnz", 15, 5, 0, 1) +FLAG(NJ, "nj", 21, 5, 0, 1) +FLAG(NM, "nm", 23, 5, 0, 1) +FLAG(NO_T, "nt", 24, 5, 0, 1) + + /* FLAG. */ +FLAG(FLAG, "f", 1, 1, 15, 1) +FLAG(FFAKE, "f", 0, 0, 0, 1) +FLAG(AQ, "aq", 1, 1, 15, 1) +FLAG(RL, "rl", 1, 1, 15, 1) + + /* Atomic operations. */ +FLAG(ATO_ADD, "add", 0, 3, 0, 1) +FLAG(ATO_OR, "or", 1, 3, 0, 1) +FLAG(ATO_AND, "and", 2, 3, 0, 1) +FLAG(ATO_XOR, "xor", 3, 3, 0, 1) +FLAG(ATO_MINU, "minu", 4, 3, 0, 1) +FLAG(ATO_MAXU, "maxu", 5, 3, 0, 1) +FLAG(ATO_MIN, "min", 6, 3, 0, 1) +FLAG(ATO_MAX, "max", 7, 3, 0, 1) + + /* Delay slot. */ +FLAG(ND, "nd", 0, 1, 5, 0) +FLAG(D, "d", 1, 1, 5, 1) +FLAG(DFAKE, "d", 0, 0, 0, 1) +FLAG(DNZ_ND, "nd", 0, 1, 16, 0) +FLAG(DNZ_D, "d", 1, 1, 16, 1) + + /* Data size. */ +FLAG(SIZEB1, "b", 1, 2, 1, 1) +FLAG(SIZEB7, "b", 1, 2, 7, 1) +FLAG(SIZEB17, "b", 1, 2, 17, 1) +FLAG(SIZEW1, "w", 2, 2, 1, 0) +FLAG(SIZEW7, "w", 2, 2, 7, 0) +FLAG(SIZEW17, "w", 2, 2, 17, 0) + + /* Sign extension. */ +FLAG(SIGN6, "x", 1, 1, 6, 1) +FLAG(SIGN16, "x", 1, 1, 16, 1) +FLAG(SIGNX, "x", 0, 0, 0, 1) + + /* Address write-back modes. */ +FLAG(A3, "a", 1, 2, 3, 0) +FLAG(A9, "a", 1, 2, 9, 0) +FLAG(A22, "a", 1, 2, 22, 0) +FLAG(AW3, "aw", 1, 2, 3, 1) +FLAG(AW9, "aw", 1, 2, 9, 1) +FLAG(AW22, "aw", 1, 2, 22, 1) +FLAG(AB3, "ab", 2, 2, 3, 1) +FLAG(AB9, "ab", 2, 2, 9, 1) +FLAG(AB22, "ab", 2, 2, 22, 1) +FLAG(AS3, "as", 3, 2, 3, 1) +FLAG(AS9, "as", 3, 2, 9, 1) +FLAG(AS22, "as", 3, 2, 22, 1) +FLAG(ASFAKE, "as", 0, 0, 0, 1) + +/* address writebacks for 128-bit loads. + ,---.---.----------. + | X | D | mnemonic | + |---+---+----------| + | 0 | 0 | none | + | 0 | 1 | as | + | 1 | 0 | a/aw | + | 1 | 1 | ab | + `---^---^----------' */ +FLAG(AA128, "a", 2, 2, 15, 0) +FLAG(AA128W, "aw", 2, 2, 15, 1) +FLAG(AA128B, "ab", 3, 2, 15, 1) +FLAG(AA128S, "as", 1, 2, 15, 1) + + /* Cache bypass. */ +FLAG(DI5, "di", 1, 1, 5, 1) +FLAG(DI11, "di", 1, 1, 11, 1) +FLAG(DI14, "di", 1, 1, 14, 1) +FLAG(DI15, "di", 1, 1, 15, 1) + + /* ARCv2 specific. */ +FLAG(NT, "nt", 0, 1, 3, 1) +FLAG(T, "t", 1, 1, 3, 1) +FLAG(H1, "h", 2, 2, 1, 1) +FLAG(H7, "h", 2, 2, 7, 1) +FLAG(H17, "h", 2, 2, 17, 1) +/* Fake */ +FLAG(SIZED, "dd", 8, 0, 0, 0) +/* Fake */ +FLAG(SIZEL, "dl", 8, 0, 0, 0) +/* Fake */ +FLAG(SIZEW, "xx", 4, 0, 0, 0) + + /* Fake Flags. */ +FLAG(NE, "ne", 0, 0, 0, 1) + +/* ARC NPS400 Support: See comment near head of arcxx-opc.inc file. */ +FLAG(NPS_CL, "cl", 0, 0, 0, 1) +FLAG(NPS_NA, "na", 1, 1, 9, 1) +FLAG(NPS_SR, "s", 1, 1, 13, 1) +FLAG(NPS_M, "m", 1, 1, 7, 1) +FLAG(NPS_FLAG, "f", 1, 1, 20, 1) +FLAG(NPS_R, "r", 1, 1, 15, 1) +FLAG(NPS_RW, "rw", 0, 1, 7, 1) +FLAG(NPS_RD, "rd", 1, 1, 7, 1) +FLAG(NPS_WFT, "wft", 0, 0, 0, 1) +FLAG(NPS_IE1, "ie1", 1, 2, 8, 1) +FLAG(NPS_IE2, "ie2", 2, 2, 8, 1) +FLAG(NPS_IE12, "ie12", 3, 2, 8, 1) +FLAG(NPS_SYNC_RD, "rd", 0, 1, 6, 1) +FLAG(NPS_SYNC_WR, "wr", 1, 1, 6, 1) +FLAG(NPS_HWS_OFF, "off", 0, 0, 0, 1) +FLAG(NPS_HWS_RESTORE, "restore", 0, 0, 0, 1) +FLAG(NPS_SX, "sx", 1, 1, 14, 1) +FLAG(NPS_AR, "ar", 0, 1, 0, 1) +FLAG(NPS_AL, "al", 1, 1, 0, 1) +FLAG(NPS_S, "s", 0, 0, 0, 1) +FLAG(NPS_ZNCV_RD, "rd", 0, 1, 15, 1) +FLAG(NPS_ZNCV_WR, "wr", 1, 1, 15, 1) +FLAG(NPS_P0, "p0", 0, 0, 0, 1) +FLAG(NPS_P1, "p1", 0, 0, 0, 1) +FLAG(NPS_P2, "p2", 0, 0, 0, 1) +FLAG(NPS_P3, "p3", 0, 0, 0, 1) +FLAG(NPS_LDBIT_DI, "di", 0, 0, 0, 1) +FLAG(NPS_LDBIT_CL1, "cl", 1, 1, 6, 1) +FLAG(NPS_LDBIT_CL2, "cl", 1, 1, 16, 1) +FLAG(NPS_LDBIT_X2_1, "x2", 1, 2, 9, 1) +FLAG(NPS_LDBIT_X2_2, "x2", 1, 2, 22, 1) +FLAG(NPS_LDBIT_X4_1, "x4", 2, 2, 9, 1) +FLAG(NPS_LDBIT_X4_2, "x4", 2, 2, 22, 1) +FLAG(NPS_CORE, "core", 1, 3, 6, 1) +FLAG(NPS_CLSR, "clsr", 2, 3, 6, 1) +FLAG(NPS_ALL, "all", 3, 3, 6, 1) +FLAG(NPS_GIC, "gic", 4, 3, 6, 1) +FLAG(NPS_RSPI_GIC, "gic", 5, 3, 6, 1) diff --git a/opcodes/arc-fxi.h b/opcodes/arc-fxi.h index e2d4de6a579..d87e7755f20 100644 --- a/opcodes/arc-fxi.h +++ b/opcodes/arc-fxi.h @@ -1318,3 +1318,63 @@ extract_uimm6_axx_ (unsigned long long insn ATTRIBUTE_UNUSED, return value; } #endif /* EXTRACT_UIMM6_AXX_ */ + +/* mask = 0000022000011111. */ +#ifndef INSERT_UIMM9_A32_11_S +#define INSERT_UIMM9_A32_11_S +ATTRIBUTE_UNUSED static unsigned long long +insert_uimm9_a32_11_s (unsigned long long insn ATTRIBUTE_UNUSED, + long long int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + if (value & 0x03) + *errmsg = "Target address is not 32bit aligned."; + + insn |= ((value >> 2) & 0x001f) << 0; + insn |= ((value >> 7) & 0x0003) << 9; + return insn; +} +#endif /* INSERT_UIMM9_A32_11_S. */ + +#ifndef EXTRACT_UIMM9_A32_11_S +#define EXTRACT_UIMM9_A32_11_S +ATTRIBUTE_UNUSED static long long int +extract_uimm9_a32_11_s (unsigned long long insn ATTRIBUTE_UNUSED, + bool *invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + value |= ((insn >> 0) & 0x001f) << 2; + value |= ((insn >> 9) & 0x0003) << 7; + + return value; +} +#endif /* EXTRACT_UIMM9_A32_11_S. */ + +/* mask = 0000022222220111. */ +#ifndef INSERT_UIMM10_13_S +#define INSERT_UIMM10_13_S +ATTRIBUTE_UNUSED static unsigned long long +insert_uimm10_13_s (unsigned long long insn ATTRIBUTE_UNUSED, + long long int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + insn |= ((value >> 0) & 0x0007) << 0; + insn |= ((value >> 3) & 0x007f) << 4; + + return insn; +} +#endif /* INSERT_UIMM10_13_S. */ + +#ifndef EXTRACT_UIMM10_13_S +#define EXTRACT_UIMM10_13_S +ATTRIBUTE_UNUSED static long long int +extract_uimm10_13_s (unsigned long long insn ATTRIBUTE_UNUSED, + bool *invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + value |= ((insn >> 0) & 0x0007) << 0; + value |= ((insn >> 4) & 0x007f) << 3; + + return value; +} +#endif /* EXTRACT_UIMM10_13_S. */ diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c index 4257e79fe4b..8e7c910a18c 100644 --- a/opcodes/arc-opc.c +++ b/opcodes/arc-opc.c @@ -19,2595 +19,103 @@ along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ -#include "sysdep.h" -#include <stdio.h> -#include "bfd.h" -#include "opcode/arc.h" -#include "opintl.h" -#include "libiberty.h" - -/* ARC NPS400 Support: The ARC NPS400 core is an ARC700 with some custom - instructions. All NPS400 features are built into all ARC target builds as - this reduces the chances that regressions might creep in. */ - -/* Insert RA register into a 32-bit opcode, with checks. */ - -static unsigned long long -insert_ra_chk (unsigned long long insn, - long long value, - const char ** errmsg) -{ - if (value == 60) - *errmsg = _("LP_COUNT register cannot be used as destination register"); - - return insn | (value & 0x3F); -} - -/* Insert RB register into a 32-bit opcode. */ - -static unsigned long long -insert_rb (unsigned long long insn, - long long value, - const char ** errmsg ATTRIBUTE_UNUSED) -{ - return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12); -} - -/* Insert RB register with checks. */ - -static unsigned long long -insert_rb_chk (unsigned long long insn, - long long value, - const char ** errmsg) -{ - if (value == 60) - *errmsg = _("LP_COUNT register cannot be used as destination register"); - - return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12); -} - -static long long -extract_rb (unsigned long long insn, - bool *invalid) -{ - int value = (((insn >> 12) & 0x07) << 3) | ((insn >> 24) & 0x07); - - if (value == 0x3e && invalid) - *invalid = true; /* A limm operand, it should be extracted in a - different way. */ - - return value; -} - -static unsigned long long -insert_rad (unsigned long long insn, - long long value, - const char ** errmsg) -{ - if (value & 0x01) - *errmsg = _("cannot use odd number destination register"); - if (value == 60) - *errmsg = _("LP_COUNT register cannot be used as destination register"); - - return insn | (value & 0x3F); -} - -static unsigned long long -insert_rcd (unsigned long long insn, - long long value, - const char ** errmsg) -{ - if (value & 0x01) - *errmsg = _("cannot use odd number source register"); - - return insn | ((value & 0x3F) << 6); -} - -static unsigned long long -insert_rbd (unsigned long long insn, - long long value, - const char ** errmsg) -{ - if (value & 0x01) - *errmsg = _("cannot use odd number source register"); - if (value == 60) - *errmsg = _("LP_COUNT register cannot be used as destination register"); - - return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12); -} - -/* Dummy insert ZERO operand function. */ - -static unsigned long long -insert_za (unsigned long long insn, - long long value, - const char ** errmsg) -{ - if (value) - *errmsg = _("operand is not zero"); - return insn; -} - -/* Insert Y-bit in bbit/br instructions. This function is called only - when solving fixups. */ - -static unsigned long long -insert_Ybit (unsigned long long insn, - long long value, - const char ** errmsg ATTRIBUTE_UNUSED) -{ - if (value > 0) - insn |= 0x08; - - return insn; -} - -/* Insert Y-bit in bbit/br instructions. This function is called only - when solving fixups. */ - -static unsigned long long -insert_NYbit (unsigned long long insn, - long long value, - const char ** errmsg ATTRIBUTE_UNUSED) -{ - if (value < 0) - insn |= 0x08; - - return insn; -} - -/* Insert H register into a 16-bit opcode. */ - -static unsigned long long -insert_rhv1 (unsigned long long insn, - long long value, - const char ** errmsg ATTRIBUTE_UNUSED) -{ - return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x07); -} - -static long long -extract_rhv1 (unsigned long long insn, - bool *invalid ATTRIBUTE_UNUSED) -{ - int value = ((insn & 0x7) << 3) | ((insn >> 5) & 0x7); - - return value; -} - -/* Insert H register into a 16-bit opcode. */ - -static unsigned long long -insert_rhv2 (unsigned long long insn, - long long value, - const char ** errmsg) -{ - if (value == 0x1E) - *errmsg = _("register R30 is a limm indicator"); - else if (value < 0 || value > 31) - *errmsg = _("register out of range"); - return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x03); -} - -static long long -extract_rhv2 (unsigned long long insn, - bool *invalid ATTRIBUTE_UNUSED) -{ - int value = ((insn >> 5) & 0x07) | ((insn & 0x03) << 3); - - return value; -} - -static unsigned long long -insert_r0 (unsigned long long insn, - long long value, - const char ** errmsg) -{ - if (value != 0) - *errmsg = _("register must be R0"); - return insn; -} - -static long long -extract_r0 (unsigned long long insn ATTRIBUTE_UNUSED, - bool *invalid ATTRIBUTE_UNUSED) -{ - return 0; -} - - -static unsigned long long -insert_r1 (unsigned long long insn, - long long value, - const char ** errmsg) -{ - if (value != 1) - *errmsg = _("register must be R1"); - return insn; -} - -static long long -extract_r1 (unsigned long long insn ATTRIBUTE_UNUSED, - bool* invalid ATTRIBUTE_UNUSED) -{ - return 1; -} - -static unsigned long long -insert_r2 (unsigned long long insn, - long long value, - const char ** errmsg) -{ - if (value != 2) - *errmsg = _("register must be R2"); - return insn; -} - -static long long -extract_r2 (unsigned long long insn ATTRIBUTE_UNUSED, - bool *invalid ATTRIBUTE_UNUSED) -{ - return 2; -} - -static unsigned long long -insert_r3 (unsigned long long insn, - long long value, - const char ** errmsg) -{ - if (value != 3) - *errmsg = _("register must be R3"); - return insn; -} - -static long long -extract_r3 (unsigned long long insn ATTRIBUTE_UNUSED, - bool *invalid ATTRIBUTE_UNUSED) -{ - return 3; -} - -static unsigned long long -insert_sp (unsigned long long insn, - long long value, - const char ** errmsg) -{ - if (value != 28) - *errmsg = _("register must be SP"); - return insn; -} - -static long long -extract_sp (unsigned long long insn ATTRIBUTE_UNUSED, - bool *invalid ATTRIBUTE_UNUSED) -{ - return 28; -} - -static unsigned long long -insert_gp (unsigned long long insn, - long long value, - const char ** errmsg) -{ - if (value != 26) - *errmsg = _("register must be GP"); - return insn; -} - -static long long -extract_gp (unsigned long long insn ATTRIBUTE_UNUSED, - bool *invalid ATTRIBUTE_UNUSED) -{ - return 26; -} - -static unsigned long long -insert_pcl (unsigned long long insn, - long long value, - const char ** errmsg) -{ - if (value != 63) - *errmsg = _("register must be PCL"); - return insn; -} - -static long long -extract_pcl (unsigned long long insn ATTRIBUTE_UNUSED, - bool *invalid ATTRIBUTE_UNUSED) -{ - return 63; -} - -static unsigned long long -insert_blink (unsigned long long insn, - long long value, - const char ** errmsg) -{ - if (value != 31) - *errmsg = _("register must be BLINK"); - return insn; -} - -static long long -extract_blink (unsigned long long insn ATTRIBUTE_UNUSED, - bool *invalid ATTRIBUTE_UNUSED) -{ - return 31; -} - -static unsigned long long -insert_ilink1 (unsigned long long insn, - long long value, - const char ** errmsg) -{ - if (value != 29) - *errmsg = _("register must be ILINK1"); - return insn; -} - -static long long -extract_ilink1 (unsigned long long insn ATTRIBUTE_UNUSED, - bool *invalid ATTRIBUTE_UNUSED) -{ - return 29; -} - -static unsigned long long -insert_ilink2 (unsigned long long insn, - long long value, - const char ** errmsg) -{ - if (value != 30) - *errmsg = _("register must be ILINK2"); - return insn; -} - -static long long -extract_ilink2 (unsigned long long insn ATTRIBUTE_UNUSED, - bool *invalid ATTRIBUTE_UNUSED) -{ - return 30; -} - -static unsigned long long -insert_ras (unsigned long long insn, - long long value, - const char ** errmsg) -{ - switch (value) - { - case 0: - case 1: - case 2: - case 3: - insn |= value; - break; - case 12: - case 13: - case 14: - case 15: - insn |= (value - 8); - break; - default: - *errmsg = _("register must be either r0-r3 or r12-r15"); - break; - } - return insn; -} - -static long long -extract_ras (unsigned long long insn, - bool *invalid ATTRIBUTE_UNUSED) -{ - int value = insn & 0x07; - - if (value > 3) - return (value + 8); - else - return value; -} - -static unsigned long long -insert_rbs (unsigned long long insn, - long long value, - const char ** errmsg) -{ - switch (value) - { - case 0: - case 1: - case 2: - case 3: - insn |= value << 8; - break; - case 12: - case 13: - case 14: - case 15: - insn |= ((value - 8)) << 8; - break; - default: - *errmsg = _("register must be either r0-r3 or r12-r15"); - break; - } - return insn; -} - -static long long -extract_rbs (unsigned long long insn, - bool *invalid ATTRIBUTE_UNUSED) -{ - int value = (insn >> 8) & 0x07; - - if (value > 3) - return (value + 8); - else - return value; -} - -static unsigned long long -insert_rcs (unsigned long long insn, - long long value, - const char ** errmsg) -{ - switch (value) - { - case 0: - case 1: - case 2: - case 3: - insn |= value << 5; - break; - case 12: - case 13: - case 14: - case 15: - insn |= ((value - 8)) << 5; - break; - default: - *errmsg = _("register must be either r0-r3 or r12-r15"); - break; - } - return insn; -} - -static long long -extract_rcs (unsigned long long insn, - bool *invalid ATTRIBUTE_UNUSED) -{ - int value = (insn >> 5) & 0x07; - - if (value > 3) - return (value + 8); - else - return value; -} - -static unsigned long long -insert_simm3s (unsigned long long insn, - long long value, - const char ** errmsg) -{ - int tmp = 0; - switch (value) - { - case -1: - tmp = 0x07; - break; - case 0: - tmp = 0x00; - break; - case 1: - tmp = 0x01; - break; - case 2: - tmp = 0x02; - break; - case 3: - tmp = 0x03; - break; - case 4: - tmp = 0x04; - break; - case 5: - tmp = 0x05; - break; - case 6: - tmp = 0x06; - break; - default: - *errmsg = _("accepted values are from -1 to 6"); - break; - } - - insn |= tmp << 8; - return insn; -} - -static long long -extract_simm3s (unsigned long long insn, - bool *invalid ATTRIBUTE_UNUSED) -{ - int value = (insn >> 8) & 0x07; - - if (value == 7) - return -1; - else - return value; -} - -static unsigned long long -insert_rrange (unsigned long long insn, - long long value, - const char ** errmsg) -{ - int reg1 = (value >> 16) & 0xFFFF; - int reg2 = value & 0xFFFF; - - if (reg1 != 13) - *errmsg = _("first register of the range should be r13"); - else if (reg2 < 13 || reg2 > 26) - *errmsg = _("last register of the range doesn't fit"); - else - insn |= ((reg2 - 12) & 0x0F) << 1; - return insn; -} - -static long long -extract_rrange (unsigned long long insn, - bool *invalid ATTRIBUTE_UNUSED) -{ - return (insn >> 1) & 0x0F; -} - -static unsigned long long -insert_r13el (unsigned long long insn, - long long int value, - const char **errmsg) -{ - if (value != 13) - { - *errmsg = _("invalid register number, should be fp"); - return insn; - } - - insn |= 0x02; - return insn; -} - -static unsigned long long -insert_fpel (unsigned long long insn, - long long value, - const char ** errmsg) -{ - if (value != 27) - { - *errmsg = _("invalid register number, should be fp"); - return insn; - } - - insn |= 0x0100; - return insn; -} - -static long long -extract_fpel (unsigned long long insn, - bool *invalid ATTRIBUTE_UNUSED) -{ - return (insn & 0x0100) ? 27 : -1; -} - -static unsigned long long -insert_blinkel (unsigned long long insn, - long long value, - const char ** errmsg) -{ - if (value != 31) - { - *errmsg = _("invalid register number, should be blink"); - return insn; - } - - insn |= 0x0200; - return insn; -} - -static long long -extract_blinkel (unsigned long long insn, - bool *invalid ATTRIBUTE_UNUSED) -{ - return (insn & 0x0200) ? 31 : -1; -} - -static unsigned long long -insert_pclel (unsigned long long insn, - long long value, - const char ** errmsg) -{ - if (value != 63) - { - *errmsg = _("invalid register number, should be pcl"); - return insn; - } - - insn |= 0x0400; - return insn; -} - -static long long -extract_pclel (unsigned long long insn, - bool *invalid ATTRIBUTE_UNUSED) -{ - return (insn & 0x0400) ? 63 : -1; -} - -#define INSERT_W6 - -/* mask = 00000000000000000000111111000000 - insn = 00011bbb000000000BBBwwwwwwDaaZZ1. */ - -static unsigned long long -insert_w6 (unsigned long long insn, - long long value, - const char ** errmsg ATTRIBUTE_UNUSED) -{ - insn |= ((value >> 0) & 0x003f) << 6; - - return insn; -} - -#define EXTRACT_W6 - -/* mask = 00000000000000000000111111000000. */ - -static long long -extract_w6 (unsigned long long insn, - bool *invalid ATTRIBUTE_UNUSED) -{ - int value = 0; - - value |= ((insn >> 6) & 0x003f) << 0; - - /* Extend the sign. */ - int signbit = 1 << 5; - value = (value ^ signbit) - signbit; - - return value; -} - -#define INSERT_G_S - -/* mask = 0000011100022000 - insn = 01000ggghhhGG0HH. */ - -static unsigned long long -insert_g_s (unsigned long long insn, - long long value, - const char ** errmsg ATTRIBUTE_UNUSED) -{ - insn |= ((value >> 0) & 0x0007) << 8; - insn |= ((value >> 3) & 0x0003) << 3; - - return insn; -} - -#define EXTRACT_G_S - -/* mask = 0000011100022000. */ - -static long long -extract_g_s (unsigned long long insn, - bool *invalid ATTRIBUTE_UNUSED) -{ - int value = 0; - int signbit = 1 << (6 - 1); - - value |= ((insn >> 8) & 0x0007) << 0; - value |= ((insn >> 3) & 0x0003) << 3; - - /* Extend the sign. */ - value = (value ^ signbit) - signbit; - - return value; -} - -/* ARC NPS400 Support: See comment near head of file. */ -#define MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(NAME,OFFSET) \ -static unsigned long long \ -insert_nps_3bit_reg_at_##OFFSET##_##NAME \ - (unsigned long long insn, \ - long long value, \ - const char ** errmsg) \ -{ \ - switch (value) \ - { \ - case 0: \ - case 1: \ - case 2: \ - case 3: \ - insn |= value << (OFFSET); \ - break; \ - case 12: \ - case 13: \ - case 14: \ - case 15: \ - insn |= (value - 8) << (OFFSET); \ - break; \ - default: \ - *errmsg = _("register must be either r0-r3 or r12-r15"); \ - break; \ - } \ - return insn; \ -} \ - \ -static long long \ -extract_nps_3bit_reg_at_##OFFSET##_##NAME \ - (unsigned long long insn, \ - bool *invalid ATTRIBUTE_UNUSED) \ -{ \ - int value = (insn >> (OFFSET)) & 0x07; \ - if (value > 3) \ - value += 8; \ - return value; \ -} \ - -MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,8) -MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,24) -MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,40) -MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,56) - -MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,5) -MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,21) -MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,37) -MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,53) - -static unsigned long long -insert_nps_bitop_size_2b (unsigned long long insn, - long long value, - const char ** errmsg) -{ - switch (value) - { - case 1: - value = 0; - break; - case 2: - value = 1; - break; - case 4: - value = 2; - break; - case 8: - value = 3; - break; - default: - value = 0; - *errmsg = _("invalid size, should be 1, 2, 4, or 8"); - break; - } - - insn |= value << 10; - return insn; -} - -static long long -extract_nps_bitop_size_2b (unsigned long long insn, - bool *invalid ATTRIBUTE_UNUSED) -{ - return 1 << ((insn >> 10) & 0x3); -} - -static unsigned long long -insert_nps_bitop_uimm8 (unsigned long long insn, - long long value, - const char ** errmsg ATTRIBUTE_UNUSED) -{ - insn |= ((value >> 5) & 7) << 12; - insn |= (value & 0x1f); - return insn; -} - -static long long -extract_nps_bitop_uimm8 (unsigned long long insn, - bool *invalid ATTRIBUTE_UNUSED) -{ - return (((insn >> 12) & 0x7) << 5) | (insn & 0x1f); -} - -static unsigned long long -insert_nps_rflt_uimm6 (unsigned long long insn, - long long value, - const char ** errmsg) -{ - switch (value) - { - case 1: - case 2: - case 4: - break; - - default: - *errmsg = _("invalid immediate, must be 1, 2, or 4"); - value = 0; - } - - insn |= (value << 6); - return insn; -} - -static long long -extract_nps_rflt_uimm6 (unsigned long long insn, - bool *invalid ATTRIBUTE_UNUSED) -{ - return (insn >> 6) & 0x3f; -} - -static unsigned long long -insert_nps_dst_pos_and_size (unsigned long long insn, - long long value, - const char ** errmsg ATTRIBUTE_UNUSED) -{ - insn |= ((value & 0x1f) | (((32 - value - 1) & 0x1f) << 10)); - return insn; -} - -static long long -extract_nps_dst_pos_and_size (unsigned long long insn, - bool *invalid ATTRIBUTE_UNUSED) -{ - return (insn & 0x1f); -} - -static unsigned long long -insert_nps_cmem_uimm16 (unsigned long long insn, - long long value, - const char ** errmsg) -{ - int top = (value >> 16) & 0xffff; - - if (top != 0x0 && top != NPS_CMEM_HIGH_VALUE) - *errmsg = _("invalid value for CMEM ld/st immediate"); - insn |= (value & 0xffff); - return insn; -} - -static long long -extract_nps_cmem_uimm16 (unsigned long long insn, - bool *invalid ATTRIBUTE_UNUSED) -{ - return (NPS_CMEM_HIGH_VALUE << 16) | (insn & 0xffff); -} - -static unsigned long long -insert_nps_imm_offset (unsigned long long insn, - long long value, - const char ** errmsg) -{ - switch (value) - { - case 0: - case 16: - case 32: - case 48: - case 64: - value = value >> 4; - break; - default: - *errmsg = _("invalid position, should be 0, 16, 32, 48 or 64."); - value = 0; - } - insn |= (value << 10); - return insn; -} - -static long long -extract_nps_imm_offset (unsigned long long insn, - bool *invalid ATTRIBUTE_UNUSED) -{ - return ((insn >> 10) & 0x7) * 16; -} - -static unsigned long long -insert_nps_imm_entry (unsigned long long insn, - long long value, - const char ** errmsg) -{ - switch (value) - { - case 16: - value = 0; - break; - case 32: - value = 1; - break; - case 64: - value = 2; - break; - case 128: - value = 3; - break; - default: - *errmsg = _("invalid position, should be 16, 32, 64 or 128."); - value = 0; - } - insn |= (value << 2); - return insn; -} - -static long long -extract_nps_imm_entry (unsigned long long insn, - bool *invalid ATTRIBUTE_UNUSED) -{ - int imm_entry = ((insn >> 2) & 0x7); - return (1 << (imm_entry + 4)); -} - -static unsigned long long -insert_nps_size_16bit (unsigned long long insn, - long long value, - const char ** errmsg) -{ - if ((value < 1) || (value > 64)) - { - *errmsg = _("invalid size value must be on range 1-64."); - value = 0; - } - value = value & 0x3f; - insn |= (value << 6); - return insn; -} - -static long long -extract_nps_size_16bit (unsigned long long insn, - bool *invalid ATTRIBUTE_UNUSED) -{ - return ((insn & 0xfc0) >> 6) ? ((insn & 0xfc0) >> 6) : 64; -} - - -#define MAKE_SRC_POS_INSERT_EXTRACT_FUNCS(NAME,SHIFT) \ -static unsigned long long \ -insert_nps_##NAME##_pos (unsigned long long insn, \ - long long value, \ - const char ** errmsg) \ -{ \ - switch (value) \ - { \ - case 0: \ - case 8: \ - case 16: \ - case 24: \ - value = value / 8; \ - break; \ - default: \ - *errmsg = _("invalid position, should be 0, 8, 16, or 24"); \ - value = 0; \ - } \ - insn |= (value << SHIFT); \ - return insn; \ -} \ - \ -static long long \ -extract_nps_##NAME##_pos (unsigned long long insn, \ - bool *invalid ATTRIBUTE_UNUSED) \ -{ \ - return ((insn >> SHIFT) & 0x3) * 8; \ -} - -MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src2, 12) -MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src1, 10) - -#define MAKE_BIAS_INSERT_EXTRACT_FUNCS(NAME,LOWER,UPPER,BITS,BIAS,SHIFT) \ -static unsigned long long \ -insert_nps_##NAME (unsigned long long insn, \ - long long value, \ - const char ** errmsg) \ - { \ - if (value < LOWER || value > UPPER) \ - { \ - *errmsg = _("invalid size, value must be " \ - #LOWER " to " #UPPER "."); \ - return insn; \ - } \ - value -= BIAS; \ - insn |= (value << SHIFT); \ - return insn; \ - } \ - \ -static long long \ -extract_nps_##NAME (unsigned long long insn, \ - bool *invalid ATTRIBUTE_UNUSED) \ -{ \ - return ((insn >> SHIFT) & ((1 << BITS) - 1)) + BIAS; \ -} - -MAKE_BIAS_INSERT_EXTRACT_FUNCS (addb_size,2,32,5,1,5) -MAKE_BIAS_INSERT_EXTRACT_FUNCS (andb_size,1,32,5,1,5) -MAKE_BIAS_INSERT_EXTRACT_FUNCS (fxorb_size,8,32,5,8,5) -MAKE_BIAS_INSERT_EXTRACT_FUNCS (wxorb_size,16,32,5,16,5) -MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop_size,1,32,5,1,10) -MAKE_BIAS_INSERT_EXTRACT_FUNCS (qcmp_size,1,8,3,1,9) -MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop1_size,1,32,5,1,20) -MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop2_size,1,32,5,1,25) -MAKE_BIAS_INSERT_EXTRACT_FUNCS (hash_width,1,32,5,1,6) -MAKE_BIAS_INSERT_EXTRACT_FUNCS (hash_len,1,8,3,1,2) -MAKE_BIAS_INSERT_EXTRACT_FUNCS (index3,4,7,2,4,0) - -static long long -extract_nps_qcmp_m3 (unsigned long long insn, - bool *invalid) -{ - int m3 = (insn >> 5) & 0xf; - if (m3 == 0xf) - *invalid = true; - return m3; -} - -static long long -extract_nps_qcmp_m2 (unsigned long long insn, - bool *invalid) -{ - bool tmp_invalid = false; - int m2 = (insn >> 15) & 0x1; - int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid); - - if (m2 == 0 && m3 == 0xf) - *invalid = true; - return m2; -} - -static long long -extract_nps_qcmp_m1 (unsigned long long insn, - bool *invalid) -{ - bool tmp_invalid = false; - int m1 = (insn >> 14) & 0x1; - int m2 = extract_nps_qcmp_m2 (insn, &tmp_invalid); - int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid); - - if (m1 == 0 && m2 == 0 && m3 == 0xf) - *invalid = true; - return m1; -} - -static unsigned long long -insert_nps_calc_entry_size (unsigned long long insn, - long long value, - const char ** errmsg) -{ - unsigned pwr; - - if (value < 1 || value > 256) - { - *errmsg = _("value out of range 1 - 256"); - return 0; - } - - for (pwr = 0; (value & 1) == 0; value >>= 1) - ++pwr; - - if (value != 1) - { - *errmsg = _("value must be power of 2"); - return 0; - } - - return insn | (pwr << 8); -} - -static long long -extract_nps_calc_entry_size (unsigned long long insn, - bool *invalid ATTRIBUTE_UNUSED) -{ - unsigned entry_size = (insn >> 8) & 0xf; - return 1 << entry_size; -} - -static unsigned long long -insert_nps_bitop_mod4 (unsigned long long insn, - long long value, - const char ** errmsg ATTRIBUTE_UNUSED) -{ - return insn | ((value & 0x2) << 30) | ((value & 0x1) << 47); -} - -static long long -extract_nps_bitop_mod4 (unsigned long long insn, - bool *invalid ATTRIBUTE_UNUSED) -{ - return ((insn >> 30) & 0x2) | ((insn >> 47) & 0x1); -} - -static unsigned long long -insert_nps_bitop_dst_pos3_pos4 (unsigned long long insn, - long long value, - const char ** errmsg ATTRIBUTE_UNUSED) -{ - return insn | (value << 42) | (value << 37); -} - -static long long -extract_nps_bitop_dst_pos3_pos4 (unsigned long long insn, - bool *invalid) -{ - if (((insn >> 42) & 0x1f) != ((insn >> 37) & 0x1f)) - *invalid = true; - return ((insn >> 37) & 0x1f); -} - -static unsigned long long -insert_nps_bitop_ins_ext (unsigned long long insn, - long long value, - const char ** errmsg) -{ - if (value < 0 || value > 28) - *errmsg = _("value must be in the range 0 to 28"); - return insn | (value << 20); -} - -static long long -extract_nps_bitop_ins_ext (unsigned long long insn, - bool *invalid) -{ - int value = (insn >> 20) & 0x1f; - - if (value > 28) - *invalid = true; - return value; -} - -#define MAKE_1BASED_INSERT_EXTRACT_FUNCS(NAME,SHIFT,UPPER,BITS) \ -static unsigned long long \ -insert_nps_##NAME (unsigned long long insn, \ - long long value, \ - const char ** errmsg) \ -{ \ - if (value < 1 || value > UPPER) \ - *errmsg = _("value must be in the range 1 to " #UPPER); \ - if (value == UPPER) \ - value = 0; \ - return insn | (value << SHIFT); \ -} \ - \ -static long long \ -extract_nps_##NAME (unsigned long long insn, \ - bool *invalid ATTRIBUTE_UNUSED) \ -{ \ - int value = (insn >> SHIFT) & ((1 << BITS) - 1); \ - if (value == 0) \ - value = UPPER; \ - return value; \ -} - -MAKE_1BASED_INSERT_EXTRACT_FUNCS (field_size, 6, 8, 3) -MAKE_1BASED_INSERT_EXTRACT_FUNCS (shift_factor, 9, 8, 3) -MAKE_1BASED_INSERT_EXTRACT_FUNCS (bits_to_scramble, 12, 8, 3) -MAKE_1BASED_INSERT_EXTRACT_FUNCS (bdlen_max_len, 5, 256, 8) -MAKE_1BASED_INSERT_EXTRACT_FUNCS (bd_num_buff, 6, 8, 3) -MAKE_1BASED_INSERT_EXTRACT_FUNCS (pmu_num_job, 6, 4, 2) -MAKE_1BASED_INSERT_EXTRACT_FUNCS (proto_size, 16, 64, 6) - -static unsigned long long -insert_nps_min_hofs (unsigned long long insn, - long long value, - const char ** errmsg) -{ - if (value < 0 || value > 240) - *errmsg = _("value must be in the range 0 to 240"); - if ((value % 16) != 0) - *errmsg = _("value must be a multiple of 16"); - value = value / 16; - return insn | (value << 6); -} - -static long long -extract_nps_min_hofs (unsigned long long insn, - bool *invalid ATTRIBUTE_UNUSED) -{ - int value = (insn >> 6) & 0xF; - return value * 16; -} - -#define MAKE_INSERT_NPS_ADDRTYPE(NAME, VALUE) \ -static unsigned long long \ -insert_nps_##NAME (unsigned long long insn, \ - long long value, \ - const char ** errmsg) \ -{ \ - if (value != ARC_NPS400_ADDRTYPE_##VALUE) \ - *errmsg = _("invalid address type for operand"); \ - return insn; \ -} \ - \ -static long long \ -extract_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \ - bool *invalid ATTRIBUTE_UNUSED) \ -{ \ - return ARC_NPS400_ADDRTYPE_##VALUE; \ -} - -MAKE_INSERT_NPS_ADDRTYPE (bd, BD) -MAKE_INSERT_NPS_ADDRTYPE (jid, JID) -MAKE_INSERT_NPS_ADDRTYPE (lbd, LBD) -MAKE_INSERT_NPS_ADDRTYPE (mbd, MBD) -MAKE_INSERT_NPS_ADDRTYPE (sd, SD) -MAKE_INSERT_NPS_ADDRTYPE (sm, SM) -MAKE_INSERT_NPS_ADDRTYPE (xa, XA) -MAKE_INSERT_NPS_ADDRTYPE (xd, XD) -MAKE_INSERT_NPS_ADDRTYPE (cd, CD) -MAKE_INSERT_NPS_ADDRTYPE (cbd, CBD) -MAKE_INSERT_NPS_ADDRTYPE (cjid, CJID) -MAKE_INSERT_NPS_ADDRTYPE (clbd, CLBD) -MAKE_INSERT_NPS_ADDRTYPE (cm, CM) -MAKE_INSERT_NPS_ADDRTYPE (csd, CSD) -MAKE_INSERT_NPS_ADDRTYPE (cxa, CXA) -MAKE_INSERT_NPS_ADDRTYPE (cxd, CXD) - -static unsigned long long -insert_nps_rbdouble_64 (unsigned long long insn, - long long value, - const char ** errmsg) -{ - if (value < 0 || value > 31) - *errmsg = _("value must be in the range 0 to 31"); - return insn | (value << 43) | (value << 48); -} - - -static long long -extract_nps_rbdouble_64 (unsigned long long insn, - bool *invalid) -{ - int value1 = (insn >> 43) & 0x1F; - int value2 = (insn >> 48) & 0x1F; - - if (value1 != value2) - *invalid = true; - - return value1; -} - -static unsigned long long -insert_nps_misc_imm_offset (unsigned long long insn, - long long value, - const char ** errmsg) -{ - if (value & 0x3) - { - *errmsg = _("invalid position, should be one of: 0,4,8,...124."); - value = 0; - } - insn |= (value << 6); - return insn; -} - -static long long int -extract_nps_misc_imm_offset (unsigned long long insn, - bool *invalid ATTRIBUTE_UNUSED) -{ - return ((insn >> 8) & 0x1f) * 4; -} - -static long long int -extract_uimm12_20 (unsigned long long insn ATTRIBUTE_UNUSED, - bool *invalid ATTRIBUTE_UNUSED) -{ - int value = 0; - - value |= ((insn >> 6) & 0x003f) << 0; - value |= ((insn >> 0) & 0x003f) << 6; - - return value; -} - -/* Include the generic extract/insert functions. Order is important - as some of the functions present in the .h may be disabled via - defines. */ -#include "arc-fxi.h" - -/* The flag operands table. - - The format of the table is - NAME CODE BITS SHIFT FAVAIL. */ -const struct arc_flag_operand arc_flag_operands[] = -{ -#define F_NULL 0 - { 0, 0, 0, 0, 0}, -#define F_ALWAYS (F_NULL + 1) - { "al", 0, 0, 0, 0 }, -#define F_RA (F_ALWAYS + 1) - { "ra", 0, 0, 0, 0 }, -#define F_EQUAL (F_RA + 1) - { "eq", 1, 5, 0, 1 }, -#define F_ZERO (F_EQUAL + 1) - { "z", 1, 5, 0, 0 }, -#define F_NOTEQUAL (F_ZERO + 1) - { "ne", 2, 5, 0, 1 }, -#define F_NOTZERO (F_NOTEQUAL + 1) - { "nz", 2, 5, 0, 0 }, -#define F_POZITIVE (F_NOTZERO + 1) - { "p", 3, 5, 0, 1 }, -#define F_PL (F_POZITIVE + 1) - { "pl", 3, 5, 0, 0 }, -#define F_NEGATIVE (F_PL + 1) - { "n", 4, 5, 0, 1 }, -#define F_MINUS (F_NEGATIVE + 1) - { "mi", 4, 5, 0, 0 }, -#define F_CARRY (F_MINUS + 1) - { "c", 5, 5, 0, 1 }, -#define F_CARRYSET (F_CARRY + 1) - { "cs", 5, 5, 0, 0 }, -#define F_LOWER (F_CARRYSET + 1) - { "lo", 5, 5, 0, 0 }, -#define F_CARRYCLR (F_LOWER + 1) - { "cc", 6, 5, 0, 0 }, -#define F_NOTCARRY (F_CARRYCLR + 1) - { "nc", 6, 5, 0, 1 }, -#define F_HIGHER (F_NOTCARRY + 1) - { "hs", 6, 5, 0, 0 }, -#define F_OVERFLOWSET (F_HIGHER + 1) - { "vs", 7, 5, 0, 0 }, -#define F_OVERFLOW (F_OVERFLOWSET + 1) - { "v", 7, 5, 0, 1 }, -#define F_NOTOVERFLOW (F_OVERFLOW + 1) - { "nv", 8, 5, 0, 1 }, -#define F_OVERFLOWCLR (F_NOTOVERFLOW + 1) - { "vc", 8, 5, 0, 0 }, -#define F_GT (F_OVERFLOWCLR + 1) - { "gt", 9, 5, 0, 1 }, -#define F_GE (F_GT + 1) - { "ge", 10, 5, 0, 1 }, -#define F_LT (F_GE + 1) - { "lt", 11, 5, 0, 1 }, -#define F_LE (F_LT + 1) - { "le", 12, 5, 0, 1 }, -#define F_HI (F_LE + 1) - { "hi", 13, 5, 0, 1 }, -#define F_LS (F_HI + 1) - { "ls", 14, 5, 0, 1 }, -#define F_PNZ (F_LS + 1) - { "pnz", 15, 5, 0, 1 }, -#define F_NJ (F_PNZ + 1) - { "nj", 21, 5, 0, 1 }, -#define F_NM (F_NJ + 1) - { "nm", 23, 5, 0, 1 }, -#define F_NO_T (F_NM + 1) - { "nt", 24, 5, 0, 1 }, - - /* FLAG. */ -#define F_FLAG (F_NO_T + 1) - { "f", 1, 1, 15, 1 }, -#define F_FFAKE (F_FLAG + 1) - { "f", 0, 0, 0, 1 }, - - /* Delay slot. */ -#define F_ND (F_FFAKE + 1) - { "nd", 0, 1, 5, 0 }, -#define F_D (F_ND + 1) - { "d", 1, 1, 5, 1 }, -#define F_DFAKE (F_D + 1) - { "d", 0, 0, 0, 1 }, -#define F_DNZ_ND (F_DFAKE + 1) - { "nd", 0, 1, 16, 0 }, -#define F_DNZ_D (F_DNZ_ND + 1) - { "d", 1, 1, 16, 1 }, - - /* Data size. */ -#define F_SIZEB1 (F_DNZ_D + 1) - { "b", 1, 2, 1, 1 }, -#define F_SIZEB7 (F_SIZEB1 + 1) - { "b", 1, 2, 7, 1 }, -#define F_SIZEB17 (F_SIZEB7 + 1) - { "b", 1, 2, 17, 1 }, -#define F_SIZEW1 (F_SIZEB17 + 1) - { "w", 2, 2, 1, 0 }, -#define F_SIZEW7 (F_SIZEW1 + 1) - { "w", 2, 2, 7, 0 }, -#define F_SIZEW17 (F_SIZEW7 + 1) - { "w", 2, 2, 17, 0 }, - - /* Sign extension. */ -#define F_SIGN6 (F_SIZEW17 + 1) - { "x", 1, 1, 6, 1 }, -#define F_SIGN16 (F_SIGN6 + 1) - { "x", 1, 1, 16, 1 }, -#define F_SIGNX (F_SIGN16 + 1) - { "x", 0, 0, 0, 1 }, - - /* Address write-back modes. */ -#define F_A3 (F_SIGNX + 1) - { "a", 1, 2, 3, 0 }, -#define F_A9 (F_A3 + 1) - { "a", 1, 2, 9, 0 }, -#define F_A22 (F_A9 + 1) - { "a", 1, 2, 22, 0 }, -#define F_AW3 (F_A22 + 1) - { "aw", 1, 2, 3, 1 }, -#define F_AW9 (F_AW3 + 1) - { "aw", 1, 2, 9, 1 }, -#define F_AW22 (F_AW9 + 1) - { "aw", 1, 2, 22, 1 }, -#define F_AB3 (F_AW22 + 1) - { "ab", 2, 2, 3, 1 }, -#define F_AB9 (F_AB3 + 1) - { "ab", 2, 2, 9, 1 }, -#define F_AB22 (F_AB9 + 1) - { "ab", 2, 2, 22, 1 }, -#define F_AS3 (F_AB22 + 1) - { "as", 3, 2, 3, 1 }, -#define F_AS9 (F_AS3 + 1) - { "as", 3, 2, 9, 1 }, -#define F_AS22 (F_AS9 + 1) - { "as", 3, 2, 22, 1 }, -#define F_ASFAKE (F_AS22 + 1) - { "as", 0, 0, 0, 1 }, - - /* Cache bypass. */ -#define F_DI5 (F_ASFAKE + 1) - { "di", 1, 1, 5, 1 }, -#define F_DI11 (F_DI5 + 1) - { "di", 1, 1, 11, 1 }, -#define F_DI14 (F_DI11 + 1) - { "di", 1, 1, 14, 1 }, -#define F_DI15 (F_DI14 + 1) - { "di", 1, 1, 15, 1 }, - - /* ARCv2 specific. */ -#define F_NT (F_DI15 + 1) - { "nt", 0, 1, 3, 1}, -#define F_T (F_NT + 1) - { "t", 1, 1, 3, 1}, -#define F_H1 (F_T + 1) - { "h", 2, 2, 1, 1 }, -#define F_H7 (F_H1 + 1) - { "h", 2, 2, 7, 1 }, -#define F_H17 (F_H7 + 1) - { "h", 2, 2, 17, 1 }, -#define F_SIZED (F_H17 + 1) - { "dd", 8, 0, 0, 0 }, /* Fake. */ - - /* Fake Flags. */ -#define F_NE (F_SIZED + 1) - { "ne", 0, 0, 0, 1 }, - - /* ARC NPS400 Support: See comment near head of file. */ -#define F_NPS_CL (F_NE + 1) - { "cl", 0, 0, 0, 1 }, - -#define F_NPS_NA (F_NPS_CL + 1) - { "na", 1, 1, 9, 1 }, - -#define F_NPS_SR (F_NPS_NA + 1) - { "s", 1, 1, 13, 1 }, - -#define F_NPS_M (F_NPS_SR + 1) - { "m", 1, 1, 7, 1 }, - -#define F_NPS_FLAG (F_NPS_M + 1) - { "f", 1, 1, 20, 1 }, - -#define F_NPS_R (F_NPS_FLAG + 1) - { "r", 1, 1, 15, 1 }, - -#define F_NPS_RW (F_NPS_R + 1) - { "rw", 0, 1, 7, 1 }, - -#define F_NPS_RD (F_NPS_RW + 1) - { "rd", 1, 1, 7, 1 }, - -#define F_NPS_WFT (F_NPS_RD + 1) - { "wft", 0, 0, 0, 1 }, - -#define F_NPS_IE1 (F_NPS_WFT + 1) - { "ie1", 1, 2, 8, 1 }, - -#define F_NPS_IE2 (F_NPS_IE1 + 1) - { "ie2", 2, 2, 8, 1 }, - -#define F_NPS_IE12 (F_NPS_IE2 + 1) - { "ie12", 3, 2, 8, 1 }, - -#define F_NPS_SYNC_RD (F_NPS_IE12 + 1) - { "rd", 0, 1, 6, 1 }, - -#define F_NPS_SYNC_WR (F_NPS_SYNC_RD + 1) - { "wr", 1, 1, 6, 1 }, - -#define F_NPS_HWS_OFF (F_NPS_SYNC_WR + 1) - { "off", 0, 0, 0, 1 }, - -#define F_NPS_HWS_RESTORE (F_NPS_HWS_OFF + 1) - { "restore", 0, 0, 0, 1 }, - -#define F_NPS_SX (F_NPS_HWS_RESTORE + 1) - { "sx", 1, 1, 14, 1 }, - -#define F_NPS_AR (F_NPS_SX + 1) - { "ar", 0, 1, 0, 1 }, - -#define F_NPS_AL (F_NPS_AR + 1) - { "al", 1, 1, 0, 1 }, - -#define F_NPS_S (F_NPS_AL + 1) - { "s", 0, 0, 0, 1 }, - -#define F_NPS_ZNCV_RD (F_NPS_S + 1) - { "rd", 0, 1, 15, 1 }, - -#define F_NPS_ZNCV_WR (F_NPS_ZNCV_RD + 1) - { "wr", 1, 1, 15, 1 }, - -#define F_NPS_P0 (F_NPS_ZNCV_WR + 1) - { "p0", 0, 0, 0, 1 }, - -#define F_NPS_P1 (F_NPS_P0 + 1) - { "p1", 0, 0, 0, 1 }, - -#define F_NPS_P2 (F_NPS_P1 + 1) - { "p2", 0, 0, 0, 1 }, - -#define F_NPS_P3 (F_NPS_P2 + 1) - { "p3", 0, 0, 0, 1 }, - -#define F_NPS_LDBIT_DI (F_NPS_P3 + 1) - { "di", 0, 0, 0, 1 }, - -#define F_NPS_LDBIT_CL1 (F_NPS_LDBIT_DI + 1) - { "cl", 1, 1, 6, 1 }, - -#define F_NPS_LDBIT_CL2 (F_NPS_LDBIT_CL1 + 1) - { "cl", 1, 1, 16, 1 }, - -#define F_NPS_LDBIT_X2_1 (F_NPS_LDBIT_CL2 + 1) - { "x2", 1, 2, 9, 1 }, - -#define F_NPS_LDBIT_X2_2 (F_NPS_LDBIT_X2_1 + 1) - { "x2", 1, 2, 22, 1 }, - -#define F_NPS_LDBIT_X4_1 (F_NPS_LDBIT_X2_2 + 1) - { "x4", 2, 2, 9, 1 }, - -#define F_NPS_LDBIT_X4_2 (F_NPS_LDBIT_X4_1 + 1) - { "x4", 2, 2, 22, 1 }, - -#define F_NPS_CORE (F_NPS_LDBIT_X4_2 + 1) - { "core", 1, 3, 6, 1 }, - -#define F_NPS_CLSR (F_NPS_CORE + 1) - { "clsr", 2, 3, 6, 1 }, - -#define F_NPS_ALL (F_NPS_CLSR + 1) - { "all", 3, 3, 6, 1 }, - -#define F_NPS_GIC (F_NPS_ALL + 1) - { "gic", 4, 3, 6, 1 }, - -#define F_NPS_RSPI_GIC (F_NPS_GIC + 1) - { "gic", 5, 3, 6, 1 }, -}; - -const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands); - -/* Table of the flag classes. - - The format of the table is - CLASS {FLAG_CODE}. */ -const struct arc_flag_class arc_flag_classes[] = -{ -#define C_EMPTY 0 - { F_CLASS_NONE, { F_NULL } }, - -#define C_CC_EQ (C_EMPTY + 1) - {F_CLASS_IMPLICIT | F_CLASS_COND, {F_EQUAL, F_NULL} }, - -#define C_CC_GE (C_CC_EQ + 1) - {F_CLASS_IMPLICIT | F_CLASS_COND, {F_GE, F_NULL} }, - -#define C_CC_GT (C_CC_GE + 1) - {F_CLASS_IMPLICIT | F_CLASS_COND, {F_GT, F_NULL} }, - -#define C_CC_HI (C_CC_GT + 1) - {F_CLASS_IMPLICIT | F_CLASS_COND, {F_HI, F_NULL} }, - -#define C_CC_HS (C_CC_HI + 1) - {F_CLASS_IMPLICIT | F_CLASS_COND, {F_NOTCARRY, F_NULL} }, - -#define C_CC_LE (C_CC_HS + 1) - {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LE, F_NULL} }, - -#define C_CC_LO (C_CC_LE + 1) - {F_CLASS_IMPLICIT | F_CLASS_COND, {F_CARRY, F_NULL} }, - -#define C_CC_LS (C_CC_LO + 1) - {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LS, F_NULL} }, - -#define C_CC_LT (C_CC_LS + 1) - {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LT, F_NULL} }, - -#define C_CC_NE (C_CC_LT + 1) - {F_CLASS_IMPLICIT | F_CLASS_COND, {F_NOTEQUAL, F_NULL} }, - -#define C_AA_AB (C_CC_NE + 1) - {F_CLASS_IMPLICIT | F_CLASS_WB, {F_AB3, F_NULL} }, - -#define C_AA_AW (C_AA_AB + 1) - {F_CLASS_IMPLICIT | F_CLASS_WB, {F_AW3, F_NULL} }, - -#define C_ZZ_D (C_AA_AW + 1) - {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_SIZED, F_NULL} }, - -#define C_ZZ_H (C_ZZ_D + 1) - {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_H1, F_NULL} }, - -#define C_ZZ_B (C_ZZ_H + 1) - {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_SIZEB1, F_NULL} }, - -#define C_CC (C_ZZ_B + 1) - { F_CLASS_OPTIONAL | F_CLASS_EXTEND | F_CLASS_COND, - { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, - F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS, - F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, - F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, - F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT, - F_LE, F_HI, F_LS, F_PNZ, F_NJ, F_NM, F_NO_T, F_NULL } }, - -#define C_AA_ADDR3 (C_CC + 1) -#define C_AA27 (C_CC + 1) - { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A3, F_AW3, F_AB3, F_AS3, F_NULL } }, -#define C_AA_ADDR9 (C_AA_ADDR3 + 1) -#define C_AA21 (C_AA_ADDR3 + 1) - { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A9, F_AW9, F_AB9, F_AS9, F_NULL } }, -#define C_AA_ADDR22 (C_AA_ADDR9 + 1) -#define C_AA8 (C_AA_ADDR9 + 1) - { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A22, F_AW22, F_AB22, F_AS22, F_NULL } }, - -#define C_F (C_AA_ADDR22 + 1) - { F_CLASS_OPTIONAL, { F_FLAG, F_NULL } }, -#define C_FHARD (C_F + 1) - { F_CLASS_OPTIONAL, { F_FFAKE, F_NULL } }, - -#define C_T (C_FHARD + 1) - { F_CLASS_OPTIONAL, { F_NT, F_T, F_NULL } }, -#define C_D (C_T + 1) - { F_CLASS_OPTIONAL, { F_ND, F_D, F_NULL } }, -#define C_DNZ_D (C_D + 1) - { F_CLASS_OPTIONAL, { F_DNZ_ND, F_DNZ_D, F_NULL } }, - -#define C_DHARD (C_DNZ_D + 1) - { F_CLASS_OPTIONAL, { F_DFAKE, F_NULL } }, - -#define C_DI20 (C_DHARD + 1) - { F_CLASS_OPTIONAL, { F_DI11, F_NULL }}, -#define C_DI14 (C_DI20 + 1) - { F_CLASS_OPTIONAL, { F_DI14, F_NULL }}, -#define C_DI16 (C_DI14 + 1) - { F_CLASS_OPTIONAL, { F_DI15, F_NULL }}, -#define C_DI26 (C_DI16 + 1) - { F_CLASS_OPTIONAL, { F_DI5, F_NULL }}, - -#define C_X25 (C_DI26 + 1) - { F_CLASS_OPTIONAL, { F_SIGN6, F_NULL }}, -#define C_X15 (C_X25 + 1) - { F_CLASS_OPTIONAL, { F_SIGN16, F_NULL }}, -#define C_XHARD (C_X15 + 1) -#define C_X (C_X15 + 1) - { F_CLASS_OPTIONAL, { F_SIGNX, F_NULL }}, - -#define C_ZZ13 (C_X + 1) - { F_CLASS_OPTIONAL, { F_SIZEB17, F_SIZEW17, F_H17, F_NULL}}, -#define C_ZZ23 (C_ZZ13 + 1) - { F_CLASS_OPTIONAL, { F_SIZEB7, F_SIZEW7, F_H7, F_NULL}}, -#define C_ZZ29 (C_ZZ23 + 1) - { F_CLASS_OPTIONAL, { F_SIZEB1, F_SIZEW1, F_H1, F_NULL}}, - -#define C_AS (C_ZZ29 + 1) - { F_CLASS_OPTIONAL, { F_ASFAKE, F_NULL}}, - -#define C_NE (C_AS + 1) - { F_CLASS_REQUIRED, { F_NE, F_NULL}}, - - /* ARC NPS400 Support: See comment near head of file. */ -#define C_NPS_CL (C_NE + 1) - { F_CLASS_REQUIRED, { F_NPS_CL, F_NULL}}, - -#define C_NPS_NA (C_NPS_CL + 1) - { F_CLASS_OPTIONAL, { F_NPS_NA, F_NULL}}, - -#define C_NPS_SR (C_NPS_NA + 1) - { F_CLASS_OPTIONAL, { F_NPS_SR, F_NULL}}, - -#define C_NPS_M (C_NPS_SR + 1) - { F_CLASS_OPTIONAL, { F_NPS_M, F_NULL}}, - -#define C_NPS_F (C_NPS_M + 1) - { F_CLASS_OPTIONAL, { F_NPS_FLAG, F_NULL}}, - -#define C_NPS_R (C_NPS_F + 1) - { F_CLASS_OPTIONAL, { F_NPS_R, F_NULL}}, - -#define C_NPS_SCHD_RW (C_NPS_R + 1) - { F_CLASS_REQUIRED, { F_NPS_RW, F_NPS_RD, F_NULL}}, - -#define C_NPS_SCHD_TRIG (C_NPS_SCHD_RW + 1) - { F_CLASS_REQUIRED, { F_NPS_WFT, F_NULL}}, - -#define C_NPS_SCHD_IE (C_NPS_SCHD_TRIG + 1) - { F_CLASS_OPTIONAL, { F_NPS_IE1, F_NPS_IE2, F_NPS_IE12, F_NULL}}, - -#define C_NPS_SYNC (C_NPS_SCHD_IE + 1) - { F_CLASS_REQUIRED, { F_NPS_SYNC_RD, F_NPS_SYNC_WR, F_NULL}}, - -#define C_NPS_HWS_OFF (C_NPS_SYNC + 1) - { F_CLASS_REQUIRED, { F_NPS_HWS_OFF, F_NULL}}, - -#define C_NPS_HWS_RESTORE (C_NPS_HWS_OFF + 1) - { F_CLASS_REQUIRED, { F_NPS_HWS_RESTORE, F_NULL}}, - -#define C_NPS_SX (C_NPS_HWS_RESTORE + 1) - { F_CLASS_OPTIONAL, { F_NPS_SX, F_NULL}}, - -#define C_NPS_AR_AL (C_NPS_SX + 1) - { F_CLASS_REQUIRED, { F_NPS_AR, F_NPS_AL, F_NULL}}, - -#define C_NPS_S (C_NPS_AR_AL + 1) - { F_CLASS_REQUIRED, { F_NPS_S, F_NULL}}, - -#define C_NPS_ZNCV (C_NPS_S + 1) - { F_CLASS_REQUIRED, { F_NPS_ZNCV_RD, F_NPS_ZNCV_WR, F_NULL}}, - -#define C_NPS_P0 (C_NPS_ZNCV + 1) - { F_CLASS_REQUIRED, { F_NPS_P0, F_NULL }}, - -#define C_NPS_P1 (C_NPS_P0 + 1) - { F_CLASS_REQUIRED, { F_NPS_P1, F_NULL }}, - -#define C_NPS_P2 (C_NPS_P1 + 1) - { F_CLASS_REQUIRED, { F_NPS_P2, F_NULL }}, - -#define C_NPS_P3 (C_NPS_P2 + 1) - { F_CLASS_REQUIRED, { F_NPS_P3, F_NULL }}, - -#define C_NPS_LDBIT_DI (C_NPS_P3 + 1) - { F_CLASS_REQUIRED, { F_NPS_LDBIT_DI, F_NULL }}, - -#define C_NPS_LDBIT_CL1 (C_NPS_LDBIT_DI + 1) - { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL1, F_NULL }}, - -#define C_NPS_LDBIT_CL2 (C_NPS_LDBIT_CL1 + 1) - { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL2, F_NULL }}, - -#define C_NPS_LDBIT_X_1 (C_NPS_LDBIT_CL2 + 1) - { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_1, F_NPS_LDBIT_X4_1, F_NULL }}, - -#define C_NPS_LDBIT_X_2 (C_NPS_LDBIT_X_1 + 1) - { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_2, F_NPS_LDBIT_X4_2, F_NULL }}, - -#define C_NPS_CORE (C_NPS_LDBIT_X_2 + 1) - { F_CLASS_REQUIRED, { F_NPS_CORE, F_NULL}}, - -#define C_NPS_CLSR (C_NPS_CORE + 1) - { F_CLASS_REQUIRED, { F_NPS_CLSR, F_NULL}}, - -#define C_NPS_ALL (C_NPS_CLSR + 1) - { F_CLASS_REQUIRED, { F_NPS_ALL, F_NULL}}, - -#define C_NPS_GIC (C_NPS_ALL + 1) - { F_CLASS_REQUIRED, { F_NPS_GIC, F_NULL}}, - -#define C_NPS_RSPI_GIC (C_NPS_GIC + 1) - { F_CLASS_REQUIRED, { F_NPS_RSPI_GIC, F_NULL}}, -}; - -const unsigned char flags_none[] = { 0 }; -const unsigned char flags_f[] = { C_F }; -const unsigned char flags_cc[] = { C_CC }; -const unsigned char flags_ccf[] = { C_CC, C_F }; - -/* The operands table. - - The format of the operands table is: - - BITS SHIFT DEFAULT_RELOC FLAGS INSERT_FUN EXTRACT_FUN. */ -const struct arc_operand arc_operands[] = -{ - /* The fields are bits, shift, insert, extract, flags. The zero - index is used to indicate end-of-list. */ -#define UNUSED 0 - { 0, 0, 0, 0, 0, 0 }, - -#define IGNORED (UNUSED + 1) - { 0, 0, 0, ARC_OPERAND_IGNORE | ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 0, 0 }, - - /* The plain integer register fields. Used by 32 bit - instructions. */ -#define RA (IGNORED + 1) - { 6, 0, 0, ARC_OPERAND_IR, 0, 0 }, -#define RA_CHK (RA + 1) - { 6, 0, 0, ARC_OPERAND_IR, insert_ra_chk, 0 }, -#define RB (RA_CHK + 1) - { 6, 12, 0, ARC_OPERAND_IR, insert_rb, extract_rb }, -#define RB_CHK (RB + 1) - { 6, 12, 0, ARC_OPERAND_IR, insert_rb_chk, extract_rb }, -#define RC (RB_CHK + 1) - { 6, 6, 0, ARC_OPERAND_IR, 0, 0 }, -#define RBdup (RC + 1) - { 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rb, extract_rb }, - -#define RAD (RBdup + 1) - { 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0 }, -#define RAD_CHK (RAD + 1) - { 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0 }, -#define RCD (RAD_CHK + 1) - { 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rcd, 0 }, -#define RBD (RCD + 1) - { 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rbd, extract_rb }, -#define RBDdup (RBD + 1) - { 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_TRUNCATE, - insert_rbd, extract_rb }, - - /* The plain integer register fields. Used by short - instructions. */ -#define RA16 (RBDdup + 1) -#define RA_S (RBDdup + 1) - { 4, 0, 0, ARC_OPERAND_IR, insert_ras, extract_ras }, -#define RB16 (RA16 + 1) -#define RB_S (RA16 + 1) - { 4, 8, 0, ARC_OPERAND_IR, insert_rbs, extract_rbs }, -#define RB16dup (RB16 + 1) -#define RB_Sdup (RB16 + 1) - { 4, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rbs, extract_rbs }, -#define RC16 (RB16dup + 1) -#define RC_S (RB16dup + 1) - { 4, 5, 0, ARC_OPERAND_IR, insert_rcs, extract_rcs }, -#define R6H (RC16 + 1) /* 6bit register field 'h' used - by V1 cpus. */ - { 6, 5, 0, ARC_OPERAND_IR, insert_rhv1, extract_rhv1 }, -#define R5H (R6H + 1) /* 5bit register field 'h' used - by V2 cpus. */ -#define RH_S (R6H + 1) /* 5bit register field 'h' used - by V2 cpus. */ - { 5, 5, 0, ARC_OPERAND_IR, insert_rhv2, extract_rhv2 }, -#define R5Hdup (R5H + 1) -#define RH_Sdup (R5H + 1) - { 5, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, - insert_rhv2, extract_rhv2 }, - -#define RG (R5Hdup + 1) -#define G_S (R5Hdup + 1) - { 5, 5, 0, ARC_OPERAND_IR, insert_g_s, extract_g_s }, - - /* Fix registers. */ -#define R0 (RG + 1) -#define R0_S (RG + 1) - { 0, 0, 0, ARC_OPERAND_IR, insert_r0, extract_r0 }, -#define R1 (R0 + 1) -#define R1_S (R0 + 1) - { 1, 0, 0, ARC_OPERAND_IR, insert_r1, extract_r1 }, -#define R2 (R1 + 1) -#define R2_S (R1 + 1) - { 2, 0, 0, ARC_OPERAND_IR, insert_r2, extract_r2 }, -#define R3 (R2 + 1) -#define R3_S (R2 + 1) - { 2, 0, 0, ARC_OPERAND_IR, insert_r3, extract_r3 }, -#define RSP (R3 + 1) -#define SP_S (R3 + 1) - { 5, 0, 0, ARC_OPERAND_IR, insert_sp, extract_sp }, -#define SPdup (RSP + 1) -#define SP_Sdup (RSP + 1) - { 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_sp, extract_sp }, -#define GP (SPdup + 1) -#define GP_S (SPdup + 1) - { 5, 0, 0, ARC_OPERAND_IR, insert_gp, extract_gp }, - -#define PCL_S (GP + 1) - { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_pcl, extract_pcl }, - -#define BLINK (PCL_S + 1) -#define BLINK_S (PCL_S + 1) - { 5, 0, 0, ARC_OPERAND_IR, insert_blink, extract_blink }, - -#define ILINK1 (BLINK + 1) - { 5, 0, 0, ARC_OPERAND_IR, insert_ilink1, extract_ilink1 }, -#define ILINK2 (ILINK1 + 1) - { 5, 0, 0, ARC_OPERAND_IR, insert_ilink2, extract_ilink2 }, - - /* Long immediate. */ -#define LIMM (ILINK2 + 1) -#define LIMM_S (ILINK2 + 1) - { 32, 0, BFD_RELOC_ARC_32_ME, ARC_OPERAND_LIMM, insert_limm, 0 }, -#define LIMMdup (LIMM + 1) - { 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_DUPLICATE, insert_limm, 0 }, - - /* Special operands. */ -#define ZA (LIMMdup + 1) -#define ZB (LIMMdup + 1) -#define ZA_S (LIMMdup + 1) -#define ZB_S (LIMMdup + 1) -#define ZC_S (LIMMdup + 1) - { 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0 }, - -#define RRANGE_EL (ZA + 1) - { 4, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK | ARC_OPERAND_TRUNCATE, - insert_rrange, extract_rrange}, -#define R13_EL (RRANGE_EL + 1) - { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, - insert_r13el, extract_rrange }, -#define FP_EL (R13_EL + 1) - { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, - insert_fpel, extract_fpel }, -#define BLINK_EL (FP_EL + 1) - { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, - insert_blinkel, extract_blinkel }, -#define PCL_EL (BLINK_EL + 1) - { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, - insert_pclel, extract_pclel }, - - /* Fake operand to handle the T flag. */ -#define BRAKET (PCL_EL + 1) -#define BRAKETdup (PCL_EL + 1) - { 0, 0, 0, ARC_OPERAND_FAKE | ARC_OPERAND_BRAKET, 0, 0 }, - - /* Fake operand to handle the T flag. */ -#define FKT_T (BRAKET + 1) - { 1, 3, 0, ARC_OPERAND_FAKE, insert_Ybit, 0 }, - /* Fake operand to handle the T flag. */ -#define FKT_NT (FKT_T + 1) - { 1, 3, 0, ARC_OPERAND_FAKE, insert_NYbit, 0 }, - - /* UIMM6_20 mask = 00000000000000000000111111000000. */ -#define UIMM6_20 (FKT_NT + 1) - {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_20, extract_uimm6_20}, - - /* Exactly like the above but used by relaxation. */ -#define UIMM6_20R (UIMM6_20 + 1) - {6, 0, -UIMM6_20R, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL, - insert_uimm6_20, extract_uimm6_20}, - - /* SIMM12_20 mask = 00000000000000000000111111222222. */ -#define SIMM12_20 (UIMM6_20R + 1) - {12, 0, 0, ARC_OPERAND_SIGNED, insert_simm12_20, extract_simm12_20}, - - /* Exactly like the above but used by relaxation. */ -#define SIMM12_20R (SIMM12_20 + 1) - {12, 0, -SIMM12_20R, ARC_OPERAND_SIGNED | ARC_OPERAND_PCREL, - insert_simm12_20, extract_simm12_20}, - - /* UIMM12_20 mask = 00000000000000000000111111222222. */ -#define UIMM12_20 (SIMM12_20R + 1) - {12, 0, 0, ARC_OPERAND_UNSIGNED, insert_simm12_20, extract_uimm12_20}, - - /* SIMM3_5_S mask = 0000011100000000. */ -#define SIMM3_5_S (UIMM12_20 + 1) - {3, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_NCHK, - insert_simm3s, extract_simm3s}, - - /* UIMM7_A32_11_S mask = 0000000000011111. */ -#define UIMM7_A32_11_S (SIMM3_5_S + 1) - {7, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 - | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm7_a32_11_s, - extract_uimm7_a32_11_s}, - - /* The same as above but used by relaxation. */ -#define UIMM7_A32_11R_S (UIMM7_A32_11_S + 1) - {7, 0, -UIMM7_A32_11R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 - | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE | ARC_OPERAND_PCREL, - insert_uimm7_a32_11_s, extract_uimm7_a32_11_s}, - - /* UIMM7_9_S mask = 0000000001111111. */ -#define UIMM7_9_S (UIMM7_A32_11R_S + 1) - {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_9_s, extract_uimm7_9_s}, - - /* UIMM3_13_S mask = 0000000000000111. */ -#define UIMM3_13_S (UIMM7_9_S + 1) - {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_13_s, extract_uimm3_13_s}, - - /* Exactly like the above but used for relaxation. */ -#define UIMM3_13R_S (UIMM3_13_S + 1) - {3, 0, -UIMM3_13R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL, - insert_uimm3_13_s, extract_uimm3_13_s}, - - /* SIMM11_A32_7_S mask = 0000000111111111. */ -#define SIMM11_A32_7_S (UIMM3_13R_S + 1) - {11, 0, BFD_RELOC_ARC_SDA16_LD2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 - | ARC_OPERAND_TRUNCATE, insert_simm11_a32_7_s, extract_simm11_a32_7_s}, - - /* UIMM6_13_S mask = 0000000002220111. */ -#define UIMM6_13_S (SIMM11_A32_7_S + 1) - {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_13_s, extract_uimm6_13_s}, - /* UIMM5_11_S mask = 0000000000011111. */ -#define UIMM5_11_S (UIMM6_13_S + 1) - {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_IGNORE, insert_uimm5_11_s, - extract_uimm5_11_s}, - - /* SIMM9_A16_8 mask = 00000000111111102000000000000000. */ -#define SIMM9_A16_8 (UIMM5_11_S + 1) - {9, 0, -SIMM9_A16_8, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 - | ARC_OPERAND_PCREL | ARC_OPERAND_TRUNCATE, insert_simm9_a16_8, - extract_simm9_a16_8}, - - /* UIMM6_8 mask = 00000000000000000000111111000000. */ -#define UIMM6_8 (SIMM9_A16_8 + 1) - {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_8, extract_uimm6_8}, - - /* SIMM21_A16_5 mask = 00000111111111102222222222000000. */ -#define SIMM21_A16_5 (UIMM6_8 + 1) - {21, 0, BFD_RELOC_ARC_S21H_PCREL, ARC_OPERAND_SIGNED - | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, - insert_simm21_a16_5, extract_simm21_a16_5}, - - /* SIMM25_A16_5 mask = 00000111111111102222222222003333. */ -#define SIMM25_A16_5 (SIMM21_A16_5 + 1) - {25, 0, BFD_RELOC_ARC_S25H_PCREL, ARC_OPERAND_SIGNED - | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, - insert_simm25_a16_5, extract_simm25_a16_5}, - - /* SIMM10_A16_7_S mask = 0000000111111111. */ -#define SIMM10_A16_7_S (SIMM25_A16_5 + 1) - {10, 0, -SIMM10_A16_7_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 - | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm10_a16_7_s, - extract_simm10_a16_7_s}, - -#define SIMM10_A16_7_Sbis (SIMM10_A16_7_S + 1) - {10, 0, -SIMM10_A16_7_Sbis, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 - | ARC_OPERAND_TRUNCATE, insert_simm10_a16_7_s, extract_simm10_a16_7_s}, - - /* SIMM7_A16_10_S mask = 0000000000111111. */ -#define SIMM7_A16_10_S (SIMM10_A16_7_Sbis + 1) - {7, 0, -SIMM7_A16_10_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 - | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm7_a16_10_s, - extract_simm7_a16_10_s}, - - /* SIMM21_A32_5 mask = 00000111111111002222222222000000. */ -#define SIMM21_A32_5 (SIMM7_A16_10_S + 1) - {21, 0, BFD_RELOC_ARC_S21W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 - | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm21_a32_5, - extract_simm21_a32_5}, - - /* SIMM25_A32_5 mask = 00000111111111002222222222003333. */ -#define SIMM25_A32_5 (SIMM21_A32_5 + 1) - {25, 0, BFD_RELOC_ARC_S25W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 - | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm25_a32_5, - extract_simm25_a32_5}, - - /* SIMM13_A32_5_S mask = 0000011111111111. */ -#define SIMM13_A32_5_S (SIMM25_A32_5 + 1) - {13, 0, BFD_RELOC_ARC_S13_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 - | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a32_5_s, - extract_simm13_a32_5_s}, - - /* SIMM8_A16_9_S mask = 0000000001111111. */ -#define SIMM8_A16_9_S (SIMM13_A32_5_S + 1) - {8, 0, -SIMM8_A16_9_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 - | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm8_a16_9_s, - extract_simm8_a16_9_s}, - -/* UIMM10_6_S_JLIOFF mask = 0000001111111111. */ -#define UIMM10_6_S_JLIOFF (SIMM8_A16_9_S + 1) - {12, 0, BFD_RELOC_ARC_JLI_SECTOFF, ARC_OPERAND_UNSIGNED - | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE, insert_uimm10_6_s, - extract_uimm10_6_s}, - - /* UIMM3_23 mask = 00000000000000000000000111000000. */ -#define UIMM3_23 (UIMM10_6_S_JLIOFF + 1) - {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_23, extract_uimm3_23}, - - /* UIMM10_6_S mask = 0000001111111111. */ -#define UIMM10_6_S (UIMM3_23 + 1) - {10, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm10_6_s, extract_uimm10_6_s}, - - /* UIMM6_11_S mask = 0000002200011110. */ -#define UIMM6_11_S (UIMM10_6_S + 1) - {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_11_s, extract_uimm6_11_s}, - - /* SIMM9_8 mask = 00000000111111112000000000000000. */ -#define SIMM9_8 (UIMM6_11_S + 1) - {9, 0, BFD_RELOC_ARC_SDA_LDST, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE, - insert_simm9_8, extract_simm9_8}, - - /* The same as above but used by relaxation. */ -#define SIMM9_8R (SIMM9_8 + 1) - {9, 0, -SIMM9_8R, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE - | ARC_OPERAND_PCREL, insert_simm9_8, extract_simm9_8}, - - /* UIMM10_A32_8_S mask = 0000000011111111. */ -#define UIMM10_A32_8_S (SIMM9_8R + 1) - {10, 0, -UIMM10_A32_8_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 - | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm10_a32_8_s, - extract_uimm10_a32_8_s}, - - /* SIMM9_7_S mask = 0000000111111111. */ -#define SIMM9_7_S (UIMM10_A32_8_S + 1) - {9, 0, BFD_RELOC_ARC_SDA16_LD, ARC_OPERAND_SIGNED, insert_simm9_7_s, - extract_simm9_7_s}, - - /* UIMM6_A16_11_S mask = 0000000000011111. */ -#define UIMM6_A16_11_S (SIMM9_7_S + 1) - {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16 - | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm6_a16_11_s, - extract_uimm6_a16_11_s}, - - /* UIMM5_A32_11_S mask = 0000020000011000. */ -#define UIMM5_A32_11_S (UIMM6_A16_11_S + 1) - {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 - | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm5_a32_11_s, - extract_uimm5_a32_11_s}, - - /* SIMM11_A32_13_S mask = 0000022222200111. */ -#define SIMM11_A32_13_S (UIMM5_A32_11_S + 1) - {11, 0, BFD_RELOC_ARC_SDA16_ST2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 - | ARC_OPERAND_TRUNCATE, insert_simm11_a32_13_s, extract_simm11_a32_13_s}, - - /* UIMM7_13_S mask = 0000000022220111. */ -#define UIMM7_13_S (SIMM11_A32_13_S + 1) - {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_13_s, extract_uimm7_13_s}, - - /* UIMM6_A16_21 mask = 00000000000000000000011111000000. */ -#define UIMM6_A16_21 (UIMM7_13_S + 1) - {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16 - | ARC_OPERAND_TRUNCATE, insert_uimm6_a16_21, extract_uimm6_a16_21}, - - /* UIMM7_11_S mask = 0000022200011110. */ -#define UIMM7_11_S (UIMM6_A16_21 + 1) - {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_11_s, extract_uimm7_11_s}, - - /* UIMM7_A16_20 mask = 00000000000000000000111111000000. */ -#define UIMM7_A16_20 (UIMM7_11_S + 1) - {7, 0, -UIMM7_A16_20, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16 - | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm7_a16_20, - extract_uimm7_a16_20}, - - /* SIMM13_A16_20 mask = 00000000000000000000111111222222. */ -#define SIMM13_A16_20 (UIMM7_A16_20 + 1) - {13, 0, -SIMM13_A16_20, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 - | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a16_20, - extract_simm13_a16_20}, - - /* UIMM8_8_S mask = 0000000011111111. */ -#define UIMM8_8_S (SIMM13_A16_20 + 1) - {8, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm8_8_s, extract_uimm8_8_s}, - - /* The same as above but used for relaxation. */ -#define UIMM8_8R_S (UIMM8_8_S + 1) - {8, 0, -UIMM8_8R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL, - insert_uimm8_8_s, extract_uimm8_8_s}, - - /* W6 mask = 00000000000000000000111111000000. */ -#define W6 (UIMM8_8R_S + 1) - {6, 0, 0, ARC_OPERAND_SIGNED, insert_w6, extract_w6}, - - /* UIMM6_5_S mask = 0000011111100000. */ -#define UIMM6_5_S (W6 + 1) - {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_5_s, extract_uimm6_5_s}, - - /* ARC NPS400 Support: See comment near head of file. */ -#define NPS_R_DST_3B (UIMM6_5_S + 1) - { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, - insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst }, - -#define NPS_R_SRC1_3B (NPS_R_DST_3B + 1) - { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, - insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst }, - -#define NPS_R_SRC2_3B (NPS_R_SRC1_3B + 1) - { 3, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, - insert_nps_3bit_reg_at_21_src2, extract_nps_3bit_reg_at_21_src2 }, - -#define NPS_R_DST (NPS_R_SRC2_3B + 1) - { 6, 21, 0, ARC_OPERAND_IR, NULL, NULL }, - -#define NPS_R_SRC1 (NPS_R_DST + 1) - { 6, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL }, - -#define NPS_BITOP_DST_POS (NPS_R_SRC1 + 1) - { 5, 5, 0, ARC_OPERAND_UNSIGNED, 0, 0 }, - -#define NPS_BITOP_SRC_POS (NPS_BITOP_DST_POS + 1) - { 5, 0, 0, ARC_OPERAND_UNSIGNED, 0, 0 }, - -#define NPS_BITOP_SIZE (NPS_BITOP_SRC_POS + 1) - { 5, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, - insert_nps_bitop_size, extract_nps_bitop_size }, - -#define NPS_BITOP_DST_POS_SZ (NPS_BITOP_SIZE + 1) - { 5, 0, 0, ARC_OPERAND_UNSIGNED, - insert_nps_dst_pos_and_size, extract_nps_dst_pos_and_size }, - -#define NPS_BITOP_SIZE_2B (NPS_BITOP_DST_POS_SZ + 1) - { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, - insert_nps_bitop_size_2b, extract_nps_bitop_size_2b }, - -#define NPS_BITOP_UIMM8 (NPS_BITOP_SIZE_2B + 1) - { 8, 0, 0, ARC_OPERAND_UNSIGNED, - insert_nps_bitop_uimm8, extract_nps_bitop_uimm8 }, - -#define NPS_UIMM16 (NPS_BITOP_UIMM8 + 1) - { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, - -#define NPS_SIMM16 (NPS_UIMM16 + 1) - { 16, 0, 0, ARC_OPERAND_SIGNED, NULL, NULL }, - -#define NPS_RFLT_UIMM6 (NPS_SIMM16 + 1) - { 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, - insert_nps_rflt_uimm6, extract_nps_rflt_uimm6 }, - -#define NPS_XLDST_UIMM16 (NPS_RFLT_UIMM6 + 1) - { 16, 0, BFD_RELOC_ARC_NPS_CMEM16, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, - insert_nps_cmem_uimm16, extract_nps_cmem_uimm16 }, - -#define NPS_SRC2_POS (NPS_XLDST_UIMM16 + 1) - { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, - insert_nps_src2_pos, extract_nps_src2_pos }, - -#define NPS_SRC1_POS (NPS_SRC2_POS + 1) - { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, - insert_nps_src1_pos, extract_nps_src1_pos }, - -#define NPS_ADDB_SIZE (NPS_SRC1_POS + 1) - { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, - insert_nps_addb_size, extract_nps_addb_size }, - -#define NPS_ANDB_SIZE (NPS_ADDB_SIZE + 1) - { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, - insert_nps_andb_size, extract_nps_andb_size }, - -#define NPS_FXORB_SIZE (NPS_ANDB_SIZE + 1) - { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, - insert_nps_fxorb_size, extract_nps_fxorb_size }, - -#define NPS_WXORB_SIZE (NPS_FXORB_SIZE + 1) - { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, - insert_nps_wxorb_size, extract_nps_wxorb_size }, - -#define NPS_R_XLDST (NPS_WXORB_SIZE + 1) - { 6, 5, 0, ARC_OPERAND_IR, NULL, NULL }, - -#define NPS_DIV_UIMM4 (NPS_R_XLDST + 1) - { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, - -#define NPS_QCMP_SIZE (NPS_DIV_UIMM4 + 1) - { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, - insert_nps_qcmp_size, extract_nps_qcmp_size }, - -#define NPS_QCMP_M1 (NPS_QCMP_SIZE + 1) - { 1, 14, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m1 }, - -#define NPS_QCMP_M2 (NPS_QCMP_M1 + 1) - { 1, 15, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m2 }, - -#define NPS_QCMP_M3 (NPS_QCMP_M2 + 1) - { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m3 }, - -#define NPS_CALC_ENTRY_SIZE (NPS_QCMP_M3 + 1) - { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, - insert_nps_calc_entry_size, extract_nps_calc_entry_size }, - -#define NPS_R_DST_3B_SHORT (NPS_CALC_ENTRY_SIZE + 1) - { 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, - insert_nps_3bit_reg_at_8_dst, extract_nps_3bit_reg_at_8_dst }, - -#define NPS_R_SRC1_3B_SHORT (NPS_R_DST_3B_SHORT + 1) - { 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, - insert_nps_3bit_reg_at_8_dst, extract_nps_3bit_reg_at_8_dst }, - -#define NPS_R_SRC2_3B_SHORT (NPS_R_SRC1_3B_SHORT + 1) - { 3, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, - insert_nps_3bit_reg_at_5_src2, extract_nps_3bit_reg_at_5_src2 }, - -#define NPS_BITOP_SIZE2 (NPS_R_SRC2_3B_SHORT + 1) - { 5, 25, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, - insert_nps_bitop2_size, extract_nps_bitop2_size }, - -#define NPS_BITOP_SIZE1 (NPS_BITOP_SIZE2 + 1) - { 5, 20, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, - insert_nps_bitop1_size, extract_nps_bitop1_size }, - -#define NPS_BITOP_DST_POS3_POS4 (NPS_BITOP_SIZE1 + 1) - { 5, 0, 0, ARC_OPERAND_UNSIGNED, - insert_nps_bitop_dst_pos3_pos4, extract_nps_bitop_dst_pos3_pos4 }, - -#define NPS_BITOP_DST_POS4 (NPS_BITOP_DST_POS3_POS4 + 1) - { 5, 42, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, - -#define NPS_BITOP_DST_POS3 (NPS_BITOP_DST_POS4 + 1) - { 5, 37, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, - -#define NPS_BITOP_DST_POS2 (NPS_BITOP_DST_POS3 + 1) - { 5, 15, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, - -#define NPS_BITOP_DST_POS1 (NPS_BITOP_DST_POS2 + 1) - { 5, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, - -#define NPS_BITOP_SRC_POS4 (NPS_BITOP_DST_POS1 + 1) - { 5, 32, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, - -#define NPS_BITOP_SRC_POS3 (NPS_BITOP_SRC_POS4 + 1) - { 5, 20, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, - -#define NPS_BITOP_SRC_POS2 (NPS_BITOP_SRC_POS3 + 1) - { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, - -#define NPS_BITOP_SRC_POS1 (NPS_BITOP_SRC_POS2 + 1) - { 5, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, - -#define NPS_BITOP_MOD4 (NPS_BITOP_SRC_POS1 + 1) - { 2, 0, 0, ARC_OPERAND_UNSIGNED, - insert_nps_bitop_mod4, extract_nps_bitop_mod4 }, - -#define NPS_BITOP_MOD3 (NPS_BITOP_MOD4 + 1) - { 2, 29, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, - -#define NPS_BITOP_MOD2 (NPS_BITOP_MOD3 + 1) - { 2, 27, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, - -#define NPS_BITOP_MOD1 (NPS_BITOP_MOD2 + 1) - { 2, 25, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, - -#define NPS_BITOP_INS_EXT (NPS_BITOP_MOD1 + 1) - { 5, 20, 0, ARC_OPERAND_UNSIGNED, - insert_nps_bitop_ins_ext, extract_nps_bitop_ins_ext }, - -#define NPS_FIELD_START_POS (NPS_BITOP_INS_EXT + 1) - { 3, 3, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, - -#define NPS_FIELD_SIZE (NPS_FIELD_START_POS + 1) - { 3, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, - insert_nps_field_size, extract_nps_field_size }, - -#define NPS_SHIFT_FACTOR (NPS_FIELD_SIZE + 1) - { 3, 9, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, - insert_nps_shift_factor, extract_nps_shift_factor }, - -#define NPS_BITS_TO_SCRAMBLE (NPS_SHIFT_FACTOR + 1) - { 3, 12, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, - insert_nps_bits_to_scramble, extract_nps_bits_to_scramble }, - -#define NPS_SRC2_POS_5B (NPS_BITS_TO_SCRAMBLE + 1) - { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, - -#define NPS_BDLEN_MAX_LEN (NPS_SRC2_POS_5B + 1) - { 8, 5, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, - insert_nps_bdlen_max_len, extract_nps_bdlen_max_len }, - -#define NPS_MIN_HOFS (NPS_BDLEN_MAX_LEN + 1) - { 4, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, - insert_nps_min_hofs, extract_nps_min_hofs }, - -#define NPS_PSBC (NPS_MIN_HOFS + 1) - { 1, 11, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, - -#define NPS_DPI_DST (NPS_PSBC + 1) - { 5, 11, 0, ARC_OPERAND_IR, NULL, NULL }, - - /* NPS_DPI_SRC1_3B is similar to NPS_R_SRC1_3B - but doesn't duplicate an operand. */ -#define NPS_DPI_SRC1_3B (NPS_DPI_DST + 1) - { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, - insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst }, - -#define NPS_HASH_WIDTH (NPS_DPI_SRC1_3B + 1) - { 5, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, - insert_nps_hash_width, extract_nps_hash_width }, - -#define NPS_HASH_PERM (NPS_HASH_WIDTH + 1) - { 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, - -#define NPS_HASH_NONLINEAR (NPS_HASH_PERM + 1) - { 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, - -#define NPS_HASH_BASEMAT (NPS_HASH_NONLINEAR + 1) - { 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, - -#define NPS_HASH_LEN (NPS_HASH_BASEMAT + 1) - { 3, 2, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, - insert_nps_hash_len, extract_nps_hash_len }, - -#define NPS_HASH_OFS (NPS_HASH_LEN + 1) - { 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, - -#define NPS_HASH_BASEMAT2 (NPS_HASH_OFS + 1) - { 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, - -#define NPS_E4BY_INDEX0 (NPS_HASH_BASEMAT2 + 1) - { 3, 8, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, - -#define NPS_E4BY_INDEX1 (NPS_E4BY_INDEX0 + 1) - { 3, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, - -#define NPS_E4BY_INDEX2 (NPS_E4BY_INDEX1 + 1) - { 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, - -#define NPS_E4BY_INDEX3 (NPS_E4BY_INDEX2 + 1) - { 2, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, - insert_nps_index3, extract_nps_index3 }, - -#define COLON (NPS_E4BY_INDEX3 + 1) - { 0, 0, 0, ARC_OPERAND_COLON | ARC_OPERAND_FAKE, NULL, NULL }, - -#define NPS_BD (COLON + 1) - { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, - insert_nps_bd, extract_nps_bd }, - -#define NPS_JID (NPS_BD + 1) - { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, - insert_nps_jid, extract_nps_jid }, - -#define NPS_LBD (NPS_JID + 1) - { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, - insert_nps_lbd, extract_nps_lbd }, - -#define NPS_MBD (NPS_LBD + 1) - { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, - insert_nps_mbd, extract_nps_mbd }, - -#define NPS_SD (NPS_MBD + 1) - { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, - insert_nps_sd, extract_nps_sd }, - -#define NPS_SM (NPS_SD + 1) - { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, - insert_nps_sm, extract_nps_sm }, - -#define NPS_XA (NPS_SM + 1) - { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, - insert_nps_xa, extract_nps_xa }, - -#define NPS_XD (NPS_XA + 1) - { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, - insert_nps_xd, extract_nps_xd }, - -#define NPS_CD (NPS_XD + 1) - { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, - insert_nps_cd, extract_nps_cd }, - -#define NPS_CBD (NPS_CD + 1) - { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, - insert_nps_cbd, extract_nps_cbd }, - -#define NPS_CJID (NPS_CBD + 1) - { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, - insert_nps_cjid, extract_nps_cjid }, - -#define NPS_CLBD (NPS_CJID + 1) - { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, - insert_nps_clbd, extract_nps_clbd }, - -#define NPS_CM (NPS_CLBD + 1) - { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, - insert_nps_cm, extract_nps_cm }, - -#define NPS_CSD (NPS_CM + 1) - { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, - insert_nps_csd, extract_nps_csd }, - -#define NPS_CXA (NPS_CSD + 1) - { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, - insert_nps_cxa, extract_nps_cxa }, - -#define NPS_CXD (NPS_CXA + 1) - { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, - insert_nps_cxd, extract_nps_cxd }, - -#define NPS_BD_TYPE (NPS_CXD + 1) - { 1, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, - -#define NPS_BMU_NUM (NPS_BD_TYPE + 1) - { 3, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, - insert_nps_bd_num_buff, extract_nps_bd_num_buff }, - -#define NPS_PMU_NXT_DST (NPS_BMU_NUM + 1) - { 4, 6, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, - -#define NPS_WHASH_SIZE (NPS_PMU_NXT_DST + 1) - { 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, - insert_nps_size_16bit, extract_nps_size_16bit }, - -#define NPS_PMU_NUM_JOB (NPS_WHASH_SIZE + 1) - { 2, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, - insert_nps_pmu_num_job, extract_nps_pmu_num_job }, - -#define NPS_DMA_IMM_ENTRY (NPS_PMU_NUM_JOB + 1) - { 3, 2, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, - insert_nps_imm_entry, extract_nps_imm_entry }, - -#define NPS_DMA_IMM_OFFSET (NPS_DMA_IMM_ENTRY + 1) - { 4, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, - insert_nps_imm_offset, extract_nps_imm_offset }, - -#define NPS_MISC_IMM_SIZE (NPS_DMA_IMM_OFFSET + 1) - { 7, 0, 0, ARC_OPERAND_UNSIGNED , NULL, NULL }, - -#define NPS_MISC_IMM_OFFSET (NPS_MISC_IMM_SIZE + 1) - { 5, 8, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, - insert_nps_misc_imm_offset, extract_nps_misc_imm_offset }, - -#define NPS_R_DST_3B_48 (NPS_MISC_IMM_OFFSET + 1) - { 3, 40, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, - insert_nps_3bit_reg_at_40_dst, extract_nps_3bit_reg_at_40_dst }, - -#define NPS_R_SRC1_3B_48 (NPS_R_DST_3B_48 + 1) - { 3, 40, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, - insert_nps_3bit_reg_at_40_dst, extract_nps_3bit_reg_at_40_dst }, - -#define NPS_R_SRC2_3B_48 (NPS_R_SRC1_3B_48 + 1) - { 3, 37, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, - insert_nps_3bit_reg_at_37_src2, extract_nps_3bit_reg_at_37_src2 }, - -#define NPS_R_DST_3B_64 (NPS_R_SRC2_3B_48 + 1) - { 3, 56, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, - insert_nps_3bit_reg_at_56_dst, extract_nps_3bit_reg_at_56_dst }, - -#define NPS_R_SRC1_3B_64 (NPS_R_DST_3B_64 + 1) - { 3, 56, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, - insert_nps_3bit_reg_at_56_dst, extract_nps_3bit_reg_at_56_dst }, - -#define NPS_R_SRC2_3B_64 (NPS_R_SRC1_3B_64 + 1) - { 3, 53, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, - insert_nps_3bit_reg_at_53_src2, extract_nps_3bit_reg_at_53_src2 }, - -#define NPS_RA_64 (NPS_R_SRC2_3B_64 + 1) - { 6, 53, 0, ARC_OPERAND_IR, NULL, NULL }, - -#define NPS_RB_64 (NPS_RA_64 + 1) - { 5, 48, 0, ARC_OPERAND_IR, NULL, NULL }, - -#define NPS_RBdup_64 (NPS_RB_64 + 1) - { 5, 43, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL }, - -#define NPS_RBdouble_64 (NPS_RBdup_64 + 1) - { 10, 43, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, - insert_nps_rbdouble_64, extract_nps_rbdouble_64 }, - -#define NPS_RC_64 (NPS_RBdouble_64 + 1) - { 5, 43, 0, ARC_OPERAND_IR, NULL, NULL }, - -#define NPS_UIMM16_0_64 (NPS_RC_64 + 1) - { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, - -#define NPS_PROTO_SIZE (NPS_UIMM16_0_64 + 1) - { 6, 16, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, - insert_nps_proto_size, extract_nps_proto_size } -}; -const unsigned arc_num_operands = ARRAY_SIZE (arc_operands); - -const unsigned arc_Toperand = FKT_T; -const unsigned arc_NToperand = FKT_NT; - -const unsigned char arg_none[] = { 0 }; -const unsigned char arg_32bit_rarbrc[] = { RA, RB, RC }; -const unsigned char arg_32bit_zarbrc[] = { ZA, RB, RC }; -const unsigned char arg_32bit_rbrbrc[] = { RB, RBdup, RC }; -const unsigned char arg_32bit_rarbu6[] = { RA, RB, UIMM6_20 }; -const unsigned char arg_32bit_zarbu6[] = { ZA, RB, UIMM6_20 }; -const unsigned char arg_32bit_rbrbu6[] = { RB, RBdup, UIMM6_20 }; -const unsigned char arg_32bit_rbrbs12[] = { RB, RBdup, SIMM12_20 }; -const unsigned char arg_32bit_ralimmrc[] = { RA, LIMM, RC }; -const unsigned char arg_32bit_rarblimm[] = { RA, RB, LIMM }; -const unsigned char arg_32bit_zalimmrc[] = { ZA, LIMM, RC }; -const unsigned char arg_32bit_zarblimm[] = { ZA, RB, LIMM }; - -const unsigned char arg_32bit_rbrblimm[] = { RB, RBdup, LIMM }; -const unsigned char arg_32bit_ralimmu6[] = { RA, LIMM, UIMM6_20 }; -const unsigned char arg_32bit_zalimmu6[] = { ZA, LIMM, UIMM6_20 }; - -const unsigned char arg_32bit_zalimms12[] = { ZA, LIMM, SIMM12_20 }; -const unsigned char arg_32bit_ralimmlimm[] = { RA, LIMM, LIMMdup }; -const unsigned char arg_32bit_zalimmlimm[] = { ZA, LIMM, LIMMdup }; - -const unsigned char arg_32bit_rbrc[] = { RB, RC }; -const unsigned char arg_32bit_zarc[] = { ZA, RC }; -const unsigned char arg_32bit_rbu6[] = { RB, UIMM6_20 }; -const unsigned char arg_32bit_zau6[] = { ZA, UIMM6_20 }; -const unsigned char arg_32bit_rblimm[] = { RB, LIMM }; -const unsigned char arg_32bit_zalimm[] = { ZA, LIMM }; - -const unsigned char arg_32bit_limmrc[] = { LIMM, RC }; -const unsigned char arg_32bit_limmu6[] = { LIMM, UIMM6_20 }; -const unsigned char arg_32bit_limms12[] = { LIMM, SIMM12_20 }; -const unsigned char arg_32bit_limmlimm[] = { LIMM, LIMMdup }; - -const unsigned char arg_32bit_rc[] = { RC }; -const unsigned char arg_32bit_u6[] = { UIMM6_20 }; -const unsigned char arg_32bit_limm[] = { LIMM }; +#include "arcxx-opc.inc" + +/* Common combinations of FLAGS. */ +#define FLAGS_NONE { 0 } +#define FLAGS_F { C_F } +#define FLAGS_CC { C_CC } +#define FLAGS_CCF { C_CC, C_F } + +/* Common combination of arguments. */ +#define ARG_NONE { 0 } +#define ARG_32BIT_RARBRC { RA, RB, RC } +#define ARG_32BIT_ZARBRC { ZA, RB, RC } +#define ARG_32BIT_RBRBRC { RB, RBdup, RC } +#define ARG_32BIT_RARBU6 { RA, RB, UIMM6_20 } +#define ARG_32BIT_ZARBU6 { ZA, RB, UIMM6_20 } +#define ARG_32BIT_RBRBU6 { RB, RBdup, UIMM6_20 } +#define ARG_32BIT_RBRBS12 { RB, RBdup, SIMM12_20 } +#define ARG_32BIT_RALIMMRC { RA, LIMM, RC } +#define ARG_32BIT_RARBLIMM { RA, RB, LIMM } +#define ARG_32BIT_ZALIMMRC { ZA, LIMM, RC } +#define ARG_32BIT_ZARBLIMM { ZA, RB, LIMM } + +#define ARG_32BIT_RBRBLIMM { RB, RBdup, LIMM } +#define ARG_32BIT_RALIMMU6 { RA, LIMM, UIMM6_20 } +#define ARG_32BIT_ZALIMMU6 { ZA, LIMM, UIMM6_20 } + +#define ARG_32BIT_ZALIMMS12 { ZA, LIMM, SIMM12_20 } +#define ARG_32BIT_RALIMMLIMM { RA, LIMM, LIMMdup } +#define ARG_32BIT_ZALIMMLIMM { ZA, LIMM, LIMMdup } + +#define ARG_32BIT_RBRC { RB, RC } +#define ARG_32BIT_ZARC { ZA, RC } +#define ARG_32BIT_RBU6 { RB, UIMM6_20 } +#define ARG_32BIT_ZAU6 { ZA, UIMM6_20 } +#define ARG_32BIT_RBLIMM { RB, LIMM } +#define ARG_32BIT_ZALIMM { ZA, LIMM } + +/* Macro to generate 2 operand extension instruction. */ +#define EXTINSN2OPF(NAME, CPU, CLASS, SCLASS, MOP, SOP, FL) \ + { NAME, INSN2OP_BC (MOP,SOP), MINSN2OP_BC, CPU, CLASS, SCLASS, \ + ARG_32BIT_RBRC, FL }, \ + { NAME, INSN2OP_0C (MOP,SOP), MINSN2OP_0C, CPU, CLASS, SCLASS, \ + ARG_32BIT_ZARC, FL }, \ + { NAME, INSN2OP_BU (MOP,SOP), MINSN2OP_BU, CPU, CLASS, SCLASS, \ + ARG_32BIT_RBU6, FL }, \ + { NAME, INSN2OP_0U (MOP,SOP), MINSN2OP_0U, CPU, CLASS, SCLASS, \ + ARG_32BIT_ZAU6, FL }, \ + { NAME, INSN2OP_BL (MOP,SOP), MINSN2OP_BL, CPU, CLASS, SCLASS, \ + ARG_32BIT_RBLIMM, FL }, \ + { NAME, INSN2OP_0L (MOP,SOP), MINSN2OP_0L, CPU, CLASS, SCLASS, \ + ARG_32BIT_ZALIMM, FL }, + +#define EXTINSN2OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \ + EXTINSN2OPF (NAME, CPU, CLASS, SCLASS, MOP, SOP, FLAGS_F) + +/* Macro to generate 3 operand extesion instruction. */ +#define EXTINSN3OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \ + { NAME, INSN3OP_ABC (MOP,SOP), MINSN3OP_ABC, CPU, CLASS, SCLASS, \ + ARG_32BIT_RARBRC, FLAGS_F }, \ + { NAME, INSN3OP_0BC (MOP,SOP), MINSN3OP_0BC, CPU, CLASS, SCLASS, \ + ARG_32BIT_ZARBRC, FLAGS_F }, \ + { NAME, INSN3OP_CBBC (MOP,SOP), MINSN3OP_CBBC, CPU, CLASS, SCLASS, \ + ARG_32BIT_RBRBRC, FLAGS_CCF }, \ + { NAME, INSN3OP_ABU (MOP,SOP), MINSN3OP_ABU, CPU, CLASS, SCLASS, \ + ARG_32BIT_RARBU6, FLAGS_F }, \ + { NAME, INSN3OP_0BU (MOP,SOP), MINSN3OP_0BU, CPU, CLASS, SCLASS, \ + ARG_32BIT_ZARBU6, FLAGS_F }, \ + { NAME, INSN3OP_CBBU (MOP,SOP), MINSN3OP_CBBU, CPU, CLASS, SCLASS, \ + ARG_32BIT_RBRBU6, FLAGS_CCF }, \ + { NAME, INSN3OP_BBS (MOP,SOP), MINSN3OP_BBS, CPU, CLASS, SCLASS, \ + ARG_32BIT_RBRBS12, FLAGS_F }, \ + { NAME, INSN3OP_ALC (MOP,SOP), MINSN3OP_ALC, CPU, CLASS, SCLASS, \ + ARG_32BIT_RALIMMRC, FLAGS_F }, \ + { NAME, INSN3OP_ABL (MOP,SOP), MINSN3OP_ABL, CPU, CLASS, SCLASS, \ + ARG_32BIT_RARBLIMM, FLAGS_F }, \ + { NAME, INSN3OP_0LC (MOP,SOP), MINSN3OP_0LC, CPU, CLASS, SCLASS, \ + ARG_32BIT_ZALIMMRC, FLAGS_F }, \ + { NAME, INSN3OP_0BL (MOP,SOP), MINSN3OP_0BL, CPU, CLASS, SCLASS, \ + ARG_32BIT_ZARBLIMM, FLAGS_F }, \ + { NAME, INSN3OP_C0LC (MOP,SOP), MINSN3OP_C0LC, CPU, CLASS, SCLASS, \ + ARG_32BIT_ZALIMMRC, FLAGS_CCF }, \ + { NAME, INSN3OP_CBBL (MOP,SOP), MINSN3OP_CBBL, CPU, CLASS, SCLASS, \ + ARG_32BIT_RBRBLIMM, FLAGS_CCF }, \ + { NAME, INSN3OP_ALU (MOP,SOP), MINSN3OP_ALU, CPU, CLASS, SCLASS, \ + ARG_32BIT_RALIMMU6, FLAGS_F }, \ + { NAME, INSN3OP_0LU (MOP,SOP), MINSN3OP_0LU, CPU, CLASS, SCLASS, \ + ARG_32BIT_ZALIMMU6, FLAGS_F }, \ + { NAME, INSN3OP_C0LU (MOP,SOP), MINSN3OP_C0LU, CPU, CLASS, SCLASS, \ + ARG_32BIT_ZALIMMU6, FLAGS_CCF }, \ + { NAME, INSN3OP_0LS (MOP,SOP), MINSN3OP_0LS, CPU, CLASS, SCLASS, \ + ARG_32BIT_ZALIMMS12, FLAGS_F }, \ + { NAME, INSN3OP_ALL (MOP,SOP), MINSN3OP_ALL, CPU, CLASS, SCLASS, \ + ARG_32BIT_RALIMMLIMM, FLAGS_F }, \ + { NAME, INSN3OP_0LL (MOP,SOP), MINSN3OP_0LL, CPU, CLASS, SCLASS, \ + ARG_32BIT_ZALIMMLIMM, FLAGS_F }, \ + { NAME, INSN3OP_C0LL (MOP,SOP), MINSN3OP_C0LL, CPU, CLASS, SCLASS, \ + ARG_32BIT_ZALIMMLIMM, FLAGS_CCF }, /* The opcode table. @@ -2644,307 +152,19 @@ const unsigned char arg_32bit_limm[] = { LIMM }; mnemonic, so we end up with two groups for the sync instruction, the first within the core arc instruction table, and the second within the nps extension instructions. */ + const struct arc_opcode arc_opcodes[] = { #include "arc-tbl.h" #include "arc-nps400-tbl.h" -#include "arc-ext-tbl.h" - - { NULL, 0, 0, 0, 0, 0, { 0 }, { 0 } } -}; - -/* List with special cases instructions and the applicable flags. */ -const struct arc_flag_special arc_flag_special_cases[] = -{ - { "b", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, - F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, - F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, - F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NJ, F_NM, - F_NO_T, F_NULL } }, - { "bl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, - F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, - F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, - F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, - { "br", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, - F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, - F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, - F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, - { "j", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, - F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, - F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, - F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, - { "jl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, - F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, - F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, - F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, - { "lp", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, - F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, - F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, - F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, - { "set", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, - F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, - F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, - F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, - { "ld", { F_SIZEB17, F_SIZEW17, F_H17, F_NULL } }, - { "st", { F_SIZEB1, F_SIZEW1, F_H1, F_NULL } } -}; - -const unsigned arc_num_flag_special = ARRAY_SIZE (arc_flag_special_cases); - -/* Relocations. */ -const struct arc_reloc_equiv_tab arc_reloc_equiv[] = -{ - { "sda", "ld", { F_ASFAKE, F_H1, F_NULL }, - BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 }, - { "sda", "st", { F_ASFAKE, F_H1, F_NULL }, - BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 }, - { "sda", "ld", { F_ASFAKE, F_SIZEW7, F_NULL }, - BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 }, - { "sda", "st", { F_ASFAKE, F_SIZEW7, F_NULL }, - BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 }, - - /* Next two entries will cover the undefined behavior ldb/stb with - address scaling. */ - { "sda", "ld", { F_ASFAKE, F_SIZEB7, F_NULL }, - BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST }, - { "sda", "st", { F_ASFAKE, F_SIZEB7, F_NULL }, - BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST}, - - { "sda", "ld", { F_ASFAKE, F_NULL }, - BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 }, - { "sda", "st", { F_ASFAKE, F_NULL }, - BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2}, - { "sda", "ldd", { F_ASFAKE, F_NULL }, - BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 }, - { "sda", "std", { F_ASFAKE, F_NULL }, - BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2}, - - /* Short instructions. */ - { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD, BFD_RELOC_ARC_SDA16_LD }, - { "sda", 0, { F_NULL }, -SIMM10_A16_7_Sbis, BFD_RELOC_ARC_SDA16_LD1 }, - { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD2, BFD_RELOC_ARC_SDA16_LD2 }, - { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_ST2, BFD_RELOC_ARC_SDA16_ST2 }, - - { "sda", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_SDA32_ME }, - { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST }, - - { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25H_PCREL, - BFD_RELOC_ARC_S25H_PCREL_PLT }, - { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21H_PCREL, - BFD_RELOC_ARC_S21H_PCREL_PLT }, - { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25W_PCREL, - BFD_RELOC_ARC_S25W_PCREL_PLT }, - { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21W_PCREL, - BFD_RELOC_ARC_S21W_PCREL_PLT }, - - { "plt", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_PLT32 } -}; - -const unsigned arc_num_equiv_tab = ARRAY_SIZE (arc_reloc_equiv); - -const struct arc_pseudo_insn arc_pseudo_insns[] = -{ - { "push", "st", ".aw", 5, { { RC, 0, 0, 0 }, { BRAKET, 1, 0, 1 }, - { RB, 1, 28, 2 }, { SIMM9_8, 1, -4, 3 }, - { BRAKETdup, 1, 0, 4} } }, - { "pop", "ld", ".ab", 5, { { RA, 0, 0, 0 }, { BRAKET, 1, 0, 1 }, - { RB, 1, 28, 2 }, { SIMM9_8, 1, 4, 3 }, - { BRAKETdup, 1, 0, 4} } }, - - { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 }, - { SIMM9_A16_8, 0, 0, 2 } } }, - { "brgt", "brge", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, - { SIMM9_A16_8, 0, 0, 2 } } }, - { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 }, - { SIMM9_A16_8, 0, 0, 2 } } }, - { "brgt", "brlt", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 }, - { SIMM9_A16_8, 0, 0, 2 } } }, - { "brgt", "brge", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, - { SIMM9_A16_8, 0, 0, 2 } } }, - - { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 }, - { SIMM9_A16_8, 0, 0, 2 } } }, - { "brhi", "brhs", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, - { SIMM9_A16_8, 0, 0, 2 } } }, - { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 }, - { SIMM9_A16_8, 0, 0, 2 } } }, - { "brhi", "brlo", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 }, - { SIMM9_A16_8, 0, 0, 2 } } }, - { "brhi", "brhs", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, - { SIMM9_A16_8, 0, 0, 2 } } }, - - { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 }, - { SIMM9_A16_8, 0, 0, 2 } } }, - { "brle", "brlt", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, - { SIMM9_A16_8, 0, 0, 2 } } }, - { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 }, - { SIMM9_A16_8, 0, 0, 2 } } }, - { "brle", "brge", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 }, - { SIMM9_A16_8, 0, 0, 2 } } }, - { "brle", "brlt", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, - { SIMM9_A16_8, 0, 0, 2 } } }, - - { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 }, - { SIMM9_A16_8, 0, 0, 2 } } }, - { "brls", "brlo", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, - { SIMM9_A16_8, 0, 0, 2 } } }, - { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 }, - { SIMM9_A16_8, 0, 0, 2 } } }, - { "brls", "brhs", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 }, - { SIMM9_A16_8, 0, 0, 2 } } }, - { "brls", "brlo", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, - { SIMM9_A16_8, 0, 0, 2 } } }, -}; - -const unsigned arc_num_pseudo_insn = - sizeof (arc_pseudo_insns) / sizeof (*arc_pseudo_insns); - -const struct arc_aux_reg arc_aux_regs[] = -{ -#undef DEF -#define DEF(ADDR, CPU, SUBCLASS, NAME) \ - { ADDR, CPU, SUBCLASS, #NAME, sizeof (#NAME)-1 }, - -#include "arc-regs.h" -#undef DEF -}; - -const unsigned arc_num_aux_regs = ARRAY_SIZE (arc_aux_regs); - -/* NOTE: The order of this array MUST be consistent with 'enum - arc_rlx_types' located in tc-arc.h! */ -const struct arc_opcode arc_relax_opcodes[] = -{ - { NULL, 0x0, 0x0, 0x0, ARITH, NONE, { UNUSED }, { 0 } }, - - /* bl_s s13 11111sssssssssss. */ - { "bl_s", 0x0000F800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 - | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, - { SIMM13_A32_5_S }, { 0 }}, - - /* bl<.d> s25 00001sssssssss10SSSSSSSSSSNRtttt. */ - { "bl", 0x08020000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 - | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, - { SIMM25_A32_5 }, { C_D }}, - - /* b_s s10 1111000sssssssss. */ - { "b_s", 0x0000F000, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 - | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, - { SIMM10_A16_7_S }, { 0 }}, - - /* b<.d> s25 00000ssssssssss1SSSSSSSSSSNRtttt. */ - { "b", 0x00010000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 - | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, - { SIMM25_A16_5 }, { C_D }}, - - /* add_s c,b,u3 01101bbbccc00uuu. */ - { "add_s", 0x00006800, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 - | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, - { RC_S, RB_S, UIMM3_13R_S }, { 0 }}, - - /* add<.f> a,b,u6 00100bbb01000000FBBBuuuuuuAAAAAA. */ - { "add", 0x20400000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 - | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, - { RA, RB, UIMM6_20R }, { C_F }}, - - /* add<.f> a,b,limm 00100bbb00000000FBBB111110AAAAAA. */ - { "add", 0x20000F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 - | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, - { RA, RB, LIMM }, { C_F }}, - - /* ld_s c,b,u7 10000bbbcccuuuuu. */ - { "ld_s", 0x00008000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 - | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, - { RC_S, BRAKET, RB_S, UIMM7_A32_11R_S, BRAKETdup }, { 0 }}, - - /* ld<.di><.aa><.x><zz> a,b,s9 - 00010bbbssssssssSBBBDaaZZXAAAAAA. */ - { "ld", 0x10000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 - | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, - { RA, BRAKET, RB, SIMM9_8R, BRAKETdup }, - { C_ZZ23, C_DI20, C_AA21, C_X25 }}, - - /* ld<.di><.aa><.x><zz> a,b,limm 00100bbbaa110ZZXDBBB111110AAAAAA. */ - { "ld", 0x20300F80, 0xF8380FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 - | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, - { RA, BRAKET, RB, LIMM, BRAKETdup }, - { C_ZZ13, C_DI16, C_AA8, C_X15 }}, - - /* mov_s b,u8 11011bbbuuuuuuuu. */ - { "mov_s", 0x0000D800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 - | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, - { RB_S, UIMM8_8R_S }, { 0 }}, - - /* mov<.f> b,s12 00100bbb10001010FBBBssssssSSSSSS. */ - { "mov", 0x208A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 - | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, - { RB, SIMM12_20R }, { C_F }}, + /* Extension instruction declarations. */ + EXTINSN2OP ("dsp_fp_flt2i", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE1, 7, 43) + EXTINSN2OP ("dsp_fp_i2flt", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE1, 7, 44) + EXTINSN2OP ("dsp_fp_sqrt", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE2, 7, 45) - /* mov<.f> b,limm 00100bbb00001010FBBB111110RRRRRR. */ - { "mov", 0x200A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 - | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, - { RB, LIMM }, { C_F }}, + EXTINSN3OP ("dsp_fp_div", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE2, 7, 42) + EXTINSN3OP ("dsp_fp_cmp", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE1, 7, 43) - /* sub_s c,b,u3 01101bbbccc01uuu. */ - { "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 - | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, - { RC_S, RB_S, UIMM3_13R_S }, { 0 }}, - - /* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA. */ - { "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 - | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, - { RA, RB, UIMM6_20R }, { C_F }}, - - /* sub<.f> a,b,limm 00100bbb00000010FBBB111110AAAAAA. */ - { "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 - | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, - { RA, RB, LIMM }, { C_F }}, - - /* mpy<.f> a,b,u6 00100bbb01011010FBBBuuuuuuAAAAAA. */ - { "mpy", 0x205A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM - | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, UIMM6_20R }, { C_F }}, - - /* mpy<.f> a,b,limm 00100bbb00011010FBBB111110AAAAAA. */ - { "mpy", 0x201A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM - | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, LIMM }, { C_F }}, - - /* mov<.f><.cc> b,u6 00100bbb11001010FBBBuuuuuu1QQQQQ. */ - { "mov", 0x20CA0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 - | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, - { RB, UIMM6_20R }, { C_F, C_CC }}, - - /* mov<.f><.cc> b,limm 00100bbb11001010FBBB1111100QQQQQ. */ - { "mov", 0x20CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 - | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, - { RB, LIMM }, { C_F, C_CC }}, - - /* add<.f><.cc> b,b,u6 00100bbb11000000FBBBuuuuuu1QQQQQ. */ - { "add", 0x20C00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 - | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, - { RB, RBdup, UIMM6_20R }, { C_F, C_CC }}, - - /* add<.f><.cc> b,b,limm 00100bbb11000000FBBB1111100QQQQQ. */ - { "add", 0x20C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 - | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, - { RB, RBdup, LIMM }, { C_F, C_CC }} + { NULL, 0, 0, 0, 0, 0, { 0 }, { 0 } } }; - -const unsigned arc_num_relax_opcodes = ARRAY_SIZE (arc_relax_opcodes); - -/* Return length of an opcode in bytes. */ - -int -arc_opcode_len (const struct arc_opcode *opcode) -{ - if (opcode->mask < 0x10000ull) - return 2; - - if (opcode->mask < 0x100000000ull) - return 4; - - if (opcode->mask < 0x1000000000000ull) - return 6; - - return 8; -} diff --git a/opcodes/arc-operands.def b/opcodes/arc-operands.def new file mode 100644 index 00000000000..b7aae00e5d8 --- /dev/null +++ b/opcodes/arc-operands.def @@ -0,0 +1,502 @@ +/* ARC operands defintions. + Copyright (C) 2023 Free Software Foundation, Inc. + + Contributed by Claudiu Zissulescu (claziss@synopsys.com) + Refactored by Cupertino Miranda (cmiranda@synopsys.com) + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + + +/* + * ARC_OPERAND(NAME, BITS, SHIFT, RELO, FLAGS, FUN) + * + * BITS => The number of bits in the operand. + * SHIFT => How far the operand is left shifted in the instruction. + * RELO => The default relocation type for this operand. + * FLAGS => One bit syntax flags. + * FUN => Insertion function. This is used by the assembler. +*/ + +ARC_OPERAND(IGNORED, 0, 0, 0, ARC_OPERAND_IGNORE | ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 0, 0) + +/* The plain integer register fields. Used by 32 bit instructions. */ +ARC_OPERAND(RA, 6, 0, 0, ARC_OPERAND_IR, 0, 0) +ARC_OPERAND(RA_CHK, 6, 0, 0, ARC_OPERAND_IR, insert_ra_chk, 0) +ARC_OPERAND(RB, 6, 12, 0, ARC_OPERAND_IR, insert_rb, extract_rb) +ARC_OPERAND(RB_CHK, 6, 12, 0, ARC_OPERAND_IR, insert_rb_chk, extract_rb) +ARC_OPERAND(RBB_S, 6, 12, 0, ARC_OPERAND_IR, insert_rbb, extract_rbb) +ARC_OPERAND(RC, 6, 6, 0, ARC_OPERAND_IR, 0, 0) +ARC_OPERAND(RC_CHK, 6, 6, 0, ARC_OPERAND_IR, 0, 0) +ARC_OPERAND(RBdup, 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rb, extract_rb) + +ARC_OPERAND(RAD, 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0) +ARC_OPERAND(RAD_CHK, 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0) +ARC_OPERAND(RCD, 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rcd, 0) +ARC_OPERAND(RBD, 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rbd, extract_rb) +ARC_OPERAND(RBDdup, 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_TRUNCATE, insert_rbd, extract_rb) + +/* The plain integer register fields. Used by short instructions. */ +ARC_OPERAND(RA16, 4, 0, 0, ARC_OPERAND_IR, insert_ras, extract_ras) +ARC_OPERAND(RA_S, 4, 0, 0, ARC_OPERAND_IR, insert_ras, extract_ras) +ARC_OPERAND(RB16, 4, 8, 0, ARC_OPERAND_IR, insert_rbs, extract_rbs) +ARC_OPERAND(RB_S, 4, 8, 0, ARC_OPERAND_IR, insert_rbs, extract_rbs) +ARC_OPERAND(RB16dup, 4, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rbs, extract_rbs) +ARC_OPERAND(RB_Sdup, 4, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rbs, extract_rbs) +ARC_OPERAND(RC16, 4, 5, 0, ARC_OPERAND_IR, insert_rcs, extract_rcs) +ARC_OPERAND(RC_S, 4, 5, 0, ARC_OPERAND_IR, insert_rcs, extract_rcs) + +/* 6bit register field 'h' used by V1 cpus. */ +ARC_OPERAND(R6H, 6, 5, 0, ARC_OPERAND_IR, insert_rhv1, extract_rhv1) +/* 5bit register field 'h' used by V2 cpus. */ +ARC_OPERAND(R5H, 5, 5, 0, ARC_OPERAND_IR, insert_rhv2, extract_rhv2) +ARC_OPERAND(RH_S, 5, 5, 0, ARC_OPERAND_IR, insert_rhv2, extract_rhv2) +ARC_OPERAND(R5Hdup, 5, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rhv2, extract_rhv2) +ARC_OPERAND(RH_Sdup, 5, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rhv2, extract_rhv2) + +ARC_OPERAND(RG, 5, 5, 0, ARC_OPERAND_IR, insert_g_s, extract_g_s) +ARC_OPERAND(G_S, 5, 5, 0, ARC_OPERAND_IR, insert_g_s, extract_g_s) + +/* Fix registers. */ +ARC_OPERAND(R0, 0, 0, 0, ARC_OPERAND_IR, insert_r0, extract_r0) +ARC_OPERAND(R0_S, 0, 0, 0, ARC_OPERAND_IR, insert_r0, extract_r0) +ARC_OPERAND(R1, 1, 0, 0, ARC_OPERAND_IR, insert_r1, extract_r1) +ARC_OPERAND(R1_S, 1, 0, 0, ARC_OPERAND_IR, insert_r1, extract_r1) +ARC_OPERAND(R2, 2, 0, 0, ARC_OPERAND_IR, insert_r2, extract_r2) +ARC_OPERAND(R2_S, 2, 0, 0, ARC_OPERAND_IR, insert_r2, extract_r2) +ARC_OPERAND(R3, 2, 0, 0, ARC_OPERAND_IR, insert_r3, extract_r3) +ARC_OPERAND(R3_S, 2, 0, 0, ARC_OPERAND_IR, insert_r3, extract_r3) +ARC_OPERAND(RSP, 5, 0, 0, ARC_OPERAND_IR, insert_sp, extract_sp) +ARC_OPERAND(SP_S, 5, 0, 0, ARC_OPERAND_IR, insert_sp, extract_sp) +ARC_OPERAND(SPdup, 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_sp, extract_sp) +ARC_OPERAND(SP_Sdup, 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_sp, extract_sp) +ARC_OPERAND(GP, 5, 0, 0, ARC_OPERAND_IR, insert_gp, extract_gp) +ARC_OPERAND(GP_S, 5, 0, 0, ARC_OPERAND_IR, insert_gp, extract_gp) + +ARC_OPERAND(PCL_S, 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_pcl, extract_pcl) + +ARC_OPERAND(BLINK, 5, 0, 0, ARC_OPERAND_IR, insert_blink, extract_blink) +ARC_OPERAND(BLINK_S, 5, 0, 0, ARC_OPERAND_IR, insert_blink, extract_blink) + +ARC_OPERAND(ILINK1, 5, 0, 0, ARC_OPERAND_IR, insert_ilink1, extract_ilink1) +ARC_OPERAND(ILINK2, 5, 0, 0, ARC_OPERAND_IR, insert_ilink2, extract_ilink2) + + /* Long immediate. */ +ARC_OPERAND(LIMM, 32, 0, BFD_RELOC_ARC_32_ME, ARC_OPERAND_LIMM, insert_limm, 0) +ARC_OPERAND(LIMM_S, 32, 0, BFD_RELOC_ARC_32_ME, ARC_OPERAND_LIMM, insert_limm, 0) +ARC_OPERAND(LO32, 32, 0, BFD_RELOC_ARC_LO32_ME, ARC_OPERAND_LIMM, insert_limm, 0) +ARC_OPERAND(HI32, 32, 0, BFD_RELOC_ARC_HI32_ME, ARC_OPERAND_LIMM, insert_limm, 0) +ARC_OPERAND(LIMM34, 34, 0, BFD_RELOC_ARC_PCLO32_ME_2, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_limm, 0) +ARC_OPERAND(XIMM_S, 32, 0, BFD_RELOC_ARC_LO32_ME, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED, insert_limm, 0) +ARC_OPERAND(XIMM, 32, 0, BFD_RELOC_ARC_LO32_ME, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED, insert_limm, 0) +ARC_OPERAND(LIMMdup, 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_DUPLICATE, insert_limm, 0) +ARC_OPERAND(XIMMdup, 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_DUPLICATE | ARC_OPERAND_SIGNED, insert_limm, 0) + + /* Special operands. */ +ARC_OPERAND(ZA, 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0) +ARC_OPERAND(ZB, 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0) +ARC_OPERAND(ZA_S, 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0) +ARC_OPERAND(ZB_S, 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0) +ARC_OPERAND(ZC_S, 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0) + +ARC_OPERAND(RRANGE_EL, 4, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK | ARC_OPERAND_TRUNCATE, insert_rrange, extract_rrange) +ARC_OPERAND(R13_EL, 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, insert_r13el, extract_rrange) +ARC_OPERAND(FP_EL, 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, insert_fpel, extract_fpel) +ARC_OPERAND(BLINK_EL, 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, insert_blinkel, extract_blinkel) +ARC_OPERAND(PCL_EL, 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, insert_pclel, extract_pclel) + + /* Fake operand to handle the T flag. */ +ARC_OPERAND(BRAKET, 0, 0, 0, ARC_OPERAND_FAKE | ARC_OPERAND_BRAKET, 0, 0) +ARC_OPERAND(BRAKETdup, 0, 0, 0, ARC_OPERAND_FAKE | ARC_OPERAND_BRAKET, 0, 0) + + /* Fake operand to handle the T flag. */ +ARC_OPERAND(FKT_T, 1, 3, 0, ARC_OPERAND_FAKE, insert_Ybit, 0) + /* Fake operand to handle the T flag. */ +ARC_OPERAND(FKT_NT, 1, 3, 0, ARC_OPERAND_FAKE, insert_NYbit, 0) + + /* UIMM6_20 mask = 00000000000000000000111111000000. */ +ARC_OPERAND(UIMM6_20, 6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_20, extract_uimm6_20) + + /* Exactly like the above but used by relaxation. */ +ARC_OPERAND(UIMM6_20R, 6, 0, -UIMM6_20R, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL, insert_uimm6_20, extract_uimm6_20) + + /* SIMM12_20 mask = 00000000000000000000111111222222. */ +ARC_OPERAND(SIMM12_20, 12, 0, 0, ARC_OPERAND_SIGNED, insert_simm12_20, extract_simm12_20) + + /* Exactly like the above but used by relaxation. */ +ARC_OPERAND(SIMM12_20R, 12, 0, -SIMM12_20R, ARC_OPERAND_SIGNED | ARC_OPERAND_PCREL, insert_simm12_20, extract_simm12_20) + + /* UIMM12_20 mask = 00000000000000000000111111222222. */ +ARC_OPERAND(UIMM12_20, 12, 0, 0, ARC_OPERAND_UNSIGNED, insert_simm12_20, extract_uimm12_20) + + /* SIMM3_5_S mask = 0000011100000000. */ +ARC_OPERAND(SIMM3_5_S, 3, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_NCHK, insert_simm3s, extract_simm3s) + + /* UIMM7_A32_11_S mask = 0000000000011111. */ +ARC_OPERAND(UIMM7_A32_11_S, 7, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm7_a32_11_s, extract_uimm7_a32_11_s) + + /* The same as above but used by relaxation. */ +ARC_OPERAND(UIMM7_A32_11R_S, 7, 0, -UIMM7_A32_11R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE | ARC_OPERAND_PCREL, insert_uimm7_a32_11_s, extract_uimm7_a32_11_s) + +ARC_OPERAND(UIMM9_A32_11_S, 9, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm9_a32_11_s, extract_uimm9_a32_11_s) + + /* UIMM7_9_S mask = 0000000001111111. */ +ARC_OPERAND(UIMM7_9_S, 7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_9_s, extract_uimm7_9_s) + + /* UIMM3_13_S mask = 0000000000000111. */ +ARC_OPERAND(UIMM3_13_S, 3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_13_s, extract_uimm3_13_s) + + /* Exactly like the above but used for relaxation. */ +ARC_OPERAND(UIMM3_13R_S, 3, 0, -UIMM3_13R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL, insert_uimm3_13_s, extract_uimm3_13_s) + + /* SIMM11_A32_7_S mask = 0000000111111111. */ +ARC_OPERAND(SIMM11_A32_7_S, 11, 0, BFD_RELOC_ARC_SDA16_LD2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_7_s, extract_simm11_a32_7_s) + + /* UIMM6_13_S mask = 0000000002220111. */ +ARC_OPERAND(UIMM6_13_S, 6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_13_s, extract_uimm6_13_s) + /* UIMM5_11_S mask = 0000000000011111. */ +ARC_OPERAND(UIMM5_11_S, 5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_IGNORE, insert_uimm5_11_s, extract_uimm5_11_s) + + /* SIMM9_A16_8 mask = 00000000111111102000000000000000. */ +ARC_OPERAND(SIMM9_A16_8, 9, 0, BFD_RELOC_ARC_S9H_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_PCREL | ARC_OPERAND_TRUNCATE, insert_simm9_a16_8, extract_simm9_a16_8) + + /* UIMM6_8 mask = 00000000000000000000111111000000. */ +ARC_OPERAND(UIMM6_8, 6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_8, extract_uimm6_8) + + /* SIMM21_A16_5 mask = 00000111111111102222222222000000. */ +ARC_OPERAND(SIMM21_A16_5, 21, 0, BFD_RELOC_ARC_S21H_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm21_a16_5, extract_simm21_a16_5) + + /* SIMM25_A16_5 mask = 00000111111111102222222222003333. */ +ARC_OPERAND(SIMM25_A16_5, 25, 0, BFD_RELOC_ARC_S25H_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm25_a16_5, extract_simm25_a16_5) + + /* SIMM10_A16_7_S mask = 0000000111111111. */ +ARC_OPERAND(SIMM10_A16_7_S, 10, 0, BFD_RELOC_ARC_S10H_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm10_a16_7_s, extract_simm10_a16_7_s) + +ARC_OPERAND(SIMM10_A16_7_Sbis, 10, 0, -SIMM10_A16_7_Sbis, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE, insert_simm10_a16_7_s, extract_simm10_a16_7_s) + + /* SIMM7_A16_10_S mask = 0000000000111111. */ +ARC_OPERAND(SIMM7_A16_10_S, 7, 0, BFD_RELOC_ARC_S7H_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm7_a16_10_s, extract_simm7_a16_10_s) + + /* SIMM21_A32_5 mask = 00000111111111002222222222000000. */ +ARC_OPERAND(SIMM21_A32_5, 21, 0, BFD_RELOC_ARC_S21W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm21_a32_5, extract_simm21_a32_5) + + /* SIMM25_A32_5 mask = 00000111111111002222222222003333. */ +ARC_OPERAND(SIMM25_A32_5, 25, 0, BFD_RELOC_ARC_S25W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm25_a32_5, extract_simm25_a32_5) + + /* SIMM13_A32_5_S mask = 0000011111111111. */ +ARC_OPERAND(SIMM13_A32_5_S, 13, 0, BFD_RELOC_ARC_S13_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a32_5_s, extract_simm13_a32_5_s) + + /* SIMM8_A16_9_S mask = 0000000001111111. */ +ARC_OPERAND(SIMM8_A16_9_S, 8, 0, BFD_RELOC_ARC_S8H_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm8_a16_9_s, extract_simm8_a16_9_s) + +/* UIMM10_6_S_JLIOFF mask = 0000001111111111. */ +ARC_OPERAND(UIMM10_6_S_JLIOFF, 12, 0, BFD_RELOC_ARC_JLI_SECTOFF, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE, insert_uimm10_6_s, extract_uimm10_6_s) + + /* UIMM3_23 mask = 00000000000000000000000111000000. */ +ARC_OPERAND(UIMM3_23, 3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_23, extract_uimm3_23) + + /* UIMM10_6_S mask = 0000001111111111. */ +ARC_OPERAND(UIMM10_6_S, 10, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm10_6_s, extract_uimm10_6_s) + +ARC_OPERAND(UIMM10_13_S, 10, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm10_13_s, extract_uimm10_13_s) + + /* UIMM6_11_S mask = 0000002200011110. */ +ARC_OPERAND(UIMM6_11_S, 6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_11_s, extract_uimm6_11_s) + + /* SIMM9_8 mask = 00000000111111112000000000000000. */ +ARC_OPERAND(SIMM9_8, 9, 0, BFD_RELOC_ARC_SDA_LDST, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE, insert_simm9_8, extract_simm9_8) + + /* The same as above but used by relaxation. */ +ARC_OPERAND(SIMM9_8R, 9, 0, -SIMM9_8R, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE | ARC_OPERAND_PCREL, insert_simm9_8, extract_simm9_8) + + /* UIMM10_A32_8_S mask = 0000000011111111. */ +ARC_OPERAND(UIMM10_A32_8_S, 10, 0, -UIMM10_A32_8_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm10_a32_8_s, extract_uimm10_a32_8_s) + + /* SIMM9_7_S mask = 0000000111111111. */ +ARC_OPERAND(SIMM9_7_S, 9, 0, BFD_RELOC_ARC_SDA16_LD, ARC_OPERAND_SIGNED, insert_simm9_7_s, extract_simm9_7_s) + + /* UIMM6_A16_11_S mask = 0000000000011111. */ +ARC_OPERAND(UIMM6_A16_11_S, 6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm6_a16_11_s, extract_uimm6_a16_11_s) + + /* UIMM5_A32_11_S mask = 0000020000011000. */ +ARC_OPERAND(UIMM5_A32_11_S, 5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm5_a32_11_s, extract_uimm5_a32_11_s) + + /* SIMM11_A32_13_S mask = 0000022222200111. */ +ARC_OPERAND(SIMM11_A32_13_S, 11, 0, BFD_RELOC_ARC_SDA16_ST2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_13_s, extract_simm11_a32_13_s) + + /* UIMM7_13_S mask = 0000000022220111. */ +ARC_OPERAND(UIMM7_13_S, 7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_13_s, extract_uimm7_13_s) + + /* UIMM6_A16_21 mask = 00000000000000000000011111000000. */ +ARC_OPERAND(UIMM6_A16_21, 6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE, insert_uimm6_a16_21, extract_uimm6_a16_21) + + /* UIMM7_11_S mask = 0000022200011110. */ +ARC_OPERAND(UIMM7_11_S, 7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_11_s, extract_uimm7_11_s) + + /* UIMM7_A16_20 mask = 00000000000000000000111111000000. */ +ARC_OPERAND(UIMM7_A16_20, 7, 0, -UIMM7_A16_20, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm7_a16_20, extract_uimm7_a16_20) + + /* SIMM13_A16_20 mask = 00000000000000000000111111222222. */ +ARC_OPERAND(SIMM13_A16_20, 13, 0, BFD_RELOC_ARC_S13H_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a16_20, extract_simm13_a16_20) + + /* UIMM8_8_S mask = 0000000011111111. */ +ARC_OPERAND(UIMM8_8_S, 8, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm8_8_s, extract_uimm8_8_s) + + /* The same as above but used for relaxation. */ +ARC_OPERAND(UIMM8_8R_S, 8, 0, -UIMM8_8R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL, insert_uimm8_8_s, extract_uimm8_8_s) + + /* W6 mask = 00000000000000000000111111000000. */ +ARC_OPERAND(W6, 6, 0, 0, ARC_OPERAND_SIGNED, insert_w6, extract_w6) + + /* UIMM6_5_S mask = 0000011111100000. */ +ARC_OPERAND(UIMM6_5_S, 6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_5_s, extract_uimm6_5_s) + + /* ARC NPS400 Support: See comment near head of file. */ +ARC_OPERAND(NPS_R_DST_3B, 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst) + +ARC_OPERAND(NPS_R_SRC1_3B, 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst) + +ARC_OPERAND(NPS_R_SRC2_3B, 3, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_21_src2, extract_nps_3bit_reg_at_21_src2) + +ARC_OPERAND(NPS_R_DST, 6, 21, 0, ARC_OPERAND_IR, NULL, NULL) + +ARC_OPERAND(NPS_R_SRC1, 6, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL) + +ARC_OPERAND(NPS_BITOP_DST_POS, 5, 5, 0, ARC_OPERAND_UNSIGNED, 0, 0) + +ARC_OPERAND(NPS_BITOP_SRC_POS, 5, 0, 0, ARC_OPERAND_UNSIGNED, 0, 0) + +ARC_OPERAND(NPS_BITOP_SIZE, 5, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop_size, extract_nps_bitop_size) + +ARC_OPERAND(NPS_BITOP_DST_POS_SZ, 5, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_dst_pos_and_size, extract_nps_dst_pos_and_size) + +ARC_OPERAND(NPS_BITOP_SIZE_2B, 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop_size_2b, extract_nps_bitop_size_2b) + +ARC_OPERAND(NPS_BITOP_UIMM8, 8, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_uimm8, extract_nps_bitop_uimm8) + +ARC_OPERAND(NPS_UIMM16, 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) + +ARC_OPERAND(NPS_SIMM16, 16, 0, 0, ARC_OPERAND_SIGNED, NULL, NULL) + +ARC_OPERAND(NPS_RFLT_UIMM6, 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_rflt_uimm6, extract_nps_rflt_uimm6) + +ARC_OPERAND(NPS_XLDST_UIMM16, 16, 0, BFD_RELOC_ARC_NPS_CMEM16, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_cmem_uimm16, extract_nps_cmem_uimm16) + +ARC_OPERAND(NPS_SRC2_POS, 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_src2_pos, extract_nps_src2_pos) + +ARC_OPERAND(NPS_SRC1_POS, 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_src1_pos, extract_nps_src1_pos) + +ARC_OPERAND(NPS_ADDB_SIZE, 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_addb_size, extract_nps_addb_size) + +ARC_OPERAND(NPS_ANDB_SIZE, 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_andb_size, extract_nps_andb_size) + +ARC_OPERAND(NPS_FXORB_SIZE, 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_fxorb_size, extract_nps_fxorb_size) + +ARC_OPERAND(NPS_WXORB_SIZE, 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_wxorb_size, extract_nps_wxorb_size) + +ARC_OPERAND(NPS_R_XLDST, 6, 5, 0, ARC_OPERAND_IR, NULL, NULL) + +ARC_OPERAND(NPS_DIV_UIMM4, 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) + +ARC_OPERAND(NPS_QCMP_SIZE, 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_qcmp_size, extract_nps_qcmp_size) + +ARC_OPERAND(NPS_QCMP_M1, 1, 14, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m1) + +ARC_OPERAND(NPS_QCMP_M2, 1, 15, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m2) + +ARC_OPERAND(NPS_QCMP_M3, 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m3) + +ARC_OPERAND(NPS_CALC_ENTRY_SIZE, 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_calc_entry_size, extract_nps_calc_entry_size) + +ARC_OPERAND(NPS_R_DST_3B_SHORT, 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_8_dst, extract_nps_3bit_reg_at_8_dst) + +ARC_OPERAND(NPS_R_SRC1_3B_SHORT, 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_8_dst, extract_nps_3bit_reg_at_8_dst) + +ARC_OPERAND(NPS_R_SRC2_3B_SHORT, 3, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_5_src2, extract_nps_3bit_reg_at_5_src2) + +ARC_OPERAND(NPS_BITOP_SIZE2, 5, 25, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop2_size, extract_nps_bitop2_size) + +ARC_OPERAND(NPS_BITOP_SIZE1, 5, 20, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop1_size, extract_nps_bitop1_size) + +ARC_OPERAND(NPS_BITOP_DST_POS3_POS4, 5, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_dst_pos3_pos4, extract_nps_bitop_dst_pos3_pos4) + +ARC_OPERAND(NPS_BITOP_DST_POS4, 5, 42, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) + +ARC_OPERAND(NPS_BITOP_DST_POS3, 5, 37, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) + +ARC_OPERAND(NPS_BITOP_DST_POS2, 5, 15, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) + +ARC_OPERAND(NPS_BITOP_DST_POS1, 5, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) + +ARC_OPERAND(NPS_BITOP_SRC_POS4, 5, 32, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) + +ARC_OPERAND(NPS_BITOP_SRC_POS3, 5, 20, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) + +ARC_OPERAND(NPS_BITOP_SRC_POS2, 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) + +ARC_OPERAND(NPS_BITOP_SRC_POS1, 5, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) + +ARC_OPERAND(NPS_BITOP_MOD4, 2, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_mod4, extract_nps_bitop_mod4) + +ARC_OPERAND(NPS_BITOP_MOD3, 2, 29, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) + +ARC_OPERAND(NPS_BITOP_MOD2, 2, 27, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) + +ARC_OPERAND(NPS_BITOP_MOD1, 2, 25, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) + +ARC_OPERAND(NPS_BITOP_INS_EXT, 5, 20, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_ins_ext, extract_nps_bitop_ins_ext) + +ARC_OPERAND(NPS_FIELD_START_POS, 3, 3, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) + +ARC_OPERAND(NPS_FIELD_SIZE, 3, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_field_size, extract_nps_field_size) + +ARC_OPERAND(NPS_SHIFT_FACTOR, 3, 9, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_shift_factor, extract_nps_shift_factor) + +ARC_OPERAND(NPS_BITS_TO_SCRAMBLE, 3, 12, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bits_to_scramble, extract_nps_bits_to_scramble) + +ARC_OPERAND(NPS_SRC2_POS_5B, 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) + +ARC_OPERAND(NPS_BDLEN_MAX_LEN, 8, 5, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bdlen_max_len, extract_nps_bdlen_max_len) + +ARC_OPERAND(NPS_MIN_HOFS, 4, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_min_hofs, extract_nps_min_hofs) + +ARC_OPERAND(NPS_PSBC, 1, 11, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) + +ARC_OPERAND(NPS_DPI_DST, 5, 11, 0, ARC_OPERAND_IR, NULL, NULL) + + /* NPS_DPI_SRC1_3B is similar to NPS_R_SRC1_3B + but doesn't duplicate an operand. */ +ARC_OPERAND(NPS_DPI_SRC1_3B, 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst) + +ARC_OPERAND(NPS_HASH_WIDTH, 5, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_hash_width, extract_nps_hash_width) + +ARC_OPERAND(NPS_HASH_PERM, 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) + +ARC_OPERAND(NPS_HASH_NONLINEAR, 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) + +ARC_OPERAND(NPS_HASH_BASEMAT, 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) + +ARC_OPERAND(NPS_HASH_LEN, 3, 2, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_hash_len, extract_nps_hash_len) + +ARC_OPERAND(NPS_HASH_OFS, 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) + +ARC_OPERAND(NPS_HASH_BASEMAT2, 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) + +ARC_OPERAND(NPS_E4BY_INDEX0, 3, 8, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) + +ARC_OPERAND(NPS_E4BY_INDEX1, 3, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) + +ARC_OPERAND(NPS_E4BY_INDEX2, 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) + +ARC_OPERAND(NPS_E4BY_INDEX3, 2, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_index3, extract_nps_index3) + +ARC_OPERAND(COLON, 0, 0, 0, ARC_OPERAND_COLON | ARC_OPERAND_FAKE, NULL, NULL) + +ARC_OPERAND(NPS_BD, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_bd, extract_nps_bd) + +ARC_OPERAND(NPS_JID, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_jid, extract_nps_jid) + +ARC_OPERAND(NPS_LBD, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_lbd, extract_nps_lbd) + +ARC_OPERAND(NPS_MBD, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_mbd, extract_nps_mbd) + +ARC_OPERAND(NPS_SD, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_sd, extract_nps_sd) + +ARC_OPERAND(NPS_SM, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_sm, extract_nps_sm) + +ARC_OPERAND(NPS_XA, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_xa, extract_nps_xa) + +ARC_OPERAND(NPS_XD, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_xd, extract_nps_xd) + +ARC_OPERAND(NPS_CD, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cd, extract_nps_cd) + +ARC_OPERAND(NPS_CBD, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cbd, extract_nps_cbd) + +ARC_OPERAND(NPS_CJID, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cjid, extract_nps_cjid) + +ARC_OPERAND(NPS_CLBD, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_clbd, extract_nps_clbd) + +ARC_OPERAND(NPS_CM, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cm, extract_nps_cm) + +ARC_OPERAND(NPS_CSD, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_csd, extract_nps_csd) + +ARC_OPERAND(NPS_CXA, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cxa, extract_nps_cxa) + +ARC_OPERAND(NPS_CXD, 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cxd, extract_nps_cxd) + +ARC_OPERAND(NPS_BD_TYPE, 1, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) + +ARC_OPERAND(NPS_BMU_NUM, 3, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bd_num_buff, extract_nps_bd_num_buff) + +ARC_OPERAND(NPS_PMU_NXT_DST, 4, 6, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) + +ARC_OPERAND(NPS_WHASH_SIZE, 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_size_16bit, extract_nps_size_16bit) + +ARC_OPERAND(NPS_PMU_NUM_JOB, 2, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_pmu_num_job, extract_nps_pmu_num_job) + +ARC_OPERAND(NPS_DMA_IMM_ENTRY, 3, 2, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_imm_entry, extract_nps_imm_entry) + +ARC_OPERAND(NPS_DMA_IMM_OFFSET, 4, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_imm_offset, extract_nps_imm_offset) + +ARC_OPERAND(NPS_MISC_IMM_SIZE, 7, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) + +ARC_OPERAND(NPS_MISC_IMM_OFFSET, 5, 8, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_misc_imm_offset, extract_nps_misc_imm_offset) + +ARC_OPERAND(NPS_R_DST_3B_48, 3, 40, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_40_dst, extract_nps_3bit_reg_at_40_dst) + +ARC_OPERAND(NPS_R_SRC1_3B_48, 3, 40, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_40_dst, extract_nps_3bit_reg_at_40_dst) + +ARC_OPERAND(NPS_R_SRC2_3B_48, 3, 37, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_37_src2, extract_nps_3bit_reg_at_37_src2) + +ARC_OPERAND(NPS_R_DST_3B_64, 3, 56, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_56_dst, extract_nps_3bit_reg_at_56_dst) + +ARC_OPERAND(NPS_R_SRC1_3B_64, 3, 56, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_56_dst, extract_nps_3bit_reg_at_56_dst) + +ARC_OPERAND(NPS_R_SRC2_3B_64, 3, 53, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_reg_at_53_src2, extract_nps_3bit_reg_at_53_src2) + +ARC_OPERAND(NPS_RA_64, 6, 53, 0, ARC_OPERAND_IR, NULL, NULL) + +ARC_OPERAND(NPS_RB_64, 5, 48, 0, ARC_OPERAND_IR, NULL, NULL) + +ARC_OPERAND(NPS_RBdup_64, 5, 43, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL) + +ARC_OPERAND(NPS_RBdouble_64, 10, 43, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_rbdouble_64, extract_nps_rbdouble_64) + +ARC_OPERAND(NPS_RC_64, 5, 43, 0, ARC_OPERAND_IR, NULL, NULL) + +ARC_OPERAND(NPS_UIMM16_0_64, 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL) + +ARC_OPERAND(NPS_PROTO_SIZE, 6, 16, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_proto_size, extract_nps_proto_size) + + /* ARC64's floating point registers. */ +ARC_OPERAND(FA, 5, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_FP, 0, 0) +ARC_OPERAND(FB, 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_FP, 0, 0) +ARC_OPERAND(FC, 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_FP, insert_fs2, extract_fs2) +ARC_OPERAND(FD, 5, 19, 0, ARC_OPERAND_IR | ARC_OPERAND_FP, 0, 0) + + /* Double 128 registers, the same like above but only the odd ones + allowed. */ +ARC_OPERAND(FDA, 5, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_FP | ARC_OPERAND_TRUNCATE, 0, 0) +ARC_OPERAND(FDB, 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_FP | ARC_OPERAND_TRUNCATE, 0, 0) +ARC_OPERAND(FDC, 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_FP | ARC_OPERAND_TRUNCATE, insert_fs2, extract_fs2) +ARC_OPERAND(FDD, 5, 19, 0, ARC_OPERAND_IR | ARC_OPERAND_FP | ARC_OPERAND_TRUNCATE, 0, 0) + + /* 5bit integer registers used by fp instructions. */ +ARC_OPERAND(FRD, 5, 6, 0, ARC_OPERAND_IR, 0, 0) +ARC_OPERAND(FRB, 5, 0, 0, ARC_OPERAND_IR, insert_fs2, extract_fs2) + + /* 5bit unsigned immediate used by vfext and vfins. */ +ARC_OPERAND(UIMM5_FP, 5, 0, 0, ARC_OPERAND_UNSIGNED, insert_fs2, extract_fs2) diff --git a/opcodes/arc-regs.h b/opcodes/arc-regs.h index 2699ce8f02e..9864f16d206 100644 --- a/opcodes/arc-regs.h +++ b/opcodes/arc-regs.h @@ -208,7 +208,7 @@ DEF (0xad, ARC_OPCODE_ARCALL, NONE, se_watch) DEF (0xc0, ARC_OPCODE_ARCALL, NONE, bpu_build) DEF (0xc1, ARC_OPCODE_ARC600, NONE, arc600_build_config) DEF (0xc1, ARC_OPCODE_ARC700, NONE, isa_config) -DEF (0xc1, ARC_OPCODE_ARCV2, NONE, isa_config) +DEF (0xc1, ARC_OPCODE_ARCVx, NONE, isa_config) DEF (0xf4, ARC_OPCODE_ARCALL, NONE, hwp_build) DEF (0xf5, ARC_OPCODE_ARCALL, NONE, pct_build) DEF (0xf6, ARC_OPCODE_ARCALL, NONE, cc_build) @@ -346,11 +346,17 @@ DEF (0x451, ARC_OPCODE_ARC600, NONE, wake) DEF (0x452, ARC_OPCODE_ARC600, NONE, dvfs_performance) DEF (0x453, ARC_OPCODE_ARC600, NONE, pwr_ctrl) DEF (0x460, ARC_OPCODE_ARCv2HS, NONE, tlbpd0) +DEF (0x460, ARC_OPCODE_ARC64, NONE, mmu_rtp0_lo) DEF (0x461, ARC_OPCODE_ARCv2HS, NONE, tlbpd1) +DEF (0x461, ARC_OPCODE_ARC64, NONE, mmu_rtp0_hi) +DEF (0x462, ARC_OPCODE_ARC64, NONE, mmu_rtp1_lo) +DEF (0x463, ARC_OPCODE_ARC64, NONE, mmu_rtp1_hi) DEF (0x464, ARC_OPCODE_ARCv2HS, NONE, tlbindex) DEF (0x465, ARC_OPCODE_ARCv2HS, NONE, tlbcommand) DEF (0x468, ARC_OPCODE_ARCv2HS, NONE, pid) DEF (0x46c, ARC_OPCODE_ARCv2HS, NONE, scratch_data0) +DEF (0x468, ARC_OPCODE_ARC64, NONE, mmu_ctrl) +DEF (0x469, ARC_OPCODE_ARC64, NONE, mmu_ttbc) DEF (0x500, ARC_OPCODE_ARC700, NONE, aux_vlc_buf_idx) DEF (0x501, ARC_OPCODE_ARC700, NONE, aux_vlc_read_buf) DEF (0x502, ARC_OPCODE_ARC700, NONE, aux_vlc_valid_bits) diff --git a/opcodes/arc64-opc.c b/opcodes/arc64-opc.c new file mode 100644 index 00000000000..f1e79376c44 --- /dev/null +++ b/opcodes/arc64-opc.c @@ -0,0 +1,834 @@ +/* Opcode table for ARC64. + Copyright (C) 2023 Free Software Foundation, Inc. + + Contributed by Claudiu Zissulescu (claziss@synopsys.com) + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#include "arcxx-opc.inc" + +#define F32_BR0 0x00 +#define F32_BR1 0x01 +#define F32_LD_OFFSET 0x02 +#define F32_ST_OFFSET 0x03 +#define F32_GEN4 0x04 +#define F32_EXT5 0x05 +#define F32_EXT6 0x06 +#define F32_APEX 0x07 + +#define F16_COMPACT0 0x08 +#define F16_COMPACT1 0x08 +#define F16_MOVL 0x08 + +#define F16_LD_ADD_SUB 0x09 + +#define LD_ST_R01 0x0A +#define LDI_S 0x0A +#define JLI_S_U10 0x0A + +#define F16_JLI_EI 0x0B +#define F32_GEN_OP64 0x0B + +/* Macros required for ARCv3 floating point instructions. */ +/* Flags. */ +#define FL_NONE { 0 } +#define FL_CC { C_FPCC } + +/* Arguments. */ +#define ARG_NONE { 0 } +#define ARG_64FP_3OP { FA, FB, FC, FD } +#define ARG_128FP_3OP { FDA, FDB, FDC, FDD } +#define ARG_64FP_2OP { FA, FB, FC } +#define ARG_64FP_CMP { FB, FC } +#define ARG_128FP_2OP { FDA, FDB, FDC } +#define ARG_64FP_1OP { FA, FC } +#define ARG_64FP_SOP { FA, FB } +#define ARG_128FP_SOP { FDA, FDB } + +#define ARG_64FP_CVI2F { FA, FRB } +#define ARG_64FP_CVF2I { FRD, FC } + +/* Macros to help generating floating point pattern instructions. */ +/* Define FP_TOP. */ +#define FIELDS1(word) (word & 0x1F) +#define FIELDS2(word) (((word & 0x07) << 24) | (((word >> 3) & 0x03) << 12)) +#define FIELDS3(word) ((word & 0x1F) << 19) +#define FIELDD(word) ((word & 0x1F) << 6) +#define FIELDTOP(word) (((word & 0x01) << 5) | ((word >> 1) & 0x07) << 16) +#define FIELDP(word) ((word & 0x03) << 14) +#define MASK_32BIT(VAL) (0xffffffff & (VAL)) + +#define INSNFP3OP(TOPF, P) \ + ((0x1C << 27) | FIELDTOP (TOPF) | FIELDP (P) | (1 << 11)) +#define MINSNFP3OP \ + (MASK_32BIT (~(FIELDS1 (31) | FIELDS2 (31) | FIELDS3 (31) | FIELDD (31)))) + +/* Define FP_DOP. */ +#define FIELDDOP(ops) ((ops & 0x1f) << 16) + +#define INSNFP2OP(DOPF, P) \ + ((0x1C << 27) | FIELDDOP (DOPF) | FIELDP (P) | (1 << 5)) +#define MINSNFP2OP \ + (MASK_32BIT (~(FIELDS2 (31) | FIELDS1 (31) | FIELDD (31)))) + +/* Define FP_CVF2F. */ +#define FIELDCVTF(WORD) ((WORD & 0x03) << 16) +#define FIELDU0(BIT) (BIT & 0x01) +#define FIELDU1(BIT) (BIT & 0x02) +#define FIELDU3(BIT) (BIT & 0x08) +#define FIELDU4(BIT) (BIT & 0x10) + +#define FP_CVF2F_MACHINE(CVTF, BIT) \ + ((0x1C << 27) | (0x03 << 21) | FIELDCVTF (CVTF) \ + | (1 << 5) | (1 << 2) | FIELDU0 (BIT) | FIELDU3 (BIT) | FIELDU4 (BIT)) +#define MFP_CVF2F (MASK_32BIT (~(FIELDS2 (31) | FIELDD (31)))) + +/* Define FP_RND. */ +#define FP_RND_MACHINE(CVTF, BIT) \ +((0x1C << 27) | (0x03 << 21) | FIELDCVTF (CVTF) | (1 << 5) | (0x03 << 1) \ + | FIELDU3 (BIT)) +#define MFP_RND (MASK_32BIT (~(FIELDS2 (31) | FIELDD (31)))) + +/* Define FP_CVF2I. */ +#define FP_CVF2I_MACHINE(CVTF, BIT) ((0x1C << 27) | (0x03 << 21) \ + | FIELDCVTF (CVTF) | (1 << 5) | 1 \ + | FIELDU3 (BIT) | FIELDU1 (BIT)) +#define MFP_CVF2I (MASK_32BIT (~(FIELDS2 (31) | FIELDD (31)))) + +/* Define FMVVF2I. */ +#define FM_VVF2I(CVTF, BIT) ((0x1C << 27) | (0x03 << 21) | FIELDCVTF (CVTF) \ + | (1 << 5) | 1 << 4 | 1) +#define MFM_VVF2I (MASK_32BIT (~(FIELDS2 (31) | FIELDD (31)))) + +/* Define FP_SOP. */ +#define FP_SOP_MACHINE(SOPF, P) \ + ((0x1C << 27) | (0x02 << 21) | FIELDCVTF (SOPF) | FIELDP (P) | (1 << 5)) +#define MFP_SOP_MACHINE (MASK_32BIT (~(FIELDS1 (31) | FIELDD (31)))) + +/* Define FP_COP. */ +#define FP_COP_MACHINE(COPF, P) \ + ((0x1C << 27) | (0x09 << 19) | FIELDCVTF (COPF) | FIELDP (P) | (1 << 5)) +#define MFP_COP_MACHINE \ + (MASK_32BIT (~(FIELDS1 (31) | FIELDD (31) | FIELDS2(31)))) + +/* Define FP_ZOP. */ +#define INSNFPZOP(COPF) \ + ((0x1C << 27) | (0x07 << 20) | FIELDCVTF (COPF) | (1 << 5)) + +/* Define FP_VMVI. */ +#define INSNFPVMVI(WMVF, P) \ + ((0x1C << 27) | (0x05 << 20) | FIELDCVTF (WMVF) | FIELDP (P) | (1 << 5)) +#define MINSNFPCOP (MASK_32BIT (~(FIELDS1 (31) | FIELDD (31) | FIELDS2 (31)))) +#define MINSNFPVMVIZ (MASK_32BIT (~(FIELDS1 (31) | FIELDD (31)))) + +/* Define FP_VMVR. */ +#define INSNFPVMVR(WMVF, P) \ + ((0x1C << 27) | (0x01 << 23) | FIELDCVTF (WMVF) | FIELDP (P) | (1 << 5)) +#define MINSNFPVMVR (MASK_32BIT (~(FIELDS1 (31) | FIELDD (31) | FIELDS2 (31)))) + +/* Define FP_CVI2F. */ +#define INSNFPCVI2F(CVTF, BIT) ((0x1C << 27) | (0x07 << 21) | FIELDCVTF (CVTF) \ + | (1 << 5) | FIELDU3 (BIT) | FIELDU1 (BIT)) +#define MINSNFPCVI2F (MASK_32BIT (~(FIELDS2 (31) | FIELDD (31)))) + +/* Define FMVI2F. */ +#define INSNFMVI2F(CVTF, BIT) ((0x1C << 27) | (0x07 << 21) | FIELDCVTF (CVTF) \ + | (1 << 5) | (1 << 4)) +#define MINSNFMVI2F (MASK_32BIT (~(FIELDS2 (31) | FIELDD (31)))) + +/* Define FMVF2I. */ +#define INSNFMVF2I(CVTF, BIT) ((0x1C << 27) | (0x03 << 21) | FIELDCVTF (CVTF) \ + | (1 << 5) | (1 << 4) | (1)) +#define MINSNFMVF2I (MASK_32BIT (~(FIELDS2 (31) | FIELDD (31)))) + +/* Define FP_LOAD. */ +#define FP_LOAD_ENCODING(SIZE, D) (0x0D << 27 | ((SIZE & 0x03) << 1) \ + | ((D & 0x01) << 5)) +#define MSK_FP_LOAD (MASK_32BIT (~(FIELDB (63) | FIELDD (31) | (0x03 << 3) \ + | (0x1FF << 15)))) + +#define FP_LSYM_ENCODING(SIZE, D) (0x0D << 27 | ((SIZE & 0x03) << 1) \ + | FIELDB(62) | ((D & 0x01) << 5)) +#define MSK_FP_SYM (MASK_32BIT (~(FIELDD (31)))) + +/* Define FP_STORE. */ +#define FP_STORE_ENCODING(SIZE, D) ((0x0D << 27) | ((SIZE & 0x03) << 1) \ + | ((D & 0x01) << 5) | (1)) +#define MSK_FP_STORE (MASK_32BIT (~(FIELDB (63) | FIELDD (31) | (0x03 << 3) \ + | (0x1FF << 15)))) +#define FP_SSYM_ENCODING(SIZE, D) (0x0D << 27 | ((SIZE & 0x03) << 1) \ + | FIELDB(62) | ((D & 0x01) << 5) | (1)) + +/* FP Load/Store. */ +#define FP_LOAD(NAME, SIZE, D) \ + { #NAME, FP_LOAD_ENCODING (SIZE, D), MSK_FP_LOAD, ARC_OPCODE_ARC64, LOAD, \ + NONE, { FA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 } }, \ + { #NAME, FP_LSYM_ENCODING (SIZE, D), MSK_FP_SYM, ARC_OPCODE_ARC64, LOAD, \ + NONE, { FA, BRAKET, LIMM, BRAKETdup }, FL_NONE }, + +#define FP_STORE(NAME, SIZE, D) \ + { #NAME, FP_STORE_ENCODING (SIZE, D), MSK_FP_STORE, ARC_OPCODE_ARC64, STORE, \ + NONE, { FA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 } }, \ + { #NAME, FP_SSYM_ENCODING (SIZE, D), MSK_FP_SYM, ARC_OPCODE_ARC64, LOAD, \ + NONE, { FA, BRAKET, LIMM, BRAKETdup }, FL_NONE }, + +/* Macros used to generate conversion instructions. */ +#define FMVF2I_INSN(NAME, CPU, CLASS, SCLASS, OPS, BIT, ARG) \ + { NAME, INSNFMVF2I (OPS, BIT), MINSNFMVF2I, CPU, CLASS, \ + SCLASS, ARG, FL_NONE }, + +#define FMVF2I(NAME, OPS, BIT) \ + FMVF2I_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, OPS, \ + BIT, ARG_64FP_CVF2I) + +#define FMVI2F_INSN(NAME, CPU, CLASS, SCLASS, OPS, BIT, ARG) \ + { NAME, INSNFMVI2F (OPS, BIT), MINSNFMVI2F, CPU, CLASS, \ + SCLASS, ARG, FL_NONE }, + +#define FMVI2F(NAME, OPS, BIT) \ + FMVI2F_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, OPS, \ + BIT, ARG_64FP_CVI2F) + +#define FP_RND_INSN(NAME, CPU, CLASS, SCLASS, OPS, BIT, ARG) \ + { NAME, FP_RND_MACHINE (OPS, BIT), MFP_RND, CPU, CLASS, \ + SCLASS, ARG, FL_NONE }, + +#define FP_RND(NAME, OPS, BIT) \ + FP_RND_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, OPS, \ + BIT, ARG_64FP_1OP) + +#define FP_CVF2F_INSN(NAME, CPU, CLASS, SCLASS, OPS, BIT, ARG) \ + { NAME, FP_CVF2F_MACHINE (OPS, BIT), MFP_CVF2F, CPU, CLASS, \ + SCLASS, ARG, FL_NONE }, + +#define FP_CVF2F(NAME, OPS, BIT) \ + FP_CVF2F_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, OPS, \ + BIT, ARG_64FP_1OP) + +#define FP_CVF2I_INSN(NAME, CPU, CLASS, SCLASS, OPS, BIT, ARG) \ + { NAME, FP_CVF2I_MACHINE (OPS, BIT), MFP_CVF2I, CPU, CLASS, \ + SCLASS, ARG, FL_NONE }, + +#define FP_CVF2I(NAME, OPS, BIT) \ + FP_CVF2I_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, OPS, \ + BIT, ARG_64FP_CVF2I) + +#define FP_CVI2F_INSN(NAME, CPU, CLASS, SCLASS, OPS, BIT, ARG) \ + { NAME, INSNFPCVI2F (OPS, BIT), MINSNFPCVI2F, CPU, CLASS, \ + SCLASS, ARG, FL_NONE }, + +#define FP_CVI2F(NAME, OPS, BIT) \ + FP_CVI2F_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, OPS, \ + BIT, ARG_64FP_CVI2F) + +/* Macro to generate 1 operand extension instruction. */ +#define FP_SOP_INSN(NAME, CPU, CLASS, SCLASS, OPS, PRC, ARG) \ + { NAME, FP_SOP_MACHINE (OPS, PRC), MFP_SOP_MACHINE, CPU, CLASS, SCLASS, \ + ARG, FL_NONE }, + +#define FP_SOP(NAME, OPS, PRECISION) \ + FP_SOP_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, SOPF_ ## OPS, \ + P_ ## PRECISION, ARG_64FP_SOP) + +#define FP_SOP_D(NAME, OPS, PRECISION) \ + FP_SOP_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, SOPF_ ## OPS, \ + P_ ## PRECISION, ARG_128FP_SOP) + +/* Macro to generate 2 operand extension instruction. */ +#define FP_DOP_INSN(NAME, CPU, CLASS, SCLASS, OPS, PRC, ARG) \ + { NAME, INSNFP2OP (OPS, PRC), MINSNFP2OP, CPU, CLASS, SCLASS, \ + ARG, FL_NONE }, + +#define FP_DOP(NAME, OPS, PRECISION) \ + FP_DOP_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, DOPF_ ## OPS, \ + P_ ## PRECISION, ARG_64FP_2OP) + +#define FP_DOPC_INSN(NAME, CPU, CLASS, SCLASS, OPS, PRC, ARG) \ + { NAME, INSNFP2OP (OPS, PRC) | FIELDD (0), MINSNFP2OP, CPU, \ + CLASS, SCLASS, ARG, FL_NONE }, + +#define FP_DOP_C(NAME, OPS, PRECISION) \ + FP_DOPC_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, DOPF_ ## OPS, \ + P_ ## PRECISION, ARG_64FP_CMP) + +#define FP_DOP_D(NAME, OPS, PRECISION) \ + FP_DOP_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, DOPF_ ## OPS, \ + P_ ## PRECISION, ARG_128FP_2OP) + +/* Macro to generate 3 operand generic instruction. */ +#define FP_TOP_INSN(NAME, CPU, CLASS, SCLASS, TOPF, P, ARG) \ + { NAME, INSNFP3OP (TOPF, P), MINSNFP3OP, CPU, CLASS, SCLASS, \ + ARG, FL_NONE }, + +#define FP_TOP(NAME, OPS, PRECISION) \ + FP_TOP_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, TOPF_ ## OPS, \ + P_ ## PRECISION, ARG_64FP_3OP) + +#define FP_TOP_D(NAME, OPS, PRECISION) \ + FP_TOP_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, TOPF_ ## OPS, \ + P_ ## PRECISION, ARG_128FP_3OP) + +/* Conditional mov instructions. */ +#define FP_COP_INSN(NAME, CPU, CLASS, SCLASS, OPS, PRC, ARG) \ + { NAME, FP_COP_MACHINE (OPS, PRC), MFP_COP_MACHINE, CPU, CLASS, SCLASS, \ + ARG, FL_CC }, + +#define FP_COP(NAME, OPS, PRECISION) \ + FP_COP_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, COPF_ ## OPS, \ + P_ ## PRECISION, ARG_64FP_SOP) + +#define FP_EXT(NAME, PRECISION) \ + {#NAME, INSNFPVMVI (0x00, P_ ## PRECISION), MINSNFPCOP, \ + ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, BRAKET, UIMM5_FP, \ + BRAKETdup }, FL_NONE }, \ + {#NAME, INSNFPVMVR (0x00, P_ ## PRECISION), MINSNFPVMVR, \ + ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, BRAKET, FRB, BRAKETdup}, \ + FL_NONE }, + +#define FP_INS(NAME, PRECISION) \ + {#NAME, INSNFPVMVI (0x01, P_ ## PRECISION), MINSNFPCOP, \ + ARC_OPCODE_ARC64, FLOAT, NONE, { FA, BRAKET, UIMM5_FP, BRAKETdup, \ + FB }, FL_NONE }, \ + {#NAME, INSNFPVMVR (0x01, P_ ## PRECISION), MINSNFPVMVR, \ + ARC_OPCODE_ARC64, FLOAT, NONE, { FA, BRAKET, FRB, BRAKETdup, \ + FB }, FL_NONE }, + +#define FP_REP(NAME, PRECISION) \ + {#NAME, INSNFPVMVI (0x02, P_ ## PRECISION) | FIELDS2 (0x00), \ + MINSNFPVMVIZ, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB }, FL_NONE }, + + +/* Common combinations of FLAGS. */ +#define FLAGS_NONE { 0 } +#define FLAGS_F { C_F } +#define FLAGS_CC { C_CC } +#define FLAGS_CCF { C_CC, C_F } + +/* Common combination of arguments. */ +#define ARG_NONE { 0 } +#define ARG_32BIT_RARBRC { RA, RB, RC } +#define ARG_32BIT_ZARBRC { ZA, RB, RC } +#define ARG_32BIT_RBRBRC { RB, RBdup, RC } +#define ARG_32BIT_RARBU6 { RA, RB, UIMM6_20 } +#define ARG_32BIT_ZARBU6 { ZA, RB, UIMM6_20 } +#define ARG_32BIT_RBRBU6 { RB, RBdup, UIMM6_20 } +#define ARG_32BIT_RBRBS12 { RB, RBdup, SIMM12_20 } +#define ARG_32BIT_RALIMMRC { RA, LIMM, RC } +#define ARG_32BIT_RARBLIMM { RA, RB, LIMM } +#define ARG_32BIT_ZALIMMRC { ZA, LIMM, RC } +#define ARG_32BIT_ZARBLIMM { ZA, RB, LIMM } + +#define ARG_32BIT_RBRBLIMM { RB, RBdup, LIMM } +#define ARG_32BIT_RALIMMU6 { RA, LIMM, UIMM6_20 } +#define ARG_32BIT_ZALIMMU6 { ZA, LIMM, UIMM6_20 } + +#define ARG_32BIT_ZALIMMS12 { ZA, LIMM, SIMM12_20 } +#define ARG_32BIT_RALIMMLIMM { RA, LIMM, LIMMdup } +#define ARG_32BIT_ZALIMMLIMM { ZA, LIMM, LIMMdup } + +#define ARG_32BIT_RBRC { RB, RC } +#define ARG_32BIT_ZARC { ZA, RC } +#define ARG_32BIT_RBU6 { RB, UIMM6_20 } +#define ARG_32BIT_ZAU6 { ZA, UIMM6_20 } +#define ARG_32BIT_RBLIMM { RB, LIMM } +#define ARG_32BIT_ZALIMM { ZA, LIMM } + +#define ARG_32BIT_RAXIMMRC { RA, XIMM, RC } +#define ARG_32BIT_RARBXIMM { RA, RB, XIMM } +#define ARG_32BIT_RBRBXIMM { RB, RBdup, XIMM } +#define ARG_32BIT_RAXIMMU6 { RA, XIMM, UIMM6_20 } + +/* Macro to generate 2 operand extension instruction. */ +#define EXTINSN2OPF(NAME, CPU, CLASS, SCLASS, MOP, SOP, FL) \ + { NAME, INSN2OP_BC (MOP,SOP), MINSN2OP_BC, CPU, CLASS, SCLASS, \ + ARG_32BIT_RBRC, FL }, \ + { NAME, INSN2OP_0C (MOP,SOP), MINSN2OP_0C, CPU, CLASS, SCLASS, \ + ARG_32BIT_ZARC, FL }, \ + { NAME, INSN2OP_BU (MOP,SOP), MINSN2OP_BU, CPU, CLASS, SCLASS, \ + ARG_32BIT_RBU6, FL }, \ + { NAME, INSN2OP_0U (MOP,SOP), MINSN2OP_0U, CPU, CLASS, SCLASS, \ + ARG_32BIT_ZAU6, FL }, \ + { NAME, INSN2OP_BL (MOP,SOP), MINSN2OP_BL, CPU, CLASS, SCLASS, \ + ARG_32BIT_RBLIMM, FL }, \ + { NAME, INSN2OP_0L (MOP,SOP), MINSN2OP_0L, CPU, CLASS, SCLASS, \ + ARG_32BIT_ZALIMM, FL }, + +#define EXTINSN2OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \ + EXTINSN2OPF(NAME, CPU, CLASS, SCLASS, MOP, SOP, FLAGS_F) + +/* Macro to generate 3 operand extesion instruction. */ +#define EXTINSN3OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \ + { NAME, INSN3OP_ABC (MOP,SOP), MINSN3OP_ABC, CPU, CLASS, SCLASS, \ + ARG_32BIT_RARBRC, FLAGS_F }, \ + { NAME, INSN3OP_0BC (MOP,SOP), MINSN3OP_0BC, CPU, CLASS, SCLASS, \ + ARG_32BIT_ZARBRC, FLAGS_F }, \ + { NAME, INSN3OP_CBBC (MOP,SOP), MINSN3OP_CBBC, CPU, CLASS, SCLASS, \ + ARG_32BIT_RBRBRC, FLAGS_CCF }, \ + { NAME, INSN3OP_ABU (MOP,SOP), MINSN3OP_ABU, CPU, CLASS, SCLASS, \ + ARG_32BIT_RARBU6, FLAGS_F }, \ + { NAME, INSN3OP_0BU (MOP,SOP), MINSN3OP_0BU, CPU, CLASS, SCLASS, \ + ARG_32BIT_ZARBU6, FLAGS_F }, \ + { NAME, INSN3OP_CBBU (MOP,SOP), MINSN3OP_CBBU, CPU, CLASS, SCLASS, \ + ARG_32BIT_RBRBU6, FLAGS_CCF }, \ + { NAME, INSN3OP_BBS (MOP,SOP), MINSN3OP_BBS, CPU, CLASS, SCLASS, \ + ARG_32BIT_RBRBS12, FLAGS_F }, \ + { NAME, INSN3OP_ALC (MOP,SOP), MINSN3OP_ALC, CPU, CLASS, SCLASS, \ + ARG_32BIT_RALIMMRC, FLAGS_F }, \ + { NAME, INSN3OP_ABL (MOP,SOP), MINSN3OP_ABL, CPU, CLASS, SCLASS, \ + ARG_32BIT_RARBLIMM, FLAGS_F }, \ + { NAME, INSN3OP_0LC (MOP,SOP), MINSN3OP_0LC, CPU, CLASS, SCLASS, \ + ARG_32BIT_ZALIMMRC, FLAGS_F }, \ + { NAME, INSN3OP_0BL (MOP,SOP), MINSN3OP_0BL, CPU, CLASS, SCLASS, \ + ARG_32BIT_ZARBLIMM, FLAGS_F }, \ + { NAME, INSN3OP_C0LC (MOP,SOP), MINSN3OP_C0LC, CPU, CLASS, SCLASS, \ + ARG_32BIT_ZALIMMRC, FLAGS_CCF }, \ + { NAME, INSN3OP_CBBL (MOP,SOP), MINSN3OP_CBBL, CPU, CLASS, SCLASS, \ + ARG_32BIT_RBRBLIMM, FLAGS_CCF }, \ + { NAME, INSN3OP_ALU (MOP,SOP), MINSN3OP_ALU, CPU, CLASS, SCLASS, \ + ARG_32BIT_RALIMMU6, FLAGS_F }, \ + { NAME, INSN3OP_0LU (MOP,SOP), MINSN3OP_0LU, CPU, CLASS, SCLASS, \ + ARG_32BIT_ZALIMMU6, FLAGS_F }, \ + { NAME, INSN3OP_C0LU (MOP,SOP), MINSN3OP_C0LU, CPU, CLASS, SCLASS, \ + ARG_32BIT_ZALIMMU6, FLAGS_CCF }, \ + { NAME, INSN3OP_0LS (MOP,SOP), MINSN3OP_0LS, CPU, CLASS, SCLASS, \ + ARG_32BIT_ZALIMMS12, FLAGS_F }, \ + { NAME, INSN3OP_ALL (MOP,SOP), MINSN3OP_ALL, CPU, CLASS, SCLASS, \ + ARG_32BIT_RALIMMLIMM, FLAGS_F }, \ + { NAME, INSN3OP_0LL (MOP,SOP), MINSN3OP_0LL, CPU, CLASS, SCLASS, \ + ARG_32BIT_ZALIMMLIMM, FLAGS_F }, \ + { NAME, INSN3OP_C0LL (MOP,SOP), MINSN3OP_C0LL, CPU, CLASS, SCLASS, \ + ARG_32BIT_ZALIMMLIMM, FLAGS_CCF }, + + +/* Generate sign extend 32-bit immediate instructions. */ +#define INSN3OP_AXC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDB (60)) +#define INSN3OP_ABX(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDC (60)) +#define INSN3OP_CBBX(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (60)) +#define INSN3OP_AXU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x01 << 22) | FIELDB (60)) + +/* Macro to generate 3 operand 64bit instruction. */ +#define OP64INSN3OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \ + { NAME, INSN3OP_ABC (MOP,SOP), MINSN3OP_ABC, CPU, CLASS, SCLASS, \ + ARG_32BIT_RARBRC, FLAGS_F }, \ + { NAME, INSN3OP_0BC (MOP,SOP), MINSN3OP_0BC, CPU, CLASS, SCLASS, \ + ARG_32BIT_ZARBRC, FLAGS_F }, \ + { NAME, INSN3OP_CBBC (MOP,SOP), MINSN3OP_CBBC, CPU, CLASS, SCLASS, \ + ARG_32BIT_RBRBRC, FLAGS_CCF }, \ + { NAME, INSN3OP_ABU (MOP,SOP), MINSN3OP_ABU, CPU, CLASS, SCLASS, \ + ARG_32BIT_RARBU6, FLAGS_F }, \ + { NAME, INSN3OP_0BU (MOP,SOP), MINSN3OP_0BU, CPU, CLASS, SCLASS, \ + ARG_32BIT_ZARBU6, FLAGS_F }, \ + { NAME, INSN3OP_CBBU (MOP,SOP), MINSN3OP_CBBU, CPU, CLASS, SCLASS, \ + ARG_32BIT_RBRBU6, FLAGS_CCF }, \ + { NAME, INSN3OP_BBS (MOP,SOP), MINSN3OP_BBS, CPU, CLASS, SCLASS, \ + ARG_32BIT_RBRBS12, FLAGS_F }, \ + { NAME, INSN3OP_AXC (MOP,SOP), MINSN3OP_ALC, CPU, CLASS, SCLASS, \ + ARG_32BIT_RAXIMMRC, FLAGS_F }, \ + { NAME, INSN3OP_ABX (MOP,SOP), MINSN3OP_ABL, CPU, CLASS, SCLASS, \ + ARG_32BIT_RARBXIMM, FLAGS_F }, \ + { NAME, INSN3OP_CBBX (MOP,SOP), MINSN3OP_CBBL, CPU, CLASS, SCLASS, \ + ARG_32BIT_RBRBXIMM, FLAGS_CCF }, \ + { NAME, INSN3OP_AXU (MOP,SOP), MINSN3OP_ALU, CPU, CLASS, SCLASS, \ + ARG_32BIT_RAXIMMU6, FLAGS_F }, \ + { NAME, INSN3OP_ALC (MOP,SOP), MINSN3OP_ALC, CPU, CLASS, SCLASS, \ + ARG_32BIT_RALIMMRC, FLAGS_F }, \ + { NAME, INSN3OP_ABL (MOP,SOP), MINSN3OP_ABL, CPU, CLASS, SCLASS, \ + ARG_32BIT_RARBLIMM, FLAGS_F }, \ + { NAME, INSN3OP_CBBL (MOP,SOP), MINSN3OP_CBBL, CPU, CLASS, SCLASS, \ + ARG_32BIT_RBRBLIMM, FLAGS_CCF }, \ + { NAME, INSN3OP_ALU (MOP,SOP), MINSN3OP_ALU, CPU, CLASS, SCLASS, \ + ARG_32BIT_RALIMMU6, FLAGS_F }, + + +#define STDL_ENCODING(K, ZZ) ((F32_ST_OFFSET << 27) | (1 << 5) | (ZZ << 1) \ + | (K)) +#define MSK_STDL (MASK_32BIT (~(FIELDB (63) | (0x1ff << 15) | FIELDC (63) \ + | (0x3 << 3)))) +#define STDL_ASYM_ENCODING(K, ZZ, X) ((F32_ST_OFFSET << 27) | FIELDB (X) \ + | (1 << 5) | (ZZ << 1) | (K)) +#define STDL_DIMM_ENCODING(K, ZZ, X) ((F32_ST_OFFSET << 27) | FIELDC (X) \ + | (1 << 5) | (ZZ << 1) | (K)) + +/* stdl<.aa> c,[b,s9] + stdl<.aa> w6,[b,s9] + stdl<.as> c,[ximm] + stdl<.as> w6,[ximm] + stdl<.aa> ximm,[b,s9] + stdl<.aa> limm,[b,s9] +*/ +#define STDL \ + { "stdl", STDL_ENCODING (0, 0x03), MSK_STDL, ARC_OPCODE_ARC64, STORE, \ + NONE, { RCD, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 }}, \ + { "stdl", STDL_ENCODING (1, 0x02), MSK_STDL, ARC_OPCODE_ARC64, STORE, \ + NONE, { W6, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 }}, \ + { "stdl", STDL_ASYM_ENCODING (0, 0x03, 60), 0xFF007027, ARC_OPCODE_ARC64, \ + STORE, NONE, { RCD, BRAKET, XIMM, BRAKETdup }, {C_AS27 }}, \ + { "stdl", STDL_ASYM_ENCODING (1, 0x02, 60), 0xFF007027, ARC_OPCODE_ARC64, \ + STORE, NONE, { W6, BRAKET, XIMM, BRAKETdup }, { C_AS27 }}, \ + { "stdl", STDL_ASYM_ENCODING (0, 0x03, 62), 0xFF007027, ARC_OPCODE_ARC64, \ + STORE, NONE, { RCD, BRAKET, LIMM, BRAKETdup }, {C_AS27 }}, \ + { "stdl", STDL_ASYM_ENCODING (1, 0x02, 62), 0xFF007027, ARC_OPCODE_ARC64, \ + STORE, NONE, { W6, BRAKET, LIMM, BRAKETdup }, { C_AS27 }}, \ + { "stdl", STDL_DIMM_ENCODING (0, 0x03, 60), 0XF8000FE7, ARC_OPCODE_ARC64, \ + STORE, NONE, { XIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 }}, \ + { "stdl", STDL_DIMM_ENCODING (0, 0x03, 62), 0xF8000FE7, ARC_OPCODE_ARC64, \ + STORE, NONE, { LIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 }}, + +#define STL_ENCODING(DI) ((F32_ST_OFFSET << 27) | (DI << 5) | (0X03 << 1) \ + | (1)) +#define MSK_STL (MASK_32BIT (~(FIELDB (63) | (0x1ff << 15) | FIELDC (63) \ + | (0x03 << 3)))) +#define STL_ASYM_ENCODING(DI, X) ((F32_ST_OFFSET << 27) | (DI << 5) \ + | (0X03 << 1) | FIELDB (X) | (1)) +#define STL_DSYM_ENCODING(X) ((F32_ST_OFFSET << 27) | (0X03 << 1) \ + | FIELDC (X) | (1)) + +/* stl<.aa> c,[b,s9] + stl<.aa> w6,[b,s9] + stl<.as> c,[ximm] + stl<.as> w6,[ximm] + stl<.aa> ximm,[b,s9] + stl<.aa> limm,[b,s9] +*/ +#define STL \ + { "stl", STL_ENCODING (0), MSK_STL, ARC_OPCODE_ARC64, STORE, NONE, \ + { RC, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 }}, \ + { "stl", STL_ENCODING (1), MSK_STL, ARC_OPCODE_ARC64, STORE, NONE, \ + { W6, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 }}, \ + { "stl", STL_ASYM_ENCODING (0, 60), 0xFFFFF03F, ARC_OPCODE_ARC64, STORE, \ + NONE, { RC, BRAKET, XIMM, BRAKETdup }, { C_AS27 }}, \ + { "stl", STL_ASYM_ENCODING (1, 60), 0xFFFFF03F, ARC_OPCODE_ARC64, STORE, \ + NONE, { W6, BRAKET, XIMM, BRAKETdup }, { C_AS27 }}, \ + { "stl", STL_ASYM_ENCODING (0, 62), 0xFFFFF03F, ARC_OPCODE_ARC64, STORE, \ + NONE, { RC, BRAKET, LIMM, BRAKETdup }, { C_AS27 }}, \ + { "stl", STL_ASYM_ENCODING (1, 62), 0xFFFFF03F, ARC_OPCODE_ARC64, STORE, \ + NONE, { W6, BRAKET, LIMM, BRAKETdup }, { C_AS27 }}, \ + { "stl", STL_DSYM_ENCODING (60), 0xF8000FC7, ARC_OPCODE_ARC64, STORE, \ + NONE, { XIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 }}, \ + { "stl", STL_DSYM_ENCODING (62), 0xF8000FC7, ARC_OPCODE_ARC64, STORE, \ + NONE, { LIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 }}, + +/* The opcode table. + + The format of the opcode table is: + + NAME OPCODE MASK CPU CLASS SUBCLASS { OPERANDS } { FLAGS }. + + The table is organised such that, where possible, all instructions with + the same mnemonic are together in a block. When the assembler searches + for a suitable instruction the entries are checked in table order, so + more specific, or specialised cases should appear earlier in the table. + + As an example, consider two instructions 'add a,b,u6' and 'add + a,b,limm'. The first takes a 6-bit immediate that is encoded within the + 32-bit instruction, while the second takes a 32-bit immediate that is + encoded in a follow-on 32-bit, making the total instruction length + 64-bits. In this case the u6 variant must appear first in the table, as + all u6 immediates could also be encoded using the 'limm' extension, + however, we want to use the shorter instruction wherever possible. + + It is possible though to split instructions with the same mnemonic into + multiple groups. However, the instructions are still checked in table + order, even across groups. The only time that instructions with the + same mnemonic should be split into different groups is when different + variants of the instruction appear in different architectures, in which + case, grouping all instructions from a particular architecture together + might be preferable to merging the instruction into the main instruction + table. + + An example of this split instruction groups can be found with the 'sync' + instruction. The core arc architecture provides a 'sync' instruction, + while the nps instruction set extension provides 'sync.rd' and + 'sync.wr'. The rd/wr flags are instruction flags, not part of the + mnemonic, so we end up with two groups for the sync instruction, the + first within the core arc instruction table, and the second within the + nps extension instructions. */ + +const struct arc_opcode arc_opcodes[] = +{ + + /* STL and STDL instructions. */ + STL + STDL + +#include "arc64-tbl.h" + + FP_TOP (fhmadd , FMADD , HALF) + FP_TOP (fhmsub , FMSUB , HALF) + FP_TOP (fhnmadd, FNMADD, HALF) + FP_TOP (fhnmsub, FNMSUB, HALF) + + FP_TOP (fsmadd , FMADD , SINGLE) + FP_TOP (fsmsub , FMSUB , SINGLE) + FP_TOP (fsnmadd, FNMADD, SINGLE) + FP_TOP (fsnmsub, FNMSUB, SINGLE) + + FP_TOP (fdmadd , FMADD , DOUBLE) + FP_TOP (fdmsub , FMSUB , DOUBLE) + FP_TOP (fdnmadd, FNMADD, DOUBLE) + FP_TOP (fdnmsub, FNMSUB, DOUBLE) + + /* Vectors. */ + FP_TOP (vfhmadd , VFMADD , HALF) + FP_TOP (vfhmsub , VFMSUB , HALF) + FP_TOP (vfhnmadd, VFNMADD, HALF) + FP_TOP (vfhnmsub, VFNMSUB, HALF) + FP_TOP (vfhmadds , VFMADDS , HALF) + FP_TOP (vfhmsubs , VFMSUBS , HALF) + FP_TOP (vfhnmadds, VFNMADDS, HALF) + FP_TOP (vfhnmsubs, VFNMSUBS, HALF) + + FP_TOP (vfsmadd , VFMADD , SINGLE) + FP_TOP (vfsmsub , VFMSUB , SINGLE) + FP_TOP (vfsnmadd, VFNMADD, SINGLE) + FP_TOP (vfsnmsub, VFNMSUB, SINGLE) + FP_TOP (vfsmadds , VFMADDS , SINGLE) + FP_TOP (vfsmsubs , VFMSUBS , SINGLE) + FP_TOP (vfsnmadds, VFNMADDS, SINGLE) + FP_TOP (vfsnmsubs, VFNMSUBS, SINGLE) + + FP_TOP_D (vfdmadd , VFMADD , DOUBLE) + FP_TOP_D (vfdmsub , VFMSUB , DOUBLE) + FP_TOP_D (vfdnmadd, VFNMADD, DOUBLE) + FP_TOP_D (vfdnmsub, VFNMSUB, DOUBLE) + FP_TOP_D (vfdmadds , VFMADDS , DOUBLE) + FP_TOP_D (vfdmsubs , VFMSUBS , DOUBLE) + FP_TOP_D (vfdnmadds, VFNMADDS, DOUBLE) + FP_TOP_D (vfdnmsubs, VFNMSUBS, DOUBLE) + + /* 2OPS. */ + FP_DOP (fhadd , FADD , HALF) + FP_DOP (fhsub , FSUB , HALF) + FP_DOP (fhmul , FMUL , HALF) + FP_DOP (fhdiv , FDIV , HALF) + FP_DOP (fhmin , FMIN , HALF) + FP_DOP (fhmax , FMAX , HALF) + FP_DOP (fhsgnj , FSGNJ , HALF) + FP_DOP (fhsgnjn, FSGNJN, HALF) + FP_DOP (fhsgnjx, FSGNJX, HALF) + + FP_DOP (fsadd , FADD , SINGLE) + FP_DOP (fssub , FSUB , SINGLE) + FP_DOP (fsmul , FMUL , SINGLE) + FP_DOP (fsdiv , FDIV , SINGLE) + FP_DOP (fsmin , FMIN , SINGLE) + FP_DOP (fsmax , FMAX , SINGLE) + FP_DOP (fssgnj , FSGNJ , SINGLE) + FP_DOP (fssgnjn, FSGNJN, SINGLE) + FP_DOP (fssgnjx, FSGNJX, SINGLE) + + FP_DOP (fdadd , FADD , DOUBLE) + FP_DOP (fdsub , FSUB , DOUBLE) + FP_DOP (fdmul , FMUL , DOUBLE) + FP_DOP (fddiv , FDIV , DOUBLE) + FP_DOP (fdmin , FMIN , DOUBLE) + FP_DOP (fdmax , FMAX , DOUBLE) + FP_DOP (fdsgnj , FSGNJ , DOUBLE) + FP_DOP (fdsgnjn, FSGNJN, DOUBLE) + FP_DOP (fdsgnjx, FSGNJX, DOUBLE) + + FP_DOP_C (fhcmp , FCMP , HALF) + FP_DOP_C (fhcmpf, FCMPF, HALF) + FP_DOP_C (fscmp , FCMP , SINGLE) + FP_DOP_C (fscmpf, FCMPF, SINGLE) + FP_DOP_C (fdcmp , FCMP , DOUBLE) + FP_DOP_C (fdcmpf, FCMPF, DOUBLE) + + /* Vectors. */ + FP_DOP (vfhadd , VFADD , HALF) + FP_DOP (vfhsub , VFSUB , HALF) + FP_DOP (vfhmul , VFMUL , HALF) + FP_DOP (vfhdiv , VFDIV , HALF) + FP_DOP (vfhadds, VFADDS, HALF) + FP_DOP (vfhsubs, VFSUBS, HALF) + FP_DOP (vfhmuls, VFMULS, HALF) + FP_DOP (vfhdivs, VFDIVS, HALF) + + FP_DOP (vfhunpkl , VFUNPKL , HALF) + FP_DOP (vfhunpkm , VFUNPKM , HALF) + FP_DOP (vfhpackl , VFPACKL , HALF) + FP_DOP (vfhpackm , VFPACKM , HALF) + FP_DOP (vfhbflyl , VFBFLYL , HALF) + FP_DOP (vfhbflym , VFBFLYM , HALF) + FP_DOP (vfhaddsub, VFADDSUB, HALF) + FP_DOP (vfhsubadd, VFSUBADD, HALF) + + FP_DOP (vfsadd , VFADD , SINGLE) + FP_DOP (vfssub , VFSUB , SINGLE) + FP_DOP (vfsmul , VFMUL , SINGLE) + FP_DOP (vfsdiv , VFDIV , SINGLE) + FP_DOP (vfsadds, VFADDS, SINGLE) + FP_DOP (vfssubs, VFSUBS, SINGLE) + FP_DOP (vfsmuls, VFMULS, SINGLE) + FP_DOP (vfsdivs, VFDIVS, SINGLE) + + FP_DOP (vfsunpkl , VFUNPKL , SINGLE) + FP_DOP (vfsunpkm , VFUNPKM , SINGLE) + FP_DOP (vfspackl , VFPACKL , SINGLE) + FP_DOP (vfspackm , VFPACKM , SINGLE) + FP_DOP (vfsbflyl , VFBFLYL , SINGLE) + FP_DOP (vfsbflym , VFBFLYM , SINGLE) + FP_DOP (vfsaddsub, VFADDSUB, SINGLE) + FP_DOP (vfssubadd, VFSUBADD, SINGLE) + + FP_DOP_D (vfdadd , VFADD , DOUBLE) + FP_DOP_D (vfdsub , VFSUB , DOUBLE) + FP_DOP_D (vfdmul , VFMUL , DOUBLE) + FP_DOP_D (vfddiv , VFDIV , DOUBLE) + FP_DOP_D (vfdadds, VFADDS, DOUBLE) + FP_DOP_D (vfdsubs, VFSUBS, DOUBLE) + FP_DOP_D (vfdmuls, VFMULS, DOUBLE) + FP_DOP_D (vfddivs, VFDIVS, DOUBLE) + + FP_DOP_D (vfdunpkl , VFUNPKL , DOUBLE) + FP_DOP_D (vfdunpkm , VFUNPKM , DOUBLE) + FP_DOP_D (vfdpackl , VFPACKL , DOUBLE) + FP_DOP_D (vfdpackm , VFPACKM , DOUBLE) + FP_DOP_D (vfdbflyl , VFBFLYL , DOUBLE) + FP_DOP_D (vfdbflym , VFBFLYM , DOUBLE) + FP_DOP_D (vfdaddsub, VFADDSUB, DOUBLE) + FP_DOP_D (vfdsubadd, VFSUBADD, DOUBLE) + + FP_SOP (fhsqrt, FSQRT, HALF) + FP_SOP (fssqrt, FSQRT, SINGLE) + FP_SOP (fdsqrt, FSQRT, DOUBLE) + FP_SOP (vfhsqrt, VFSQRT, HALF) + FP_SOP (vfssqrt, VFSQRT, SINGLE) + FP_SOP_D (vfdsqrt, VFSQRT,DOUBLE) + + FP_SOP (vfhexch, VFEXCH, HALF) + FP_SOP (vfsexch, VFEXCH, SINGLE) + FP_SOP_D (vfdexch, VFEXCH, DOUBLE) + + FP_COP (fhmov, FMOV, HALF) + FP_COP (fsmov, FMOV, SINGLE) + FP_COP (fdmov, FMOV, DOUBLE) + FP_COP (vfhmov, VFMOV, HALF) + FP_COP (vfsmov, VFMOV, SINGLE) + FP_COP (vfdmov, VFMOV, DOUBLE) + + FP_CVI2F (fuint2s, FUINT2S, 0x00) + FP_CVI2F (fuint2d, FUINT2D, 0x00) + FP_CVI2F (ful2s, FUL2S, 0x00) + FP_CVI2F (ful2d, FUL2D, 0x00) + + FP_CVF2I (fs2uint, FS2UINT, 0x01) + FP_CVF2I (fs2ul, FS2UL, 0x01) + FP_CVF2I (fd2uint, FD2UINT, 0x01) + FP_CVF2I (fd2ul, FD2UL, 0x01) + + FP_CVI2F (fint2s, FINT2S, 0x02) + FP_CVI2F (fint2d, FINT2D, 0x02) + FP_CVI2F (fl2s, FL2S, 0x02) + FP_CVI2F (fl2d, FL2D, 0x02) + + FP_CVF2I (fs2int, FS2INT, 0x03) + FP_CVF2I (fs2l, FS2L, 0x03) + FP_CVF2I (fd2int, FD2INT, 0x03) + FP_CVF2I (fd2l, FD2L, 0x03) + + FP_CVF2F (fs2d, FS2D, 0x04) + FP_CVF2F (fd2s, FD2S, 0x04) + + FP_RND (fsrnd, FSRND, 0x06) + FP_RND (fdrnd, FDRND, 0x06) + + FP_CVF2I (fs2uint_rz, F2UINT_RZ, 0x09) + FP_CVF2I (fs2ul_rz, FS2UL_RZ, 0x09) + FP_CVF2I (fd2uint_rz, FD2UINT_RZ, 0x09) + FP_CVF2I (fd2ul_rz, FD2UL_RZ, 0x09) + + FP_CVF2I (fs2int_rz, FSINT_RZ, 0x0B) + FP_CVF2I (fs2l_rz, FS2L_RZ, 0x0B) + FP_CVF2I (fd2int_rz, FD2INT_RZ, 0x0B) + FP_CVF2I (fd2l_rz, FD2L_RZ, 0x0B) + + FP_RND (fsrnd_rz, FSRND_RZ, 0x0E) + FP_RND (fdrnd_rz, FDRND_RZ, 0x0E) + + FMVI2F (fmvi2s, FMVI2S, 0x10) + FMVI2F (fmvl2d, FMVL2D, 0x10) + + FMVF2I (fmvs2i, FMVS2I, 0x11) + FMVF2I (fmvd2l, FMVD2L, 0x11) + + FP_CVF2F (fs2h, FS2H, 0x14) + FP_CVF2F (fh2s, FH2S, 0x15) + FP_CVF2F (fs2h_rz, FS2H_RZ, 0x1C) + + FP_LOAD (fld16, 0x02, 0) + FP_LOAD (fld32, 0x00, 0) + FP_LOAD (fld64, 0x01, 0) + FP_LOAD (fldd32, 0x00, 1) + FP_LOAD (fldd64, 0x01, 1) + + FP_STORE (fst16, 0x02, 0) + FP_STORE (fst32, 0x00, 0) + FP_STORE (fst64, 0x01, 0) + FP_STORE (fstd32, 0x00, 1) + FP_STORE (fstd64, 0x01, 1) + + FP_EXT (vfhext, HALF) + FP_EXT (vfsext, SINGLE) + FP_EXT (vfdext, DOUBLE) + + FP_INS (vfhins, HALF) + FP_INS (vfsins, SINGLE) + FP_INS (vfdins, DOUBLE) + + FP_REP (vfhrep, HALF) + FP_REP (vfsrep, SINGLE) + FP_REP (vfdrep, DOUBLE) + +#undef FLAGS_F +#define FLAGS_F { 0 } + +#undef FLAGS_CCF +#define FLAGS_CCF { C_CC } + +#undef FIELDF +#define FIELDF 0x0 + + EXTINSN3OP ("vmin2", ARC_OPCODE_ARC32, MOVE, NONE, F32_GEN4, 0x11) + EXTINSN3OP ("vmax2", ARC_OPCODE_ARC32, MOVE, NONE, F32_GEN4, 0x0b) + +#undef HARD_FIELDF +#define HARD_FIELDF (0x01 << 15) + + EXTINSN3OP ("vmin2", ARC_OPCODE_ARC64, MOVE, NONE, F32_EXT5, 0x38) + EXTINSN3OP ("vmax2", ARC_OPCODE_ARC64, MOVE, NONE, F32_EXT5, 0x39) + + EXTINSN3OP ("vpack4hl", ARC_OPCODE_ARC64, MOVE, NONE, F32_GEN_OP64, 0x30) + EXTINSN3OP ("vpack4hm", ARC_OPCODE_ARC64, MOVE, NONE, F32_GEN_OP64, 0x31) + EXTINSN3OP ("vpack2wl", ARC_OPCODE_ARC64, MOVE, NONE, F32_GEN_OP64, 0x32) + EXTINSN3OP ("vpack2wm", ARC_OPCODE_ARC64, MOVE, NONE, F32_GEN_OP64, 0x33) + EXTINSN3OP ("vpack2hm", ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MOVE, NONE, + F32_EXT5, 0x29) + +#undef HARD_FIELDF +#define HARD_FIELDF (0x0) + + OP64INSN3OP ("mpyl", ARC_OPCODE_ARC64, ARITH, NONE, F32_GEN_OP64, 0x30) + OP64INSN3OP ("mpyml", ARC_OPCODE_ARC64, ARITH, NONE, F32_GEN_OP64, 0x31) + OP64INSN3OP ("mpymul", ARC_OPCODE_ARC64, ARITH, NONE, F32_GEN_OP64, 0x32) + OP64INSN3OP ("mpymsul", ARC_OPCODE_ARC64, ARITH, NONE, F32_GEN_OP64, 0x33) + + EXTINSN3OP ("vpack2hl", ARC_OPCODE_ARC32 | ARC_OPCODE_ARC64, MOVE, NONE, + F32_EXT5, 0x29) + + { NULL, 0, 0, 0, 0, 0, { 0 }, { 0 } } +}; diff --git a/opcodes/arcxx-opc.inc b/opcodes/arcxx-opc.inc new file mode 100644 index 00000000000..7c72e5f9019 --- /dev/null +++ b/opcodes/arcxx-opc.inc @@ -0,0 +1,1840 @@ +/* Opcode table for the ARC. + Copyright (C) 1994-2023 Free Software Foundation, Inc. + + Contributed by Claudiu Zissulescu (claziss@synopsys.com) + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#include "sysdep.h" +#include <stdio.h> +#include "bfd.h" +#include "opcode/arc.h" +#include "opintl.h" +#include "libiberty.h" + +/* ARC NPS400 Support: The ARC NPS400 core is an ARC700 with some + custom instructions. All NPS400 features are built into all ARC + target builds as this reduces the chances that regressions might + creep in. */ + +/* Insert RA register into a 32-bit opcode, with checks. */ + +static unsigned long long +insert_ra_chk (unsigned long long insn, + long long value, + const char **errmsg) +{ + if (value == 60) + *errmsg = _("LP_COUNT register cannot be used as destination register"); + + return insn | (value & 0x3F); +} + +/* Insert RB register into a 32-bit opcode. */ + +static unsigned long long +insert_rb (unsigned long long insn, + long long value, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12); +} + +/* Insert RB register into a push(d)l/pop(d)l instruction. */ + +static unsigned long long +insert_rbb (unsigned long long insn, + long long value, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn | ((value & 0x07) << 8) | (((value >> 3) & 0x07) << 1); +} + +/* Insert RB register with checks. */ + +static unsigned long long +insert_rb_chk (unsigned long long insn, + long long value, + const char **errmsg) +{ + if (value == 60) + *errmsg = _("LP_COUNT register cannot be used as destination register"); + + return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12); +} + +/* Insert a floating point register into fs2 slot. */ + +static unsigned long long +insert_fs2 (unsigned long long insn, + long long value, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x03) << 12); +} + +/* Insert address writeback mode for 128-bit loads. */ + +static unsigned long long +insert_qq (unsigned long long insn, + long long value, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn | ((value & 0x01) << 11) | ((value & 0x02) << (6-1)); +} + +static long long +extract_rb (unsigned long long insn, + bool *invalid) +{ + int value = (((insn >> 12) & 0x07) << 3) | ((insn >> 24) & 0x07); + + if (value == 0x3e && invalid) + *invalid = true; /* A limm operand, it should be extracted in a + different way. */ + + return value; +} + +static long long +extract_rbb (unsigned long long insn, + bool *invalid) +{ + int value = (((insn >> 1) & 0x07) << 3) | ((insn >> 8) & 0x07); + + if (value == 0x3e && invalid) + *invalid = true; /* A limm operand, it should be extracted in a + different way. */ + + return value; +} + +/* Extract the floating point register number from fs2 slot. */ + +static long long +extract_fs2 (unsigned long long insn, + bool *invalid ATTRIBUTE_UNUSED) +{ + long long value; + value = (((insn >> 12) & 0x03) << 3) | ((insn >> 24) & 0x07); + return value; +} + +/* Extract address writeback mode for 128-bit loads. */ + +static long long +extract_qq (unsigned long long insn, + bool * invalid ATTRIBUTE_UNUSED) +{ + long long value; + value = ((insn & 0x800) >> 11) | ((insn & 0x40) >> (6 - 1)); + return value; +} + +static unsigned long long +insert_rad (unsigned long long insn, + long long value, + const char **errmsg) +{ + if (value & 0x01) + *errmsg = _("cannot use odd number destination register"); + if (value == 60) + *errmsg = _("LP_COUNT register cannot be used as destination register"); + + return insn | (value & 0x3F); +} + +static unsigned long long +insert_rcd (unsigned long long insn, + long long value, + const char **errmsg) +{ + if (value & 0x01) + *errmsg = _("cannot use odd number source register"); + + return insn | ((value & 0x3F) << 6); +} + +static unsigned long long +insert_rbd (unsigned long long insn, + long long value, + const char **errmsg) +{ + if (value & 0x01) + *errmsg = _("cannot use odd number source register"); + if (value == 60) + *errmsg = _("LP_COUNT register cannot be used as destination register"); + + return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12); +} + +/* Dummy insert ZERO operand function. */ + +static unsigned long long +insert_za (unsigned long long insn, + long long value, + const char **errmsg) +{ + if (value) + *errmsg = _("operand is not zero"); + return insn; +} + +/* Insert Y-bit in bbit/br instructions. This function is called only + when solving fixups. */ + +static unsigned long long +insert_Ybit (unsigned long long insn, + long long value, + const char **errmsg ATTRIBUTE_UNUSED) +{ + if (value > 0) + insn |= 0x08; + + return insn; +} + +/* Insert Y-bit in bbit/br instructions. This function is called only + when solving fixups. */ + +static unsigned long long +insert_NYbit (unsigned long long insn, + long long value, + const char **errmsg ATTRIBUTE_UNUSED) +{ + if (value < 0) + insn |= 0x08; + + return insn; +} + +/* Insert H register into a 16-bit opcode. */ + +static unsigned long long +insert_rhv1 (unsigned long long insn, + long long value, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x07); +} + +static long long +extract_rhv1 (unsigned long long insn, + bool *invalid ATTRIBUTE_UNUSED) +{ + int value = ((insn & 0x7) << 3) | ((insn >> 5) & 0x7); + + return value; +} + +/* Insert H register into a 16-bit opcode. */ + +static unsigned long long +insert_rhv2 (unsigned long long insn, + long long value, + const char **errmsg) +{ + if (value == 0x1E) + *errmsg = _("register R30 is a limm indicator"); + else if (value < 0 || value > 31) + *errmsg = _("register out of range"); + return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x03); +} + +static long long +extract_rhv2 (unsigned long long insn, + bool *invalid ATTRIBUTE_UNUSED) +{ + int value = ((insn >> 5) & 0x07) | ((insn & 0x03) << 3); + + return value; +} + +static unsigned long long +insert_r0 (unsigned long long insn, + long long value, + const char **errmsg) +{ + if (value != 0) + *errmsg = _("register must be R0"); + return insn; +} + +static long long +extract_r0 (unsigned long long insn ATTRIBUTE_UNUSED, + bool *invalid ATTRIBUTE_UNUSED) +{ + return 0; +} + + +static unsigned long long +insert_r1 (unsigned long long insn, + long long value, + const char **errmsg) +{ + if (value != 1) + *errmsg = _("register must be R1"); + return insn; +} + +static long long +extract_r1 (unsigned long long insn ATTRIBUTE_UNUSED, + bool* invalid ATTRIBUTE_UNUSED) +{ + return 1; +} + +static unsigned long long +insert_r2 (unsigned long long insn, + long long value, + const char **errmsg) +{ + if (value != 2) + *errmsg = _("register must be R2"); + return insn; +} + +static long long +extract_r2 (unsigned long long insn ATTRIBUTE_UNUSED, + bool *invalid ATTRIBUTE_UNUSED) +{ + return 2; +} + +static unsigned long long +insert_r3 (unsigned long long insn, + long long value, + const char **errmsg) +{ + if (value != 3) + *errmsg = _("register must be R3"); + return insn; +} + +static long long +extract_r3 (unsigned long long insn ATTRIBUTE_UNUSED, + bool *invalid ATTRIBUTE_UNUSED) +{ + return 3; +} + +static unsigned long long +insert_sp (unsigned long long insn, + long long value, + const char **errmsg) +{ + if (value != 28) + *errmsg = _("register must be SP"); + return insn; +} + +static long long +extract_sp (unsigned long long insn ATTRIBUTE_UNUSED, + bool *invalid ATTRIBUTE_UNUSED) +{ + return 28; +} + +static unsigned long long +insert_gp (unsigned long long insn, + long long value, + const char **errmsg) +{ + if (value != 26 + && value != 30) + *errmsg = _("register must be GP"); + return insn; +} + +static long long +extract_gp (unsigned long long insn ATTRIBUTE_UNUSED, + bool *invalid ATTRIBUTE_UNUSED) +{ + return 26; +} + +static unsigned long long +insert_pcl (unsigned long long insn, + long long value, + const char **errmsg) +{ + if (value != 63) + *errmsg = _("register must be PCL"); + return insn; +} + +static long long +extract_pcl (unsigned long long insn ATTRIBUTE_UNUSED, + bool *invalid ATTRIBUTE_UNUSED) +{ + return 63; +} + +static unsigned long long +insert_blink (unsigned long long insn, + long long value, + const char **errmsg) +{ + if (value != 31) + *errmsg = _("register must be BLINK"); + return insn; +} + +static long long +extract_blink (unsigned long long insn ATTRIBUTE_UNUSED, + bool *invalid ATTRIBUTE_UNUSED) +{ + return 31; +} + +static unsigned long long +insert_ilink1 (unsigned long long insn, + long long value, + const char **errmsg) +{ + if (value != 29) + *errmsg = _("register must be ILINK1"); + return insn; +} + +static long long +extract_ilink1 (unsigned long long insn ATTRIBUTE_UNUSED, + bool *invalid ATTRIBUTE_UNUSED) +{ + return 29; +} + +static unsigned long long +insert_ilink2 (unsigned long long insn, + long long value, + const char **errmsg) +{ + if (value != 30) + *errmsg = _("register must be ILINK2"); + return insn; +} + +static long long +extract_ilink2 (unsigned long long insn ATTRIBUTE_UNUSED, + bool *invalid ATTRIBUTE_UNUSED) +{ + return 30; +} + +static unsigned long long +insert_ras (unsigned long long insn, + long long value, + const char **errmsg) +{ + switch (value) + { + case 0: + case 1: + case 2: + case 3: + insn |= value; + break; + case 12: + case 13: + case 14: + case 15: + insn |= (value - 8); + break; + default: + *errmsg = _("register must be either r0-r3 or r12-r15"); + break; + } + return insn; +} + +static long long +extract_ras (unsigned long long insn, + bool *invalid ATTRIBUTE_UNUSED) +{ + int value = insn & 0x07; + + if (value > 3) + return (value + 8); + else + return value; +} + +static unsigned long long +insert_rbs (unsigned long long insn, + long long value, + const char **errmsg) +{ + switch (value) + { + case 0: + case 1: + case 2: + case 3: + insn |= value << 8; + break; + case 12: + case 13: + case 14: + case 15: + insn |= ((value - 8)) << 8; + break; + default: + *errmsg = _("register must be either r0-r3 or r12-r15"); + break; + } + return insn; +} + +static long long +extract_rbs (unsigned long long insn, + bool *invalid ATTRIBUTE_UNUSED) +{ + int value = (insn >> 8) & 0x07; + + if (value > 3) + return (value + 8); + else + return value; +} + +static unsigned long long +insert_rcs (unsigned long long insn, + long long value, + const char **errmsg) +{ + switch (value) + { + case 0: + case 1: + case 2: + case 3: + insn |= value << 5; + break; + case 12: + case 13: + case 14: + case 15: + insn |= ((value - 8)) << 5; + break; + default: + *errmsg = _("register must be either r0-r3 or r12-r15"); + break; + } + return insn; +} + +static long long +extract_rcs (unsigned long long insn, + bool *invalid ATTRIBUTE_UNUSED) +{ + int value = (insn >> 5) & 0x07; + + if (value > 3) + return (value + 8); + else + return value; +} + +static unsigned long long +insert_simm3s (unsigned long long insn, + long long value, + const char **errmsg) +{ + int tmp = 0; + switch (value) + { + case -1: + tmp = 0x07; + break; + case 0: + tmp = 0x00; + break; + case 1: + tmp = 0x01; + break; + case 2: + tmp = 0x02; + break; + case 3: + tmp = 0x03; + break; + case 4: + tmp = 0x04; + break; + case 5: + tmp = 0x05; + break; + case 6: + tmp = 0x06; + break; + default: + *errmsg = _("accepted values are from -1 to 6"); + break; + } + + insn |= tmp << 8; + return insn; +} + +static long long +extract_simm3s (unsigned long long insn, + bool *invalid ATTRIBUTE_UNUSED) +{ + int value = (insn >> 8) & 0x07; + + if (value == 7) + return -1; + else + return value; +} + +static unsigned long long +insert_rrange (unsigned long long insn, + long long value, + const char **errmsg) +{ + int reg1 = (value >> 16) & 0xFFFF; + int reg2 = value & 0xFFFF; + + if (reg1 != 13) + *errmsg = _("first register of the range should be r13"); + else if (reg2 < 13 || reg2 > 26) + *errmsg = _("last register of the range doesn't fit"); + else + insn |= ((reg2 - 12) & 0x0F) << 1; + return insn; +} + +static long long +extract_rrange (unsigned long long insn, + bool *invalid ATTRIBUTE_UNUSED) +{ + return (insn >> 1) & 0x0F; +} + +static unsigned long long +insert_r13el (unsigned long long insn, + long long int value, + const char **errmsg) +{ + if (value != 13) + { + *errmsg = _("invalid register number, should be fp"); + return insn; + } + + insn |= 0x02; + return insn; +} + +static unsigned long long +insert_fpel (unsigned long long insn, + long long value, + const char **errmsg) +{ + if (value != 27) + { + *errmsg = _("invalid register number, should be fp"); + return insn; + } + + insn |= 0x0100; + return insn; +} + +static long long +extract_fpel (unsigned long long insn, + bool *invalid ATTRIBUTE_UNUSED) +{ + return (insn & 0x0100) ? 27 : -1; +} + +static unsigned long long +insert_blinkel (unsigned long long insn, + long long value, + const char **errmsg) +{ + if (value != 31) + { + *errmsg = _("invalid register number, should be blink"); + return insn; + } + + insn |= 0x0200; + return insn; +} + +static long long +extract_blinkel (unsigned long long insn, + bool *invalid ATTRIBUTE_UNUSED) +{ + return (insn & 0x0200) ? 31 : -1; +} + +static unsigned long long +insert_pclel (unsigned long long insn, + long long value, + const char **errmsg) +{ + if (value != 63) + { + *errmsg = _("invalid register number, should be pcl"); + return insn; + } + + insn |= 0x0400; + return insn; +} + +static long long +extract_pclel (unsigned long long insn, + bool *invalid ATTRIBUTE_UNUSED) +{ + return (insn & 0x0400) ? 63 : -1; +} + +#define INSERT_W6 + +/* mask = 00000000000000000000111111000000 + insn = 00011bbb000000000BBBwwwwwwDaaZZ1. */ + +static unsigned long long +insert_w6 (unsigned long long insn, + long long value, + const char **errmsg ATTRIBUTE_UNUSED) +{ + insn |= ((value >> 0) & 0x003f) << 6; + + return insn; +} + +#define EXTRACT_W6 + +/* mask = 00000000000000000000111111000000. */ + +static long long +extract_w6 (unsigned long long insn, + bool *invalid ATTRIBUTE_UNUSED) +{ + int value = 0; + + value |= ((insn >> 6) & 0x003f) << 0; + + /* Extend the sign. */ + int signbit = 1 << 5; + value = (value ^ signbit) - signbit; + + return value; +} + +#define INSERT_G_S + +/* mask = 0000011100022000 + insn = 01000ggghhhGG0HH. */ + +static unsigned long long +insert_g_s (unsigned long long insn, + long long value, + const char **errmsg ATTRIBUTE_UNUSED) +{ + insn |= ((value >> 0) & 0x0007) << 8; + insn |= ((value >> 3) & 0x0003) << 3; + + return insn; +} + +#define EXTRACT_G_S + +/* mask = 0000011100022000. */ + +static long long +extract_g_s (unsigned long long insn, + bool *invalid ATTRIBUTE_UNUSED) +{ + int value = 0; + int signbit = 1 << (6 - 1); + + value |= ((insn >> 8) & 0x0007) << 0; + value |= ((insn >> 3) & 0x0003) << 3; + + /* Extend the sign. */ + value = (value ^ signbit) - signbit; + + return value; +} + +/* ARC NPS400 Support: See comment near head of file. */ +#define MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(NAME,OFFSET) \ +static unsigned long long \ + insert_nps_3bit_reg_at_##OFFSET##_##NAME \ + (unsigned long long insn, \ + long long value, \ + const char **errmsg) \ +{ \ + switch (value) \ + { \ + case 0: \ + case 1: \ + case 2: \ + case 3: \ + insn |= value << (OFFSET); \ + break; \ + case 12: \ + case 13: \ + case 14: \ + case 15: \ + insn |= (value - 8) << (OFFSET); \ + break; \ + default: \ + *errmsg = _("register must be either r0-r3 or r12-r15"); \ + break; \ + } \ + return insn; \ +} \ + \ +static long long \ +extract_nps_3bit_reg_at_##OFFSET##_##NAME \ + (unsigned long long insn, \ + bool *invalid ATTRIBUTE_UNUSED) \ +{ \ + int value = (insn >> (OFFSET)) & 0x07; \ + if (value > 3) \ + value += 8; \ + return value; \ +} \ + +MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS (dst,8) +MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS (dst,24) +MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS (dst,40) +MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS (dst,56) + +MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS (src2,5) +MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS (src2,21) +MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS (src2,37) +MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS (src2,53) + +static unsigned long long +insert_nps_bitop_size_2b (unsigned long long insn, + long long value, + const char **errmsg) +{ + switch (value) + { + case 1: + value = 0; + break; + case 2: + value = 1; + break; + case 4: + value = 2; + break; + case 8: + value = 3; + break; + default: + value = 0; + *errmsg = _("invalid size, should be 1, 2, 4, or 8"); + break; + } + + insn |= value << 10; + return insn; +} + +static long long +extract_nps_bitop_size_2b (unsigned long long insn, + bool *invalid ATTRIBUTE_UNUSED) +{ + return 1 << ((insn >> 10) & 0x3); +} + +static unsigned long long +insert_nps_bitop_uimm8 (unsigned long long insn, + long long value, + const char **errmsg ATTRIBUTE_UNUSED) +{ + insn |= ((value >> 5) & 7) << 12; + insn |= (value & 0x1f); + return insn; +} + +static long long +extract_nps_bitop_uimm8 (unsigned long long insn, + bool *invalid ATTRIBUTE_UNUSED) +{ + return (((insn >> 12) & 0x7) << 5) | (insn & 0x1f); +} + +static unsigned long long +insert_nps_rflt_uimm6 (unsigned long long insn, + long long value, + const char **errmsg) +{ + switch (value) + { + case 1: + case 2: + case 4: + break; + + default: + *errmsg = _("invalid immediate, must be 1, 2, or 4"); + value = 0; + } + + insn |= (value << 6); + return insn; +} + +static long long +extract_nps_rflt_uimm6 (unsigned long long insn, + bool *invalid ATTRIBUTE_UNUSED) +{ + return (insn >> 6) & 0x3f; +} + +static unsigned long long +insert_nps_dst_pos_and_size (unsigned long long insn, + long long value, + const char **errmsg ATTRIBUTE_UNUSED) +{ + insn |= ((value & 0x1f) | (((32 - value - 1) & 0x1f) << 10)); + return insn; +} + +static long long +extract_nps_dst_pos_and_size (unsigned long long insn, + bool *invalid ATTRIBUTE_UNUSED) +{ + return (insn & 0x1f); +} + +static unsigned long long +insert_nps_cmem_uimm16 (unsigned long long insn, + long long value, + const char **errmsg) +{ + int top = (value >> 16) & 0xffff; + + if (top != 0x0 && top != NPS_CMEM_HIGH_VALUE) + *errmsg = _("invalid value for CMEM ld/st immediate"); + insn |= (value & 0xffff); + return insn; +} + +static long long +extract_nps_cmem_uimm16 (unsigned long long insn, + bool *invalid ATTRIBUTE_UNUSED) +{ + return (NPS_CMEM_HIGH_VALUE << 16) | (insn & 0xffff); +} + +static unsigned long long +insert_nps_imm_offset (unsigned long long insn, + long long value, + const char **errmsg) +{ + switch (value) + { + case 0: + case 16: + case 32: + case 48: + case 64: + value = value >> 4; + break; + default: + *errmsg = _("invalid position, should be 0, 16, 32, 48 or 64."); + value = 0; + } + insn |= (value << 10); + return insn; +} + +static long long +extract_nps_imm_offset (unsigned long long insn, + bool *invalid ATTRIBUTE_UNUSED) +{ + return ((insn >> 10) & 0x7) * 16; +} + +static unsigned long long +insert_nps_imm_entry (unsigned long long insn, + long long value, + const char **errmsg) +{ + switch (value) + { + case 16: + value = 0; + break; + case 32: + value = 1; + break; + case 64: + value = 2; + break; + case 128: + value = 3; + break; + default: + *errmsg = _("invalid position, should be 16, 32, 64 or 128."); + value = 0; + } + insn |= (value << 2); + return insn; +} + +static long long +extract_nps_imm_entry (unsigned long long insn, + bool *invalid ATTRIBUTE_UNUSED) +{ + int imm_entry = ((insn >> 2) & 0x7); + return (1 << (imm_entry + 4)); +} + +static unsigned long long +insert_nps_size_16bit (unsigned long long insn, + long long value, + const char **errmsg) +{ + if ((value < 1) || (value > 64)) + { + *errmsg = _("invalid size value must be on range 1-64."); + value = 0; + } + value = value & 0x3f; + insn |= (value << 6); + return insn; +} + +static long long +extract_nps_size_16bit (unsigned long long insn, + bool *invalid ATTRIBUTE_UNUSED) +{ + return ((insn & 0xfc0) >> 6) ? ((insn & 0xfc0) >> 6) : 64; +} + + +#define MAKE_SRC_POS_INSERT_EXTRACT_FUNCS(NAME,SHIFT) \ + static unsigned long long \ + insert_nps_##NAME##_pos (unsigned long long insn, \ + long long value, \ + const char **errmsg) \ +{ \ + switch (value) \ + { \ + case 0: \ + case 8: \ + case 16: \ + case 24: \ + value = value / 8; \ + break; \ + default: \ + *errmsg = _("invalid position, should be 0, 8, 16, or 24"); \ + value = 0; \ + } \ + insn |= (value << SHIFT); \ + return insn; \ +} \ + \ + static long long \ + extract_nps_##NAME##_pos (unsigned long long insn, \ + bool *invalid ATTRIBUTE_UNUSED) \ + { \ + return ((insn >> SHIFT) & 0x3) * 8; \ + } + +MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src2, 12) +MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src1, 10) + +#define MAKE_BIAS_INSERT_EXTRACT_FUNCS(NAME,LOWER,UPPER,BITS,BIAS,SHIFT) \ +static unsigned long long \ +insert_nps_##NAME (unsigned long long insn, \ + long long value, \ + const char **errmsg) \ +{ \ + if (value < LOWER || value > UPPER) \ + { \ + *errmsg = _("invalid size, value must be " \ + #LOWER " to " #UPPER "."); \ + return insn; \ + } \ + value -= BIAS; \ + insn |= (value << SHIFT); \ + return insn; \ +} \ + \ +static long long \ +extract_nps_##NAME (unsigned long long insn, \ + bool *invalid ATTRIBUTE_UNUSED) \ +{ \ + return ((insn >> SHIFT) & ((1 << BITS) - 1)) + BIAS; \ +} + +MAKE_BIAS_INSERT_EXTRACT_FUNCS (addb_size,2,32,5,1,5) +MAKE_BIAS_INSERT_EXTRACT_FUNCS (andb_size,1,32,5,1,5) +MAKE_BIAS_INSERT_EXTRACT_FUNCS (fxorb_size,8,32,5,8,5) +MAKE_BIAS_INSERT_EXTRACT_FUNCS (wxorb_size,16,32,5,16,5) +MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop_size,1,32,5,1,10) +MAKE_BIAS_INSERT_EXTRACT_FUNCS (qcmp_size,1,8,3,1,9) +MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop1_size,1,32,5,1,20) +MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop2_size,1,32,5,1,25) +MAKE_BIAS_INSERT_EXTRACT_FUNCS (hash_width,1,32,5,1,6) +MAKE_BIAS_INSERT_EXTRACT_FUNCS (hash_len,1,8,3,1,2) +MAKE_BIAS_INSERT_EXTRACT_FUNCS (index3,4,7,2,4,0) + +static long long +extract_nps_qcmp_m3 (unsigned long long insn, + bool *invalid) +{ + int m3 = (insn >> 5) & 0xf; + if (m3 == 0xf) + *invalid = true; + return m3; +} + +static long long +extract_nps_qcmp_m2 (unsigned long long insn, + bool *invalid) +{ + bool tmp_invalid = false; + int m2 = (insn >> 15) & 0x1; + int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid); + + if (m2 == 0 && m3 == 0xf) + *invalid = true; + return m2; +} + +static long long +extract_nps_qcmp_m1 (unsigned long long insn, + bool *invalid) +{ + bool tmp_invalid = false; + int m1 = (insn >> 14) & 0x1; + int m2 = extract_nps_qcmp_m2 (insn, &tmp_invalid); + int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid); + + if (m1 == 0 && m2 == 0 && m3 == 0xf) + *invalid = true; + return m1; +} + +static unsigned long long +insert_nps_calc_entry_size (unsigned long long insn, + long long value, + const char **errmsg) +{ + unsigned pwr; + + if (value < 1 || value > 256) + { + *errmsg = _("value out of range 1 - 256"); + return 0; + } + + for (pwr = 0; (value & 1) == 0; value >>= 1) + ++pwr; + + if (value != 1) + { + *errmsg = _("value must be power of 2"); + return 0; + } + + return insn | (pwr << 8); +} + +static long long +extract_nps_calc_entry_size (unsigned long long insn, + bool *invalid ATTRIBUTE_UNUSED) +{ + unsigned entry_size = (insn >> 8) & 0xf; + return 1 << entry_size; +} + +static unsigned long long +insert_nps_bitop_mod4 (unsigned long long insn, + long long value, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn | ((value & 0x2) << 30) | ((value & 0x1) << 47); +} + +static long long +extract_nps_bitop_mod4 (unsigned long long insn, + bool *invalid ATTRIBUTE_UNUSED) +{ + return ((insn >> 30) & 0x2) | ((insn >> 47) & 0x1); +} + +static unsigned long long +insert_nps_bitop_dst_pos3_pos4 (unsigned long long insn, + long long value, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn | (value << 42) | (value << 37); +} + +static long long +extract_nps_bitop_dst_pos3_pos4 (unsigned long long insn, + bool *invalid) +{ + if (((insn >> 42) & 0x1f) != ((insn >> 37) & 0x1f)) + *invalid = true; + return ((insn >> 37) & 0x1f); +} + +static unsigned long long +insert_nps_bitop_ins_ext (unsigned long long insn, + long long value, + const char **errmsg) +{ + if (value < 0 || value > 28) + *errmsg = _("value must be in the range 0 to 28"); + return insn | (value << 20); +} + +static long long +extract_nps_bitop_ins_ext (unsigned long long insn, + bool *invalid) +{ + int value = (insn >> 20) & 0x1f; + + if (value > 28) + *invalid = true; + return value; +} + +#define MAKE_1BASED_INSERT_EXTRACT_FUNCS(NAME,SHIFT,UPPER,BITS) \ +static unsigned long long \ +insert_nps_##NAME (unsigned long long insn, \ + long long value, \ + const char **errmsg) \ +{ \ + if (value < 1 || value > UPPER) \ + *errmsg = _("value must be in the range 1 to " #UPPER); \ + if (value == UPPER) \ + value = 0; \ + return insn | (value << SHIFT); \ +} \ + \ +static long long \ +extract_nps_##NAME (unsigned long long insn, \ + bool *invalid ATTRIBUTE_UNUSED) \ +{ \ + int value = (insn >> SHIFT) & ((1 << BITS) - 1); \ + if (value == 0) \ + value = UPPER; \ + return value; \ +} + +MAKE_1BASED_INSERT_EXTRACT_FUNCS (field_size, 6, 8, 3) +MAKE_1BASED_INSERT_EXTRACT_FUNCS (shift_factor, 9, 8, 3) +MAKE_1BASED_INSERT_EXTRACT_FUNCS (bits_to_scramble, 12, 8, 3) +MAKE_1BASED_INSERT_EXTRACT_FUNCS (bdlen_max_len, 5, 256, 8) +MAKE_1BASED_INSERT_EXTRACT_FUNCS (bd_num_buff, 6, 8, 3) +MAKE_1BASED_INSERT_EXTRACT_FUNCS (pmu_num_job, 6, 4, 2) +MAKE_1BASED_INSERT_EXTRACT_FUNCS (proto_size, 16, 64, 6) + +static unsigned long long +insert_nps_min_hofs (unsigned long long insn, + long long value, + const char **errmsg) +{ + if (value < 0 || value > 240) + *errmsg = _("value must be in the range 0 to 240"); + if ((value % 16) != 0) + *errmsg = _("value must be a multiple of 16"); + value = value / 16; + return insn | (value << 6); +} + +static long long +extract_nps_min_hofs (unsigned long long insn, + bool *invalid ATTRIBUTE_UNUSED) +{ + int value = (insn >> 6) & 0xF; + return value * 16; +} + +#define MAKE_INSERT_NPS_ADDRTYPE(NAME, VALUE) \ + static unsigned long long \ +insert_nps_##NAME (unsigned long long insn, \ + long long value, \ + const char **errmsg) \ +{ \ + if (value != ARC_NPS400_ADDRTYPE_##VALUE) \ + *errmsg = _("invalid address type for operand"); \ + return insn; \ +} \ + \ +static long long \ +extract_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \ + bool *invalid ATTRIBUTE_UNUSED) \ +{ \ + return ARC_NPS400_ADDRTYPE_##VALUE; \ +} + +MAKE_INSERT_NPS_ADDRTYPE (bd, BD) +MAKE_INSERT_NPS_ADDRTYPE (jid, JID) +MAKE_INSERT_NPS_ADDRTYPE (lbd, LBD) +MAKE_INSERT_NPS_ADDRTYPE (mbd, MBD) +MAKE_INSERT_NPS_ADDRTYPE (sd, SD) +MAKE_INSERT_NPS_ADDRTYPE (sm, SM) +MAKE_INSERT_NPS_ADDRTYPE (xa, XA) +MAKE_INSERT_NPS_ADDRTYPE (xd, XD) +MAKE_INSERT_NPS_ADDRTYPE (cd, CD) +MAKE_INSERT_NPS_ADDRTYPE (cbd, CBD) +MAKE_INSERT_NPS_ADDRTYPE (cjid, CJID) +MAKE_INSERT_NPS_ADDRTYPE (clbd, CLBD) +MAKE_INSERT_NPS_ADDRTYPE (cm, CM) +MAKE_INSERT_NPS_ADDRTYPE (csd, CSD) +MAKE_INSERT_NPS_ADDRTYPE (cxa, CXA) +MAKE_INSERT_NPS_ADDRTYPE (cxd, CXD) + +static unsigned long long +insert_nps_rbdouble_64 (unsigned long long insn, + long long value, + const char **errmsg) +{ + if (value < 0 || value > 31) + *errmsg = _("value must be in the range 0 to 31"); + return insn | (value << 43) | (value << 48); +} + + +static long long +extract_nps_rbdouble_64 (unsigned long long insn, + bool *invalid) +{ + int value1 = (insn >> 43) & 0x1F; + int value2 = (insn >> 48) & 0x1F; + + if (value1 != value2) + *invalid = true; + + return value1; +} + +static unsigned long long +insert_nps_misc_imm_offset (unsigned long long insn, + long long value, + const char **errmsg) +{ + if (value & 0x3) + { + *errmsg = _("invalid position, should be one of: 0,4,8,...124."); + value = 0; + } + insn |= (value << 6); + return insn; +} + +static long long int +extract_nps_misc_imm_offset (unsigned long long insn, + bool *invalid ATTRIBUTE_UNUSED) +{ + return ((insn >> 8) & 0x1f) * 4; +} + +static long long int +extract_uimm12_20 (unsigned long long insn ATTRIBUTE_UNUSED, + bool *invalid ATTRIBUTE_UNUSED) +{ + int value = 0; + + value |= ((insn >> 6) & 0x003f) << 0; + value |= ((insn >> 0) & 0x003f) << 6; + + return value; +} + +/* Include the generic extract/insert functions. Order is important + as some of the functions present in the .h may be disabled via + defines. */ +#include "arc-fxi.h" + +/* The flag operands enum. */ +#define FLAG(NAME, NAMESTR, CODE, BITS, SHIFT, FAVAIL) \ + F_##NAME, +enum arc_flag_operand_enum { + F_INVALID = -1, + F_NULL = 0, +#include "arc-flag.def" + F_SIZE, +}; +#undef FLAG + +/* The flag operands name. */ +#define FLAG(NAME, NAMESTR, CODE, BITS, SHIFT, FAVAIL) \ + "F_" #NAME, +const char *flag_operand_name[F_SIZE] = { + "F_NULL", +#include "arc-flag.def" +}; +#undef FLAG + +/* The flag operands table. + + The format of the table is + NAME CODE BITS SHIFT FAVAIL. */ +#define FLAG(NAME, NAMESTR, CODE, BITS, SHIFT, FAVAIL) \ + [F_##NAME] = { NAMESTR, CODE, BITS, SHIFT, FAVAIL }, +const struct arc_flag_operand arc_flag_operands[F_SIZE] = +{ + [F_NULL] = { 0, 0, 0, 0, 0 }, + #include "arc-flag.def" +}; +#undef FLAG + +const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands); + +/* Enum of the flag classes. */ +#define FLAG_CLASS(NAME, CLASS, INSERT_FN, EXTRACT_FN, ...) \ + C_##NAME, +enum arc_flag_class_enum { + C_INVALID = -1, + #include "arc-flag-classes.def" + C_SIZE +}; +#undef FLAG_CLASS + +/* Table of the flag classes. + + The format of the table is + CLASS {FLAG_CODE}. */ +#define FLAG_CLASS(NAME, CLASS, INSERT_FN, EXTRACT_FN, ...) \ + [C_##NAME] = { \ + .flag_class = CLASS, \ + .insert = INSERT_FN, \ + .extract = EXTRACT_FN, \ + .flags = { __VA_ARGS__, F_NULL } \ + }, +const struct arc_flag_class arc_flag_classes[C_SIZE] = +{ + #include "arc-flag-classes.def" +}; +#undef FLAG_CLASS + +const unsigned char flags_none[] = { 0 }; +const unsigned char flags_f[] = { C_F }; +const unsigned char flags_cc[] = { C_CC }; +const unsigned char flags_ccf[] = { C_CC, C_F }; + +/* The operands enum. */ +#define ARC_OPERAND(NAME, BITS, SHIFT, RELO, FLAGS, INSERT_FN, EXTRACT_FN) \ + NAME, +enum arc_operand_enum { + ARC_OPERAND_INVALID = -1, + UNUSED = 0, +#include "arc-operands.def" + ARC_OPERAND_SIZE +}; +#undef ARC_OPERAND + +/* The operands name. */ +#define ARC_OPERAND(NAME, BITS, SHIFT, RELO, FLAGS, INSERT_FN, EXTRACT_FN) \ + #NAME, +const char *arc_operand_name[ARC_OPERAND_SIZE] = { + "UNUSED", +#include "arc-operands.def" +}; +#undef ARC_OPERAND +/* The operands table. + + The format of the operands table is: + + BITS SHIFT DEFAULT_RELOC FLAGS INSERT_FUN EXTRACT_FUN. */ +#define ARC_OPERAND(NAME, BITS, SHIFT, RELOC, FLAGS, INSERT_FN, EXTRACT_FN) \ + [NAME] = { \ + .bits = BITS, \ + .shift = SHIFT, \ + .default_reloc = RELOC, \ + .flags = FLAGS, \ + .insert = INSERT_FN, \ + .extract = EXTRACT_FN \ + }, +const struct arc_operand arc_operands[ARC_OPERAND_SIZE] = +{ + /* The fields are bits, shift, insert, extract, flags. The zero + index is used to indicate end-of-list. */ + [UNUSED] = { 0, 0, 0, 0, 0, 0 }, +#include "arc-operands.def" +}; +#undef ARC_OPERAND + +const unsigned arc_num_operands = ARRAY_SIZE (arc_operands); + +const unsigned arc_Toperand = FKT_T; +const unsigned arc_NToperand = FKT_NT; + +const unsigned char arg_none[] = { 0 }; +const unsigned char arg_32bit_rarbrc[] = { RA, RB, RC }; +const unsigned char arg_32bit_zarbrc[] = { ZA, RB, RC }; +const unsigned char arg_32bit_rbrbrc[] = { RB, RBdup, RC }; +const unsigned char arg_32bit_rarbu6[] = { RA, RB, UIMM6_20 }; +const unsigned char arg_32bit_zarbu6[] = { ZA, RB, UIMM6_20 }; +const unsigned char arg_32bit_rbrbu6[] = { RB, RBdup, UIMM6_20 }; +const unsigned char arg_32bit_rbrbs12[] = { RB, RBdup, SIMM12_20 }; +const unsigned char arg_32bit_ralimmrc[] = { RA, LIMM, RC }; +const unsigned char arg_32bit_rarblimm[] = { RA, RB, LIMM }; +const unsigned char arg_32bit_zalimmrc[] = { ZA, LIMM, RC }; +const unsigned char arg_32bit_zarblimm[] = { ZA, RB, LIMM }; + +const unsigned char arg_32bit_rbrblimm[] = { RB, RBdup, LIMM }; +const unsigned char arg_32bit_ralimmu6[] = { RA, LIMM, UIMM6_20 }; +const unsigned char arg_32bit_zalimmu6[] = { ZA, LIMM, UIMM6_20 }; + +const unsigned char arg_32bit_zalimms12[] = { ZA, LIMM, SIMM12_20 }; +const unsigned char arg_32bit_ralimmlimm[] = { RA, LIMM, LIMMdup }; +const unsigned char arg_32bit_zalimmlimm[] = { ZA, LIMM, LIMMdup }; + +const unsigned char arg_32bit_rbrc[] = { RB, RC }; +const unsigned char arg_32bit_zarc[] = { ZA, RC }; +const unsigned char arg_32bit_rbu6[] = { RB, UIMM6_20 }; +const unsigned char arg_32bit_zau6[] = { ZA, UIMM6_20 }; +const unsigned char arg_32bit_rblimm[] = { RB, LIMM }; +const unsigned char arg_32bit_zalimm[] = { ZA, LIMM }; + +const unsigned char arg_32bit_limmrc[] = { LIMM, RC }; +const unsigned char arg_32bit_limmu6[] = { LIMM, UIMM6_20 }; +const unsigned char arg_32bit_limms12[] = { LIMM, SIMM12_20 }; +const unsigned char arg_32bit_limmlimm[] = { LIMM, LIMMdup }; + +const unsigned char arg_32bit_rc[] = { RC }; +const unsigned char arg_32bit_u6[] = { UIMM6_20 }; +const unsigned char arg_32bit_limm[] = { LIMM }; + +/* List with special cases instructions and the applicable flags. */ +const struct arc_flag_special arc_flag_special_cases[] = +{ + { "b", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, + F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, + F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, + F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NJ, F_NM, + F_NO_T, F_NULL } }, + { "bl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, + F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, + F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, + F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, + F_NULL } }, + { "br", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, + F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, + F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, + F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, + F_NULL } }, + { "j", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, + F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, + F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, + F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, + F_NULL } }, + { "jl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, + F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, + F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, + F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, + F_NULL } }, + { "lp", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, + F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, + F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, + F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, + F_NULL } }, + { "set", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, + F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, + F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, + F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, + F_NULL } }, + { "ld", { F_SIZEB17, F_SIZEW17, F_H17, F_NULL } }, + { "st", { F_SIZEB1, F_SIZEW1, F_H1, F_NULL } } +}; + +const unsigned arc_num_flag_special = ARRAY_SIZE (arc_flag_special_cases); + +/* Relocations. */ +const struct arc_reloc_equiv_tab arc_reloc_equiv[] = +{ + { "sda", "ld", { F_ASFAKE, F_H1, F_NULL }, + BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 }, + { "sda", "st", { F_ASFAKE, F_H1, F_NULL }, + BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 }, + { "sda", "ld", { F_ASFAKE, F_SIZEW7, F_NULL }, + BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 }, + { "sda", "st", { F_ASFAKE, F_SIZEW7, F_NULL }, + BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 }, + + /* Next two entries will cover the undefined behavior ldb/stb with + address scaling. */ + { "sda", "ld", { F_ASFAKE, F_SIZEB7, F_NULL }, + BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST }, + { "sda", "st", { F_ASFAKE, F_SIZEB7, F_NULL }, + BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST}, + + { "sda", "ld", { F_ASFAKE, F_NULL }, + BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 }, + { "sda", "st", { F_ASFAKE, F_NULL }, + BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2}, + { "sda", "ldd", { F_ASFAKE, F_NULL }, + BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 }, + { "sda", "std", { F_ASFAKE, F_NULL }, + BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2}, + + /* Short instructions. */ + { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD, BFD_RELOC_ARC_SDA16_LD }, + { "sda", 0, { F_NULL }, -SIMM10_A16_7_Sbis, BFD_RELOC_ARC_SDA16_LD1 }, + { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD2, BFD_RELOC_ARC_SDA16_LD2 }, + { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_ST2, BFD_RELOC_ARC_SDA16_ST2 }, + + { "sda", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_SDA32_ME }, + { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST }, + + { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25H_PCREL, + BFD_RELOC_ARC_S25H_PCREL_PLT }, + { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21H_PCREL, + BFD_RELOC_ARC_S21H_PCREL_PLT }, + { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25W_PCREL, + BFD_RELOC_ARC_S25W_PCREL_PLT }, + { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21W_PCREL, + BFD_RELOC_ARC_S21W_PCREL_PLT }, + + { "plt", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_PLT32 } +}; + +const unsigned arc_num_equiv_tab = ARRAY_SIZE (arc_reloc_equiv); + +const struct arc_pseudo_insn arc_pseudo_insns[] = +{ + { "push", "st", ".aw", 5, { { RC, 0, 0, 0 }, { BRAKET, 1, 0, 1 }, + { RB, 1, 28, 2 }, { SIMM9_8, 1, -4, 3 }, + { BRAKETdup, 1, 0, 4} } }, + { "pop", "ld", ".ab", 5, { { RA, 0, 0, 0 }, { BRAKET, 1, 0, 1 }, + { RB, 1, 28, 2 }, { SIMM9_8, 1, 4, 3 }, + { BRAKETdup, 1, 0, 4} } }, + + { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 }, + { SIMM9_A16_8, 0, 0, 2 } } }, + { "brgt", "brge", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, + { SIMM9_A16_8, 0, 0, 2 } } }, + { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 }, + { SIMM9_A16_8, 0, 0, 2 } } }, + { "brgt", "brlt", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 }, + { SIMM9_A16_8, 0, 0, 2 } } }, + { "brgt", "brge", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, + { SIMM9_A16_8, 0, 0, 2 } } }, + + { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 }, + { SIMM9_A16_8, 0, 0, 2 } } }, + { "brhi", "brhs", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, + { SIMM9_A16_8, 0, 0, 2 } } }, + { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 }, + { SIMM9_A16_8, 0, 0, 2 } } }, + { "brhi", "brlo", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 }, + { SIMM9_A16_8, 0, 0, 2 } } }, + { "brhi", "brhs", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, + { SIMM9_A16_8, 0, 0, 2 } } }, + + { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 }, + { SIMM9_A16_8, 0, 0, 2 } } }, + { "brle", "brlt", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, + { SIMM9_A16_8, 0, 0, 2 } } }, + { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 }, + { SIMM9_A16_8, 0, 0, 2 } } }, + { "brle", "brge", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 }, + { SIMM9_A16_8, 0, 0, 2 } } }, + { "brle", "brlt", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, + { SIMM9_A16_8, 0, 0, 2 } } }, + + { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 }, + { SIMM9_A16_8, 0, 0, 2 } } }, + { "brls", "brlo", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, + { SIMM9_A16_8, 0, 0, 2 } } }, + { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 }, + { SIMM9_A16_8, 0, 0, 2 } } }, + { "brls", "brhs", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 }, + { SIMM9_A16_8, 0, 0, 2 } } }, + { "brls", "brlo", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, + { SIMM9_A16_8, 0, 0, 2 } } }, +}; + +const unsigned arc_num_pseudo_insn = + sizeof (arc_pseudo_insns) / sizeof (*arc_pseudo_insns); + +/* ARC64 pseudo instructions. */ +const struct arc_pseudo_insn arc64_pseudo_insns[] = +{ + { "pushl", "stl", ".aw", 5, { { RC, 0, 0, 0 }, { BRAKET, 1, 0, 1 }, + { RB, 1, 28, 2 }, { SIMM9_8, 1, -8, 3 }, + { BRAKETdup, 1, 0, 4} } }, + { "popl", "ldl", ".ab", 5, { { RA, 0, 0, 0 }, { BRAKET, 1, 0, 1 }, + { RB, 1, 28, 2 }, { SIMM9_8, 1, 8, 3 }, + { BRAKETdup, 1, 0, 4} } }, +}; + +const unsigned arc64_num_pseudo_insn = + sizeof (arc64_pseudo_insns) / sizeof (*arc64_pseudo_insns); + +const struct arc_aux_reg arc_aux_regs[] = +{ +#undef DEF +#define DEF(ADDR, CPU, SUBCLASS, NAME) \ + { ADDR, CPU, SUBCLASS, #NAME, sizeof (#NAME)-1 }, + +#include "arc-regs.h" + +#undef DEF +}; + +const unsigned arc_num_aux_regs = ARRAY_SIZE (arc_aux_regs); + +/* NOTE: The order of this array MUST be consistent with 'enum + arc_rlx_types' located in tc-arc.h! */ +const struct arc_opcode arc_relax_opcodes[] = +{ + { NULL, 0x0, 0x0, 0x0, ARITH, NONE, { UNUSED }, { 0 } }, + + /* bl_s s13 11111sssssssssss. */ + { "bl_s", 0x0000F800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 + | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, + { SIMM13_A32_5_S }, { 0 }}, + + /* bl<.d> s25 00001sssssssss10SSSSSSSSSSNRtttt. */ + { "bl", 0x08020000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 + | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, + { SIMM25_A32_5 }, { C_D }}, + + /* b_s s10 1111000sssssssss. */ + { "b_s", 0x0000F000, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 + | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, + { SIMM10_A16_7_S }, { 0 }}, + + /* b<.d> s25 00000ssssssssss1SSSSSSSSSSNRtttt. */ + { "b", 0x00010000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 + | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, + { SIMM25_A16_5 }, { C_D }}, + + /* add_s c,b,u3 01101bbbccc00uuu. */ + { "add_s", 0x00006800, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 + | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, + { RC_S, RB_S, UIMM3_13R_S }, { 0 }}, + + /* add<.f> a,b,u6 00100bbb01000000FBBBuuuuuuAAAAAA. */ + { "add", 0x20400000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 + | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, + { RA, RB, UIMM6_20R }, { C_F }}, + + /* add<.f> a,b,limm 00100bbb00000000FBBB111110AAAAAA. */ + { "add", 0x20000F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 + | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, + { RA, RB, LIMM }, { C_F }}, + + /* ld_s c,b,u7 10000bbbcccuuuuu. */ + { "ld_s", 0x00008000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 + | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, + { RC_S, BRAKET, RB_S, UIMM7_A32_11R_S, BRAKETdup }, { 0 }}, + + /* ld<.di><.aa><.x><zz> a,b,s9 + 00010bbbssssssssSBBBDaaZZXAAAAAA. */ + { "ld", 0x10000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 + | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, + { RA, BRAKET, RB, SIMM9_8R, BRAKETdup }, + { C_ZZ23, C_DI20, C_AA21, C_X25 }}, + + /* ld<.di><.aa><.x><zz> a,b,limm 00100bbbaa110ZZXDBBB111110AAAAAA. */ + { "ld", 0x20300F80, 0xF8380FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 + | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, + { RA, BRAKET, RB, LIMM, BRAKETdup }, + { C_ZZ13, C_DI16, C_AA8, C_X15 }}, + + /* mov_s b,u8 11011bbbuuuuuuuu. */ + { "mov_s", 0x0000D800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 + | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, + { RB_S, UIMM8_8R_S }, { 0 }}, + + /* mov<.f> b,s12 00100bbb10001010FBBBssssssSSSSSS. */ + { "mov", 0x208A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 + | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, + { RB, SIMM12_20R }, { C_F }}, + + /* mov<.f> b,limm 00100bbb00001010FBBB111110RRRRRR. */ + { "mov", 0x200A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 + | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, + { RB, LIMM }, { C_F }}, + + /* sub_s c,b,u3 01101bbbccc01uuu. */ + { "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 + | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, + { RC_S, RB_S, UIMM3_13R_S }, { 0 }}, + + /* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA. */ + { "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 + | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, + { RA, RB, UIMM6_20R }, { C_F }}, + + /* sub<.f> a,b,limm 00100bbb00000010FBBB111110AAAAAA. */ + { "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 + | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, + { RA, RB, LIMM }, { C_F }}, + + /* mpy<.f> a,b,u6 00100bbb01011010FBBBuuuuuuAAAAAA. */ + { "mpy", 0x205A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM + | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, UIMM6_20R }, { C_F }}, + + /* mpy<.f> a,b,limm 00100bbb00011010FBBB111110AAAAAA. */ + { "mpy", 0x201A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM + | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, LIMM }, { C_F }}, + + /* mov<.f><.cc> b,u6 00100bbb11001010FBBBuuuuuu1QQQQQ. */ + { "mov", 0x20CA0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 + | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, + { RB, UIMM6_20R }, { C_F, C_CC }}, + + /* mov<.f><.cc> b,limm 00100bbb11001010FBBB1111100QQQQQ. */ + { "mov", 0x20CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 + | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, + { RB, LIMM }, { C_F, C_CC }}, + + /* add<.f><.cc> b,b,u6 00100bbb11000000FBBBuuuuuu1QQQQQ. */ + { "add", 0x20C00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 + | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, + { RB, RBdup, UIMM6_20R }, { C_F, C_CC }}, + + /* add<.f><.cc> b,b,limm 00100bbb11000000FBBB1111100QQQQQ. */ + { "add", 0x20C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 + | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, + { RB, RBdup, LIMM }, { C_F, C_CC }} +}; + +const unsigned arc_num_relax_opcodes = ARRAY_SIZE (arc_relax_opcodes); + +/* Return length of an opcode in bytes. */ + +int +arc_opcode_len (const struct arc_opcode *opcode) +{ + if (opcode->mask < 0x10000ull) + return 2; + + if (opcode->mask < 0x100000000ull) + return 4; + + if (opcode->mask < 0x1000000000000ull) + return 6; + + return 8; +} diff --git a/opcodes/configure b/opcodes/configure index a65b0a2f95b..f1c077f4d42 100755 --- a/opcodes/configure +++ b/opcodes/configure @@ -12551,6 +12551,7 @@ if test x${all_targets} = xfalse ; then bfd_alpha_arch) ta="$ta alpha-dis.lo alpha-opc.lo" ;; bfd_amdgcn_arch) ;; bfd_arc_arch) ta="$ta arc-dis.lo arc-opc.lo arc-ext.lo" ;; + bfd_arc64_arch) ta="$ta arc-dis.lo arc64-opc.lo arc-ext.lo" ;; bfd_arm_arch) ta="$ta arm-dis.lo" ;; bfd_avr_arch) ta="$ta avr-dis.lo" ;; bfd_bfin_arch) ta="$ta bfin-dis.lo" ;; diff --git a/opcodes/configure.ac b/opcodes/configure.ac index cae2a67ff10..d11257453b2 100644 --- a/opcodes/configure.ac +++ b/opcodes/configure.ac @@ -268,6 +268,7 @@ if test x${all_targets} = xfalse ; then bfd_alpha_arch) ta="$ta alpha-dis.lo alpha-opc.lo" ;; bfd_amdgcn_arch) ;; bfd_arc_arch) ta="$ta arc-dis.lo arc-opc.lo arc-ext.lo" ;; + bfd_arc64_arch) ta="$ta arc-dis.lo arc64-opc.lo arc-ext.lo" ;; bfd_arm_arch) ta="$ta arm-dis.lo" ;; bfd_avr_arch) ta="$ta avr-dis.lo" ;; bfd_bfin_arch) ta="$ta bfin-dis.lo" ;; diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c index 3067445485b..dff0995c926 100644 --- a/opcodes/disassemble.c +++ b/opcodes/disassemble.c @@ -38,6 +38,7 @@ #define ARCH_tilegx #endif #define ARCH_arc +#define ARCH_arc64 #define ARCH_arm #define ARCH_avr #define ARCH_bfin @@ -136,6 +137,11 @@ disassembler (enum bfd_architecture a, disassemble = arc_get_disassembler (abfd); break; #endif +#ifdef ARCH_arc64 + case bfd_arch_arc64: + disassemble = arc_get_disassembler (abfd); + break; +#endif #ifdef ARCH_arm case bfd_arch_arm: if (big) -- 2.30.2 ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2023-09-19 8:13 UTC | newest] Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2023-09-19 8:12 [PATCH 0/7] arc: Add new ARCv3 isa support to ARC's backend Claudiu Zissulescu 2023-09-19 8:12 ` [PATCH 1/7] arc: Add new GAS tests for ARCv3 Claudiu Zissulescu 2023-09-19 8:12 ` [PATCH 2/7] arc: Add new LD " Claudiu Zissulescu 2023-09-19 8:12 ` [PATCH 3/7] arc: Add new ARCv3 ISA to BFD Claudiu Zissulescu 2023-09-19 8:12 ` [PATCH 4/7] arc: Add new linker emulation and scripts for ARCv3 ISA Claudiu Zissulescu 2023-09-19 8:12 ` [PATCH 5/7] arc: Update opcode related include files for ARCv3 Claudiu Zissulescu 2023-09-19 8:12 ` [PATCH 6/7] arc: Update ARC's Gnu Assembler backend with ARCv3 ISA Claudiu Zissulescu 2023-09-19 8:12 ` [PATCH 7/7] arc: Add new opcode functions for " Claudiu Zissulescu
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