From: Jin Ma <jinma@linux.alibaba.com>
To: binutils@sourceware.org, nelson@rivosinc.com
Cc: christoph.muellner@vrull.eu, lifang_xia@linux.alibaba.com,
jinma.contrib@gmail.com, Jin Ma <jinma@linux.alibaba.com>
Subject: [PATCH v2 09/12] RISC-V: Add floating-point arithmetic instructions for T-Head VECTOR vendor extension
Date: Sat, 18 Nov 2023 15:07:39 +0800 [thread overview]
Message-ID: <20231118070739.1469-1-jinma@linux.alibaba.com> (raw)
In-Reply-To: <20231118064928.849-1-jinma@linux.alibaba.com>
T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.
This patch adds floating-point arithmetic instructions for the
"XTheadVector" extension. The 'th' prefix and the
"XTheadVector" extension are documented in a PR for the
RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>
gas/ChangeLog:
* testsuite/gas/riscv/x-thead-vector.d: Add tests for
floating-point arithmetic instructions.
* testsuite/gas/riscv/x-thead-vector.s: Likewise.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_TH_VFSQRTV): New.
opcodes/ChangeLog:
* riscv-opc.c: Likewise.
---
gas/testsuite/gas/riscv/x-thead-vector.d | 170 ++++++++++++++++++++
gas/testsuite/gas/riscv/x-thead-vector.s | 188 +++++++++++++++++++++++
include/opcode/riscv-opc.h | 36 +++++
opcodes/riscv-opc.c | 86 +++++++++++
4 files changed, 480 insertions(+)
diff --git a/gas/testsuite/gas/riscv/x-thead-vector.d b/gas/testsuite/gas/riscv/x-thead-vector.d
index bbcf6d4890a..178e2465110 100644
--- a/gas/testsuite/gas/riscv/x-thead-vector.d
+++ b/gas/testsuite/gas/riscv/x-thead-vector.d
@@ -1390,3 +1390,173 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+bc85c257[ ]+th.vnclip.vx[ ]+v4,v8,a1,v0.t
[ ]+[0-9a-f]+:[ ]+bc80b257[ ]+th.vnclip.vi[ ]+v4,v8,1,v0.t
[ ]+[0-9a-f]+:[ ]+bc8fb257[ ]+th.vnclip.vi[ ]+v4,v8,31,v0.t
+[ ]+[0-9a-f]+:[ ]+02861257[ ]+th.vfadd.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+02865257[ ]+th.vfadd.vf[ ]+v4,v8,fa2
+[ ]+[0-9a-f]+:[ ]+00861257[ ]+th.vfadd.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+00865257[ ]+th.vfadd.vf[ ]+v4,v8,fa2,v0.t
+[ ]+[0-9a-f]+:[ ]+0a861257[ ]+th.vfsub.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+0a865257[ ]+th.vfsub.vf[ ]+v4,v8,fa2
+[ ]+[0-9a-f]+:[ ]+08861257[ ]+th.vfsub.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+08865257[ ]+th.vfsub.vf[ ]+v4,v8,fa2,v0.t
+[ ]+[0-9a-f]+:[ ]+9e865257[ ]+th.vfrsub.vf[ ]+v4,v8,fa2
+[ ]+[0-9a-f]+:[ ]+9c865257[ ]+th.vfrsub.vf[ ]+v4,v8,fa2,v0.t
+[ ]+[0-9a-f]+:[ ]+c2861257[ ]+th.vfwadd.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+c2865257[ ]+th.vfwadd.vf[ ]+v4,v8,fa2
+[ ]+[0-9a-f]+:[ ]+c0861257[ ]+th.vfwadd.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+c0865257[ ]+th.vfwadd.vf[ ]+v4,v8,fa2,v0.t
+[ ]+[0-9a-f]+:[ ]+ca861257[ ]+th.vfwsub.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+ca865257[ ]+th.vfwsub.vf[ ]+v4,v8,fa2
+[ ]+[0-9a-f]+:[ ]+c8861257[ ]+th.vfwsub.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+c8865257[ ]+th.vfwsub.vf[ ]+v4,v8,fa2,v0.t
+[ ]+[0-9a-f]+:[ ]+d2861257[ ]+th.vfwadd.wv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+d2865257[ ]+th.vfwadd.wf[ ]+v4,v8,fa2
+[ ]+[0-9a-f]+:[ ]+d0861257[ ]+th.vfwadd.wv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+d0865257[ ]+th.vfwadd.wf[ ]+v4,v8,fa2,v0.t
+[ ]+[0-9a-f]+:[ ]+da861257[ ]+th.vfwsub.wv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+da865257[ ]+th.vfwsub.wf[ ]+v4,v8,fa2
+[ ]+[0-9a-f]+:[ ]+d8861257[ ]+th.vfwsub.wv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+d8865257[ ]+th.vfwsub.wf[ ]+v4,v8,fa2,v0.t
+[ ]+[0-9a-f]+:[ ]+92861257[ ]+th.vfmul.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+92865257[ ]+th.vfmul.vf[ ]+v4,v8,fa2
+[ ]+[0-9a-f]+:[ ]+90861257[ ]+th.vfmul.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+90865257[ ]+th.vfmul.vf[ ]+v4,v8,fa2,v0.t
+[ ]+[0-9a-f]+:[ ]+82861257[ ]+th.vfdiv.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+82865257[ ]+th.vfdiv.vf[ ]+v4,v8,fa2
+[ ]+[0-9a-f]+:[ ]+80861257[ ]+th.vfdiv.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+80865257[ ]+th.vfdiv.vf[ ]+v4,v8,fa2,v0.t
+[ ]+[0-9a-f]+:[ ]+86865257[ ]+th.vfrdiv.vf[ ]+v4,v8,fa2
+[ ]+[0-9a-f]+:[ ]+84865257[ ]+th.vfrdiv.vf[ ]+v4,v8,fa2,v0.t
+[ ]+[0-9a-f]+:[ ]+e2861257[ ]+th.vfwmul.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+e2865257[ ]+th.vfwmul.vf[ ]+v4,v8,fa2
+[ ]+[0-9a-f]+:[ ]+e0861257[ ]+th.vfwmul.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+e0865257[ ]+th.vfwmul.vf[ ]+v4,v8,fa2,v0.t
+[ ]+[0-9a-f]+:[ ]+a2861257[ ]+th.vfmadd.vv[ ]+v4,v12,v8
+[ ]+[0-9a-f]+:[ ]+a2865257[ ]+th.vfmadd.vf[ ]+v4,fa2,v8
+[ ]+[0-9a-f]+:[ ]+a6861257[ ]+th.vfnmadd.vv[ ]+v4,v12,v8
+[ ]+[0-9a-f]+:[ ]+a6865257[ ]+th.vfnmadd.vf[ ]+v4,fa2,v8
+[ ]+[0-9a-f]+:[ ]+aa861257[ ]+th.vfmsub.vv[ ]+v4,v12,v8
+[ ]+[0-9a-f]+:[ ]+aa865257[ ]+th.vfmsub.vf[ ]+v4,fa2,v8
+[ ]+[0-9a-f]+:[ ]+ae861257[ ]+th.vfnmsub.vv[ ]+v4,v12,v8
+[ ]+[0-9a-f]+:[ ]+ae865257[ ]+th.vfnmsub.vf[ ]+v4,fa2,v8
+[ ]+[0-9a-f]+:[ ]+a0861257[ ]+th.vfmadd.vv[ ]+v4,v12,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+a0865257[ ]+th.vfmadd.vf[ ]+v4,fa2,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+a4861257[ ]+th.vfnmadd.vv[ ]+v4,v12,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+a4865257[ ]+th.vfnmadd.vf[ ]+v4,fa2,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+a8861257[ ]+th.vfmsub.vv[ ]+v4,v12,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+a8865257[ ]+th.vfmsub.vf[ ]+v4,fa2,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+ac861257[ ]+th.vfnmsub.vv[ ]+v4,v12,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+ac865257[ ]+th.vfnmsub.vf[ ]+v4,fa2,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+b2861257[ ]+th.vfmacc.vv[ ]+v4,v12,v8
+[ ]+[0-9a-f]+:[ ]+b2865257[ ]+th.vfmacc.vf[ ]+v4,fa2,v8
+[ ]+[0-9a-f]+:[ ]+b6861257[ ]+th.vfnmacc.vv[ ]+v4,v12,v8
+[ ]+[0-9a-f]+:[ ]+b6865257[ ]+th.vfnmacc.vf[ ]+v4,fa2,v8
+[ ]+[0-9a-f]+:[ ]+ba861257[ ]+th.vfmsac.vv[ ]+v4,v12,v8
+[ ]+[0-9a-f]+:[ ]+ba865257[ ]+th.vfmsac.vf[ ]+v4,fa2,v8
+[ ]+[0-9a-f]+:[ ]+be861257[ ]+th.vfnmsac.vv[ ]+v4,v12,v8
+[ ]+[0-9a-f]+:[ ]+be865257[ ]+th.vfnmsac.vf[ ]+v4,fa2,v8
+[ ]+[0-9a-f]+:[ ]+b0861257[ ]+th.vfmacc.vv[ ]+v4,v12,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+b0865257[ ]+th.vfmacc.vf[ ]+v4,fa2,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+b4861257[ ]+th.vfnmacc.vv[ ]+v4,v12,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+b4865257[ ]+th.vfnmacc.vf[ ]+v4,fa2,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+b8861257[ ]+th.vfmsac.vv[ ]+v4,v12,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+b8865257[ ]+th.vfmsac.vf[ ]+v4,fa2,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+bc861257[ ]+th.vfnmsac.vv[ ]+v4,v12,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+bc865257[ ]+th.vfnmsac.vf[ ]+v4,fa2,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+f2861257[ ]+th.vfwmacc.vv[ ]+v4,v12,v8
+[ ]+[0-9a-f]+:[ ]+f2865257[ ]+th.vfwmacc.vf[ ]+v4,fa2,v8
+[ ]+[0-9a-f]+:[ ]+f6861257[ ]+th.vfwnmacc.vv[ ]+v4,v12,v8
+[ ]+[0-9a-f]+:[ ]+f6865257[ ]+th.vfwnmacc.vf[ ]+v4,fa2,v8
+[ ]+[0-9a-f]+:[ ]+fa861257[ ]+th.vfwmsac.vv[ ]+v4,v12,v8
+[ ]+[0-9a-f]+:[ ]+fa865257[ ]+th.vfwmsac.vf[ ]+v4,fa2,v8
+[ ]+[0-9a-f]+:[ ]+fe861257[ ]+th.vfwnmsac.vv[ ]+v4,v12,v8
+[ ]+[0-9a-f]+:[ ]+fe865257[ ]+th.vfwnmsac.vf[ ]+v4,fa2,v8
+[ ]+[0-9a-f]+:[ ]+f0861257[ ]+th.vfwmacc.vv[ ]+v4,v12,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+f0865257[ ]+th.vfwmacc.vf[ ]+v4,fa2,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+f4861257[ ]+th.vfwnmacc.vv[ ]+v4,v12,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+f4865257[ ]+th.vfwnmacc.vf[ ]+v4,fa2,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+f8861257[ ]+th.vfwmsac.vv[ ]+v4,v12,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+f8865257[ ]+th.vfwmsac.vf[ ]+v4,fa2,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+fc861257[ ]+th.vfwnmsac.vv[ ]+v4,v12,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+fc865257[ ]+th.vfwnmsac.vf[ ]+v4,fa2,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+8e801257[ ]+th.vfsqrt.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+8c801257[ ]+th.vfsqrt.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+12861257[ ]+th.vfmin.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+12865257[ ]+th.vfmin.vf[ ]+v4,v8,fa2
+[ ]+[0-9a-f]+:[ ]+1a861257[ ]+th.vfmax.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+1a865257[ ]+th.vfmax.vf[ ]+v4,v8,fa2
+[ ]+[0-9a-f]+:[ ]+10861257[ ]+th.vfmin.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+10865257[ ]+th.vfmin.vf[ ]+v4,v8,fa2,v0.t
+[ ]+[0-9a-f]+:[ ]+18861257[ ]+th.vfmax.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+18865257[ ]+th.vfmax.vf[ ]+v4,v8,fa2,v0.t
+[ ]+[0-9a-f]+:[ ]+22861257[ ]+th.vfsgnj.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+22865257[ ]+th.vfsgnj.vf[ ]+v4,v8,fa2
+[ ]+[0-9a-f]+:[ ]+26861257[ ]+th.vfsgnjn.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+26865257[ ]+th.vfsgnjn.vf[ ]+v4,v8,fa2
+[ ]+[0-9a-f]+:[ ]+2a861257[ ]+th.vfsgnjx.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+2a865257[ ]+th.vfsgnjx.vf[ ]+v4,v8,fa2
+[ ]+[0-9a-f]+:[ ]+20861257[ ]+th.vfsgnj.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+20865257[ ]+th.vfsgnj.vf[ ]+v4,v8,fa2,v0.t
+[ ]+[0-9a-f]+:[ ]+24861257[ ]+th.vfsgnjn.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+24865257[ ]+th.vfsgnjn.vf[ ]+v4,v8,fa2,v0.t
+[ ]+[0-9a-f]+:[ ]+28861257[ ]+th.vfsgnjx.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+28865257[ ]+th.vfsgnjx.vf[ ]+v4,v8,fa2,v0.t
+[ ]+[0-9a-f]+:[ ]+6ec41257[ ]+th.vmflt.vv[ ]+v4,v12,v8
+[ ]+[0-9a-f]+:[ ]+66c41257[ ]+th.vmfle.vv[ ]+v4,v12,v8
+[ ]+[0-9a-f]+:[ ]+6cc41257[ ]+th.vmflt.vv[ ]+v4,v12,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+64c41257[ ]+th.vmfle.vv[ ]+v4,v12,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+62861257[ ]+th.vmfeq.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+62865257[ ]+th.vmfeq.vf[ ]+v4,v8,fa2
+[ ]+[0-9a-f]+:[ ]+72861257[ ]+th.vmfne.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+72865257[ ]+th.vmfne.vf[ ]+v4,v8,fa2
+[ ]+[0-9a-f]+:[ ]+6e861257[ ]+th.vmflt.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+6e865257[ ]+th.vmflt.vf[ ]+v4,v8,fa2
+[ ]+[0-9a-f]+:[ ]+66861257[ ]+th.vmfle.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+66865257[ ]+th.vmfle.vf[ ]+v4,v8,fa2
+[ ]+[0-9a-f]+:[ ]+76865257[ ]+th.vmfgt.vf[ ]+v4,v8,fa2
+[ ]+[0-9a-f]+:[ ]+7e865257[ ]+th.vmfge.vf[ ]+v4,v8,fa2
+[ ]+[0-9a-f]+:[ ]+60861257[ ]+th.vmfeq.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+60865257[ ]+th.vmfeq.vf[ ]+v4,v8,fa2,v0.t
+[ ]+[0-9a-f]+:[ ]+70861257[ ]+th.vmfne.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+70865257[ ]+th.vmfne.vf[ ]+v4,v8,fa2,v0.t
+[ ]+[0-9a-f]+:[ ]+6c861257[ ]+th.vmflt.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+6c865257[ ]+th.vmflt.vf[ ]+v4,v8,fa2,v0.t
+[ ]+[0-9a-f]+:[ ]+64861257[ ]+th.vmfle.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+64865257[ ]+th.vmfle.vf[ ]+v4,v8,fa2,v0.t
+[ ]+[0-9a-f]+:[ ]+74865257[ ]+th.vmfgt.vf[ ]+v4,v8,fa2,v0.t
+[ ]+[0-9a-f]+:[ ]+7c865257[ ]+th.vmfge.vf[ ]+v4,v8,fa2,v0.t
+[ ]+[0-9a-f]+:[ ]+6a861257[ ]+th.vmford.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+6a865257[ ]+th.vmford.vf[ ]+v4,v8,fa2
+[ ]+[0-9a-f]+:[ ]+68861257[ ]+th.vmford.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+68865257[ ]+th.vmford.vf[ ]+v4,v8,fa2,v0.t
+[ ]+[0-9a-f]+:[ ]+8e881257[ ]+th.vfclass.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+8c881257[ ]+th.vfclass.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+5c865257[ ]+th.vfmerge.vfm[ ]+v4,v8,fa2,v0
+[ ]+[0-9a-f]+:[ ]+5e05d257[ ]+th.vfmv.v.f[ ]+v4,fa1
+[ ]+[0-9a-f]+:[ ]+8a801257[ ]+th.vfcvt.xu.f.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+8a809257[ ]+th.vfcvt.x.f.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+8a811257[ ]+th.vfcvt.f.xu.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+8a819257[ ]+th.vfcvt.f.x.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+88801257[ ]+th.vfcvt.xu.f.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+88809257[ ]+th.vfcvt.x.f.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+88811257[ ]+th.vfcvt.f.xu.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+88819257[ ]+th.vfcvt.f.x.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+8a841257[ ]+th.vfwcvt.xu.f.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+8a849257[ ]+th.vfwcvt.x.f.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+8a851257[ ]+th.vfwcvt.f.xu.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+8a859257[ ]+th.vfwcvt.f.x.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+8a861257[ ]+th.vfwcvt.f.f.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+88841257[ ]+th.vfwcvt.xu.f.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+88849257[ ]+th.vfwcvt.x.f.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+88851257[ ]+th.vfwcvt.f.xu.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+88859257[ ]+th.vfwcvt.f.x.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+88861257[ ]+th.vfwcvt.f.f.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+8a881257[ ]+th.vfncvt.xu.f.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+8a889257[ ]+th.vfncvt.x.f.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+8a891257[ ]+th.vfncvt.f.xu.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+8a899257[ ]+th.vfncvt.f.x.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+8a8a1257[ ]+th.vfncvt.f.f.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+88881257[ ]+th.vfncvt.xu.f.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+88889257[ ]+th.vfncvt.x.f.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+88891257[ ]+th.vfncvt.f.xu.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+88899257[ ]+th.vfncvt.f.x.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+888a1257[ ]+th.vfncvt.f.f.v[ ]+v4,v8,v0.t
diff --git a/gas/testsuite/gas/riscv/x-thead-vector.s b/gas/testsuite/gas/riscv/x-thead-vector.s
index 97a0e1a5d79..92e90068b7f 100644
--- a/gas/testsuite/gas/riscv/x-thead-vector.s
+++ b/gas/testsuite/gas/riscv/x-thead-vector.s
@@ -1432,3 +1432,191 @@
th.vnclip.vx v4, v8, a1, v0.t
th.vnclip.vi v4, v8, 1, v0.t
th.vnclip.vi v4, v8, 31, v0.t
+
+ th.vfadd.vv v4, v8, v12
+ th.vfadd.vf v4, v8, fa2
+ th.vfadd.vv v4, v8, v12, v0.t
+ th.vfadd.vf v4, v8, fa2, v0.t
+ th.vfsub.vv v4, v8, v12
+ th.vfsub.vf v4, v8, fa2
+ th.vfsub.vv v4, v8, v12, v0.t
+ th.vfsub.vf v4, v8, fa2, v0.t
+ th.vfrsub.vf v4, v8, fa2
+ th.vfrsub.vf v4, v8, fa2, v0.t
+
+ th.vfwadd.vv v4, v8, v12
+ th.vfwadd.vf v4, v8, fa2
+ th.vfwadd.vv v4, v8, v12, v0.t
+ th.vfwadd.vf v4, v8, fa2, v0.t
+ th.vfwsub.vv v4, v8, v12
+ th.vfwsub.vf v4, v8, fa2
+ th.vfwsub.vv v4, v8, v12, v0.t
+ th.vfwsub.vf v4, v8, fa2, v0.t
+ th.vfwadd.wv v4, v8, v12
+ th.vfwadd.wf v4, v8, fa2
+ th.vfwadd.wv v4, v8, v12, v0.t
+ th.vfwadd.wf v4, v8, fa2, v0.t
+ th.vfwsub.wv v4, v8, v12
+ th.vfwsub.wf v4, v8, fa2
+ th.vfwsub.wv v4, v8, v12, v0.t
+ th.vfwsub.wf v4, v8, fa2, v0.t
+
+ th.vfmul.vv v4, v8, v12
+ th.vfmul.vf v4, v8, fa2
+ th.vfmul.vv v4, v8, v12, v0.t
+ th.vfmul.vf v4, v8, fa2, v0.t
+ th.vfdiv.vv v4, v8, v12
+ th.vfdiv.vf v4, v8, fa2
+ th.vfdiv.vv v4, v8, v12, v0.t
+ th.vfdiv.vf v4, v8, fa2, v0.t
+ th.vfrdiv.vf v4, v8, fa2
+ th.vfrdiv.vf v4, v8, fa2, v0.t
+
+ th.vfwmul.vv v4, v8, v12
+ th.vfwmul.vf v4, v8, fa2
+ th.vfwmul.vv v4, v8, v12, v0.t
+ th.vfwmul.vf v4, v8, fa2, v0.t
+
+ th.vfmadd.vv v4, v12, v8
+ th.vfmadd.vf v4, fa2, v8
+ th.vfnmadd.vv v4, v12, v8
+ th.vfnmadd.vf v4, fa2, v8
+ th.vfmsub.vv v4, v12, v8
+ th.vfmsub.vf v4, fa2, v8
+ th.vfnmsub.vv v4, v12, v8
+ th.vfnmsub.vf v4, fa2, v8
+ th.vfmadd.vv v4, v12, v8, v0.t
+ th.vfmadd.vf v4, fa2, v8, v0.t
+ th.vfnmadd.vv v4, v12, v8, v0.t
+ th.vfnmadd.vf v4, fa2, v8, v0.t
+ th.vfmsub.vv v4, v12, v8, v0.t
+ th.vfmsub.vf v4, fa2, v8, v0.t
+ th.vfnmsub.vv v4, v12, v8, v0.t
+ th.vfnmsub.vf v4, fa2, v8, v0.t
+ th.vfmacc.vv v4, v12, v8
+ th.vfmacc.vf v4, fa2, v8
+ th.vfnmacc.vv v4, v12, v8
+ th.vfnmacc.vf v4, fa2, v8
+ th.vfmsac.vv v4, v12, v8
+ th.vfmsac.vf v4, fa2, v8
+ th.vfnmsac.vv v4, v12, v8
+ th.vfnmsac.vf v4, fa2, v8
+ th.vfmacc.vv v4, v12, v8, v0.t
+ th.vfmacc.vf v4, fa2, v8, v0.t
+ th.vfnmacc.vv v4, v12, v8, v0.t
+ th.vfnmacc.vf v4, fa2, v8, v0.t
+ th.vfmsac.vv v4, v12, v8, v0.t
+ th.vfmsac.vf v4, fa2, v8, v0.t
+ th.vfnmsac.vv v4, v12, v8, v0.t
+ th.vfnmsac.vf v4, fa2, v8, v0.t
+
+ th.vfwmacc.vv v4, v12, v8
+ th.vfwmacc.vf v4, fa2, v8
+ th.vfwnmacc.vv v4, v12, v8
+ th.vfwnmacc.vf v4, fa2, v8
+ th.vfwmsac.vv v4, v12, v8
+ th.vfwmsac.vf v4, fa2, v8
+ th.vfwnmsac.vv v4, v12, v8
+ th.vfwnmsac.vf v4, fa2, v8
+ th.vfwmacc.vv v4, v12, v8, v0.t
+ th.vfwmacc.vf v4, fa2, v8, v0.t
+ th.vfwnmacc.vv v4, v12, v8, v0.t
+ th.vfwnmacc.vf v4, fa2, v8, v0.t
+ th.vfwmsac.vv v4, v12, v8, v0.t
+ th.vfwmsac.vf v4, fa2, v8, v0.t
+ th.vfwnmsac.vv v4, v12, v8, v0.t
+ th.vfwnmsac.vf v4, fa2, v8, v0.t
+
+ th.vfsqrt.v v4, v8
+ th.vfsqrt.v v4, v8, v0.t
+
+ th.vfmin.vv v4, v8, v12
+ th.vfmin.vf v4, v8, fa2
+ th.vfmax.vv v4, v8, v12
+ th.vfmax.vf v4, v8, fa2
+ th.vfmin.vv v4, v8, v12, v0.t
+ th.vfmin.vf v4, v8, fa2, v0.t
+ th.vfmax.vv v4, v8, v12, v0.t
+ th.vfmax.vf v4, v8, fa2, v0.t
+
+ th.vfsgnj.vv v4, v8, v12
+ th.vfsgnj.vf v4, v8, fa2
+ th.vfsgnjn.vv v4, v8, v12
+ th.vfsgnjn.vf v4, v8, fa2
+ th.vfsgnjx.vv v4, v8, v12
+ th.vfsgnjx.vf v4, v8, fa2
+ th.vfsgnj.vv v4, v8, v12, v0.t
+ th.vfsgnj.vf v4, v8, fa2, v0.t
+ th.vfsgnjn.vv v4, v8, v12, v0.t
+ th.vfsgnjn.vf v4, v8, fa2, v0.t
+ th.vfsgnjx.vv v4, v8, v12, v0.t
+ th.vfsgnjx.vf v4, v8, fa2, v0.t
+
+ # Aliases
+ th.vmfgt.vv v4, v8, v12
+ th.vmfge.vv v4, v8, v12
+ th.vmfgt.vv v4, v8, v12, v0.t
+ th.vmfge.vv v4, v8, v12, v0.t
+
+ th.vmfeq.vv v4, v8, v12
+ th.vmfeq.vf v4, v8, fa2
+ th.vmfne.vv v4, v8, v12
+ th.vmfne.vf v4, v8, fa2
+ th.vmflt.vv v4, v8, v12
+ th.vmflt.vf v4, v8, fa2
+ th.vmfle.vv v4, v8, v12
+ th.vmfle.vf v4, v8, fa2
+ th.vmfgt.vf v4, v8, fa2
+ th.vmfge.vf v4, v8, fa2
+ th.vmfeq.vv v4, v8, v12, v0.t
+ th.vmfeq.vf v4, v8, fa2, v0.t
+ th.vmfne.vv v4, v8, v12, v0.t
+ th.vmfne.vf v4, v8, fa2, v0.t
+ th.vmflt.vv v4, v8, v12, v0.t
+ th.vmflt.vf v4, v8, fa2, v0.t
+ th.vmfle.vv v4, v8, v12, v0.t
+ th.vmfle.vf v4, v8, fa2, v0.t
+ th.vmfgt.vf v4, v8, fa2, v0.t
+ th.vmfge.vf v4, v8, fa2, v0.t
+
+ th.vmford.vv v4, v8, v12
+ th.vmford.vf v4, v8, fa2
+ th.vmford.vv v4, v8, v12, v0.t
+ th.vmford.vf v4, v8, fa2, v0.t
+
+ th.vfclass.v v4, v8
+ th.vfclass.v v4, v8, v0.t
+
+ th.vfmerge.vfm v4, v8, fa2, v0
+ th.vfmv.v.f v4, fa1
+
+ th.vfcvt.xu.f.v v4, v8
+ th.vfcvt.x.f.v v4, v8
+ th.vfcvt.f.xu.v v4, v8
+ th.vfcvt.f.x.v v4, v8
+ th.vfcvt.xu.f.v v4, v8, v0.t
+ th.vfcvt.x.f.v v4, v8, v0.t
+ th.vfcvt.f.xu.v v4, v8, v0.t
+ th.vfcvt.f.x.v v4, v8, v0.t
+
+ th.vfwcvt.xu.f.v v4, v8
+ th.vfwcvt.x.f.v v4, v8
+ th.vfwcvt.f.xu.v v4, v8
+ th.vfwcvt.f.x.v v4, v8
+ th.vfwcvt.f.f.v v4, v8
+ th.vfwcvt.xu.f.v v4, v8, v0.t
+ th.vfwcvt.x.f.v v4, v8, v0.t
+ th.vfwcvt.f.xu.v v4, v8, v0.t
+ th.vfwcvt.f.x.v v4, v8, v0.t
+ th.vfwcvt.f.f.v v4, v8, v0.t
+
+ th.vfncvt.xu.f.v v4, v8
+ th.vfncvt.x.f.v v4, v8
+ th.vfncvt.f.xu.v v4, v8
+ th.vfncvt.f.x.v v4, v8
+ th.vfncvt.f.f.v v4, v8
+ th.vfncvt.xu.f.v v4, v8, v0.t
+ th.vfncvt.x.f.v v4, v8, v0.t
+ th.vfncvt.f.xu.v v4, v8, v0.t
+ th.vfncvt.f.x.v v4, v8, v0.t
+ th.vfncvt.f.f.v v4, v8, v0.t
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 5cca4c5bb43..2e5b4fe63ee 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2909,6 +2909,42 @@
#define MASK_TH_VASUBVX 0xfc00707f
#define MATCH_TH_VWSMACCSUVV 0xf8000057
#define MASK_TH_VWSMACCSUVV 0xfc00707f
+#define MATCH_TH_VFSQRTV 0x8c001057
+#define MASK_TH_VFSQRTV 0xfc0ff07f
+#define MATCH_TH_VMFORDVV 0x68001057
+#define MASK_TH_VMFORDVV 0xfc00707f
+#define MATCH_TH_VMFORDVF 0x68005057
+#define MASK_TH_VMFORDVF 0xfc00707f
+#define MATCH_TH_VFCLASSV 0x8c081057
+#define MASK_TH_VFCLASSV 0xfc0ff07f
+#define MATCH_TH_VFCVTXUFV 0x88001057
+#define MASK_TH_VFCVTXUFV 0xfc0ff07f
+#define MATCH_TH_VFCVTXFV 0x88009057
+#define MASK_TH_VFCVTXFV 0xfc0ff07f
+#define MATCH_TH_VFCVTFXUV 0x88011057
+#define MASK_TH_VFCVTFXUV 0xfc0ff07f
+#define MATCH_TH_VFCVTFXV 0x88019057
+#define MASK_TH_VFCVTFXV 0xfc0ff07f
+#define MATCH_TH_VFWCVTXUFV 0x88041057
+#define MASK_TH_VFWCVTXUFV 0xfc0ff07f
+#define MATCH_TH_VFWCVTXFV 0x88049057
+#define MASK_TH_VFWCVTXFV 0xfc0ff07f
+#define MATCH_TH_VFWCVTFXUV 0x88051057
+#define MASK_TH_VFWCVTFXUV 0xfc0ff07f
+#define MATCH_TH_VFWCVTFXV 0x88059057
+#define MASK_TH_VFWCVTFXV 0xfc0ff07f
+#define MATCH_TH_VFWCVTFFV 0x88061057
+#define MASK_TH_VFWCVTFFV 0xfc0ff07f
+#define MATCH_TH_VFNCVTXUFV 0x88081057
+#define MASK_TH_VFNCVTXUFV 0xfc0ff07f
+#define MATCH_TH_VFNCVTXFV 0x88089057
+#define MASK_TH_VFNCVTXFV 0xfc0ff07f
+#define MATCH_TH_VFNCVTFXUV 0x88091057
+#define MASK_TH_VFNCVTFXUV 0xfc0ff07f
+#define MATCH_TH_VFNCVTFXV 0x88099057
+#define MASK_TH_VFNCVTFXV 0xfc0ff07f
+#define MATCH_TH_VFNCVTFFV 0x880a1057
+#define MASK_TH_VFNCVTFFV 0xfc0ff07f
/* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
#define MATCH_VT_MASKC 0x607b
#define MASK_VT_MASKC 0xfe00707f
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 6a8d41df0e6..31689a63948 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2758,6 +2758,92 @@ const struct riscv_opcode riscv_opcodes[] =
{"th.vnclip.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VNCLIPWV, MASK_VNCLIPWV, match_opcode, 0 },
{"th.vnclip.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VNCLIPWX, MASK_VNCLIPWX, match_opcode, 0 },
{"th.vnclip.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_VNCLIPWI, MASK_VNCLIPWI, match_opcode, 0 },
+{"th.vfadd.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFADDVV, MASK_VFADDVV, match_opcode, 0},
+{"th.vfadd.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFADDVF, MASK_VFADDVF, match_opcode, 0},
+{"th.vfsub.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFSUBVV, MASK_VFSUBVV, match_opcode, 0},
+{"th.vfsub.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFSUBVF, MASK_VFSUBVF, match_opcode, 0},
+{"th.vfrsub.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFRSUBVF, MASK_VFRSUBVF, match_opcode, 0},
+{"th.vfwadd.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFWADDVV, MASK_VFWADDVV, match_opcode, 0},
+{"th.vfwadd.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFWADDVF, MASK_VFWADDVF, match_opcode, 0},
+{"th.vfwsub.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFWSUBVV, MASK_VFWSUBVV, match_opcode, 0},
+{"th.vfwsub.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFWSUBVF, MASK_VFWSUBVF, match_opcode, 0},
+{"th.vfwadd.wv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFWADDWV, MASK_VFWADDWV, match_opcode, 0},
+{"th.vfwsub.wv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFWSUBWV, MASK_VFWSUBWV, match_opcode, 0},
+{"th.vfwadd.wf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFWADDWF, MASK_VFWADDWF, match_opcode, 0},
+{"th.vfwsub.wf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFWSUBWF, MASK_VFWSUBWF, match_opcode, 0},
+{"th.vfmul.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFMULVV, MASK_VFMULVV, match_opcode, 0},
+{"th.vfmul.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFMULVF, MASK_VFMULVF, match_opcode, 0},
+{"th.vfdiv.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFDIVVV, MASK_VFDIVVV, match_opcode, 0},
+{"th.vfdiv.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFDIVVF, MASK_VFDIVVF, match_opcode, 0},
+{"th.vfrdiv.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFRDIVVF, MASK_VFRDIVVF, match_opcode, 0},
+{"th.vfwmul.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFWMULVV, MASK_VFWMULVV, match_opcode, 0},
+{"th.vfwmul.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFWMULVF, MASK_VFWMULVF, match_opcode, 0},
+{"th.vfmadd.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VFMADDVV, MASK_VFMADDVV, match_opcode, 0},
+{"th.vfmadd.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_VFMADDVF, MASK_VFMADDVF, match_opcode, 0},
+{"th.vfnmadd.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VFNMADDVV, MASK_VFNMADDVV, match_opcode, 0},
+{"th.vfnmadd.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_VFNMADDVF, MASK_VFNMADDVF, match_opcode, 0},
+{"th.vfmsub.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VFMSUBVV, MASK_VFMSUBVV, match_opcode, 0},
+{"th.vfmsub.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_VFMSUBVF, MASK_VFMSUBVF, match_opcode, 0},
+{"th.vfnmsub.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VFNMSUBVV, MASK_VFNMSUBVV, match_opcode, 0},
+{"th.vfnmsub.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_VFNMSUBVF, MASK_VFNMSUBVF, match_opcode, 0},
+{"th.vfmacc.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VFMACCVV, MASK_VFMACCVV, match_opcode, 0},
+{"th.vfmacc.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_VFMACCVF, MASK_VFMACCVF, match_opcode, 0},
+{"th.vfnmacc.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VFNMACCVV, MASK_VFNMACCVV, match_opcode, 0},
+{"th.vfnmacc.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_VFNMACCVF, MASK_VFNMACCVF, match_opcode, 0},
+{"th.vfmsac.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VFMSACVV, MASK_VFMSACVV, match_opcode, 0},
+{"th.vfmsac.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_VFMSACVF, MASK_VFMSACVF, match_opcode, 0},
+{"th.vfnmsac.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VFNMSACVV, MASK_VFNMSACVV, match_opcode, 0},
+{"th.vfnmsac.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_VFNMSACVF, MASK_VFNMSACVF, match_opcode, 0},
+{"th.vfwmacc.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VFWMACCVV, MASK_VFWMACCVV, match_opcode, 0},
+{"th.vfwmacc.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_VFWMACCVF, MASK_VFWMACCVF, match_opcode, 0},
+{"th.vfwnmacc.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VFWNMACCVV, MASK_VFWNMACCVV, match_opcode, 0},
+{"th.vfwnmacc.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_VFWNMACCVF, MASK_VFWNMACCVF, match_opcode, 0},
+{"th.vfwmsac.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VFWMSACVV, MASK_VFWMSACVV, match_opcode, 0},
+{"th.vfwmsac.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_VFWMSACVF, MASK_VFWMSACVF, match_opcode, 0},
+{"th.vfwnmsac.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VFWNMSACVV, MASK_VFWNMSACVV, match_opcode, 0},
+{"th.vfwnmsac.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_VFWNMSACVF, MASK_VFWNMSACVF, match_opcode, 0},
+{"th.vfsqrt.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFSQRTV, MASK_TH_VFSQRTV, match_opcode, 0},
+{"th.vfmin.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFMINVV, MASK_VFMINVV, match_opcode, 0},
+{"th.vfmin.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFMINVF, MASK_VFMINVF, match_opcode, 0},
+{"th.vfmax.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFMAXVV, MASK_VFMAXVV, match_opcode, 0},
+{"th.vfmax.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFMAXVF, MASK_VFMAXVF, match_opcode, 0},
+{"th.vfsgnj.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFSGNJVV, MASK_VFSGNJVV, match_opcode, 0},
+{"th.vfsgnj.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFSGNJVF, MASK_VFSGNJVF, match_opcode, 0},
+{"th.vfsgnjn.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFSGNJNVV, MASK_VFSGNJNVV, match_opcode, 0},
+{"th.vfsgnjn.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFSGNJNVF, MASK_VFSGNJNVF, match_opcode, 0},
+{"th.vfsgnjx.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFSGNJXVV, MASK_VFSGNJXVV, match_opcode, 0},
+{"th.vfsgnjx.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VFSGNJXVF, MASK_VFSGNJXVF, match_opcode, 0},
+{"th.vmfeq.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VMFEQVV, MASK_VMFEQVV, match_opcode, 0},
+{"th.vmfeq.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VMFEQVF, MASK_VMFEQVF, match_opcode, 0},
+{"th.vmfne.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VMFNEVV, MASK_VMFNEVV, match_opcode, 0},
+{"th.vmfne.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VMFNEVF, MASK_VMFNEVF, match_opcode, 0},
+{"th.vmflt.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VMFLTVV, MASK_VMFLTVV, match_opcode, 0},
+{"th.vmflt.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VMFLTVF, MASK_VMFLTVF, match_opcode, 0},
+{"th.vmfle.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VMFLEVV, MASK_VMFLEVV, match_opcode, 0},
+{"th.vmfle.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VMFLEVF, MASK_VMFLEVF, match_opcode, 0},
+{"th.vmfgt.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VMFGTVF, MASK_VMFGTVF, match_opcode, 0},
+{"th.vmfge.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_VMFGEVF, MASK_VMFGEVF, match_opcode, 0},
+{"th.vmfgt.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VMFLTVV, MASK_VMFLTVV, match_opcode, INSN_ALIAS},
+{"th.vmfge.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VMFLEVV, MASK_VMFLEVV, match_opcode, INSN_ALIAS},
+{"th.vmford.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VMFORDVV, MASK_TH_VMFORDVV, match_opcode, 0},
+{"th.vmford.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VMFORDVF, MASK_TH_VMFORDVF, match_opcode, 0},
+{"th.vfclass.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFCLASSV, MASK_TH_VFCLASSV, match_opcode, 0},
+{"th.vfmerge.vfm",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,S,V0", MATCH_VFMERGEVFM, MASK_VFMERGEVFM, match_opcode, 0},
+{"th.vfmv.v.f", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S", MATCH_VFMVVF, MASK_VFMVVF, match_opcode, 0 },
+{"th.vfcvt.xu.f.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFCVTXUFV, MASK_TH_VFCVTXUFV, match_opcode, 0},
+{"th.vfcvt.x.f.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFCVTXFV, MASK_TH_VFCVTXFV, match_opcode, 0},
+{"th.vfcvt.f.xu.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFCVTFXUV, MASK_TH_VFCVTFXUV, match_opcode, 0},
+{"th.vfcvt.f.x.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFCVTFXV, MASK_TH_VFCVTFXV, match_opcode, 0},
+{"th.vfwcvt.xu.f.v",0,INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFWCVTXUFV, MASK_TH_VFWCVTXUFV, match_opcode, 0},
+{"th.vfwcvt.x.f.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFWCVTXFV, MASK_TH_VFWCVTXFV, match_opcode, 0},
+{"th.vfwcvt.f.xu.v",0,INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFWCVTFXUV, MASK_TH_VFWCVTFXUV, match_opcode, 0},
+{"th.vfwcvt.f.x.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFWCVTFXV, MASK_TH_VFWCVTFXV, match_opcode, 0},
+{"th.vfwcvt.f.f.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFWCVTFFV, MASK_TH_VFWCVTFFV, match_opcode, 0},
+{"th.vfncvt.xu.f.v",0,INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFNCVTXUFV, MASK_TH_VFNCVTXUFV, match_opcode, 0},
+{"th.vfncvt.x.f.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFNCVTXFV, MASK_TH_VFNCVTXFV, match_opcode, 0},
+{"th.vfncvt.f.xu.v",0,INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFNCVTFXUV, MASK_TH_VFNCVTFXUV, match_opcode, 0},
+{"th.vfncvt.f.x.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFNCVTFXV, MASK_TH_VFNCVTFXV, match_opcode, 0},
+{"th.vfncvt.f.f.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFNCVTFFV, MASK_TH_VFNCVTFFV, match_opcode, 0},
/* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
{"vt.maskc", 64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 },
--
2.17.1
next prev parent reply other threads:[~2023-11-18 7:07 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-18 6:49 [PATCH v2 00/12] RISC-V: Add " Jin Ma
2023-11-18 6:53 ` [PATCH v2 01/12] " Jin Ma
2023-11-18 6:58 ` [PATCH v2 02/12] RISC-V: Add CSRs for " Jin Ma
2023-11-18 7:04 ` [PATCH v2 03/12] RISC-V: Add configuration-setting instructions " Jin Ma
2023-11-18 7:04 ` [PATCH v2 04/12] RISC-V: Add load/store " Jin Ma
2023-11-18 7:05 ` [PATCH v2 05/12] RISC-V: Add load/store segment " Jin Ma
2023-11-18 7:06 ` [PATCH v2 06/12] RISC-V: Add sub-extension XTheadZvamo " Jin Ma
2023-11-18 7:07 ` [PATCH v2 07/12] RISC-V: Add integer arithmetic instructions " Jin Ma
2023-11-18 7:07 ` [PATCH v2 08/12] RISC-V: Add fixed-point " Jin Ma
2023-11-18 7:07 ` Jin Ma [this message]
2023-11-18 7:08 ` [PATCH v2 10/12] RISC-V: Add reductions " Jin Ma
2023-11-18 7:08 ` [PATCH v2 11/12] RISC-V: Add vector mask " Jin Ma
2023-11-18 7:08 ` [PATCH v2 12/12] RISC-V: Add vector permutation " Jin Ma
2023-11-23 2:37 ` [PATCH v2 00/12] RISC-V: Add " Nelson Chu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20231118070739.1469-1-jinma@linux.alibaba.com \
--to=jinma@linux.alibaba.com \
--cc=binutils@sourceware.org \
--cc=christoph.muellner@vrull.eu \
--cc=jinma.contrib@gmail.com \
--cc=lifang_xia@linux.alibaba.com \
--cc=nelson@rivosinc.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).