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From: Nelson Chu <nelson@rivosinc.com>
To: Jin Ma <jinma@linux.alibaba.com>
Cc: binutils@sourceware.org, christoph.muellner@vrull.eu,
	 lifang_xia@linux.alibaba.com, jinma.contrib@gmail.com
Subject: Re: [PATCH v2 00/12] RISC-V: Add T-Head VECTOR vendor extension.
Date: Thu, 23 Nov 2023 10:37:32 +0800	[thread overview]
Message-ID: <CAPpQWtAv6tNp6dLXo5srk3A94JGat2udyHHi77WrmPf9Ri4Y4g@mail.gmail.com> (raw)
In-Reply-To: <20231118064928.849-1-jinma@linux.alibaba.com>

[-- Attachment #1: Type: text/plain, Size: 4285 bytes --]

Generally the OP_CUSTOM_0/1/2/3 are reserved for vendor/custom/non-standard
usage.  Non-standard extensions that use space that’s reserved for standard
extensions are considered to be “non-conforming”.  We discourage (but not
disallow) non-conforming extensions, since it is highly likely that future
standard extensions will reclaim space used by them.  However, the t-head
vector is kind of different, according to my understanding, it's actually
rvv 0.7.  Since we don't have plans to support multi-version encodings, and
the reasons that t-head released rvv 0.7 are complicated, we recommended
them to use vendor/non-standard extensions to solve this problem.  Since
the patches make sure that t-head vector and standard vector won't be
enabled at the same time, the conflicted encodings should work well in
current implementation.

Anyway, committed.

Thanks
Nelson


On Sat, Nov 18, 2023 at 2:49 PM Jin Ma <jinma@linux.alibaba.com> wrote:

> V1 -> V2:
>
> V2 adopted the review comments of Nelson and modified the
> instructions encoding of vendor: Reuse the instruction
> encoding of the "V" extension as much as possible and
> remove redundant instructions encoding.
>
> V1:
>
> T-Head has a range of vendor-specific instructions ([2]).
> Therefore it makes sense to group them into smaller chunks
> in form of vendor extensions.
>
> This patch adds the "XTheadVector" extension, a collection of
> T-Head-specific vector instructions. The 'th' prefix and the
> "XTheadVector" extension are documented in a PR for the RISC-V
> toolchain conventions ([1]).
>
> Here are some things that need to be explained:
> The "XTheadVector" extension is not a custom-extension, but
> a non-standard non-conforming extension. The encoding space
> of the "TheadVector" instructions overlaps with those of
> the 'V' extension. This encoding space conflict is not on
> purpose, but the result of issues in the past that have
> been resolved since. Therefore, the "XTheadVector" extension
> and the 'V' extension are in conflict.
>
> [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
> [2]
> https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf
>
> Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
> Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>
>
> ---
>  bfd/elfxx-riscv.c                             |   17 +
>  gas/NEWS                                      |    3 +
>  gas/config/tc-riscv.c                         |    4 +
>  gas/doc/c-riscv.texi                          |   11 +
>  .../gas/riscv/x-thead-vector-csr-warn.d       |    3 +
>  .../gas/riscv/x-thead-vector-csr-warn.l       |   16 +
>  gas/testsuite/gas/riscv/x-thead-vector-csr.d  |   21 +
>  gas/testsuite/gas/riscv/x-thead-vector-csr.s  |   13 +
>  gas/testsuite/gas/riscv/x-thead-vector-fail.d |    3 +
>  gas/testsuite/gas/riscv/x-thead-vector-fail.l |    2 +
>  .../gas/riscv/x-thead-vector-zvamo.d          |   81 +
>  .../gas/riscv/x-thead-vector-zvamo.s          |   74 +
>  gas/testsuite/gas/riscv/x-thead-vector.d      | 1650 ++++++++++++++++
>  gas/testsuite/gas/riscv/x-thead-vector.s      | 1726 +++++++++++++++++
>  include/opcode/riscv-opc.h                    |  328 ++++
>  include/opcode/riscv.h                        |    2 +
>  opcodes/riscv-dis.c                           |   14 +-
>  opcodes/riscv-opc.c                           |  661 +++++++
>  18 files changed, 4627 insertions(+), 2 deletions(-)
>  create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-csr-warn.d
>  create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-csr-warn.l
>  create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-csr.d
>  create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-csr.s
>  create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-fail.d
>  create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-fail.l
>  create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-zvamo.d
>  create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-zvamo.s
>  create mode 100644 gas/testsuite/gas/riscv/x-thead-vector.d
>  create mode 100644 gas/testsuite/gas/riscv/x-thead-vector.s
>
> --
> 2.17.1
>
>

      parent reply	other threads:[~2023-11-23  2:37 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-18  6:49 Jin Ma
2023-11-18  6:53 ` [PATCH v2 01/12] " Jin Ma
2023-11-18  6:58 ` [PATCH v2 02/12] RISC-V: Add CSRs for " Jin Ma
2023-11-18  7:04 ` [PATCH v2 03/12] RISC-V: Add configuration-setting instructions " Jin Ma
2023-11-18  7:04 ` [PATCH v2 04/12] RISC-V: Add load/store " Jin Ma
2023-11-18  7:05 ` [PATCH v2 05/12] RISC-V: Add load/store segment " Jin Ma
2023-11-18  7:06 ` [PATCH v2 06/12] RISC-V: Add sub-extension XTheadZvamo " Jin Ma
2023-11-18  7:07 ` [PATCH v2 07/12] RISC-V: Add integer arithmetic instructions " Jin Ma
2023-11-18  7:07 ` [PATCH v2 08/12] RISC-V: Add fixed-point " Jin Ma
2023-11-18  7:07 ` [PATCH v2 09/12] RISC-V: Add floating-point " Jin Ma
2023-11-18  7:08 ` [PATCH v2 10/12] RISC-V: Add reductions " Jin Ma
2023-11-18  7:08 ` [PATCH v2 11/12] RISC-V: Add vector mask " Jin Ma
2023-11-18  7:08 ` [PATCH v2 12/12] RISC-V: Add vector permutation " Jin Ma
2023-11-23  2:37 ` Nelson Chu [this message]

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