[PATCH v3 0/5] LoongArch tls le model linker relaxation support.

[changjiachen <changjiachen@stu.xupt.edu.cn>]

This is the v3 version of patches to support loongarch linker tls le model relax.

Changes from v2:

* Some problems in the v2 patch are answered as follows.

Question: 

use ".reloc.,R_LARCH_TLS_LE_ADD_R,sym" to generate relocation 
or %le_add_r(sym) to generate relocation.

Reply: 

First, after a test, the R_LARCH_TLS_LE_ADD_R can be generated using ".reloc.,R_LARCH_TLS_LE_ADD_R,sym", 
or "%le_add_r(sym)". However,".reloc" generates R_LARCH_TLS_LE_ADD_R relocation directly, and it is not 
easy to add "R_LARCH_RELAX" relocation. "%le_add_r(sym)" Adds the R_LARCH_TLS_LE_ADD_R and R_LARCH_RELAX 
relocation commands, which is easier to implement.

Of course, there is another way to generate ".reloc.,R_LARCH_TLS_LE_ADD_R,sym" and 
".reloc.,R_LARCH_RELAX,sym" directly in gcc. However, this implementation causes the 
-mrelax/-mno-relax option to be set in both gcc and gas, which can be confusing.

One problem with this is that add.d $r12,$r12,$r2 and add.d $r12,$r12,$r2, 
%le_add_r(sym) are too similar, so I have to add comments in loongarch_fix_opcodes[]. 
The goal is to make it as clear as possible to developers.

* modified code format in loongarch_relax_tls_le(),use loongarch_relax_delete_bytes() 
instead of R_LARCH_DELETE to implement the delete instruction operation.

* modified R_LARCH_TLS_LE_ADD_R type_name:"tls_le_add_r"-->"le_add_r".

* modify comment information.

* some comments added to "add.d" in loongarch_opcode loongarch_fix_opcodes[].

* remove some unnecessary content from the ld/testsuite/ld-loongarch test case.




Changes from v1:

* Modified v1-0000-cover-letter.patch part of the explanatory content.

Before Modify:

example: __thread int a = 1;

old insn sequence:

lu12i.w $r12,%le_hi20_r(a)
ori     $r12,$r12,%le_lo12_r(a)
add.d   $r12,$r12,$r2,%le_add_r(a)
li.w  	$r13,$r0,1
stptr.w $r13,$r12,0

new insn sequence:

lu12i.w $r12,%le_hi20_r(a)
add.d   $r12,$r12,$r2,%le_add_r(a)
li.w  	$r13,$r0,1
st.w    $r13,$r12,%le_lo12_r(a)

After Modify:

example: __thread int a = 1;

old insn sequence(at the O0 optimization level):

lu12i.w $r12,%le_hi20(a)
ori     $r12,$r12,%le_lo12(a)
add.d   $r12,$r12,$r2
addi.w  $r13,$r0,1
stptr.w $r13,$r12,0

new insn sequence(at the O0 optimization level):

lu12i.w $r12,%le_hi20_r(a)
add.d   $r12,$r12,$r2,%le_add_r(a)
addi.w  $r13,$r0,1
st.w    $r13,$r12,%le_lo12_r(a)


changjiachen (5):
  LoongArch: bfd: Add support for tls le relax.
  LoongArch: include: Add support for tls le relax.
  LoongArch: opcodes: Add support for tls le relax.
  LoongArch: gas: Add support for tls le relax.
  LoongArch: ld: Add support for tls le relax.

 bfd/bfd-in2.h                                 |   4 +
 bfd/elfnn-loongarch.c                         |  76 +++++++++
 bfd/elfxx-loongarch.c                         |  50 ++++++
 bfd/libbfd.h                                  |   3 +
 bfd/reloc.c                                   |   6 +
 gas/config/tc-loongarch.c                     |  12 +-
 gas/testsuite/gas/loongarch/reloc.d           |  18 +++
 gas/testsuite/gas/loongarch/reloc.s           |  11 ++
 include/elf/loongarch.h                       |  12 ++
 ld/testsuite/ld-loongarch-elf/old-tls-le.s    |  19 +++
 .../relax-bound-check-tls-le.s                |  48 ++++++
 ld/testsuite/ld-loongarch-elf/relax-tls-le.s  |  17 ++
 ld/testsuite/ld-loongarch-elf/relax.exp       | 151 +++++++++++++++++-
 .../tls-relax-compatible-check-new.s          |  29 ++++
 .../tls-relax-compatible-check-old.s          |  27 ++++
 opcodes/loongarch-opc.c                       |   3 +-
 16 files changed, 482 insertions(+), 4 deletions(-)
 create mode 100644 ld/testsuite/ld-loongarch-elf/old-tls-le.s
 create mode 100644 ld/testsuite/ld-loongarch-elf/relax-bound-check-tls-le.s
 create mode 100644 ld/testsuite/ld-loongarch-elf/relax-tls-le.s
 create mode 100644 ld/testsuite/ld-loongarch-elf/tls-relax-compatible-check-new.s
 create mode 100644 ld/testsuite/ld-loongarch-elf/tls-relax-compatible-check-old.s

-- 
2.40.0