From: changjiachen <changjiachen@stu.xupt.edu.cn>
To: binutils@sourceware.org
Cc: xuchenghua@loongson.cn, chenglulu@loongson.cn,
liuzhensong@loongson.cn, xry111@xry111.site, i.swmail@xen0n.name,
maskray@google.com, cailulu@loongson.cn, luweining@loongson.cn,
wanglei@loongson.cn, hejinyang@loongson.cn, Lazy_Linux@126.com,
mengqinggang@loongson.cn,
changjiachen <changjiachen@stu.xupt.edu.cn>
Subject: [PATCH v3 4/5] LoongArch: gas: Add support for tls le relax.
Date: Fri, 15 Dec 2023 18:06:32 +0800 [thread overview]
Message-ID: <20231215100633.65397-5-changjiachen@stu.xupt.edu.cn> (raw)
In-Reply-To: <20231215100633.65397-1-changjiachen@stu.xupt.edu.cn>
Add tls le relax related relocs support and testsuites in gas.
The main test is three new relocation items,
R_LARCH_TLS_LE_ADD_R, R_LARCH_TLS_LE_HI20_R,
R_LARCH_TLS_LE_LO12_R can be generated properly.
gas/ChangeLog:
* config/tc-loongarch.c:
(loongarch_args_parser_can_match_arg_helper): Add support for relax.
* gas/testsuite/gas/loongarch/reloc.d: Likewise.
* gas/testsuite/gas/loongarch/reloc.s: Likewise.
---
gas/config/tc-loongarch.c | 12 ++++++++++--
gas/testsuite/gas/loongarch/reloc.d | 18 ++++++++++++++++++
gas/testsuite/gas/loongarch/reloc.s | 11 +++++++++++
3 files changed, 39 insertions(+), 2 deletions(-)
diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c
index 59232832cf7..c97288fe0a1 100644
--- a/gas/config/tc-loongarch.c
+++ b/gas/config/tc-loongarch.c
@@ -680,9 +680,8 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2,
as_fatal (
_("not support reloc bit-field\nfmt: %c%c %s\nargs: %s"),
esc_ch1, esc_ch2, bit_field, arg);
-
if (ip->reloc_info[0].type >= BFD_RELOC_LARCH_B16
- && ip->reloc_info[0].type < BFD_RELOC_LARCH_64_PCREL)
+ && ip->reloc_info[0].type < BFD_RELOC_UNUSED)
{
/* As we compact stack-relocs, it is no need for pop operation.
But break out until here in order to check the imm field.
@@ -690,6 +689,15 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2,
ip->reloc_num += reloc_num;
reloc_type = ip->reloc_info[0].type;
+ if (LARCH_opts.relax
+ && (BFD_RELOC_LARCH_TLS_LE_HI20_R == reloc_type
+ || BFD_RELOC_LARCH_TLS_LE_LO12_R == reloc_type
+ || BFD_RELOC_LARCH_TLS_LE_ADD_R == reloc_type))
+ {
+ ip->reloc_info[ip->reloc_num].type = BFD_RELOC_LARCH_RELAX;
+ ip->reloc_info[ip->reloc_num].value = const_0;
+ ip->reloc_num++;
+ }
if (LARCH_opts.relax && ip->macro_id
&& (BFD_RELOC_LARCH_PCALA_HI20 == reloc_type
|| BFD_RELOC_LARCH_PCALA_LO12 == reloc_type
diff --git a/gas/testsuite/gas/loongarch/reloc.d b/gas/testsuite/gas/loongarch/reloc.d
index c3820c55f98..0458830f30b 100644
--- a/gas/testsuite/gas/loongarch/reloc.d
+++ b/gas/testsuite/gas/loongarch/reloc.d
@@ -165,3 +165,21 @@ Disassembly of section .text:
[ ]+134:[ ]+R_LARCH_TLS_LE64_LO20[ ]+TLSL1\+0x8
[ ]+138:[ ]+03000085[ ]+lu52i.d[ ]+\$a1,[ ]+\$a0,[ ]+0
[ ]+138:[ ]+R_LARCH_TLS_LE64_HI12[ ]+TLSL1\+0x8
+[ ]+13c:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0
+[ ]+13c:[ ]+R_LARCH_TLS_LE_HI20_R[ ]+TLSL1
+[ ]+13c:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
+[ ]+140:[ ]+001090a5[ ]+add.d[ ]+\$a1,[ ]+\$a1,[ ]+\$a0
+[ ]+140:[ ]+R_LARCH_TLS_LE_ADD_R[ ]+TLSL1
+[ ]+140:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
+[ ]+144:[ ]+29800085[ ]+st.w[ ]+\$a1,[ ]+\$a0,[ ]+0
+[ ]+144:[ ]+R_LARCH_TLS_LE_LO12_R[ ]+TLSL1
+[ ]+144:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
+[ ]+148:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0
+[ ]+148:[ ]+R_LARCH_TLS_LE_HI20_R[ ]+TLSL1\+0x8
+[ ]+148:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
+[ ]+14c:[ ]+001090a5[ ]+add.d[ ]+\$a1,[ ]+\$a1,[ ]+\$a0
+[ ]+14c:[ ]+R_LARCH_TLS_LE_ADD_R[ ]+TLSL1\+0x8
+[ ]+14c:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
+[ ]+150:[ ]+29800085[ ]+st.w[ ]+\$a1,[ ]+\$a0,[ ]+0
+[ ]+150:[ ]+R_LARCH_TLS_LE_LO12_R[ ]+TLSL1\+0x8
+[ ]+150:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
diff --git a/gas/testsuite/gas/loongarch/reloc.s b/gas/testsuite/gas/loongarch/reloc.s
index a67fecd9429..0a343c11225 100644
--- a/gas/testsuite/gas/loongarch/reloc.s
+++ b/gas/testsuite/gas/loongarch/reloc.s
@@ -142,3 +142,14 @@ lu12i.w $r4,%le_hi20(TLSL1 + 0x8)
ori $r5,$r4,%le_lo12(TLSL1 + 0x8)
lu32i.d $r4,%le64_lo20(TLSL1 + 0x8)
lu52i.d $r5,$r4,%le64_hi12(TLSL1 + 0x8)
+
+
+/* New TLS Insn. */
+lu12i.w $r4,%le_hi20_r(TLSL1)
+add.d $r5,$r5,$r4,%le_add_r(TLSL1)
+st.w $r5,$r4,%le_lo12_r(TLSL1)
+
+/* New TLS Insn with addend. */
+lu12i.w $r4,%le_hi20_r(TLSL1 + 0x8)
+add.d $r5,$r5,$r4,%le_add_r(TLSL1 + 0x8)
+st.w $r5,$r4,%le_lo12_r(TLSL1 + 0x8)
--
2.40.0
next prev parent reply other threads:[~2023-12-15 10:06 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-15 10:06 [PATCH v3 0/5] LoongArch tls le model linker relaxation support changjiachen
2023-12-15 10:06 ` [PATCH v3 1/5] LoongArch: bfd: Add support for tls le relax changjiachen
2023-12-15 10:06 ` [PATCH v3 2/5] LoongArch: include: " changjiachen
2023-12-15 10:06 ` [PATCH v3 3/5] LoongArch: opcodes: " changjiachen
2023-12-15 10:06 ` changjiachen [this message]
2023-12-15 10:06 ` [PATCH v3 5/5] LoongArch: ld: " changjiachen
2023-12-15 12:34 ` [PATCH v3 0/5] LoongArch tls le model linker relaxation support Xi Ruoyao
2023-12-19 5:33 ` 常佳琛
2023-12-19 10:21 ` Xi Ruoyao
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