* [PING^2][PATCH v2] RISC-V: Imply 'Zicntr' and 'Zihpm' implicitly depended on 'Zicsr'
@ 2023-12-15 1:57 Xiao Zeng
2023-12-15 2:02 ` Palmer Dabbelt
0 siblings, 1 reply; 7+ messages in thread
From: Xiao Zeng @ 2023-12-15 1:57 UTC (permalink / raw)
To: binutils; +Cc: palmer, nelson, Xiao Zeng
This commit adds support for ratified extensions:
'Zicntr' and 'Zihpm', Which are all implicitly depend on 'Zicsr'.
This is based on:
<https://github.com/riscv/riscv-isa-manual/releases/download/riscv-isa-release-056b6ff-2023-10-02/unpriv-isa-asciidoc.pdf>
bfd/ChangeLog:
* elfxx-riscv.c: Add 'Zicntr' and 'Zihpm' -> 'Zicsr'.
(riscv_supported_std_z_ext) Add 'Zicntr' and 'Zihpm' to the list.
gas/ChangeLog:
* testsuite/gas/riscv/attribute-15.d: New test.
* testsuite/gas/riscv/attribute-15.s: New test.
* testsuite/gas/riscv/attribute-16.d: New test.
* testsuite/gas/riscv/attribute-16.s: New test.
---
bfd/elfxx-riscv.c | 4 ++++
gas/testsuite/gas/riscv/attribute-15.d | 6 ++++++
gas/testsuite/gas/riscv/attribute-15.s | 1 +
gas/testsuite/gas/riscv/attribute-16.d | 6 ++++++
gas/testsuite/gas/riscv/attribute-16.s | 1 +
5 files changed, 18 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/attribute-15.d
create mode 100644 gas/testsuite/gas/riscv/attribute-15.s
create mode 100644 gas/testsuite/gas/riscv/attribute-16.d
create mode 100644 gas/testsuite/gas/riscv/attribute-16.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 567631e7d96..4c91081acd1 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1144,6 +1144,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"zvl256b", "zvl128b", check_implicit_always},
{"zvl128b", "zvl64b", check_implicit_always},
{"zvl64b", "zvl32b", check_implicit_always},
+ {"zicntr", "zicsr", check_implicit_always},
+ {"zihpm", "zicsr", check_implicit_always},
{"zcd", "d", check_implicit_always},
{"zcf", "f", check_implicit_always},
{"zfa", "f", check_implicit_always},
@@ -1260,12 +1262,14 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zicbop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zicboz", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zicond", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zicntr", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 },
{"zicsr", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
{"zicsr", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
{"zifencei", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
{"zifencei", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
{"zihintntl", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 },
+ {"zihpm", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 },
{"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zfa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
diff --git a/gas/testsuite/gas/riscv/attribute-15.d b/gas/testsuite/gas/riscv/attribute-15.d
new file mode 100644
index 00000000000..a17e82c8508
--- /dev/null
+++ b/gas/testsuite/gas/riscv/attribute-15.d
@@ -0,0 +1,6 @@
+#as: -march-attr -misa-spec=20191213
+#readelf: -A
+#source: attribute-15.s
+Attribute Section: riscv
+File Attributes
+ Tag_RISCV_arch: "rv32i2p1_zicntr2p0_zicsr2p0_zihpm2p0"
diff --git a/gas/testsuite/gas/riscv/attribute-15.s b/gas/testsuite/gas/riscv/attribute-15.s
new file mode 100644
index 00000000000..ecb10a298fd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/attribute-15.s
@@ -0,0 +1 @@
+ .attribute arch,"rv32i_zicntr_zihpm"
diff --git a/gas/testsuite/gas/riscv/attribute-16.d b/gas/testsuite/gas/riscv/attribute-16.d
new file mode 100644
index 00000000000..6ca3b5351f8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/attribute-16.d
@@ -0,0 +1,6 @@
+#as: -march-attr -misa-spec=20191213
+#readelf: -A
+#source: attribute-16.s
+Attribute Section: riscv
+File Attributes
+ Tag_RISCV_arch: "rv64i2p1_zicntr2p0_zicsr2p0_zihpm2p0"
diff --git a/gas/testsuite/gas/riscv/attribute-16.s b/gas/testsuite/gas/riscv/attribute-16.s
new file mode 100644
index 00000000000..8757bb5181b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/attribute-16.s
@@ -0,0 +1 @@
+ .attribute arch,"rv64i_zicntr_zihpm"
--
2.17.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PING^2][PATCH v2] RISC-V: Imply 'Zicntr' and 'Zihpm' implicitly depended on 'Zicsr'
2023-12-15 1:57 [PING^2][PATCH v2] RISC-V: Imply 'Zicntr' and 'Zihpm' implicitly depended on 'Zicsr' Xiao Zeng
@ 2023-12-15 2:02 ` Palmer Dabbelt
2023-12-15 2:14 ` Nelson Chu
2023-12-15 2:23 ` Xiao Zeng
0 siblings, 2 replies; 7+ messages in thread
From: Palmer Dabbelt @ 2023-12-15 2:02 UTC (permalink / raw)
To: zengxiao; +Cc: binutils, nelson, zengxiao
On Thu, 14 Dec 2023 17:57:09 PST (-0800), zengxiao@eswincomputing.com wrote:
> This commit adds support for ratified extensions:
> 'Zicntr' and 'Zihpm', Which are all implicitly depend on 'Zicsr'.
>
> This is based on:
> <https://github.com/riscv/riscv-isa-manual/releases/download/riscv-isa-release-056b6ff-2023-10-02/unpriv-isa-asciidoc.pdf>
As far as I can tell the ISA doesn't actually provide that dependency,
but Zicntr and Zihpm are pretty much useless without the CSRs. So I
think this is fine to just assume, there's way bigger messes with the
whole counter/CSR retrofit.
So
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Thanks!
>
> bfd/ChangeLog:
>
> * elfxx-riscv.c: Add 'Zicntr' and 'Zihpm' -> 'Zicsr'.
> (riscv_supported_std_z_ext) Add 'Zicntr' and 'Zihpm' to the list.
>
> gas/ChangeLog:
>
> * testsuite/gas/riscv/attribute-15.d: New test.
> * testsuite/gas/riscv/attribute-15.s: New test.
> * testsuite/gas/riscv/attribute-16.d: New test.
> * testsuite/gas/riscv/attribute-16.s: New test.
> ---
> bfd/elfxx-riscv.c | 4 ++++
> gas/testsuite/gas/riscv/attribute-15.d | 6 ++++++
> gas/testsuite/gas/riscv/attribute-15.s | 1 +
> gas/testsuite/gas/riscv/attribute-16.d | 6 ++++++
> gas/testsuite/gas/riscv/attribute-16.s | 1 +
> 5 files changed, 18 insertions(+)
> create mode 100644 gas/testsuite/gas/riscv/attribute-15.d
> create mode 100644 gas/testsuite/gas/riscv/attribute-15.s
> create mode 100644 gas/testsuite/gas/riscv/attribute-16.d
> create mode 100644 gas/testsuite/gas/riscv/attribute-16.s
>
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index 567631e7d96..4c91081acd1 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1144,6 +1144,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
> {"zvl256b", "zvl128b", check_implicit_always},
> {"zvl128b", "zvl64b", check_implicit_always},
> {"zvl64b", "zvl32b", check_implicit_always},
> + {"zicntr", "zicsr", check_implicit_always},
> + {"zihpm", "zicsr", check_implicit_always},
> {"zcd", "d", check_implicit_always},
> {"zcf", "f", check_implicit_always},
> {"zfa", "f", check_implicit_always},
> @@ -1260,12 +1262,14 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
> {"zicbop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zicboz", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zicond", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"zicntr", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 },
> {"zicsr", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
> {"zicsr", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
> {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
> {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
> {"zihintntl", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 },
> + {"zihpm", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 },
> {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zfa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> diff --git a/gas/testsuite/gas/riscv/attribute-15.d b/gas/testsuite/gas/riscv/attribute-15.d
> new file mode 100644
> index 00000000000..a17e82c8508
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/attribute-15.d
> @@ -0,0 +1,6 @@
> +#as: -march-attr -misa-spec=20191213
> +#readelf: -A
> +#source: attribute-15.s
> +Attribute Section: riscv
> +File Attributes
> + Tag_RISCV_arch: "rv32i2p1_zicntr2p0_zicsr2p0_zihpm2p0"
> diff --git a/gas/testsuite/gas/riscv/attribute-15.s b/gas/testsuite/gas/riscv/attribute-15.s
> new file mode 100644
> index 00000000000..ecb10a298fd
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/attribute-15.s
> @@ -0,0 +1 @@
> + .attribute arch,"rv32i_zicntr_zihpm"
> diff --git a/gas/testsuite/gas/riscv/attribute-16.d b/gas/testsuite/gas/riscv/attribute-16.d
> new file mode 100644
> index 00000000000..6ca3b5351f8
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/attribute-16.d
> @@ -0,0 +1,6 @@
> +#as: -march-attr -misa-spec=20191213
> +#readelf: -A
> +#source: attribute-16.s
> +Attribute Section: riscv
> +File Attributes
> + Tag_RISCV_arch: "rv64i2p1_zicntr2p0_zicsr2p0_zihpm2p0"
> diff --git a/gas/testsuite/gas/riscv/attribute-16.s b/gas/testsuite/gas/riscv/attribute-16.s
> new file mode 100644
> index 00000000000..8757bb5181b
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/attribute-16.s
> @@ -0,0 +1 @@
> + .attribute arch,"rv64i_zicntr_zihpm"
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PING^2][PATCH v2] RISC-V: Imply 'Zicntr' and 'Zihpm' implicitly depended on 'Zicsr'
2023-12-15 2:02 ` Palmer Dabbelt
@ 2023-12-15 2:14 ` Nelson Chu
2023-12-15 2:34 ` Xiao Zeng
2023-12-15 2:23 ` Xiao Zeng
1 sibling, 1 reply; 7+ messages in thread
From: Nelson Chu @ 2023-12-15 2:14 UTC (permalink / raw)
To: Palmer Dabbelt; +Cc: zengxiao, binutils
[-- Attachment #1: Type: text/plain, Size: 5435 bytes --]
Okay. Since the gas/testcase/gas/riscv/attribue* test cases aren't used to
test the specific imply rules, so removed and committed. Generally more
test cases are usually good, but they still need to be precise and
meaningful.
Nelson
On Fri, Dec 15, 2023 at 10:02 AM Palmer Dabbelt <palmer@dabbelt.com> wrote:
> On Thu, 14 Dec 2023 17:57:09 PST (-0800), zengxiao@eswincomputing.com
> wrote:
> > This commit adds support for ratified extensions:
> > 'Zicntr' and 'Zihpm', Which are all implicitly depend on 'Zicsr'.
> >
> > This is based on:
> > <
> https://github.com/riscv/riscv-isa-manual/releases/download/riscv-isa-release-056b6ff-2023-10-02/unpriv-isa-asciidoc.pdf
> >
>
> As far as I can tell the ISA doesn't actually provide that dependency,
> but Zicntr and Zihpm are pretty much useless without the CSRs. So I
> think this is fine to just assume, there's way bigger messes with the
> whole counter/CSR retrofit.
>
> So
>
> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
>
> Thanks!
>
> >
> > bfd/ChangeLog:
> >
> > * elfxx-riscv.c: Add 'Zicntr' and 'Zihpm' -> 'Zicsr'.
> > (riscv_supported_std_z_ext) Add 'Zicntr' and 'Zihpm' to the list.
> >
> > gas/ChangeLog:
> >
> > * testsuite/gas/riscv/attribute-15.d: New test.
> > * testsuite/gas/riscv/attribute-15.s: New test.
> > * testsuite/gas/riscv/attribute-16.d: New test.
> > * testsuite/gas/riscv/attribute-16.s: New test.
> > ---
> > bfd/elfxx-riscv.c | 4 ++++
> > gas/testsuite/gas/riscv/attribute-15.d | 6 ++++++
> > gas/testsuite/gas/riscv/attribute-15.s | 1 +
> > gas/testsuite/gas/riscv/attribute-16.d | 6 ++++++
> > gas/testsuite/gas/riscv/attribute-16.s | 1 +
> > 5 files changed, 18 insertions(+)
> > create mode 100644 gas/testsuite/gas/riscv/attribute-15.d
> > create mode 100644 gas/testsuite/gas/riscv/attribute-15.s
> > create mode 100644 gas/testsuite/gas/riscv/attribute-16.d
> > create mode 100644 gas/testsuite/gas/riscv/attribute-16.s
> >
> > diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> > index 567631e7d96..4c91081acd1 100644
> > --- a/bfd/elfxx-riscv.c
> > +++ b/bfd/elfxx-riscv.c
> > @@ -1144,6 +1144,8 @@ static struct riscv_implicit_subset
> riscv_implicit_subsets[] =
> > {"zvl256b", "zvl128b", check_implicit_always},
> > {"zvl128b", "zvl64b", check_implicit_always},
> > {"zvl64b", "zvl32b", check_implicit_always},
> > + {"zicntr", "zicsr", check_implicit_always},
> > + {"zihpm", "zicsr", check_implicit_always},
> > {"zcd", "d", check_implicit_always},
> > {"zcf", "f", check_implicit_always},
> > {"zfa", "f", check_implicit_always},
> > @@ -1260,12 +1262,14 @@ static struct riscv_supported_ext
> riscv_supported_std_z_ext[] =
> > {"zicbop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > {"zicboz", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > {"zicond", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > + {"zicntr", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 },
> > {"zicsr", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
> > {"zicsr", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
> > {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
> > {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
> > {"zihintntl", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > {"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 },
> > + {"zihpm", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 },
> > {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > {"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > {"zfa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> > diff --git a/gas/testsuite/gas/riscv/attribute-15.d
> b/gas/testsuite/gas/riscv/attribute-15.d
> > new file mode 100644
> > index 00000000000..a17e82c8508
> > --- /dev/null
> > +++ b/gas/testsuite/gas/riscv/attribute-15.d
> > @@ -0,0 +1,6 @@
> > +#as: -march-attr -misa-spec=20191213
> > +#readelf: -A
> > +#source: attribute-15.s
> > +Attribute Section: riscv
> > +File Attributes
> > + Tag_RISCV_arch: "rv32i2p1_zicntr2p0_zicsr2p0_zihpm2p0"
> > diff --git a/gas/testsuite/gas/riscv/attribute-15.s
> b/gas/testsuite/gas/riscv/attribute-15.s
> > new file mode 100644
> > index 00000000000..ecb10a298fd
> > --- /dev/null
> > +++ b/gas/testsuite/gas/riscv/attribute-15.s
> > @@ -0,0 +1 @@
> > + .attribute arch,"rv32i_zicntr_zihpm"
> > diff --git a/gas/testsuite/gas/riscv/attribute-16.d
> b/gas/testsuite/gas/riscv/attribute-16.d
> > new file mode 100644
> > index 00000000000..6ca3b5351f8
> > --- /dev/null
> > +++ b/gas/testsuite/gas/riscv/attribute-16.d
> > @@ -0,0 +1,6 @@
> > +#as: -march-attr -misa-spec=20191213
> > +#readelf: -A
> > +#source: attribute-16.s
> > +Attribute Section: riscv
> > +File Attributes
> > + Tag_RISCV_arch: "rv64i2p1_zicntr2p0_zicsr2p0_zihpm2p0"
> > diff --git a/gas/testsuite/gas/riscv/attribute-16.s
> b/gas/testsuite/gas/riscv/attribute-16.s
> > new file mode 100644
> > index 00000000000..8757bb5181b
> > --- /dev/null
> > +++ b/gas/testsuite/gas/riscv/attribute-16.s
> > @@ -0,0 +1 @@
> > + .attribute arch,"rv64i_zicntr_zihpm"
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: Re: [PING^2][PATCH v2] RISC-V: Imply 'Zicntr' and 'Zihpm' implicitly depended on 'Zicsr'
2023-12-15 2:02 ` Palmer Dabbelt
2023-12-15 2:14 ` Nelson Chu
@ 2023-12-15 2:23 ` Xiao Zeng
2023-12-15 3:06 ` Nelson Chu
1 sibling, 1 reply; 7+ messages in thread
From: Xiao Zeng @ 2023-12-15 2:23 UTC (permalink / raw)
To: palmer; +Cc: binutils, Nelson Chu
2023-12-15 10:02 Palmer Dabbelt <palmer@dabbelt.com> wrote:
>
>On Thu, 14 Dec 2023 17:57:09 PST (-0800), zengxiao@eswincomputing.com wrote:
>> This commit adds support for ratified extensions:
>> 'Zicntr' and 'Zihpm', Which are all implicitly depend on 'Zicsr'.
>>
>> This is based on:
>> <https://github.com/riscv/riscv-isa-manual/releases/download/riscv-isa-release-056b6ff-2023-10-02/unpriv-isa-asciidoc.pdf>
>
>As far as I can tell the ISA doesn't actually provide that dependency,
Perhaps it was my mistake, but I clearly saw the following statement in the spec:
<https://github.com/riscv/riscv-isa-manual/blob/86b685a624110cf717f75cfaf5afb412b69f7f4e/src/counters.adoc#L15>
"The Zicntr extension depends on the Zicsr ext" and "The Zihpm extension
depends on the Zicsr extension. "
>but Zicntr and Zihpm are pretty much useless without the CSRs.
After reading the above spec, I understand that Zicntr and Zihpm
respectively focus on a certain type of csr register in Zicsr. More
specifically, the former focuses on "Base Counters and Timers ",
while the latter focuses on "hardware performance counters ".
>So I think this is fine to just assume, there's way bigger messes with the
>whole counter/CSR retrofit.
Of course, what I have said above is my own understanding and there
may be errors.
>
>So
>
>Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
>
>Thanks!
>
>>
>> bfd/ChangeLog:
>>
>> * elfxx-riscv.c: Add 'Zicntr' and 'Zihpm' -> 'Zicsr'.
>> (riscv_supported_std_z_ext) Add 'Zicntr' and 'Zihpm' to the list.
>>
>> gas/ChangeLog:
>>
>> * testsuite/gas/riscv/attribute-15.d: New test.
>> * testsuite/gas/riscv/attribute-15.s: New test.
>> * testsuite/gas/riscv/attribute-16.d: New test.
>> * testsuite/gas/riscv/attribute-16.s: New test.
>> ---
>> bfd/elfxx-riscv.c | 4 ++++
>> gas/testsuite/gas/riscv/attribute-15.d | 6 ++++++
>> gas/testsuite/gas/riscv/attribute-15.s | 1 +
>> gas/testsuite/gas/riscv/attribute-16.d | 6 ++++++
>> gas/testsuite/gas/riscv/attribute-16.s | 1 +
>> 5 files changed, 18 insertions(+)
>> create mode 100644 gas/testsuite/gas/riscv/attribute-15.d
>> create mode 100644 gas/testsuite/gas/riscv/attribute-15.s
>> create mode 100644 gas/testsuite/gas/riscv/attribute-16.d
>> create mode 100644 gas/testsuite/gas/riscv/attribute-16.s
>>
>> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
>> index 567631e7d96..4c91081acd1 100644
>> --- a/bfd/elfxx-riscv.c
>> +++ b/bfd/elfxx-riscv.c
>> @@ -1144,6 +1144,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
>> {"zvl256b", "zvl128b", check_implicit_always},
>> {"zvl128b", "zvl64b", check_implicit_always},
>> {"zvl64b", "zvl32b", check_implicit_always},
>> + {"zicntr", "zicsr", check_implicit_always},
>> + {"zihpm", "zicsr", check_implicit_always},
>> {"zcd", "d", check_implicit_always},
>> {"zcf", "f", check_implicit_always},
>> {"zfa", "f", check_implicit_always},
>> @@ -1260,12 +1262,14 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
>> {"zicbop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> {"zicboz", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> {"zicond", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> + {"zicntr", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 },
>> {"zicsr", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
>> {"zicsr", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
>> {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
>> {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
>> {"zihintntl", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> {"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 },
>> + {"zihpm", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 },
>> {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> {"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> {"zfa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> diff --git a/gas/testsuite/gas/riscv/attribute-15.d b/gas/testsuite/gas/riscv/attribute-15.d
>> new file mode 100644
>> index 00000000000..a17e82c8508
>> --- /dev/null
>> +++ b/gas/testsuite/gas/riscv/attribute-15.d
>> @@ -0,0 +1,6 @@
>> +#as: -march-attr -misa-spec=20191213
>> +#readelf: -A
>> +#source: attribute-15.s
>> +Attribute Section: riscv
>> +File Attributes
>> + Tag_RISCV_arch: "rv32i2p1_zicntr2p0_zicsr2p0_zihpm2p0"
>> diff --git a/gas/testsuite/gas/riscv/attribute-15.s b/gas/testsuite/gas/riscv/attribute-15.s
>> new file mode 100644
>> index 00000000000..ecb10a298fd
>> --- /dev/null
>> +++ b/gas/testsuite/gas/riscv/attribute-15.s
>> @@ -0,0 +1 @@
>> + .attribute arch,"rv32i_zicntr_zihpm"
>> diff --git a/gas/testsuite/gas/riscv/attribute-16.d b/gas/testsuite/gas/riscv/attribute-16.d
>> new file mode 100644
>> index 00000000000..6ca3b5351f8
>> --- /dev/null
>> +++ b/gas/testsuite/gas/riscv/attribute-16.d
>> @@ -0,0 +1,6 @@
>> +#as: -march-attr -misa-spec=20191213
>> +#readelf: -A
>> +#source: attribute-16.s
>> +Attribute Section: riscv
>> +File Attributes
>> + Tag_RISCV_arch: "rv64i2p1_zicntr2p0_zicsr2p0_zihpm2p0"
>> diff --git a/gas/testsuite/gas/riscv/attribute-16.s b/gas/testsuite/gas/riscv/attribute-16.s
>> new file mode 100644
>> index 00000000000..8757bb5181b
>> --- /dev/null
>> +++ b/gas/testsuite/gas/riscv/attribute-16.s
>> @@ -0,0 +1 @@
>> + .attribute arch,"rv64i_zicntr_zihpm"
Thanks
Xiao Zeng
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: Re: [PING^2][PATCH v2] RISC-V: Imply 'Zicntr' and 'Zihpm' implicitly depended on 'Zicsr'
2023-12-15 2:14 ` Nelson Chu
@ 2023-12-15 2:34 ` Xiao Zeng
0 siblings, 0 replies; 7+ messages in thread
From: Xiao Zeng @ 2023-12-15 2:34 UTC (permalink / raw)
To: Nelson Chu, palmer; +Cc: binutils
2023-12-15 10:14 Nelson Chu <nelson@rivosinc.com> wrote:
>
>Okay. Since the gas/testcase/gas/riscv/attribue* test cases aren't used to
>test the specific imply rules, so removed and committed.
Thanks
>Generally more test cases are usually good, but they still need to be precise and
>meaningful.
Yes, this is a very relevant suggestion. I will submit more precise and meaningful
test cases in the future.
>
>Nelson
>
>On Fri, Dec 15, 2023 at 10:02 AM Palmer Dabbelt <palmer@dabbelt.com> wrote:
>
>> On Thu, 14 Dec 2023 17:57:09 PST (-0800), zengxiao@eswincomputing.com
>> wrote:
>> > This commit adds support for ratified extensions:
>> > 'Zicntr' and 'Zihpm', Which are all implicitly depend on 'Zicsr'.
>> >
>> > This is based on:
>> > <
>> https://github.com/riscv/riscv-isa-manual/releases/download/riscv-isa-release-056b6ff-2023-10-02/unpriv-isa-asciidoc.pdf
>> >
>>
>> As far as I can tell the ISA doesn't actually provide that dependency,
>> but Zicntr and Zihpm are pretty much useless without the CSRs. So I
>> think this is fine to just assume, there's way bigger messes with the
>> whole counter/CSR retrofit.
>>
>> So
>>
>> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
>>
>> Thanks!
>>
>> >
>> > bfd/ChangeLog:
>> >
>> > * elfxx-riscv.c: Add 'Zicntr' and 'Zihpm' -> 'Zicsr'.
>> > (riscv_supported_std_z_ext) Add 'Zicntr' and 'Zihpm' to the list.
>> >
>> > gas/ChangeLog:
>> >
>> > * testsuite/gas/riscv/attribute-15.d: New test.
>> > * testsuite/gas/riscv/attribute-15.s: New test.
>> > * testsuite/gas/riscv/attribute-16.d: New test.
>> > * testsuite/gas/riscv/attribute-16.s: New test.
>> > ---
>> > bfd/elfxx-riscv.c | 4 ++++
>> > gas/testsuite/gas/riscv/attribute-15.d | 6 ++++++
>> > gas/testsuite/gas/riscv/attribute-15.s | 1 +
>> > gas/testsuite/gas/riscv/attribute-16.d | 6 ++++++
>> > gas/testsuite/gas/riscv/attribute-16.s | 1 +
>> > 5 files changed, 18 insertions(+)
>> > create mode 100644 gas/testsuite/gas/riscv/attribute-15.d
>> > create mode 100644 gas/testsuite/gas/riscv/attribute-15.s
>> > create mode 100644 gas/testsuite/gas/riscv/attribute-16.d
>> > create mode 100644 gas/testsuite/gas/riscv/attribute-16.s
>> >
>> > diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
>> > index 567631e7d96..4c91081acd1 100644
>> > --- a/bfd/elfxx-riscv.c
>> > +++ b/bfd/elfxx-riscv.c
>> > @@ -1144,6 +1144,8 @@ static struct riscv_implicit_subset
>> riscv_implicit_subsets[] =
>> > {"zvl256b", "zvl128b", check_implicit_always},
>> > {"zvl128b", "zvl64b", check_implicit_always},
>> > {"zvl64b", "zvl32b", check_implicit_always},
>> > + {"zicntr", "zicsr", check_implicit_always},
>> > + {"zihpm", "zicsr", check_implicit_always},
>> > {"zcd", "d", check_implicit_always},
>> > {"zcf", "f", check_implicit_always},
>> > {"zfa", "f", check_implicit_always},
>> > @@ -1260,12 +1262,14 @@ static struct riscv_supported_ext
>> riscv_supported_std_z_ext[] =
>> > {"zicbop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> > {"zicboz", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> > {"zicond", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> > + {"zicntr", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 },
>> > {"zicsr", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
>> > {"zicsr", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
>> > {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
>> > {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
>> > {"zihintntl", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> > {"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 },
>> > + {"zihpm", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 },
>> > {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> > {"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> > {"zfa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> > diff --git a/gas/testsuite/gas/riscv/attribute-15.d
>> b/gas/testsuite/gas/riscv/attribute-15.d
>> > new file mode 100644
>> > index 00000000000..a17e82c8508
>> > --- /dev/null
>> > +++ b/gas/testsuite/gas/riscv/attribute-15.d
>> > @@ -0,0 +1,6 @@
>> > +#as: -march-attr -misa-spec=20191213
>> > +#readelf: -A
>> > +#source: attribute-15.s
>> > +Attribute Section: riscv
>> > +File Attributes
>> > + Tag_RISCV_arch: "rv32i2p1_zicntr2p0_zicsr2p0_zihpm2p0"
>> > diff --git a/gas/testsuite/gas/riscv/attribute-15.s
>> b/gas/testsuite/gas/riscv/attribute-15.s
>> > new file mode 100644
>> > index 00000000000..ecb10a298fd
>> > --- /dev/null
>> > +++ b/gas/testsuite/gas/riscv/attribute-15.s
>> > @@ -0,0 +1 @@
>> > + .attribute arch,"rv32i_zicntr_zihpm"
>> > diff --git a/gas/testsuite/gas/riscv/attribute-16.d
>> b/gas/testsuite/gas/riscv/attribute-16.d
>> > new file mode 100644
>> > index 00000000000..6ca3b5351f8
>> > --- /dev/null
>> > +++ b/gas/testsuite/gas/riscv/attribute-16.d
>> > @@ -0,0 +1,6 @@
>> > +#as: -march-attr -misa-spec=20191213
>> > +#readelf: -A
>> > +#source: attribute-16.s
>> > +Attribute Section: riscv
>> > +File Attributes
>> > + Tag_RISCV_arch: "rv64i2p1_zicntr2p0_zicsr2p0_zihpm2p0"
>> > diff --git a/gas/testsuite/gas/riscv/attribute-16.s
>> b/gas/testsuite/gas/riscv/attribute-16.s
>> > new file mode 100644
>> > index 00000000000..8757bb5181b
>> > --- /dev/null
>> > +++ b/gas/testsuite/gas/riscv/attribute-16.s
>> > @@ -0,0 +1 @@
>> > + .attribute arch,"rv64i_zicntr_zihpm"
>>
Thanks
Xiao Zeng
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: Re: [PING^2][PATCH v2] RISC-V: Imply 'Zicntr' and 'Zihpm' implicitly depended on 'Zicsr'
2023-12-15 2:23 ` Xiao Zeng
@ 2023-12-15 3:06 ` Nelson Chu
2023-12-15 4:26 ` Xiao Zeng
0 siblings, 1 reply; 7+ messages in thread
From: Nelson Chu @ 2023-12-15 3:06 UTC (permalink / raw)
To: Xiao Zeng; +Cc: palmer, binutils
[-- Attachment #1: Type: text/plain, Size: 6034 bytes --]
"Depend on" means "imply", this should be clarified in,
https://github.com/riscv/riscv-v-spec/pull/845. So your understanding is
correct, if the rule doesn't change.
Nelson
On Fri, Dec 15, 2023 at 10:23 AM Xiao Zeng <zengxiao@eswincomputing.com>
wrote:
> 2023-12-15 10:02 Palmer Dabbelt <palmer@dabbelt.com> wrote:
> >
>
> >On Thu, 14 Dec 2023 17:57:09 PST (-0800), zengxiao@eswincomputing.com
> wrote:
> >> This commit adds support for ratified extensions:
> >> 'Zicntr' and 'Zihpm', Which are all implicitly depend on 'Zicsr'.
> >>
> >> This is based on:
> >> <
> https://github.com/riscv/riscv-isa-manual/releases/download/riscv-isa-release-056b6ff-2023-10-02/unpriv-isa-asciidoc.pdf
> >
> >
> >As far as I can tell the ISA doesn't actually provide that dependency,
> Perhaps it was my mistake, but I clearly saw the following statement in
> the spec:
> <
> https://github.com/riscv/riscv-isa-manual/blob/86b685a624110cf717f75cfaf5afb412b69f7f4e/src/counters.adoc#L15
> >
> "The Zicntr extension depends on the Zicsr ext" and "The Zihpm extension
> depends on the Zicsr extension. "
>
> >but Zicntr and Zihpm are pretty much useless without the CSRs.
> After reading the above spec, I understand that Zicntr and Zihpm
> respectively focus on a certain type of csr register in Zicsr. More
> specifically, the former focuses on "Base Counters and Timers ",
> while the latter focuses on "hardware performance counters ".
>
> >So I think this is fine to just assume, there's way bigger messes with the
> >whole counter/CSR retrofit.
> Of course, what I have said above is my own understanding and there
> may be errors.
>
> >
> >So
> >
> >Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
> >
> >Thanks!
> >
> >>
> >> bfd/ChangeLog:
> >>
> >> * elfxx-riscv.c: Add 'Zicntr' and 'Zihpm' -> 'Zicsr'.
> >> (riscv_supported_std_z_ext) Add 'Zicntr' and 'Zihpm' to the
> list.
> >>
> >> gas/ChangeLog:
> >>
> >> * testsuite/gas/riscv/attribute-15.d: New test.
> >> * testsuite/gas/riscv/attribute-15.s: New test.
> >> * testsuite/gas/riscv/attribute-16.d: New test.
> >> * testsuite/gas/riscv/attribute-16.s: New test.
> >> ---
> >> bfd/elfxx-riscv.c | 4 ++++
> >> gas/testsuite/gas/riscv/attribute-15.d | 6 ++++++
> >> gas/testsuite/gas/riscv/attribute-15.s | 1 +
> >> gas/testsuite/gas/riscv/attribute-16.d | 6 ++++++
> >> gas/testsuite/gas/riscv/attribute-16.s | 1 +
> >> 5 files changed, 18 insertions(+)
> >> create mode 100644 gas/testsuite/gas/riscv/attribute-15.d
> >> create mode 100644 gas/testsuite/gas/riscv/attribute-15.s
> >> create mode 100644 gas/testsuite/gas/riscv/attribute-16.d
> >> create mode 100644 gas/testsuite/gas/riscv/attribute-16.s
> >>
> >> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> >> index 567631e7d96..4c91081acd1 100644
> >> --- a/bfd/elfxx-riscv.c
> >> +++ b/bfd/elfxx-riscv.c
> >> @@ -1144,6 +1144,8 @@ static struct riscv_implicit_subset
> riscv_implicit_subsets[] =
> >> {"zvl256b", "zvl128b", check_implicit_always},
> >> {"zvl128b", "zvl64b", check_implicit_always},
> >> {"zvl64b", "zvl32b", check_implicit_always},
> >> + {"zicntr", "zicsr", check_implicit_always},
> >> + {"zihpm", "zicsr", check_implicit_always},
> >> {"zcd", "d", check_implicit_always},
> >> {"zcf", "f", check_implicit_always},
> >> {"zfa", "f", check_implicit_always},
> >> @@ -1260,12 +1262,14 @@ static struct riscv_supported_ext
> riscv_supported_std_z_ext[] =
> >> {"zicbop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> >> {"zicboz", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> >> {"zicond", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> >> + {"zicntr", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 },
> >> {"zicsr", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
> >> {"zicsr", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
> >> {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
> >> {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
> >> {"zihintntl", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> >> {"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 },
> >> + {"zihpm", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 },
> >> {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> >> {"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> >> {"zfa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> >> diff --git a/gas/testsuite/gas/riscv/attribute-15.d
> b/gas/testsuite/gas/riscv/attribute-15.d
> >> new file mode 100644
> >> index 00000000000..a17e82c8508
> >> --- /dev/null
> >> +++ b/gas/testsuite/gas/riscv/attribute-15.d
> >> @@ -0,0 +1,6 @@
> >> +#as: -march-attr -misa-spec=20191213
> >> +#readelf: -A
> >> +#source: attribute-15.s
> >> +Attribute Section: riscv
> >> +File Attributes
> >> + Tag_RISCV_arch: "rv32i2p1_zicntr2p0_zicsr2p0_zihpm2p0"
> >> diff --git a/gas/testsuite/gas/riscv/attribute-15.s
> b/gas/testsuite/gas/riscv/attribute-15.s
> >> new file mode 100644
> >> index 00000000000..ecb10a298fd
> >> --- /dev/null
> >> +++ b/gas/testsuite/gas/riscv/attribute-15.s
> >> @@ -0,0 +1 @@
> >> + .attribute arch,"rv32i_zicntr_zihpm"
> >> diff --git a/gas/testsuite/gas/riscv/attribute-16.d
> b/gas/testsuite/gas/riscv/attribute-16.d
> >> new file mode 100644
> >> index 00000000000..6ca3b5351f8
> >> --- /dev/null
> >> +++ b/gas/testsuite/gas/riscv/attribute-16.d
> >> @@ -0,0 +1,6 @@
> >> +#as: -march-attr -misa-spec=20191213
> >> +#readelf: -A
> >> +#source: attribute-16.s
> >> +Attribute Section: riscv
> >> +File Attributes
> >> + Tag_RISCV_arch: "rv64i2p1_zicntr2p0_zicsr2p0_zihpm2p0"
> >> diff --git a/gas/testsuite/gas/riscv/attribute-16.s
> b/gas/testsuite/gas/riscv/attribute-16.s
> >> new file mode 100644
> >> index 00000000000..8757bb5181b
> >> --- /dev/null
> >> +++ b/gas/testsuite/gas/riscv/attribute-16.s
> >> @@ -0,0 +1 @@
> >> + .attribute arch,"rv64i_zicntr_zihpm"
>
> Thanks
> Xiao Zeng
>
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: Re: [PING^2][PATCH v2] RISC-V: Imply 'Zicntr' and 'Zihpm' implicitly depended on 'Zicsr'
2023-12-15 3:06 ` Nelson Chu
@ 2023-12-15 4:26 ` Xiao Zeng
0 siblings, 0 replies; 7+ messages in thread
From: Xiao Zeng @ 2023-12-15 4:26 UTC (permalink / raw)
To: Nelson Chu; +Cc: palmer, binutils
2023-12-15 11:06 Nelson Chu <nelson@rivosinc.com> wrote:
>
>"Depend on" means "imply", this should be clarified in,
>https://github.com/riscv/riscv-v-spec/pull/845.
Thank you, Nelson, for providing such an accurate link URL.
>So your understanding is correct, if the rule doesn't change.
I will continue to monitor changes on the spec.
>
>Nelson
>
>On Fri, Dec 15, 2023 at 10:23 AM Xiao Zeng <zengxiao@eswincomputing.com>
>wrote:
>
>> 2023-12-15 10:02 Palmer Dabbelt <palmer@dabbelt.com> wrote:
>> >
>>
>> >On Thu, 14 Dec 2023 17:57:09 PST (-0800), zengxiao@eswincomputing.com
>> wrote:
>> >> This commit adds support for ratified extensions:
>> >> 'Zicntr' and 'Zihpm', Which are all implicitly depend on 'Zicsr'.
>> >>
>> >> This is based on:
>> >> <
>> https://github.com/riscv/riscv-isa-manual/releases/download/riscv-isa-release-056b6ff-2023-10-02/unpriv-isa-asciidoc.pdf
>> >
>> >
>> >As far as I can tell the ISA doesn't actually provide that dependency,
>> Perhaps it was my mistake, but I clearly saw the following statement in
>> the spec:
>> <
>> https://github.com/riscv/riscv-isa-manual/blob/86b685a624110cf717f75cfaf5afb412b69f7f4e/src/counters.adoc#L15
>> >
>> "The Zicntr extension depends on the Zicsr ext" and "The Zihpm extension
>> depends on the Zicsr extension. "
>>
>> >but Zicntr and Zihpm are pretty much useless without the CSRs.
>> After reading the above spec, I understand that Zicntr and Zihpm
>> respectively focus on a certain type of csr register in Zicsr. More
>> specifically, the former focuses on "Base Counters and Timers ",
>> while the latter focuses on "hardware performance counters ".
>>
>> >So I think this is fine to just assume, there's way bigger messes with the
>> >whole counter/CSR retrofit.
>> Of course, what I have said above is my own understanding and there
>> may be errors.
>>
>> >
>> >So
>> >
>> >Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
>> >
>> >Thanks!
>> >
>> >>
>> >> bfd/ChangeLog:
>> >>
>> >> * elfxx-riscv.c: Add 'Zicntr' and 'Zihpm' -> 'Zicsr'.
>> >> (riscv_supported_std_z_ext) Add 'Zicntr' and 'Zihpm' to the
>> list.
>> >>
>> >> gas/ChangeLog:
>> >>
>> >> * testsuite/gas/riscv/attribute-15.d: New test.
>> >> * testsuite/gas/riscv/attribute-15.s: New test.
>> >> * testsuite/gas/riscv/attribute-16.d: New test.
>> >> * testsuite/gas/riscv/attribute-16.s: New test.
>> >> ---
>> >> bfd/elfxx-riscv.c | 4 ++++
>> >> gas/testsuite/gas/riscv/attribute-15.d | 6 ++++++
>> >> gas/testsuite/gas/riscv/attribute-15.s | 1 +
>> >> gas/testsuite/gas/riscv/attribute-16.d | 6 ++++++
>> >> gas/testsuite/gas/riscv/attribute-16.s | 1 +
>> >> 5 files changed, 18 insertions(+)
>> >> create mode 100644 gas/testsuite/gas/riscv/attribute-15.d
>> >> create mode 100644 gas/testsuite/gas/riscv/attribute-15.s
>> >> create mode 100644 gas/testsuite/gas/riscv/attribute-16.d
>> >> create mode 100644 gas/testsuite/gas/riscv/attribute-16.s
>> >>
>> >> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
>> >> index 567631e7d96..4c91081acd1 100644
>> >> --- a/bfd/elfxx-riscv.c
>> >> +++ b/bfd/elfxx-riscv.c
>> >> @@ -1144,6 +1144,8 @@ static struct riscv_implicit_subset
>> riscv_implicit_subsets[] =
>> >> {"zvl256b", "zvl128b", check_implicit_always},
>> >> {"zvl128b", "zvl64b", check_implicit_always},
>> >> {"zvl64b", "zvl32b", check_implicit_always},
>> >> + {"zicntr", "zicsr", check_implicit_always},
>> >> + {"zihpm", "zicsr", check_implicit_always},
>> >> {"zcd", "d", check_implicit_always},
>> >> {"zcf", "f", check_implicit_always},
>> >> {"zfa", "f", check_implicit_always},
>> >> @@ -1260,12 +1262,14 @@ static struct riscv_supported_ext
>> riscv_supported_std_z_ext[] =
>> >> {"zicbop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> >> {"zicboz", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> >> {"zicond", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> >> + {"zicntr", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 },
>> >> {"zicsr", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
>> >> {"zicsr", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
>> >> {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
>> >> {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
>> >> {"zihintntl", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> >> {"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 },
>> >> + {"zihpm", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 },
>> >> {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> >> {"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> >> {"zfa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> >> diff --git a/gas/testsuite/gas/riscv/attribute-15.d
>> b/gas/testsuite/gas/riscv/attribute-15.d
>> >> new file mode 100644
>> >> index 00000000000..a17e82c8508
>> >> --- /dev/null
>> >> +++ b/gas/testsuite/gas/riscv/attribute-15.d
>> >> @@ -0,0 +1,6 @@
>> >> +#as: -march-attr -misa-spec=20191213
>> >> +#readelf: -A
>> >> +#source: attribute-15.s
>> >> +Attribute Section: riscv
>> >> +File Attributes
>> >> + Tag_RISCV_arch: "rv32i2p1_zicntr2p0_zicsr2p0_zihpm2p0"
>> >> diff --git a/gas/testsuite/gas/riscv/attribute-15.s
>> b/gas/testsuite/gas/riscv/attribute-15.s
>> >> new file mode 100644
>> >> index 00000000000..ecb10a298fd
>> >> --- /dev/null
>> >> +++ b/gas/testsuite/gas/riscv/attribute-15.s
>> >> @@ -0,0 +1 @@
>> >> + .attribute arch,"rv32i_zicntr_zihpm"
>> >> diff --git a/gas/testsuite/gas/riscv/attribute-16.d
>> b/gas/testsuite/gas/riscv/attribute-16.d
>> >> new file mode 100644
>> >> index 00000000000..6ca3b5351f8
>> >> --- /dev/null
>> >> +++ b/gas/testsuite/gas/riscv/attribute-16.d
>> >> @@ -0,0 +1,6 @@
>> >> +#as: -march-attr -misa-spec=20191213
>> >> +#readelf: -A
>> >> +#source: attribute-16.s
>> >> +Attribute Section: riscv
>> >> +File Attributes
>> >> + Tag_RISCV_arch: "rv64i2p1_zicntr2p0_zicsr2p0_zihpm2p0"
>> >> diff --git a/gas/testsuite/gas/riscv/attribute-16.s
>> b/gas/testsuite/gas/riscv/attribute-16.s
>> >> new file mode 100644
>> >> index 00000000000..8757bb5181b
>> >> --- /dev/null
>> >> +++ b/gas/testsuite/gas/riscv/attribute-16.s
>> >> @@ -0,0 +1 @@
>> >> + .attribute arch,"rv64i_zicntr_zihpm"
>>
>> Thanks
>> Xiao Zeng
>>
>>
Thanks
Xiao Zeng
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2023-12-15 4:26 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-12-15 1:57 [PING^2][PATCH v2] RISC-V: Imply 'Zicntr' and 'Zihpm' implicitly depended on 'Zicsr' Xiao Zeng
2023-12-15 2:02 ` Palmer Dabbelt
2023-12-15 2:14 ` Nelson Chu
2023-12-15 2:34 ` Xiao Zeng
2023-12-15 2:23 ` Xiao Zeng
2023-12-15 3:06 ` Nelson Chu
2023-12-15 4:26 ` Xiao Zeng
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