* [PATCH 1/2] LoongArch: Delete extra instructions when TLS type transition
@ 2024-01-26 13:55 Lulu Cai
2024-01-26 13:55 ` [PATCH 2/2] LoongArch: Fix some test cases for TLS transition and relax Lulu Cai
2024-01-26 18:22 ` [PATCH 1/2] LoongArch: Delete extra instructions when TLS type transition Xi Ruoyao
0 siblings, 2 replies; 4+ messages in thread
From: Lulu Cai @ 2024-01-26 13:55 UTC (permalink / raw)
To: binutils
Cc: xuchenghua, chenglulu, liuzhensong, mengqinggang, xry111,
i.swmail, maskray, luweining, wanglei, hejinyang, Lulu Cai
This modification mainly changes the timing of type transition,
adds relaxation to the old LE instruction sequence, and fixes
bugs in extreme code models.
We strictly distinguish between type transition and relaxation.
Type transition is from one type to another, while relaxation
is the removal of instructions under the same TLS type. Detailed
instructions are as follows:
1. For type transition, only the normal code model of DESC/IE
does type transition, and each relocation is accompanied by a
RELAX relocation. Neither abs nor extreme will do type transition,
and no RELAX relocation will be generated.
The extra instructions when DESC transitions to other TLS types
will be deleted during the type transition.
2. Implemented relaxation for the old LE instruction sequence.
The first two instructions of LE's 32-bit and 64-bit models
use the same relocations and cannot be distinguished based on
relocations. Therefore, for LE's instruction sequence, any code
model will try to relax.
3. Some function names have been adjusted to facilitate understanding,
parameters have been adjusted, and unused macros have been deleted.
---
bfd/elfnn-loongarch.c | 401 ++++++++++++++++++++++----------------
gas/config/tc-loongarch.c | 31 ++-
2 files changed, 260 insertions(+), 172 deletions(-)
diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c
index b2caa5fc3e1..c4babab5673 100644
--- a/bfd/elfnn-loongarch.c
+++ b/bfd/elfnn-loongarch.c
@@ -145,16 +145,20 @@ struct loongarch_elf_link_hash_table
#define elf_backend_rela_normal 1
#define elf_backend_default_execstack 0
-#define IS_LOONGARCH_TLS_DESC_RELOC(R_TYPE) \
- ((R_TYPE) == R_LARCH_TLS_DESC_PC_HI20 \
- || (R_TYPE) == R_LARCH_TLS_DESC_PC_LO12 \
- || (R_TYPE) == R_LARCH_TLS_DESC_LD \
- || (R_TYPE) == R_LARCH_TLS_DESC_CALL)
-
-#define IS_LOONGARCH_TLS_IE_RELOC(R_TYPE) \
- ((R_TYPE) == R_LARCH_TLS_IE_PC_HI20 \
+#define IS_LOONGARCH_TLS_TRANS_RELOC(R_TYPE) \
+ ((R_TYPE) == R_LARCH_TLS_DESC_PC_HI20 \
+ || (R_TYPE) == R_LARCH_TLS_DESC_PC_LO12 \
+ || (R_TYPE) == R_LARCH_TLS_DESC_LD \
+ || (R_TYPE) == R_LARCH_TLS_DESC_CALL \
+ || (R_TYPE) == R_LARCH_TLS_IE_PC_HI20 \
|| (R_TYPE) == R_LARCH_TLS_IE_PC_LO12)
+#define IS_OUTDATED_TLS_LE_RELOC(R_TYPE) \
+ ((R_TYPE) == R_LARCH_TLS_LE_HI20 \
+ || (R_TYPE) == R_LARCH_TLS_LE_LO12 \
+ || (R_TYPE) == R_LARCH_TLS_LE64_LO20 \
+ || (R_TYPE) == R_LARCH_TLS_LE64_HI12)
+
/* Generate a PLT header. */
static bool
@@ -642,15 +646,20 @@ loongarch_reloc_got_type (unsigned int r_type)
/* Return true if tls type transition can be performed. */
static bool
-loongarch_can_relax_tls (struct bfd_link_info *info, unsigned int r_type,
- struct elf_link_hash_entry *h, bfd *input_bfd,
- unsigned long r_symndx)
+loongarch_can_trans_tls (bfd *input_bfd,
+ struct bfd_link_info *info,
+ struct elf_link_hash_entry *h,
+ const Elf_Internal_Rela *rel,
+ unsigned int r_type)
{
char symbol_tls_type;
unsigned int reloc_got_type;
+ unsigned int r_symndx = ELFNN_R_SYM (rel->r_info);
- if (! (IS_LOONGARCH_TLS_DESC_RELOC (r_type)
- || IS_LOONGARCH_TLS_IE_RELOC (r_type)))
+ /* Only TLS DESC/IE in normal code mode will perform type
+ transition. */
+ if (! (IS_LOONGARCH_TLS_TRANS_RELOC (r_type)
+ && ELFNN_R_TYPE ((rel + 1)->r_info) == R_LARCH_RELAX))
return false;
symbol_tls_type = _bfd_loongarch_elf_tls_type (input_bfd, h, r_symndx);
@@ -707,11 +716,13 @@ loongarch_tls_transition_without_check (struct bfd_link_info *info,
}
static unsigned int
-loongarch_tls_transition (struct bfd_link_info *info, unsigned int r_type,
- struct elf_link_hash_entry *h, bfd *input_bfd,
- unsigned long r_symndx)
+loongarch_tls_transition (bfd *input_bfd,
+ struct bfd_link_info *info,
+ struct elf_link_hash_entry *h,
+ const Elf_Internal_Rela *rel,
+ unsigned int r_type)
{
- if (! loongarch_can_relax_tls (info, r_type, h, input_bfd,r_symndx))
+ if (! loongarch_can_trans_tls (input_bfd, info, h, rel, r_type))
return r_type;
return loongarch_tls_transition_without_check (info, r_type, h);
@@ -818,7 +829,7 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info,
int need_dynreloc = 0;
int only_need_pcrel = 0;
- r_type = loongarch_tls_transition (info, r_type, h, abfd, r_symndx);
+ r_type = loongarch_tls_transition (abfd, info, h, rel, r_type);
switch (r_type)
{
case R_LARCH_GOT_PC_HI20:
@@ -2534,95 +2545,6 @@ loongarch_reloc_is_fatal (struct bfd_link_info *info,
relocation += 0x100000000; \
})
-/* Transition instruction sequence to relax instruction sequence. */
-static bool
-loongarch_tls_relax (bfd *abfd, asection *sec, Elf_Internal_Rela *rel,
- int r_type, struct elf_link_hash_entry *h,
- struct bfd_link_info *info)
-{
- bool local_exec = bfd_link_executable (info)
- && SYMBOL_REFERENCES_LOCAL (info, h);
- bfd_byte *contents = elf_section_data (sec)->this_hdr.contents;
- unsigned long insn;
-
- switch (r_type)
- {
- case R_LARCH_TLS_DESC_PC_HI20:
- if (local_exec)
- /* DESC -> LE relaxation:
- pcalalau12i $a0,%desc_pc_hi20(var) =>
- lu12i.w $a0,%le_hi20(var)
- */
- bfd_put (32, abfd, LARCH_LU12I_W | LARCH_RD_A0,
- contents + rel->r_offset);
-
- /* DESC -> IE relaxation:
- pcalalau12i $a0,%desc_pc_hi20(var) =>
- pcalalau12i $a0,%ie_pc_hi20(var)
- */
- return true;
-
- case R_LARCH_TLS_DESC_PC_LO12:
- if (local_exec)
- {
- /* DESC -> LE relaxation:
- addi.d $a0,$a0,%desc_pc_lo12(var) =>
- ori $a0,$a0,le_lo12(var)
- */
- insn = LARCH_ORI | LARCH_RD_RJ_A0;
- bfd_put (32, abfd, LARCH_ORI | LARCH_RD_RJ_A0,
- contents + rel->r_offset);
- }
- else
- {
- /* DESC -> IE relaxation:
- addi.d $a0,$a0,%desc_pc_lo12(var) =>
- ld.d $a0,$a0,%%ie_pc_lo12
- */
- bfd_put (32, abfd, LARCH_LD_D | LARCH_RD_RJ_A0,
- contents + rel->r_offset);
- }
- return true;
-
- case R_LARCH_TLS_DESC_LD:
- case R_LARCH_TLS_DESC_CALL:
- /* DESC -> LE/IE relaxation:
- ld.d $ra,$a0,%desc_ld(var) => NOP
- jirl $ra,$ra,%desc_call(var) => NOP
- */
- bfd_put (32, abfd, LARCH_NOP, contents + rel->r_offset);
- return true;
-
- case R_LARCH_TLS_IE_PC_HI20:
- if (local_exec)
- {
- /* IE -> LE relaxation:
- pcalalau12i $rd,%ie_pc_hi20(var) =>
- lu12i.w $rd,%le_hi20(var)
- */
- insn = bfd_getl32 (contents + rel->r_offset);
- bfd_put (32, abfd, LARCH_LU12I_W | (insn & 0x1f),
- contents + rel->r_offset);
- }
- return true;
-
- case R_LARCH_TLS_IE_PC_LO12:
- if (local_exec)
- {
- /* IE -> LE relaxation:
- ld.d $rd,$rj,%%ie_pc_lo12 =>
- ori $rd,$rj,le_lo12(var)
- */
- insn = bfd_getl32 (contents + rel->r_offset);
- bfd_put (32, abfd, LARCH_ORI | (insn & 0x3ff),
- contents + rel->r_offset);
- }
- return true;
- }
-
- return false;
-}
-
static int
loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
@@ -2657,7 +2579,6 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
const char *name;
bfd_reloc_status_type r = bfd_reloc_ok;
bool is_ie, is_desc, is_undefweak, unresolved_reloc, defined_local;
- unsigned int relaxed_r_type;
bool resolved_local, resolved_dynly, resolved_to_const;
char tls_type;
bfd_vma relocation, off, ie_off, desc_off;
@@ -2789,16 +2710,6 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
BFD_ASSERT (!resolved_local || defined_local);
- relaxed_r_type = loongarch_tls_transition (info, r_type, h, input_bfd, r_symndx);
- if (relaxed_r_type != r_type)
- {
- howto = loongarch_elf_rtype_to_howto (input_bfd, relaxed_r_type);
- BFD_ASSERT (howto != NULL);
-
- if (loongarch_tls_relax (input_bfd, input_section, rel, r_type, h, info))
- r_type = relaxed_r_type;
- }
-
is_desc = false;
is_ie = false;
switch (r_type)
@@ -4118,6 +4029,113 @@ loongarch_relax_delete_bytes (bfd *abfd,
return true;
}
+
+/* Start perform TLS type transition.
+ Currently there are three cases of relocation handled here:
+ DESC -> IE, DEC -> LE and IE -> LE. */
+static bool
+loongarch_tls_perform_trans (bfd *abfd, asection *sec,
+ Elf_Internal_Rela *rel,
+ struct elf_link_hash_entry *h,
+ struct bfd_link_info *info)
+{
+ unsigned long insn;
+ bool local_exec = bfd_link_executable (info)
+ && SYMBOL_REFERENCES_LOCAL (info, h);
+ bfd_byte *contents = elf_section_data (sec)->this_hdr.contents;
+ unsigned long r_type = ELFNN_R_TYPE (rel->r_info);
+ unsigned long r_symndx = ELFNN_R_SYM (rel->r_info);
+
+ switch (r_type)
+ {
+ case R_LARCH_TLS_DESC_PC_HI20:
+ if (local_exec)
+ {
+ /* DESC -> LE relaxation:
+ pcalalau12i $a0,%desc_pc_hi20(var) =>
+ lu12i.w $a0,%le_hi20(var)
+ */
+ bfd_put (32, abfd, LARCH_LU12I_W | LARCH_RD_A0,
+ contents + rel->r_offset);
+ rel->r_info = ELFNN_R_INFO (r_symndx, R_LARCH_TLS_LE_HI20);
+ }
+ else
+ {
+ /* DESC -> IE relaxation:
+ pcalalau12i $a0,%desc_pc_hi20(var) =>
+ pcalalau12i $a0,%ie_pc_hi20(var)
+ */
+ rel->r_info = ELFNN_R_INFO (r_symndx, R_LARCH_TLS_IE_PC_HI20);
+ }
+ return true;
+
+ case R_LARCH_TLS_DESC_PC_LO12:
+ if (local_exec)
+ {
+ /* DESC -> LE relaxation:
+ addi.d $a0,$a0,%desc_pc_lo12(var) =>
+ ori $a0,$a0,le_lo12(var)
+ */
+ insn = LARCH_ORI | LARCH_RD_RJ_A0;
+ bfd_put (32, abfd, LARCH_ORI | LARCH_RD_RJ_A0,
+ contents + rel->r_offset);
+ rel->r_info = ELFNN_R_INFO (r_symndx, R_LARCH_TLS_LE_LO12);
+ }
+ else
+ {
+ /* DESC -> IE relaxation:
+ addi.d $a0,$a0,%desc_pc_lo12(var) =>
+ ld.d $a0,$a0,%ie_pc_lo12(var)
+ */
+ bfd_put (32, abfd, LARCH_LD_D | LARCH_RD_RJ_A0,
+ contents + rel->r_offset);
+ rel->r_info = ELFNN_R_INFO (r_symndx, R_LARCH_TLS_IE_PC_LO12);
+ }
+ return true;
+
+ case R_LARCH_TLS_DESC_LD:
+ case R_LARCH_TLS_DESC_CALL:
+ /* DESC -> LE/IE relaxation:
+ ld.d $ra,$a0,%desc_ld(var) => (delete)
+ jirl $ra,$ra,%desc_call(var) => (delete)
+ */
+ rel->r_info = ELFNN_R_INFO (0, R_LARCH_NONE);
+ loongarch_relax_delete_bytes (abfd, sec, rel->r_offset, 4, info);
+ return true;
+
+ case R_LARCH_TLS_IE_PC_HI20:
+ if (local_exec)
+ {
+ /* IE -> LE relaxation:
+ pcalalau12i $rd,%ie_pc_hi20(var) =>
+ lu12i.w $rd,%le_hi20(var)
+ */
+ insn = bfd_getl32 (contents + rel->r_offset);
+ bfd_put (32, abfd, LARCH_LU12I_W | (insn & 0x1f),
+ contents + rel->r_offset);
+ rel->r_info = ELFNN_R_INFO (r_symndx, R_LARCH_TLS_LE_HI20);
+ }
+ return true;
+
+ case R_LARCH_TLS_IE_PC_LO12:
+ if (local_exec)
+ {
+ /* IE -> LE relaxation:
+ ld.d $rd,$rj,%%ie_pc_lo12(var) =>
+ ori $rd,$rj,le_lo12(var)
+ */
+ insn = bfd_getl32 (contents + rel->r_offset);
+ bfd_put (32, abfd, LARCH_ORI | (insn & 0x3ff),
+ contents + rel->r_offset);
+ rel->r_info = ELFNN_R_INFO (r_symndx, R_LARCH_TLS_LE_LO12);
+ }
+ return true;
+ }
+
+ return false;
+}
+
+
/* Relax tls le, mainly relax the process of getting TLS le symbolic addresses.
there are three situations in which an assembly instruction sequence needs to
be relaxed:
@@ -4154,6 +4172,21 @@ loongarch_relax_delete_bytes (bfd *abfd,
lu12i.w $rd,%le_hi20_r (sym) ==> (instruction deleted)
add.{w/d} $rd,$rd,$tp,%le_add_r (sym) ==> (instruction deleted)
addi.{w/d} $rs,$rd,%le_lo12_r (sym) ==> addi.{w/d} $rs,$tp,%le_lo12_r (sym)
+
+
+ For relocation of all old LE instruction sequences, whether it is
+ a normal code model or an extreme code model, relaxation will be
+ performed when the relaxation conditions are met.
+
+ nomal code model:
+ lu12i.w $rd,%le_hi20(sym) => (deleted)
+ ori $rd,$rd,le_lo12(sym) => ori $rd,$zero,le_lo12(sym)
+
+ extreme code model:
+ lu12i.w $rd,%le_hi20(sym) => (deleted)
+ ori $rd,$rd,%le_lo12(sym) => ori $rd,$zero,le_lo12(sym)
+ lu32i.d $rd,%le64_lo20(sym) => (deleted)
+ lu52i.d $rd,$rd,%le64_hi12(sym) => (deleted)
*/
static bool
loongarch_relax_tls_le (bfd *abfd, asection *sec,
@@ -4165,31 +4198,56 @@ loongarch_relax_tls_le (bfd *abfd, asection *sec,
uint32_t insn = bfd_get (32, abfd, contents + rel->r_offset);
static uint32_t insn_rj,insn_rd;
symval = symval - elf_hash_table (link_info)->tls_sec->vma;
- /* Whether the symbol offset is in the interval (offset < 0x800). */
- if (ELFNN_R_TYPE ((rel + 1)->r_info == R_LARCH_RELAX) && (symval < 0x800))
+ /* The old LE instruction sequence can be relaxed when the symbol offset
+ is smaller than the 12-bit range. */
+ if (ELFNN_R_TYPE ((rel + 1)->r_info) == R_LARCH_RELAX && (symval <= 0xfff))
{
switch (ELFNN_R_TYPE (rel->r_info))
{
- case R_LARCH_TLS_LE_HI20_R:
- case R_LARCH_TLS_LE_ADD_R:
- /* delete insn. */
- rel->r_info = ELFNN_R_INFO (0, R_LARCH_NONE);
- loongarch_relax_delete_bytes (abfd, sec, rel->r_offset, 4, link_info);
- break;
- case R_LARCH_TLS_LE_LO12_R:
- /* Change rj to $tp. */
- insn_rj = 0x2 << 5;
- /* Get rd register. */
- insn_rd = insn & 0x1f;
- /* Write symbol offset. */
- symval <<= 10;
- /* Writes the modified instruction. */
- insn = insn & 0xffc00000;
- insn = insn | symval | insn_rj | insn_rd;
- bfd_put (32, abfd, insn, contents + rel->r_offset);
- break;
- default:
- break;
+ /*if offset < 0x800, then perform the new le instruction
+ sequence relax. */
+ case R_LARCH_TLS_LE_HI20_R:
+ case R_LARCH_TLS_LE_ADD_R:
+ /* delete insn. */
+ if (symval < 0x800)
+ {
+ rel->r_info = ELFNN_R_INFO (0, R_LARCH_NONE);
+ loongarch_relax_delete_bytes (abfd, sec, rel->r_offset,
+ 4, link_info);
+ }
+ break;
+
+ case R_LARCH_TLS_LE_LO12_R:
+ if (symval < 0x800)
+ {
+ /* Change rj to $tp. */
+ insn_rj = 0x2 << 5;
+ /* Get rd register. */
+ insn_rd = insn & 0x1f;
+ /* Write symbol offset. */
+ symval <<= 10;
+ /* Writes the modified instruction. */
+ insn = insn & 0xffc00000;
+ insn = insn | symval | insn_rj | insn_rd;
+ bfd_put (32, abfd, insn, contents + rel->r_offset);
+ }
+ break;
+
+ case R_LARCH_TLS_LE_HI20:
+ case R_LARCH_TLS_LE64_LO20:
+ case R_LARCH_TLS_LE64_HI12:
+ rel->r_info = ELFNN_R_INFO (0, R_LARCH_NONE);
+ loongarch_relax_delete_bytes (abfd, sec, rel->r_offset,
+ 4, link_info);
+ break;
+
+ case R_LARCH_TLS_LE_LO12:
+ bfd_put (32, abfd, LARCH_ORI | (insn & 0x1f),
+ contents + rel->r_offset);
+ break;
+
+ default:
+ break;
}
}
return true;
@@ -4540,7 +4598,7 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec,
R_LARCH_CALL36: symval is the symbol address for local symbols,
or the PLT entry address of the symbol. (Todo)
R_LARCHL_TLS_LD/GD/DESC_PC_HI20: symval is the GOT entry address
- of the symbol. */
+ of the symbol if transition is not possible. */
if (r_symndx < symtab_hdr->sh_info)
{
Elf_Internal_Sym *sym = (Elf_Internal_Sym *)symtab_hdr->contents
@@ -4550,20 +4608,17 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec,
if (R_LARCH_TLS_LD_PC_HI20 == r_type
|| R_LARCH_TLS_GD_PC_HI20 == r_type
- || R_LARCH_TLS_DESC_PC_HI20 == r_type)
+ || (R_LARCH_TLS_DESC_PC_HI20 == r_type
+ && ! loongarch_can_trans_tls (abfd, info, h,
+ rel, r_type)))
{
- if (loongarch_can_relax_tls (info, r_type, h, abfd, r_symndx))
- continue;
- else
- {
- sym_sec = htab->elf.sgot;
- symval = elf_local_got_offsets (abfd)[r_symndx];
- char tls_type = _bfd_loongarch_elf_tls_type (abfd, h,
- r_symndx);
- if (R_LARCH_TLS_DESC_PC_HI20 == r_type
- && GOT_TLS_GD_BOTH_P (tls_type))
- symval += 2 * GOT_ENTRY_SIZE;
- }
+ sym_sec = htab->elf.sgot;
+ symval = elf_local_got_offsets (abfd)[r_symndx];
+ char tls_type = _bfd_loongarch_elf_tls_type (abfd, h,
+ r_symndx);
+ if (R_LARCH_TLS_DESC_PC_HI20 == r_type
+ && GOT_TLS_GD_BOTH_P (tls_type))
+ symval += 2 * GOT_ENTRY_SIZE;
}
else if (sym->st_shndx == SHN_UNDEF || R_LARCH_ALIGN == r_type)
{
@@ -4594,20 +4649,17 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec,
shared object. */
if (R_LARCH_TLS_LD_PC_HI20 == r_type
|| R_LARCH_TLS_GD_PC_HI20 == r_type
- || R_LARCH_TLS_DESC_PC_HI20 == r_type)
+ || (R_LARCH_TLS_DESC_PC_HI20 == r_type
+ && !loongarch_can_trans_tls (abfd, info, h,
+ rel, r_type)))
{
- if (loongarch_can_relax_tls (info, r_type, h, abfd, r_symndx))
- continue;
- else
- {
- sym_sec = htab->elf.sgot;
- symval = h->got.offset;
- char tls_type = _bfd_loongarch_elf_tls_type (abfd, h,
- r_symndx);
- if (R_LARCH_TLS_DESC_PC_HI20 == r_type
- && GOT_TLS_GD_BOTH_P (tls_type))
- symval += 2 * GOT_ENTRY_SIZE;
- }
+ sym_sec = htab->elf.sgot;
+ symval = h->got.offset;
+ char tls_type = _bfd_loongarch_elf_tls_type (abfd, h,
+ r_symndx);
+ if (R_LARCH_TLS_DESC_PC_HI20 == r_type
+ && GOT_TLS_GD_BOTH_P (tls_type))
+ symval += 2 * GOT_ENTRY_SIZE;
}
else if ((h->root.type == bfd_link_hash_defined
|| h->root.type == bfd_link_hash_defweak)
@@ -4652,6 +4704,17 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec,
symval += sec_addr (sym_sec);
+ /* If the conditions for tls type transition are met,
+ type transition is performed instead of relax.
+ DESC -> IE/LE will delete the following two extra
+ instructions. */
+ if (IS_LOONGARCH_TLS_TRANS_RELOC (r_type)
+ && loongarch_can_trans_tls (abfd, info, h, rel, r_type))
+ {
+ loongarch_tls_perform_trans (abfd, sec, rel, h, info);
+ r_type = ELFNN_R_TYPE (rel->r_info);
+ }
+
switch (r_type)
{
case R_LARCH_ALIGN:
@@ -4670,6 +4733,10 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec,
case R_LARCH_TLS_LE_HI20_R:
case R_LARCH_TLS_LE_LO12_R:
case R_LARCH_TLS_LE_ADD_R:
+ case R_LARCH_TLS_LE_HI20:
+ case R_LARCH_TLS_LE_LO12:
+ case R_LARCH_TLS_LE64_LO20:
+ case R_LARCH_TLS_LE64_HI12:
if (0 == info->relax_pass && (i + 2) <= sec->reloc_count)
loongarch_relax_tls_le (abfd, sec, rel, info, symval);
break;
diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c
index e6a9901673f..e4e28cb702d 100644
--- a/gas/config/tc-loongarch.c
+++ b/gas/config/tc-loongarch.c
@@ -713,7 +713,11 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2,
if (LARCH_opts.relax
&& (BFD_RELOC_LARCH_TLS_LE_HI20_R == reloc_type
- || BFD_RELOC_LARCH_TLS_LE_LO12_R == reloc_type))
+ || BFD_RELOC_LARCH_TLS_LE_LO12_R == reloc_type
+ || BFD_RELOC_LARCH_TLS_LE_HI20 == reloc_type
+ || BFD_RELOC_LARCH_TLS_LE_LO12 == reloc_type
+ || BFD_RELOC_LARCH_TLS_LE64_LO20 == reloc_type
+ || BFD_RELOC_LARCH_TLS_LE64_HI12 == reloc_type))
{
ip->reloc_info[ip->reloc_num].type = BFD_RELOC_LARCH_RELAX;
ip->reloc_info[ip->reloc_num].value = const_0;
@@ -721,8 +725,12 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2,
}
/* Only one register macros (used in normal code model)
- emit R_LARCH_RELAX. */
+ emit R_LARCH_RELAX.
+ LARCH_opts.ase_labs and LARCH_opts.ase_gabs are used
+ to generate the code model of absolute addresses, and
+ we do not relax this code model. */
if (LARCH_opts.relax && (ip->expand_from_macro & 1)
+ && !(LARCH_opts.ase_labs | LARCH_opts.ase_gabs)
&& (BFD_RELOC_LARCH_PCALA_HI20 == reloc_type
|| BFD_RELOC_LARCH_PCALA_LO12 == reloc_type
|| BFD_RELOC_LARCH_GOT_PC_HI20 == reloc_type
@@ -730,7 +738,11 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2,
|| BFD_RELOC_LARCH_TLS_LD_PC_HI20 == reloc_type
|| BFD_RELOC_LARCH_TLS_GD_PC_HI20 == reloc_type
|| BFD_RELOC_LARCH_TLS_DESC_PC_HI20 == reloc_type
- || BFD_RELOC_LARCH_TLS_DESC_PC_LO12 == reloc_type))
+ || BFD_RELOC_LARCH_TLS_DESC_PC_LO12 == reloc_type
+ || BFD_RELOC_LARCH_TLS_DESC_LD == reloc_type
+ || BFD_RELOC_LARCH_TLS_DESC_CALL == reloc_type
+ || BFD_RELOC_LARCH_TLS_IE_PC_HI20 == reloc_type
+ || BFD_RELOC_LARCH_TLS_IE_PC_LO12 == reloc_type))
{
ip->reloc_info[ip->reloc_num].type = BFD_RELOC_LARCH_RELAX;
ip->reloc_info[ip->reloc_num].value = const_0;
@@ -1077,7 +1089,11 @@ append_fixp_and_insn (struct loongarch_cl_insn *ip)
if (symbol_get_frag (to) == symbol_get_frag (from)))
For macro instructions, only the first instruction expanded from macro
- need to start a new frag. */
+ need to start a new frag.
+ Since the relocations of the normal code model and the extreme code model
+ of the old LE instruction sequence are the same, it is impossible to
+ distinguish which code model it is based on relocation alone, so the
+ extreme code model has to be relaxed. */
if (LARCH_opts.relax
&& (BFD_RELOC_LARCH_PCALA_HI20 == reloc_info[0].type
|| BFD_RELOC_LARCH_GOT_PC_HI20 == reloc_info[0].type
@@ -1085,7 +1101,12 @@ append_fixp_and_insn (struct loongarch_cl_insn *ip)
|| BFD_RELOC_LARCH_TLS_LE_ADD_R == reloc_info[0].type
|| BFD_RELOC_LARCH_TLS_LD_PC_HI20 == reloc_info[0].type
|| BFD_RELOC_LARCH_TLS_GD_PC_HI20 == reloc_info[0].type
- || BFD_RELOC_LARCH_TLS_DESC_PC_HI20 == reloc_info[0].type))
+ || BFD_RELOC_LARCH_TLS_DESC_PC_HI20 == reloc_info[0].type
+ || BFD_RELOC_LARCH_TLS_IE_PC_HI20 == reloc_info[0].type
+ || BFD_RELOC_LARCH_TLS_LE_HI20 == reloc_info[0].type
+ || BFD_RELOC_LARCH_TLS_LE_LO12 == reloc_info[0].type
+ || BFD_RELOC_LARCH_TLS_LE64_LO20 == reloc_info[0].type
+ || BFD_RELOC_LARCH_TLS_LE64_HI12 == reloc_info[0].type))
{
frag_wane (frag_now);
frag_new (0);
--
2.36.0
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 2/2] LoongArch: Fix some test cases for TLS transition and relax
2024-01-26 13:55 [PATCH 1/2] LoongArch: Delete extra instructions when TLS type transition Lulu Cai
@ 2024-01-26 13:55 ` Lulu Cai
2024-01-26 18:22 ` [PATCH 1/2] LoongArch: Delete extra instructions when TLS type transition Xi Ruoyao
1 sibling, 0 replies; 4+ messages in thread
From: Lulu Cai @ 2024-01-26 13:55 UTC (permalink / raw)
To: binutils
Cc: xuchenghua, chenglulu, liuzhensong, mengqinggang, xry111,
i.swmail, maskray, luweining, wanglei, hejinyang, Lulu Cai
---
gas/testsuite/gas/loongarch/macro_op.d | 4 +
.../gas/loongarch/macro_op_extreme_abs.d | 6 +-
.../gas/loongarch/macro_op_extreme_pc.d | 138 +++----
.../gas/loongarch/macro_op_extreme_pc.s | 2 +-
gas/testsuite/gas/loongarch/reloc.d | 360 +++++++++---------
gas/testsuite/gas/loongarch/tlsdesc_64.d | 2 +
ld/testsuite/ld-loongarch-elf/desc-ie.d | 14 +-
ld/testsuite/ld-loongarch-elf/desc-ie.s | 13 +-
ld/testsuite/ld-loongarch-elf/desc-le.d | 10 +-
ld/testsuite/ld-loongarch-elf/desc-le.s | 6 +-
ld/testsuite/ld-loongarch-elf/ie-le.d | 8 +-
ld/testsuite/ld-loongarch-elf/ie-le.s | 4 +-
ld/testsuite/ld-loongarch-elf/macro_op.d | 360 +++++++++---------
ld/testsuite/ld-loongarch-elf/relax.exp | 6 +-
ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d | 84 ++--
15 files changed, 511 insertions(+), 506 deletions(-)
diff --git a/gas/testsuite/gas/loongarch/macro_op.d b/gas/testsuite/gas/loongarch/macro_op.d
index 47f8f45c663..106f619ef05 100644
--- a/gas/testsuite/gas/loongarch/macro_op.d
+++ b/gas/testsuite/gas/loongarch/macro_op.d
@@ -53,12 +53,16 @@ Disassembly of section .text:
44: R_LARCH_RELAX \*ABS\*
48: 14000004 lu12i.w \$a0, 0
48: R_LARCH_TLS_LE_HI20 TLS1
+ 48: R_LARCH_RELAX \*ABS\*
4c: 03800084 ori \$a0, \$a0, 0x0
4c: R_LARCH_TLS_LE_LO12 TLS1
+ 4c: R_LARCH_RELAX \*ABS\*
50: 1a000004 pcalau12i \$a0, 0
50: R_LARCH_TLS_IE_PC_HI20 TLS1
+ 50: R_LARCH_RELAX \*ABS\*
54: 28c00084 ld.d \$a0, \$a0, 0
54: R_LARCH_TLS_IE_PC_LO12 TLS1
+ 54: R_LARCH_RELAX \*ABS\*
58: 1a000004 pcalau12i \$a0, 0
58: R_LARCH_TLS_LD_PC_HI20 TLS1
58: R_LARCH_RELAX \*ABS\*
diff --git a/gas/testsuite/gas/loongarch/macro_op_extreme_abs.d b/gas/testsuite/gas/loongarch/macro_op_extreme_abs.d
index 5c823ba0302..6c7678ff76d 100644
--- a/gas/testsuite/gas/loongarch/macro_op_extreme_abs.d
+++ b/gas/testsuite/gas/loongarch/macro_op_extreme_abs.d
@@ -7,7 +7,7 @@
Disassembly of section .text:
-0+ <.L1>:
+0+ <.*>:
0: 14000004 lu12i.w \$a0, 0
0: R_LARCH_MARK_LA \*ABS\*
0: R_LARCH_ABS_HI20 .L1
@@ -28,10 +28,8 @@ Disassembly of section .text:
1c: R_LARCH_ABS64_HI12 .L1
20: 1a000004 pcalau12i \$a0, 0
20: R_LARCH_PCALA_HI20 .L1
- 20: R_LARCH_RELAX \*ABS\*
24: 02c00084 addi.d \$a0, \$a0, 0
24: R_LARCH_PCALA_LO12 .L1
- 24: R_LARCH_RELAX \*ABS\*
28: 14000004 lu12i.w \$a0, 0
28: R_LARCH_GOT_HI20 .L1
2c: 03800084 ori \$a0, \$a0, 0x0
@@ -43,8 +41,10 @@ Disassembly of section .text:
38: 28c00084 ld.d \$a0, \$a0, 0
3c: 14000004 lu12i.w \$a0, 0
3c: R_LARCH_TLS_LE_HI20 TLS1
+ 3c: R_LARCH_RELAX \*ABS\*
40: 03800084 ori \$a0, \$a0, 0x0
40: R_LARCH_TLS_LE_LO12 TLS1
+ 40: R_LARCH_RELAX \*ABS\*
44: 14000004 lu12i.w \$a0, 0
44: R_LARCH_TLS_IE_HI20 TLS1
48: 03800084 ori \$a0, \$a0, 0x0
diff --git a/gas/testsuite/gas/loongarch/macro_op_extreme_pc.d b/gas/testsuite/gas/loongarch/macro_op_extreme_pc.d
index 68fbb338c36..8c013c46d7e 100644
--- a/gas/testsuite/gas/loongarch/macro_op_extreme_pc.d
+++ b/gas/testsuite/gas/loongarch/macro_op_extreme_pc.d
@@ -7,71 +7,73 @@
Disassembly of section .text:
-[ ]*0000000000000000 <.L1>:
-[ ]+0:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0
-[ ]+0: R_LARCH_PCALA_HI20[ ]+.L1
-[ ]+4:[ ]+02c00005[ ]+li.d[ ]+\$a1, 0
-[ ]+4: R_LARCH_PCALA_LO12[ ]+.L1
-[ ]+8:[ ]+16000005[ ]+lu32i.d[ ]+\$a1, 0
-[ ]+8: R_LARCH_PCALA64_LO20[ ]+.L1
-[ ]+c:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1, \$a1, 0
-[ ]+c: R_LARCH_PCALA64_HI12[ ]+.L1
-[ ]+10:[ ]+00109484[ ]+add.d[ ]+\$a0, \$a0, \$a1
-[ ]+14:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0
-[ ]+14: R_LARCH_PCALA_HI20[ ]+.L1
-[ ]+18:[ ]+02c00005[ ]+li.d[ ]+\$a1, 0
-[ ]+18: R_LARCH_PCALA_LO12[ ]+.L1
-[ ]+1c:[ ]+16000005[ ]+lu32i.d[ ]+\$a1, 0
-[ ]+1c: R_LARCH_PCALA64_LO20[ ]+.L1
-[ ]+20:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1, \$a1, 0
-[ ]+20: R_LARCH_PCALA64_HI12[ ]+.L1
-[ ]+24:[ ]+00109484[ ]+add.d[ ]+\$a0, \$a0, \$a1
-[ ]+28:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0
-[ ]+28: R_LARCH_PCALA_HI20[ ]+.L1
-[ ]+2c:[ ]+02c00005[ ]+li.d[ ]+\$a1, 0
-[ ]+2c: R_LARCH_PCALA_LO12[ ]+.L1
-[ ]+30:[ ]+16000005[ ]+lu32i.d[ ]+\$a1, 0
-[ ]+30: R_LARCH_PCALA64_LO20[ ]+.L1
-[ ]+34:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1, \$a1, 0
-[ ]+34: R_LARCH_PCALA64_HI12[ ]+.L1
-[ ]+38:[ ]+00109484[ ]+add.d[ ]+\$a0, \$a0, \$a1
-[ ]+3c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0
-[ ]+3c: R_LARCH_GOT_PC_HI20[ ]+.L1
-[ ]+40:[ ]+02c00005[ ]+li.d[ ]+\$a1, 0
-[ ]+40: R_LARCH_GOT_PC_LO12[ ]+.L1
-[ ]+44:[ ]+16000005[ ]+lu32i.d[ ]+\$a1, 0
-[ ]+44: R_LARCH_GOT64_PC_LO20[ ]+.L1
-[ ]+48:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1, \$a1, 0
-[ ]+48: R_LARCH_GOT64_PC_HI12[ ]+.L1
-[ ]+4c:[ ]+380c1484[ ]+ldx.d[ ]+\$a0, \$a0, \$a1
-[ ]+50:[ ]+14000004[ ]+lu12i.w[ ]+\$a0, 0
-[ ]+50: R_LARCH_TLS_LE_HI20[ ]+TLS1
-[ ]+54:[ ]+03800084[ ]+ori[ ]+\$a0, \$a0, 0x0
-[ ]+54: R_LARCH_TLS_LE_LO12[ ]+TLS1
-[ ]+58:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0
-[ ]+58: R_LARCH_TLS_IE_PC_HI20[ ]+TLS1
-[ ]+5c:[ ]+02c00005[ ]+li.d[ ]+\$a1, 0
-[ ]+5c: R_LARCH_TLS_IE_PC_LO12[ ]+TLS1
-[ ]+60:[ ]+16000005[ ]+lu32i.d[ ]+\$a1, 0
-[ ]+60: R_LARCH_TLS_IE64_PC_LO20[ ]+TLS1
-[ ]+64:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1, \$a1, 0
-[ ]+64: R_LARCH_TLS_IE64_PC_HI12[ ]+TLS1
-[ ]+68:[ ]+380c1484[ ]+ldx.d[ ]+\$a0, \$a0, \$a1
-[ ]+6c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0
-[ ]+6c: R_LARCH_TLS_LD_PC_HI20[ ]+TLS1
-[ ]+70:[ ]+02c00005[ ]+li.d[ ]+\$a1, 0
-[ ]+70: R_LARCH_GOT_PC_LO12[ ]+TLS1
-[ ]+74:[ ]+16000005[ ]+lu32i.d[ ]+\$a1, 0
-[ ]+74: R_LARCH_GOT64_PC_LO20[ ]+TLS1
-[ ]+78:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1, \$a1, 0
-[ ]+78: R_LARCH_GOT64_PC_HI12[ ]+TLS1
-[ ]+7c:[ ]+00109484[ ]+add.d[ ]+\$a0, \$a0, \$a1
-[ ]+80:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0
-[ ]+80: R_LARCH_TLS_GD_PC_HI20[ ]+TLS1
-[ ]+84:[ ]+02c00005[ ]+li.d[ ]+\$a1, 0
-[ ]+84: R_LARCH_GOT_PC_LO12[ ]+TLS1
-[ ]+88:[ ]+16000005[ ]+lu32i.d[ ]+\$a1, 0
-[ ]+88: R_LARCH_GOT64_PC_LO20[ ]+TLS1
-[ ]+8c:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1, \$a1, 0
-[ ]+8c: R_LARCH_GOT64_PC_HI12[ ]+TLS1
-[ ]+90:[ ]+00109484[ ]+add.d[ ]+\$a0, \$a0, \$a1
+0+ <.L1>:
+ 0: 1a000004 pcalau12i \$a0, 0
+ 0: R_LARCH_PCALA_HI20 .L1
+ 4: 02c00005 li.d \$a1, 0
+ 4: R_LARCH_PCALA_LO12 .L1
+ 8: 16000005 lu32i.d \$a1, 0
+ 8: R_LARCH_PCALA64_LO20 .L1
+ c: 030000a5 lu52i.d \$a1, \$a1, 0
+ c: R_LARCH_PCALA64_HI12 .L1
+ 10: 00109484 add.d \$a0, \$a0, \$a1
+ 14: 1a000004 pcalau12i \$a0, 0
+ 14: R_LARCH_PCALA_HI20 .L1
+ 18: 02c00005 li.d \$a1, 0
+ 18: R_LARCH_PCALA_LO12 .L1
+ 1c: 16000005 lu32i.d \$a1, 0
+ 1c: R_LARCH_PCALA64_LO20 .L1
+ 20: 030000a5 lu52i.d \$a1, \$a1, 0
+ 20: R_LARCH_PCALA64_HI12 .L1
+ 24: 00109484 add.d \$a0, \$a0, \$a1
+ 28: 1a000004 pcalau12i \$a0, 0
+ 28: R_LARCH_PCALA_HI20 .L1
+ 2c: 02c00005 li.d \$a1, 0
+ 2c: R_LARCH_PCALA_LO12 .L1
+ 30: 16000005 lu32i.d \$a1, 0
+ 30: R_LARCH_PCALA64_LO20 .L1
+ 34: 030000a5 lu52i.d \$a1, \$a1, 0
+ 34: R_LARCH_PCALA64_HI12 .L1
+ 38: 00109484 add.d \$a0, \$a0, \$a1
+ 3c: 1a000004 pcalau12i \$a0, 0
+ 3c: R_LARCH_GOT_PC_HI20 .L1
+ 40: 02c00005 li.d \$a1, 0
+ 40: R_LARCH_GOT_PC_LO12 .L1
+ 44: 16000005 lu32i.d \$a1, 0
+ 44: R_LARCH_GOT64_PC_LO20 .L1
+ 48: 030000a5 lu52i.d \$a1, \$a1, 0
+ 48: R_LARCH_GOT64_PC_HI12 .L1
+ 4c: 380c1484 ldx.d \$a0, \$a0, \$a1
+ 50: 14000004 lu12i.w \$a0, 0
+ 50: R_LARCH_TLS_LE_HI20 TLS1
+ 50: R_LARCH_RELAX \*ABS\*
+ 54: 03800084 ori \$a0, \$a0, 0x0
+ 54: R_LARCH_TLS_LE_LO12 TLS1
+ 54: R_LARCH_RELAX \*ABS\*
+ 58: 1a000004 pcalau12i \$a0, 0
+ 58: R_LARCH_TLS_IE_PC_HI20 TLS1
+ 5c: 02c00005 li.d \$a1, 0
+ 5c: R_LARCH_TLS_IE_PC_LO12 TLS1
+ 60: 16000005 lu32i.d \$a1, 0
+ 60: R_LARCH_TLS_IE64_PC_LO20 TLS1
+ 64: 030000a5 lu52i.d \$a1, \$a1, 0
+ 64: R_LARCH_TLS_IE64_PC_HI12 TLS1
+ 68: 380c1484 ldx.d \$a0, \$a0, \$a1
+ 6c: 1a000004 pcalau12i \$a0, 0
+ 6c: R_LARCH_TLS_LD_PC_HI20 TLS1
+ 70: 02c00005 li.d \$a1, 0
+ 70: R_LARCH_GOT_PC_LO12 TLS1
+ 74: 16000005 lu32i.d \$a1, 0
+ 74: R_LARCH_GOT64_PC_LO20 TLS1
+ 78: 030000a5 lu52i.d \$a1, \$a1, 0
+ 78: R_LARCH_GOT64_PC_HI12 TLS1
+ 7c: 00109484 add.d \$a0, \$a0, \$a1
+ 80: 1a000004 pcalau12i \$a0, 0
+ 80: R_LARCH_TLS_GD_PC_HI20 TLS1
+ 84: 02c00005 li.d \$a1, 0
+ 84: R_LARCH_GOT_PC_LO12 TLS1
+ 88: 16000005 lu32i.d \$a1, 0
+ 88: R_LARCH_GOT64_PC_LO20 TLS1
+ 8c: 030000a5 lu52i.d \$a1, \$a1, 0
+ 8c: R_LARCH_GOT64_PC_HI12 TLS1
+ 90: 00109484 add.d \$a0, \$a0, \$a1
diff --git a/gas/testsuite/gas/loongarch/macro_op_extreme_pc.s b/gas/testsuite/gas/loongarch/macro_op_extreme_pc.s
index 4c685b5bfcb..a002fc12164 100644
--- a/gas/testsuite/gas/loongarch/macro_op_extreme_pc.s
+++ b/gas/testsuite/gas/loongarch/macro_op_extreme_pc.s
@@ -3,7 +3,7 @@ la.local $r4, $r5, .L1
la.global $r4, $r5, .L1
la.pcrel $r4, $r5, .L1
la.got $r4, $r5, .L1
-la.tls.le $r4, TLS1
+la.tls.le $r4,TLS1
la.tls.ie $r4, $r5, TLS1
la.tls.ld $r4, $r5, TLS1
la.tls.gd $r4, $r5, TLS1
diff --git a/gas/testsuite/gas/loongarch/reloc.d b/gas/testsuite/gas/loongarch/reloc.d
index fa249c58fd5..6685d785f11 100644
--- a/gas/testsuite/gas/loongarch/reloc.d
+++ b/gas/testsuite/gas/loongarch/reloc.d
@@ -7,179 +7,187 @@
Disassembly of section .text:
-00000000.* <.text>:
-[ ]+0:[ ]+03400000[ ]+nop
-[ ]+4:[ ]+58000085[ ]+beq[ ]+\$a0,[ ]+\$a1,[ ]+0[ ]+#[ ]+0x4
-[ ]+4:[ ]+R_LARCH_B16[ ]+.L1
-[ ]+8:[ ]+5c000085[ ]+bne[ ]+\$a0,[ ]+\$a1,[ ]+0[ ]+#[ ]+0x8
-[ ]+8:[ ]+R_LARCH_B16[ ]+.L1
-[ ]+c:[ ]+60000085[ ]+blt[ ]+\$a0,[ ]+\$a1,[ ]+0[ ]+#[ ]+0xc
-[ ]+c:[ ]+R_LARCH_B16[ ]+.L1
-[ ]+10:[ ]+64000085[ ]+bge[ ]+\$a0,[ ]+\$a1,[ ]+0[ ]+#[ ]+0x10
-[ ]+10:[ ]+R_LARCH_B16[ ]+.L1
-[ ]+14:[ ]+68000085[ ]+bltu[ ]+\$a0,[ ]+\$a1,[ ]+0[ ]+#[ ]+0x14
-[ ]+14:[ ]+R_LARCH_B16[ ]+.L1
-[ ]+18:[ ]+6c000085[ ]+bgeu[ ]+\$a0,[ ]+\$a1,[ ]+0[ ]+#[ ]+0x18
-[ ]+18:[ ]+R_LARCH_B16[ ]+.L1
-[ ]+1c:[ ]+4c0000a4[ ]+jirl[ ]+\$a0,[ ]+\$a1,[ ]+0
-[ ]+1c:[ ]+R_LARCH_B16[ ]+.L1
-[ ]+20:[ ]+40000080[ ]+beqz[ ]+\$a0,[ ]+0[ ]+#[ ]+0x20
-[ ]+20:[ ]+R_LARCH_B21[ ]+.L1
-[ ]+24:[ ]+44000080[ ]+bnez[ ]+\$a0,[ ]+0[ ]+#[ ]+0x24
-[ ]+24:[ ]+R_LARCH_B21[ ]+.L1
-[ ]+28:[ ]+50000000[ ]+b[ ]+0[ ]+#[ ]+0x28
-[ ]+28:[ ]+R_LARCH_B26[ ]+.L1
-[ ]+2c:[ ]+54000000[ ]+bl[ ]+0[ ]+#[ ]+0x2c
-[ ]+2c:[ ]+R_LARCH_B26[ ]+.L1
-[ ]+30:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0
-[ ]+30:[ ]+R_LARCH_ABS_HI20[ ]+.L1
-[ ]+34:[ ]+038000a4[ ]+ori[ ]+\$a0,[ ]+\$a1,[ ]+0x0
-[ ]+34:[ ]+R_LARCH_ABS_LO12[ ]+.L1
-[ ]+38:[ ]+16000004[ ]+lu32i.d[ ]+\$a0,[ ]+0
-[ ]+38:[ ]+R_LARCH_ABS64_LO20[ ]+.L1
-[ ]+3c:[ ]+03000085[ ]+lu52i.d[ ]+\$a1,[ ]+\$a0,[ ]+0
-[ ]+3c:[ ]+R_LARCH_ABS64_HI12[ ]+.L1
-[ ]+40:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
-[ ]+40:[ ]+R_LARCH_PCALA_HI20[ ]+.L1
-[ ]+44:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
-[ ]+44:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1
-[ ]+48:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
-[ ]+48:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1
-[ ]+4c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
-[ ]+4c:[ ]+R_LARCH_TLS_IE_PC_HI20[ ]+TLSL1
-[ ]+50:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
-[ ]+50:[ ]+R_LARCH_TLS_LD_PC_HI20[ ]+TLSL1
-[ ]+54:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
-[ ]+54:[ ]+R_LARCH_TLS_GD_PC_HI20[ ]+TLSL1
-[ ]+58:[ ]+02800085[ ]+addi.w[ ]+\$a1,[ ]+\$a0,[ ]+0
-[ ]+58:[ ]+R_LARCH_PCALA_LO12[ ]+.L1
-[ ]+5c:[ ]+02c00085[ ]+addi.d[ ]+\$a1,[ ]+\$a0,[ ]+0
-[ ]+5c:[ ]+R_LARCH_PCALA_LO12[ ]+.L1
-[ ]+60:[ ]+28000085[ ]+ld.b[ ]+\$a1,[ ]+\$a0,[ ]+0
-[ ]+60:[ ]+R_LARCH_PCALA_LO12[ ]+.L1
-[ ]+64:[ ]+28400085[ ]+ld.h[ ]+\$a1,[ ]+\$a0,[ ]+0
-[ ]+64:[ ]+R_LARCH_PCALA_LO12[ ]+.L1
-[ ]+68:[ ]+28800085[ ]+ld.w[ ]+\$a1,[ ]+\$a0,[ ]+0
-[ ]+68:[ ]+R_LARCH_PCALA_LO12[ ]+.L1
-[ ]+6c:[ ]+28c00085[ ]+ld.d[ ]+\$a1,[ ]+\$a0,[ ]+0
-[ ]+6c:[ ]+R_LARCH_PCALA_LO12[ ]+.L1
-[ ]+70:[ ]+16000004[ ]+lu32i.d[ ]+\$a0,[ ]+0
-[ ]+70:[ ]+R_LARCH_PCALA64_LO20[ ]+.L1
-[ ]+74:[ ]+03000085[ ]+lu52i.d[ ]+\$a1,[ ]+\$a0,[ ]+0
-[ ]+74:[ ]+R_LARCH_PCALA64_LO20[ ]+.L1
-[ ]+78:[ ]+16000004[ ]+lu32i.d[ ]+\$a0,[ ]+0
-[ ]+78:[ ]+R_LARCH_GOT64_PC_LO20[ ]+.L1
-[ ]+7c:[ ]+03000085[ ]+lu52i.d[ ]+\$a1,[ ]+\$a0,[ ]+0
-[ ]+7c:[ ]+R_LARCH_GOT64_PC_HI12[ ]+.L1
-[ ]+80:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0
-[ ]+80:[ ]+R_LARCH_GOT_HI20[ ]+.L1
-[ ]+84:[ ]+03800084[ ]+ori[ ]+\$a0,[ ]+\$a0,[ ]+0x0
-[ ]+84:[ ]+R_LARCH_GOT_LO12[ ]+.L1
-[ ]+88:[ ]+16000004[ ]+lu32i.d[ ]+\$a0,[ ]+0
-[ ]+88:[ ]+R_LARCH_GOT64_LO20[ ]+.L1
-[ ]+8c:[ ]+03000085[ ]+lu52i.d[ ]+\$a1,[ ]+\$a0,[ ]+0
-[ ]+8c:[ ]+R_LARCH_GOT64_HI12[ ]+.L1
-[ ]+90:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0
-[ ]+90:[ ]+R_LARCH_TLS_LE_HI20[ ]+TLSL1
-[ ]+94:[ ]+03800085[ ]+ori[ ]+\$a1,[ ]+\$a0,[ ]+0x0
-[ ]+94:[ ]+R_LARCH_TLS_LE_LO12[ ]+TLSL1
-[ ]+98:[ ]+16000004[ ]+lu32i.d[ ]+\$a0,[ ]+0
-[ ]+98:[ ]+R_LARCH_TLS_LE64_LO20[ ]+TLSL1
-[ ]+9c:[ ]+03000085[ ]+lu52i.d[ ]+\$a1,[ ]+\$a0,[ ]+0
-[ ]+9c:[ ]+R_LARCH_TLS_LE64_HI12[ ]+TLSL1
-[ ]+a0:[ ]+58000085[ ]+beq[ ]+\$a0,[ ]+\$a1,[ ]+0[ ]+#[ ]+0xa0
-[ ]+a0:[ ]+R_LARCH_B16[ ]+.L1\+0x8
-[ ]+a4:[ ]+5c000085[ ]+bne[ ]+\$a0,[ ]+\$a1,[ ]+0[ ]+#[ ]+0xa4
-[ ]+a4:[ ]+R_LARCH_B16[ ]+.L1\+0x8
-[ ]+a8:[ ]+60000085[ ]+blt[ ]+\$a0,[ ]+\$a1,[ ]+0[ ]+#[ ]+0xa8
-[ ]+a8:[ ]+R_LARCH_B16[ ]+.L1\+0x8
-[ ]+ac:[ ]+64000085[ ]+bge[ ]+\$a0,[ ]+\$a1,[ ]+0[ ]+#[ ]+0xac
-[ ]+ac:[ ]+R_LARCH_B16[ ]+.L1\+0x8
-[ ]+b0:[ ]+68000085[ ]+bltu[ ]+\$a0,[ ]+\$a1,[ ]+0[ ]+#[ ]+0xb0
-[ ]+b0:[ ]+R_LARCH_B16[ ]+.L1\+0x8
-[ ]+b4:[ ]+6c000085[ ]+bgeu[ ]+\$a0,[ ]+\$a1,[ ]+0[ ]+#[ ]+0xb4
-[ ]+b4:[ ]+R_LARCH_B16[ ]+.L1\+0x8
-[ ]+b8:[ ]+4c0000a4[ ]+jirl[ ]+\$a0,[ ]+\$a1,[ ]+0
-[ ]+b8:[ ]+R_LARCH_B16[ ]+.L1\+0x8
-[ ]+bc:[ ]+40000080[ ]+beqz[ ]+\$a0,[ ]+0[ ]+#[ ]+0xbc
-[ ]+bc:[ ]+R_LARCH_B21[ ]+.L1\+0x8
-[ ]+c0:[ ]+44000080[ ]+bnez[ ]+\$a0,[ ]+0[ ]+#[ ]+0xc0
-[ ]+c0:[ ]+R_LARCH_B21[ ]+.L1\+0x8
-[ ]+c4:[ ]+50000000[ ]+b[ ]+0[ ]+#[ ]+0xc4
-[ ]+c4:[ ]+R_LARCH_B26[ ]+.L1\+0x8
-[ ]+c8:[ ]+54000000[ ]+bl[ ]+0[ ]+#[ ]+0xc8
-[ ]+c8:[ ]+R_LARCH_B26[ ]+.L1\+0x8
-[ ]+cc:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0
-[ ]+cc:[ ]+R_LARCH_ABS_HI20[ ]+.L1\+0x8
-[ ]+d0:[ ]+038000a4[ ]+ori[ ]+\$a0,[ ]+\$a1,[ ]+0x0
-[ ]+d0:[ ]+R_LARCH_ABS_LO12[ ]+.L1\+0x8
-[ ]+d4:[ ]+16000004[ ]+lu32i.d[ ]+\$a0,[ ]+0
-[ ]+d4:[ ]+R_LARCH_ABS64_LO20[ ]+.L1\+0x8
-[ ]+d8:[ ]+03000085[ ]+lu52i.d[ ]+\$a1,[ ]+\$a0,[ ]+0
-[ ]+d8:[ ]+R_LARCH_ABS64_HI12[ ]+.L1\+0x8
-[ ]+dc:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
-[ ]+dc:[ ]+R_LARCH_PCALA_HI20[ ]+.L1\+0x8
-[ ]+e0:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
-[ ]+e0:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1\+0x8
-[ ]+e4:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
-[ ]+e4:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1\+0x8
-[ ]+e8:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
-[ ]+e8:[ ]+R_LARCH_TLS_IE_PC_HI20[ ]+TLSL1\+0x8
-[ ]+ec:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
-[ ]+ec:[ ]+R_LARCH_TLS_LD_PC_HI20[ ]+TLSL1\+0x8
-[ ]+f0:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
-[ ]+f0:[ ]+R_LARCH_TLS_GD_PC_HI20[ ]+TLSL1\+0x8
-[ ]+f4:[ ]+02800085[ ]+addi.w[ ]+\$a1,[ ]+\$a0,[ ]+0
-[ ]+f4:[ ]+R_LARCH_PCALA_LO12[ ]+.L1\+0x8
-[ ]+f8:[ ]+02c00085[ ]+addi.d[ ]+\$a1,[ ]+\$a0,[ ]+0
-[ ]+f8:[ ]+R_LARCH_PCALA_LO12[ ]+.L1\+0x8
-[ ]+fc:[ ]+28000085[ ]+ld.b[ ]+\$a1,[ ]+\$a0,[ ]+0
-[ ]+fc:[ ]+R_LARCH_PCALA_LO12[ ]+.L1\+0x8
-[ ]+100:[ ]+28400085[ ]+ld.h[ ]+\$a1,[ ]+\$a0,[ ]+0
-[ ]+100:[ ]+R_LARCH_PCALA_LO12[ ]+.L1\+0x8
-[ ]+104:[ ]+28800085[ ]+ld.w[ ]+\$a1,[ ]+\$a0,[ ]+0
-[ ]+104:[ ]+R_LARCH_PCALA_LO12[ ]+.L1\+0x8
-[ ]+108:[ ]+28c00085[ ]+ld.d[ ]+\$a1,[ ]+\$a0,[ ]+0
-[ ]+108:[ ]+R_LARCH_PCALA_LO12[ ]+.L1\+0x8
-[ ]+10c:[ ]+16000004[ ]+lu32i.d[ ]+\$a0,[ ]+0
-[ ]+10c:[ ]+R_LARCH_PCALA64_LO20[ ]+.L1\+0x8
-[ ]+110:[ ]+03000085[ ]+lu52i.d[ ]+\$a1,[ ]+\$a0,[ ]+0
-[ ]+110:[ ]+R_LARCH_PCALA64_LO20[ ]+.L1\+0x8
-[ ]+114:[ ]+16000004[ ]+lu32i.d[ ]+\$a0,[ ]+0
-[ ]+114:[ ]+R_LARCH_GOT64_PC_LO20[ ]+.L1\+0x8
-[ ]+118:[ ]+03000085[ ]+lu52i.d[ ]+\$a1,[ ]+\$a0,[ ]+0
-[ ]+118:[ ]+R_LARCH_GOT64_PC_HI12[ ]+.L1\+0x8
-[ ]+11c:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0
-[ ]+11c:[ ]+R_LARCH_GOT_HI20[ ]+.L1\+0x8
-[ ]+120:[ ]+03800084[ ]+ori[ ]+\$a0,[ ]+\$a0,[ ]+0x0
-[ ]+120:[ ]+R_LARCH_GOT_LO12[ ]+.L1\+0x8
-[ ]+124:[ ]+16000004[ ]+lu32i.d[ ]+\$a0,[ ]+0
-[ ]+124:[ ]+R_LARCH_GOT64_LO20[ ]+.L1\+0x8
-[ ]+128:[ ]+03000085[ ]+lu52i.d[ ]+\$a1,[ ]+\$a0,[ ]+0
-[ ]+128:[ ]+R_LARCH_GOT64_HI12[ ]+.L1\+0x8
-[ ]+12c:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0
-[ ]+12c:[ ]+R_LARCH_TLS_LE_HI20[ ]+TLSL1\+0x8
-[ ]+130:[ ]+03800085[ ]+ori[ ]+\$a1,[ ]+\$a0,[ ]+0x0
-[ ]+130:[ ]+R_LARCH_TLS_LE_LO12[ ]+TLSL1\+0x8
-[ ]+134:[ ]+16000004[ ]+lu32i.d[ ]+\$a0,[ ]+0
-[ ]+134:[ ]+R_LARCH_TLS_LE64_LO20[ ]+TLSL1\+0x8
-[ ]+138:[ ]+03000085[ ]+lu52i.d[ ]+\$a1,[ ]+\$a0,[ ]+0
-[ ]+138:[ ]+R_LARCH_TLS_LE64_HI12[ ]+TLSL1\+0x8
-[ ]+13c:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0
-[ ]+13c:[ ]+R_LARCH_TLS_LE_HI20_R[ ]+TLSL1
-[ ]+13c:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+140:[ ]+001090a5[ ]+add.d[ ]+\$a1,[ ]+\$a1,[ ]+\$a0
-[ ]+140:[ ]+R_LARCH_TLS_LE_ADD_R[ ]+TLSL1
-[ ]+140:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+144:[ ]+29800085[ ]+st.w[ ]+\$a1,[ ]+\$a0,[ ]+0
-[ ]+144:[ ]+R_LARCH_TLS_LE_LO12_R[ ]+TLSL1
-[ ]+144:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+148:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0
-[ ]+148:[ ]+R_LARCH_TLS_LE_HI20_R[ ]+TLSL1\+0x8
-[ ]+148:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+14c:[ ]+001090a5[ ]+add.d[ ]+\$a1,[ ]+\$a1,[ ]+\$a0
-[ ]+14c:[ ]+R_LARCH_TLS_LE_ADD_R[ ]+TLSL1\+0x8
-[ ]+14c:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+150:[ ]+29800085[ ]+st.w[ ]+\$a1,[ ]+\$a0,[ ]+0
-[ ]+150:[ ]+R_LARCH_TLS_LE_LO12_R[ ]+TLSL1\+0x8
-[ ]+150:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
+0+ <.*>:
+ 0: 03400000 nop
+ 4: 58000085 beq \$a0, \$a1, 0 # 0x4
+ 4: R_LARCH_B16 .L1
+ 8: 5c000085 bne \$a0, \$a1, 0 # 0x8
+ 8: R_LARCH_B16 .L1
+ c: 60000085 blt \$a0, \$a1, 0 # 0xc
+ c: R_LARCH_B16 .L1
+ 10: 64000085 bge \$a0, \$a1, 0 # 0x10
+ 10: R_LARCH_B16 .L1
+ 14: 68000085 bltu \$a0, \$a1, 0 # 0x14
+ 14: R_LARCH_B16 .L1
+ 18: 6c000085 bgeu \$a0, \$a1, 0 # 0x18
+ 18: R_LARCH_B16 .L1
+ 1c: 4c0000a4 jirl \$a0, \$a1, 0
+ 1c: R_LARCH_B16 .L1
+ 20: 40000080 beqz \$a0, 0 # 0x20
+ 20: R_LARCH_B21 .L1
+ 24: 44000080 bnez \$a0, 0 # 0x24
+ 24: R_LARCH_B21 .L1
+ 28: 50000000 b 0 # 0x28
+ 28: R_LARCH_B26 .L1
+ 2c: 54000000 bl 0 # 0x2c
+ 2c: R_LARCH_B26 .L1
+ 30: 14000004 lu12i.w \$a0, 0
+ 30: R_LARCH_ABS_HI20 .L1
+ 34: 038000a4 ori \$a0, \$a1, 0x0
+ 34: R_LARCH_ABS_LO12 .L1
+ 38: 16000004 lu32i.d \$a0, 0
+ 38: R_LARCH_ABS64_LO20 .L1
+ 3c: 03000085 lu52i.d \$a1, \$a0, 0
+ 3c: R_LARCH_ABS64_HI12 .L1
+ 40: 1a000004 pcalau12i \$a0, 0
+ 40: R_LARCH_PCALA_HI20 .L1
+ 44: 1a000004 pcalau12i \$a0, 0
+ 44: R_LARCH_GOT_PC_HI20 .L1
+ 48: 1a000004 pcalau12i \$a0, 0
+ 48: R_LARCH_GOT_PC_LO12 .L1
+ 4c: 1a000004 pcalau12i \$a0, 0
+ 4c: R_LARCH_TLS_IE_PC_HI20 TLSL1
+ 50: 1a000004 pcalau12i \$a0, 0
+ 50: R_LARCH_TLS_LD_PC_HI20 TLSL1
+ 54: 1a000004 pcalau12i \$a0, 0
+ 54: R_LARCH_TLS_GD_PC_HI20 TLSL1
+ 58: 02800085 addi.w \$a1, \$a0, 0
+ 58: R_LARCH_PCALA_LO12 .L1
+ 5c: 02c00085 addi.d \$a1, \$a0, 0
+ 5c: R_LARCH_PCALA_LO12 .L1
+ 60: 28000085 ld.b \$a1, \$a0, 0
+ 60: R_LARCH_PCALA_LO12 .L1
+ 64: 28400085 ld.h \$a1, \$a0, 0
+ 64: R_LARCH_PCALA_LO12 .L1
+ 68: 28800085 ld.w \$a1, \$a0, 0
+ 68: R_LARCH_PCALA_LO12 .L1
+ 6c: 28c00085 ld.d \$a1, \$a0, 0
+ 6c: R_LARCH_PCALA_LO12 .L1
+ 70: 16000004 lu32i.d \$a0, 0
+ 70: R_LARCH_PCALA64_LO20 .L1
+ 74: 03000085 lu52i.d \$a1, \$a0, 0
+ 74: R_LARCH_PCALA64_LO20 .L1
+ 78: 16000004 lu32i.d \$a0, 0
+ 78: R_LARCH_GOT64_PC_LO20 .L1
+ 7c: 03000085 lu52i.d \$a1, \$a0, 0
+ 7c: R_LARCH_GOT64_PC_HI12 .L1
+ 80: 14000004 lu12i.w \$a0, 0
+ 80: R_LARCH_GOT_HI20 .L1
+ 84: 03800084 ori \$a0, \$a0, 0x0
+ 84: R_LARCH_GOT_LO12 .L1
+ 88: 16000004 lu32i.d \$a0, 0
+ 88: R_LARCH_GOT64_LO20 .L1
+ 8c: 03000085 lu52i.d \$a1, \$a0, 0
+ 8c: R_LARCH_GOT64_HI12 .L1
+ 90: 14000004 lu12i.w \$a0, 0
+ 90: R_LARCH_TLS_LE_HI20 TLSL1
+ 90: R_LARCH_RELAX \*ABS\*
+ 94: 03800085 ori \$a1, \$a0, 0x0
+ 94: R_LARCH_TLS_LE_LO12 TLSL1
+ 94: R_LARCH_RELAX \*ABS\*
+ 98: 16000004 lu32i.d \$a0, 0
+ 98: R_LARCH_TLS_LE64_LO20 TLSL1
+ 98: R_LARCH_RELAX \*ABS\*
+ 9c: 03000085 lu52i.d \$a1, \$a0, 0
+ 9c: R_LARCH_TLS_LE64_HI12 TLSL1
+ 9c: R_LARCH_RELAX \*ABS\*
+ a0: 58000085 beq \$a0, \$a1, 0 # 0xa0
+ a0: R_LARCH_B16 .L1\+0x8
+ a4: 5c000085 bne \$a0, \$a1, 0 # 0xa4
+ a4: R_LARCH_B16 .L1\+0x8
+ a8: 60000085 blt \$a0, \$a1, 0 # 0xa8
+ a8: R_LARCH_B16 .L1\+0x8
+ ac: 64000085 bge \$a0, \$a1, 0 # 0xac
+ ac: R_LARCH_B16 .L1\+0x8
+ b0: 68000085 bltu \$a0, \$a1, 0 # 0xb0
+ b0: R_LARCH_B16 .L1\+0x8
+ b4: 6c000085 bgeu \$a0, \$a1, 0 # 0xb4
+ b4: R_LARCH_B16 .L1\+0x8
+ b8: 4c0000a4 jirl \$a0, \$a1, 0
+ b8: R_LARCH_B16 .L1\+0x8
+ bc: 40000080 beqz \$a0, 0 # 0xbc
+ bc: R_LARCH_B21 .L1\+0x8
+ c0: 44000080 bnez \$a0, 0 # 0xc0
+ c0: R_LARCH_B21 .L1\+0x8
+ c4: 50000000 b 0 # 0xc4
+ c4: R_LARCH_B26 .L1\+0x8
+ c8: 54000000 bl 0 # 0xc8
+ c8: R_LARCH_B26 .L1\+0x8
+ cc: 14000004 lu12i.w \$a0, 0
+ cc: R_LARCH_ABS_HI20 .L1\+0x8
+ d0: 038000a4 ori \$a0, \$a1, 0x0
+ d0: R_LARCH_ABS_LO12 .L1\+0x8
+ d4: 16000004 lu32i.d \$a0, 0
+ d4: R_LARCH_ABS64_LO20 .L1\+0x8
+ d8: 03000085 lu52i.d \$a1, \$a0, 0
+ d8: R_LARCH_ABS64_HI12 .L1\+0x8
+ dc: 1a000004 pcalau12i \$a0, 0
+ dc: R_LARCH_PCALA_HI20 .L1\+0x8
+ e0: 1a000004 pcalau12i \$a0, 0
+ e0: R_LARCH_GOT_PC_HI20 .L1\+0x8
+ e4: 1a000004 pcalau12i \$a0, 0
+ e4: R_LARCH_GOT_PC_LO12 .L1\+0x8
+ e8: 1a000004 pcalau12i \$a0, 0
+ e8: R_LARCH_TLS_IE_PC_HI20 TLSL1\+0x8
+ ec: 1a000004 pcalau12i \$a0, 0
+ ec: R_LARCH_TLS_LD_PC_HI20 TLSL1\+0x8
+ f0: 1a000004 pcalau12i \$a0, 0
+ f0: R_LARCH_TLS_GD_PC_HI20 TLSL1\+0x8
+ f4: 02800085 addi.w \$a1, \$a0, 0
+ f4: R_LARCH_PCALA_LO12 .L1\+0x8
+ f8: 02c00085 addi.d \$a1, \$a0, 0
+ f8: R_LARCH_PCALA_LO12 .L1\+0x8
+ fc: 28000085 ld.b \$a1, \$a0, 0
+ fc: R_LARCH_PCALA_LO12 .L1\+0x8
+ 100: 28400085 ld.h \$a1, \$a0, 0
+ 100: R_LARCH_PCALA_LO12 .L1\+0x8
+ 104: 28800085 ld.w \$a1, \$a0, 0
+ 104: R_LARCH_PCALA_LO12 .L1\+0x8
+ 108: 28c00085 ld.d \$a1, \$a0, 0
+ 108: R_LARCH_PCALA_LO12 .L1\+0x8
+ 10c: 16000004 lu32i.d \$a0, 0
+ 10c: R_LARCH_PCALA64_LO20 .L1\+0x8
+ 110: 03000085 lu52i.d \$a1, \$a0, 0
+ 110: R_LARCH_PCALA64_LO20 .L1\+0x8
+ 114: 16000004 lu32i.d \$a0, 0
+ 114: R_LARCH_GOT64_PC_LO20 .L1\+0x8
+ 118: 03000085 lu52i.d \$a1, \$a0, 0
+ 118: R_LARCH_GOT64_PC_HI12 .L1\+0x8
+ 11c: 14000004 lu12i.w \$a0, 0
+ 11c: R_LARCH_GOT_HI20 .L1\+0x8
+ 120: 03800084 ori \$a0, \$a0, 0x0
+ 120: R_LARCH_GOT_LO12 .L1\+0x8
+ 124: 16000004 lu32i.d \$a0, 0
+ 124: R_LARCH_GOT64_LO20 .L1\+0x8
+ 128: 03000085 lu52i.d \$a1, \$a0, 0
+ 128: R_LARCH_GOT64_HI12 .L1\+0x8
+ 12c: 14000004 lu12i.w \$a0, 0
+ 12c: R_LARCH_TLS_LE_HI20 TLSL1\+0x8
+ 12c: R_LARCH_RELAX \*ABS\*
+ 130: 03800085 ori \$a1, \$a0, 0x0
+ 130: R_LARCH_TLS_LE_LO12 TLSL1\+0x8
+ 130: R_LARCH_RELAX \*ABS\*
+ 134: 16000004 lu32i.d \$a0, 0
+ 134: R_LARCH_TLS_LE64_LO20 TLSL1\+0x8
+ 134: R_LARCH_RELAX \*ABS\*
+ 138: 03000085 lu52i.d \$a1, \$a0, 0
+ 138: R_LARCH_TLS_LE64_HI12 TLSL1\+0x8
+ 138: R_LARCH_RELAX \*ABS\*
+ 13c: 14000004 lu12i.w \$a0, 0
+ 13c: R_LARCH_TLS_LE_HI20_R TLSL1
+ 13c: R_LARCH_RELAX \*ABS\*
+ 140: 001090a5 add.d \$a1, \$a1, \$a0
+ 140: R_LARCH_TLS_LE_ADD_R TLSL1
+ 140: R_LARCH_RELAX \*ABS\*
+ 144: 29800085 st.w \$a1, \$a0, 0
+ 144: R_LARCH_TLS_LE_LO12_R TLSL1
+ 144: R_LARCH_RELAX \*ABS\*
+ 148: 14000004 lu12i.w \$a0, 0
+ 148: R_LARCH_TLS_LE_HI20_R TLSL1\+0x8
+ 148: R_LARCH_RELAX \*ABS\*
+ 14c: 001090a5 add.d \$a1, \$a1, \$a0
+ 14c: R_LARCH_TLS_LE_ADD_R TLSL1\+0x8
+ 14c: R_LARCH_RELAX \*ABS\*
+ 150: 29800085 st.w \$a1, \$a0, 0
+ 150: R_LARCH_TLS_LE_LO12_R TLSL1\+0x8
+ 150: R_LARCH_RELAX \*ABS\*
diff --git a/gas/testsuite/gas/loongarch/tlsdesc_64.d b/gas/testsuite/gas/loongarch/tlsdesc_64.d
index 2a2829c9b44..8fc9e883a4a 100644
--- a/gas/testsuite/gas/loongarch/tlsdesc_64.d
+++ b/gas/testsuite/gas/loongarch/tlsdesc_64.d
@@ -24,5 +24,7 @@ Disassembly of section .text:
14: R_LARCH_RELAX \*ABS\*
18: 28c00081 ld.d \$ra, \$a0, 0
18: R_LARCH_TLS_DESC_LD var
+ 18: R_LARCH_RELAX \*ABS\*
1c: 4c000021 jirl \$ra, \$ra, 0
1c: R_LARCH_TLS_DESC_CALL var
+ 1c: R_LARCH_RELAX \*ABS\*
diff --git a/ld/testsuite/ld-loongarch-elf/desc-ie.d b/ld/testsuite/ld-loongarch-elf/desc-ie.d
index 32e350507db..e1f49e2d556 100644
--- a/ld/testsuite/ld-loongarch-elf/desc-ie.d
+++ b/ld/testsuite/ld-loongarch-elf/desc-ie.d
@@ -1,5 +1,5 @@
#as:
-#ld: -shared -z norelro -e 0x0 --hash-style=both
+#ld: -shared -z norelro --hash-style=both
#objdump: -dr
#skip: loongarch32-*-*
@@ -7,10 +7,8 @@
Disassembly of section .text:
-0+230 <fn1>:
- 230: 1a000084 pcalau12i \$a0, 4
- 234: 28cd6084 ld.d \$a0, \$a0, 856
- 238: 03400000 nop.*
- 23c: 03400000 nop.*
- 240: 1a000084 pcalau12i \$a0, 4
- 244: 28cd6081 ld.d \$ra, \$a0, 856
+[0-9a-f]+ <fn1>:
+ +[0-9a-f]+: 1a000084 pcalau12i \$a0, .*
+ +[0-9a-f]+: 28cca084 ld.d \$a0, \$a0, .*
+ +[0-9a-f]+: 1a000084 pcalau12i \$a0, .*
+ +[0-9a-f]+: 28cca084 ld.d \$a0, \$a0, .*
diff --git a/ld/testsuite/ld-loongarch-elf/desc-ie.s b/ld/testsuite/ld-loongarch-elf/desc-ie.s
index 7f5772bcf23..441080b64b3 100644
--- a/ld/testsuite/ld-loongarch-elf/desc-ie.s
+++ b/ld/testsuite/ld-loongarch-elf/desc-ie.s
@@ -1,6 +1,6 @@
- .global v1
+ .global var
.section .tdata,"awT",@progbits
-v1:
+var:
.word 1
.text
.global fn1
@@ -9,10 +9,5 @@ fn1:
# Use DESC and IE to access the same symbol,
# DESC will relax to IE.
- pcalau12i $a0,%desc_pc_hi20(var)
- addi.d $a0,$a0,%desc_pc_lo12(var)
- ld.d $ra,$a0,%desc_ld(var)
- jirl $ra,$ra,%desc_call(var)
-
- pcalau12i $a0,%ie_pc_hi20(var)
- ld.d $ra,$a0,%ie_pc_lo12(var)
+ la.tls.ie $a0,var
+ la.tls.desc $a0,var
diff --git a/ld/testsuite/ld-loongarch-elf/desc-le.d b/ld/testsuite/ld-loongarch-elf/desc-le.d
index b4ca9f82eb3..53bf2b8c3e4 100644
--- a/ld/testsuite/ld-loongarch-elf/desc-le.d
+++ b/ld/testsuite/ld-loongarch-elf/desc-le.d
@@ -1,5 +1,5 @@
#as:
-#ld: -z norelro -e 0x0
+#ld: -z norelro -e0
#objdump: -dr
#skip: loongarch32-*-*
@@ -8,8 +8,6 @@
Disassembly of section .text:
-0+1200000e8 <fn1>:
- 1200000e8: 14000004 lu12i.w \$a0, 0
- 1200000ec: 03800084 ori \$a0, \$a0, 0x0
- 1200000f0: 03400000 nop.*
- 1200000f4: 03400000 nop.*
+[0-9a-f]+ <fn1>:
+ +[0-9a-f]+: 14000024 lu12i.w \$a0, .*
+ +[0-9a-f]+: 03800084 ori \$a0, \$a0, .*
diff --git a/ld/testsuite/ld-loongarch-elf/desc-le.s b/ld/testsuite/ld-loongarch-elf/desc-le.s
index 9ffaa2d668d..5781cb212d6 100644
--- a/ld/testsuite/ld-loongarch-elf/desc-le.s
+++ b/ld/testsuite/ld-loongarch-elf/desc-le.s
@@ -1,5 +1,6 @@
.global var
.section .tdata,"awT",@progbits
+ .fill 0x1000,1,0
var:
.word 1
.text
@@ -8,7 +9,4 @@ var:
fn1:
# DESC will relax to LE.
- pcalau12i $a0,%desc_pc_hi20(var)
- addi.d $a0,$a0,%desc_pc_lo12(var)
- ld.d $ra,$a0,%desc_ld(var)
- jirl $ra,$ra,%desc_call(var)
+ la.tls.desc $a0,var
diff --git a/ld/testsuite/ld-loongarch-elf/ie-le.d b/ld/testsuite/ld-loongarch-elf/ie-le.d
index 42694d7f9f0..b37acc9403f 100644
--- a/ld/testsuite/ld-loongarch-elf/ie-le.d
+++ b/ld/testsuite/ld-loongarch-elf/ie-le.d
@@ -1,5 +1,5 @@
#as:
-#ld: -z norelro -e 0x0
+#ld: -z norelro -e0
#objdump: -dr
#skip: loongarch32-*-*
@@ -8,6 +8,6 @@
Disassembly of section .text:
-0+1200000e8 <fn1>:
- 1200000e8: 14000004 lu12i.w \$a0, 0
- 1200000ec: 03800084 ori \$a0, \$a0, 0x0
+[0-9a-f]+ <.*>:
+ +[0-9a-f]+: 14000024 lu12i.w \$a0, .*
+ +[0-9a-f]+: 03800084 ori \$a0, \$a0, .*
diff --git a/ld/testsuite/ld-loongarch-elf/ie-le.s b/ld/testsuite/ld-loongarch-elf/ie-le.s
index 795c7ce49cf..db87a2d3a75 100644
--- a/ld/testsuite/ld-loongarch-elf/ie-le.s
+++ b/ld/testsuite/ld-loongarch-elf/ie-le.s
@@ -1,5 +1,6 @@
.data
.section .tdata,"awT",@progbits
+ .fill 0x1000,1,0
var:
.word 1
.text
@@ -7,5 +8,4 @@ var:
.type gn1,@function
fn1:
# expect IE to relax LE.
- pcalau12i $a0,%ie_pc_hi20(var)
- ld.d $a0,$a0,%ie_pc_lo12(var)
+ la.tls.ie $a0,var
diff --git a/ld/testsuite/ld-loongarch-elf/macro_op.d b/ld/testsuite/ld-loongarch-elf/macro_op.d
index c9493918a93..96bca8434ee 100644
--- a/ld/testsuite/ld-loongarch-elf/macro_op.d
+++ b/ld/testsuite/ld-loongarch-elf/macro_op.d
@@ -7,181 +7,185 @@
Disassembly of section .text:
-[ ]*0000000000000000 <.L1>:
-[ ]+0:[ ]+00150004[ ]+move[ ]+\$a0, \$zero
-[ ]+4:[ ]+02bffc04[ ]+li.w[ ]+\$a0, -1
-[ ]+8:[ ]+00150004[ ]+move[ ]+\$a0, \$zero
-[ ]+c:[ ]+02bffc04[ ]+li.w[ ]+\$a0, -1
-[ ]+10:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0
-[ ]+10: R_LARCH_GOT_PC_HI20[ ]+.L1
-[ ]+10: R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+14:[ ]+28c00084[ ]+ld.d[ ]+\$a0, \$a0, 0
-[ ]+14: R_LARCH_GOT_PC_LO12[ ]+.L1
-[ ]+14: R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+18:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0
-[ ]+18: R_LARCH_GOT_PC_HI20[ ]+.L1
-[ ]+18: R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+1c:[ ]+28c00084[ ]+ld.d[ ]+\$a0, \$a0, 0
-[ ]+1c: R_LARCH_GOT_PC_LO12[ ]+.L1
-[ ]+1c: R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+20:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0
-[ ]+20: R_LARCH_GOT_PC_HI20[ ]+.L1
-[ ]+24:[ ]+02c00005[ ]+li.d[ ]+\$a1, 0
-[ ]+24: R_LARCH_GOT_PC_LO12[ ]+.L1
-[ ]+28:[ ]+16000005[ ]+lu32i.d[ ]+\$a1, 0
-[ ]+28: R_LARCH_GOT64_PC_LO20[ ]+.L1
-[ ]+2c:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1, \$a1, 0
-[ ]+2c: R_LARCH_GOT64_PC_HI12[ ]+.L1
-[ ]+30:[ ]+380c1484[ ]+ldx.d[ ]+\$a0, \$a0, \$a1
-[ ]+34:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0
-[ ]+34: R_LARCH_GOT_PC_HI20[ ]+.L1
-[ ]+34: R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+38:[ ]+28c00084[ ]+ld.d[ ]+\$a0, \$a0, 0
-[ ]+38: R_LARCH_GOT_PC_LO12[ ]+.L1
-[ ]+38: R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+3c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0
-[ ]+3c: R_LARCH_GOT_PC_HI20[ ]+.L1
-[ ]+40:[ ]+02c00005[ ]+li.d[ ]+\$a1, 0
-[ ]+40: R_LARCH_GOT_PC_LO12[ ]+.L1
-[ ]+44:[ ]+16000005[ ]+lu32i.d[ ]+\$a1, 0
-[ ]+44: R_LARCH_GOT64_PC_LO20[ ]+.L1
-[ ]+48:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1, \$a1, 0
-[ ]+48: R_LARCH_GOT64_PC_HI12[ ]+.L1
-[ ]+4c:[ ]+380c1484[ ]+ldx.d[ ]+\$a0, \$a0, \$a1
-[ ]+50:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0
-[ ]+50: R_LARCH_GOT_PC_HI20[ ]+.L1
-[ ]+50: R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+54:[ ]+28c00084[ ]+ld.d[ ]+\$a0, \$a0, 0
-[ ]+54: R_LARCH_GOT_PC_LO12[ ]+.L1
-[ ]+54: R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+58:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0
-[ ]+58: R_LARCH_GOT_PC_HI20[ ]+.L1
-[ ]+5c:[ ]+02c00005[ ]+li.d[ ]+\$a1, 0
-[ ]+5c: R_LARCH_GOT_PC_LO12[ ]+.L1
-[ ]+60:[ ]+16000005[ ]+lu32i.d[ ]+\$a1, 0
-[ ]+60: R_LARCH_GOT64_PC_LO20[ ]+.L1
-[ ]+64:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1, \$a1, 0
-[ ]+64: R_LARCH_GOT64_PC_HI12[ ]+.L1
-[ ]+68:[ ]+380c1484[ ]+ldx.d[ ]+\$a0, \$a0, \$a1
-[ ]+6c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0
-[ ]+6c: R_LARCH_PCALA_HI20[ ]+.L1
-[ ]+6c: R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+70:[ ]+02c00084[ ]+addi.d[ ]+\$a0, \$a0, 0
-[ ]+70: R_LARCH_PCALA_LO12[ ]+.L1
-[ ]+70: R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+74:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0
-[ ]+74: R_LARCH_PCALA_HI20[ ]+.L1
-[ ]+78:[ ]+02c00005[ ]+li.d[ ]+\$a1, 0
-[ ]+78: R_LARCH_PCALA_LO12[ ]+.L1
-[ ]+7c:[ ]+16000005[ ]+lu32i.d[ ]+\$a1, 0
-[ ]+7c: R_LARCH_PCALA64_LO20[ ]+.L1
-[ ]+80:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1, \$a1, 0
-[ ]+80: R_LARCH_PCALA64_HI12[ ]+.L1
-[ ]+84:[ ]+00109484[ ]+add.d[ ]+\$a0, \$a0, \$a1
-[ ]+88:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0
-[ ]+88: R_LARCH_PCALA_HI20[ ]+.L1
-[ ]+88: R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+8c:[ ]+02c00084[ ]+addi.d[ ]+\$a0, \$a0, 0
-[ ]+8c: R_LARCH_PCALA_LO12[ ]+.L1
-[ ]+8c: R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+90:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0
-[ ]+90: R_LARCH_PCALA_HI20[ ]+.L1
-[ ]+94:[ ]+02c00005[ ]+li.d[ ]+\$a1, 0
-[ ]+94: R_LARCH_PCALA_LO12[ ]+.L1
-[ ]+98:[ ]+16000005[ ]+lu32i.d[ ]+\$a1, 0
-[ ]+98: R_LARCH_PCALA64_LO20[ ]+.L1
-[ ]+9c:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1, \$a1, 0
-[ ]+9c: R_LARCH_PCALA64_HI12[ ]+.L1
-[ ]+a0:[ ]+00109484[ ]+add.d[ ]+\$a0, \$a0, \$a1
-[ ]+a4:[ ]+14000004[ ]+lu12i.w[ ]+\$a0, 0
-[ ]+a4: R_LARCH_MARK_LA[ ]+\*ABS\*
-[ ]+a4: R_LARCH_ABS_HI20[ ]+.L1
-[ ]+a8:[ ]+03800084[ ]+ori[ ]+\$a0, \$a0, 0x0
-[ ]+a8: R_LARCH_ABS_LO12[ ]+.L1
-[ ]+ac:[ ]+16000004[ ]+lu32i.d[ ]+\$a0, 0
-[ ]+ac: R_LARCH_ABS64_LO20[ ]+.L1
-[ ]+b0:[ ]+03000084[ ]+lu52i.d[ ]+\$a0, \$a0, 0
-[ ]+b0: R_LARCH_ABS64_HI12[ ]+.L1
-[ ]+b4:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0
-[ ]+b4: R_LARCH_PCALA_HI20[ ]+.L1
-[ ]+b4: R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+b8:[ ]+02c00084[ ]+addi.d[ ]+\$a0, \$a0, 0
-[ ]+b8: R_LARCH_PCALA_LO12[ ]+.L1
-[ ]+b8: R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+bc:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0
-[ ]+bc: R_LARCH_PCALA_HI20[ ]+.L1
-[ ]+bc: R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+c0:[ ]+02c00084[ ]+addi.d[ ]+\$a0, \$a0, 0
-[ ]+c0: R_LARCH_PCALA_LO12[ ]+.L1
-[ ]+c0: R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+c4:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0
-[ ]+c4: R_LARCH_PCALA_HI20[ ]+.L1
-[ ]+c8:[ ]+02c00005[ ]+li.d[ ]+\$a1, 0
-[ ]+c8: R_LARCH_PCALA_LO12[ ]+.L1
-[ ]+cc:[ ]+16000005[ ]+lu32i.d[ ]+\$a1, 0
-[ ]+cc: R_LARCH_PCALA64_LO20[ ]+.L1
-[ ]+d0:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1, \$a1, 0
-[ ]+d0: R_LARCH_PCALA64_HI12[ ]+.L1
-[ ]+d4:[ ]+00109484[ ]+add.d[ ]+\$a0, \$a0, \$a1
-[ ]+d8:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0
-[ ]+d8: R_LARCH_GOT_PC_HI20[ ]+.L1
-[ ]+d8: R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+dc:[ ]+28c00084[ ]+ld.d[ ]+\$a0, \$a0, 0
-[ ]+dc: R_LARCH_GOT_PC_LO12[ ]+.L1
-[ ]+dc: R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+e0:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0
-[ ]+e0: R_LARCH_GOT_PC_HI20[ ]+.L1
-[ ]+e4:[ ]+02c00005[ ]+li.d[ ]+\$a1, 0
-[ ]+e4: R_LARCH_GOT_PC_LO12[ ]+.L1
-[ ]+e8:[ ]+16000005[ ]+lu32i.d[ ]+\$a1, 0
-[ ]+e8: R_LARCH_GOT64_PC_LO20[ ]+.L1
-[ ]+ec:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1, \$a1, 0
-[ ]+ec: R_LARCH_GOT64_PC_HI12[ ]+.L1
-[ ]+f0:[ ]+380c1484[ ]+ldx.d[ ]+\$a0, \$a0, \$a1
-[ ]+f4:[ ]+14000004[ ]+lu12i.w[ ]+\$a0, 0
-[ ]+f4: R_LARCH_TLS_LE_HI20[ ]+TLS1
-[ ]+f8:[ ]+03800084[ ]+ori[ ]+\$a0, \$a0, 0x0
-[ ]+f8: R_LARCH_TLS_LE_LO12[ ]+TLS1
-[ ]+fc:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0
-[ ]+fc: R_LARCH_TLS_IE_PC_HI20[ ]+TLS1
-[ ]+100:[ ]+28c00084[ ]+ld.d[ ]+\$a0, \$a0, 0
-[ ]+100: R_LARCH_TLS_IE_PC_LO12[ ]+TLS1
-[ ]+104:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0
-[ ]+104: R_LARCH_TLS_IE_PC_HI20[ ]+TLS1
-[ ]+108:[ ]+02c00005[ ]+li.d[ ]+\$a1, 0
-[ ]+108: R_LARCH_TLS_IE_PC_LO12[ ]+TLS1
-[ ]+10c:[ ]+16000005[ ]+lu32i.d[ ]+\$a1, 0
-[ ]+10c: R_LARCH_TLS_IE64_PC_LO20[ ]+TLS1
-[ ]+110:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1, \$a1, 0
-[ ]+110: R_LARCH_TLS_IE64_PC_HI12[ ]+TLS1
-[ ]+114:[ ]+380c1484[ ]+ldx.d[ ]+\$a0, \$a0, \$a1
-[ ]+118:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0
-[ ]+118: R_LARCH_TLS_LD_PC_HI20[ ]+TLS1
-[ ]+118: R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+11c:[ ]+02c00084[ ]+addi.d[ ]+\$a0, \$a0, 0
-[ ]+11c: R_LARCH_GOT_PC_LO12[ ]+TLS1
-[ ]+11c: R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+120:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0
-[ ]+120: R_LARCH_TLS_LD_PC_HI20[ ]+TLS1
-[ ]+124:[ ]+02c00005[ ]+li.d[ ]+\$a1, 0
-[ ]+124: R_LARCH_GOT_PC_LO12[ ]+TLS1
-[ ]+128:[ ]+16000005[ ]+lu32i.d[ ]+\$a1, 0
-[ ]+128: R_LARCH_GOT64_PC_LO20[ ]+TLS1
-[ ]+12c:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1, \$a1, 0
-[ ]+12c: R_LARCH_GOT64_PC_HI12[ ]+TLS1
-[ ]+130:[ ]+00109484[ ]+add.d[ ]+\$a0, \$a0, \$a1
-[ ]+134:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0
-[ ]+134: R_LARCH_TLS_GD_PC_HI20[ ]+TLS1
-[ ]+134: R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+138:[ ]+02c00084[ ]+addi.d[ ]+\$a0, \$a0, 0
-[ ]+138: R_LARCH_GOT_PC_LO12[ ]+TLS1
-[ ]+138: R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+13c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0
-[ ]+13c: R_LARCH_TLS_GD_PC_HI20[ ]+TLS1
-[ ]+140:[ ]+02c00005[ ]+li.d[ ]+\$a1, 0
-[ ]+140: R_LARCH_GOT_PC_LO12[ ]+TLS1
-[ ]+144:[ ]+16000005[ ]+lu32i.d[ ]+\$a1, 0
-[ ]+144: R_LARCH_GOT64_PC_LO20[ ]+TLS1
-[ ]+148:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1, \$a1, 0
-[ ]+148: R_LARCH_GOT64_PC_HI12[ ]+TLS1
-[ ]+14c:[ ]+00109484[ ]+add.d[ ]+\$a0, \$a0, \$a1
+0+ <.*>:
+ 0: 00150004 move \$a0, \$zero
+ 4: 02bffc04 li.w \$a0, -1
+ 8: 00150004 move \$a0, \$zero
+ c: 02bffc04 li.w \$a0, -1
+ 10: 1a000004 pcalau12i \$a0, 0
+ 10: R_LARCH_GOT_PC_HI20 .L1
+ 10: R_LARCH_RELAX \*ABS\*
+ 14: 28c00084 ld.d \$a0, \$a0, 0
+ 14: R_LARCH_GOT_PC_LO12 .L1
+ 14: R_LARCH_RELAX \*ABS\*
+ 18: 1a000004 pcalau12i \$a0, 0
+ 18: R_LARCH_GOT_PC_HI20 .L1
+ 18: R_LARCH_RELAX \*ABS\*
+ 1c: 28c00084 ld.d \$a0, \$a0, 0
+ 1c: R_LARCH_GOT_PC_LO12 .L1
+ 1c: R_LARCH_RELAX \*ABS\*
+ 20: 1a000004 pcalau12i \$a0, 0
+ 20: R_LARCH_GOT_PC_HI20 .L1
+ 24: 02c00005 li.d \$a1, 0
+ 24: R_LARCH_GOT_PC_LO12 .L1
+ 28: 16000005 lu32i.d \$a1, 0
+ 28: R_LARCH_GOT64_PC_LO20 .L1
+ 2c: 030000a5 lu52i.d \$a1, \$a1, 0
+ 2c: R_LARCH_GOT64_PC_HI12 .L1
+ 30: 380c1484 ldx.d \$a0, \$a0, \$a1
+ 34: 1a000004 pcalau12i \$a0, 0
+ 34: R_LARCH_GOT_PC_HI20 .L1
+ 34: R_LARCH_RELAX \*ABS\*
+ 38: 28c00084 ld.d \$a0, \$a0, 0
+ 38: R_LARCH_GOT_PC_LO12 .L1
+ 38: R_LARCH_RELAX \*ABS\*
+ 3c: 1a000004 pcalau12i \$a0, 0
+ 3c: R_LARCH_GOT_PC_HI20 .L1
+ 40: 02c00005 li.d \$a1, 0
+ 40: R_LARCH_GOT_PC_LO12 .L1
+ 44: 16000005 lu32i.d \$a1, 0
+ 44: R_LARCH_GOT64_PC_LO20 .L1
+ 48: 030000a5 lu52i.d \$a1, \$a1, 0
+ 48: R_LARCH_GOT64_PC_HI12 .L1
+ 4c: 380c1484 ldx.d \$a0, \$a0, \$a1
+ 50: 1a000004 pcalau12i \$a0, 0
+ 50: R_LARCH_GOT_PC_HI20 .L1
+ 50: R_LARCH_RELAX \*ABS\*
+ 54: 28c00084 ld.d \$a0, \$a0, 0
+ 54: R_LARCH_GOT_PC_LO12 .L1
+ 54: R_LARCH_RELAX \*ABS\*
+ 58: 1a000004 pcalau12i \$a0, 0
+ 58: R_LARCH_GOT_PC_HI20 .L1
+ 5c: 02c00005 li.d \$a1, 0
+ 5c: R_LARCH_GOT_PC_LO12 .L1
+ 60: 16000005 lu32i.d \$a1, 0
+ 60: R_LARCH_GOT64_PC_LO20 .L1
+ 64: 030000a5 lu52i.d \$a1, \$a1, 0
+ 64: R_LARCH_GOT64_PC_HI12 .L1
+ 68: 380c1484 ldx.d \$a0, \$a0, \$a1
+ 6c: 1a000004 pcalau12i \$a0, 0
+ 6c: R_LARCH_PCALA_HI20 .L1
+ 6c: R_LARCH_RELAX \*ABS\*
+ 70: 02c00084 addi.d \$a0, \$a0, 0
+ 70: R_LARCH_PCALA_LO12 .L1
+ 70: R_LARCH_RELAX \*ABS\*
+ 74: 1a000004 pcalau12i \$a0, 0
+ 74: R_LARCH_PCALA_HI20 .L1
+ 78: 02c00005 li.d \$a1, 0
+ 78: R_LARCH_PCALA_LO12 .L1
+ 7c: 16000005 lu32i.d \$a1, 0
+ 7c: R_LARCH_PCALA64_LO20 .L1
+ 80: 030000a5 lu52i.d \$a1, \$a1, 0
+ 80: R_LARCH_PCALA64_HI12 .L1
+ 84: 00109484 add.d \$a0, \$a0, \$a1
+ 88: 1a000004 pcalau12i \$a0, 0
+ 88: R_LARCH_PCALA_HI20 .L1
+ 88: R_LARCH_RELAX \*ABS\*
+ 8c: 02c00084 addi.d \$a0, \$a0, 0
+ 8c: R_LARCH_PCALA_LO12 .L1
+ 8c: R_LARCH_RELAX \*ABS\*
+ 90: 1a000004 pcalau12i \$a0, 0
+ 90: R_LARCH_PCALA_HI20 .L1
+ 94: 02c00005 li.d \$a1, 0
+ 94: R_LARCH_PCALA_LO12 .L1
+ 98: 16000005 lu32i.d \$a1, 0
+ 98: R_LARCH_PCALA64_LO20 .L1
+ 9c: 030000a5 lu52i.d \$a1, \$a1, 0
+ 9c: R_LARCH_PCALA64_HI12 .L1
+ a0: 00109484 add.d \$a0, \$a0, \$a1
+ a4: 14000004 lu12i.w \$a0, 0
+ a4: R_LARCH_MARK_LA \*ABS\*
+ a4: R_LARCH_ABS_HI20 .L1
+ a8: 03800084 ori \$a0, \$a0, 0x0
+ a8: R_LARCH_ABS_LO12 .L1
+ ac: 16000004 lu32i.d \$a0, 0
+ ac: R_LARCH_ABS64_LO20 .L1
+ b0: 03000084 lu52i.d \$a0, \$a0, 0
+ b0: R_LARCH_ABS64_HI12 .L1
+ b4: 1a000004 pcalau12i \$a0, 0
+ b4: R_LARCH_PCALA_HI20 .L1
+ b4: R_LARCH_RELAX \*ABS\*
+ b8: 02c00084 addi.d \$a0, \$a0, 0
+ b8: R_LARCH_PCALA_LO12 .L1
+ b8: R_LARCH_RELAX \*ABS\*
+ bc: 1a000004 pcalau12i \$a0, 0
+ bc: R_LARCH_PCALA_HI20 .L1
+ bc: R_LARCH_RELAX \*ABS\*
+ c0: 02c00084 addi.d \$a0, \$a0, 0
+ c0: R_LARCH_PCALA_LO12 .L1
+ c0: R_LARCH_RELAX \*ABS\*
+ c4: 1a000004 pcalau12i \$a0, 0
+ c4: R_LARCH_PCALA_HI20 .L1
+ c8: 02c00005 li.d \$a1, 0
+ c8: R_LARCH_PCALA_LO12 .L1
+ cc: 16000005 lu32i.d \$a1, 0
+ cc: R_LARCH_PCALA64_LO20 .L1
+ d0: 030000a5 lu52i.d \$a1, \$a1, 0
+ d0: R_LARCH_PCALA64_HI12 .L1
+ d4: 00109484 add.d \$a0, \$a0, \$a1
+ d8: 1a000004 pcalau12i \$a0, 0
+ d8: R_LARCH_GOT_PC_HI20 .L1
+ d8: R_LARCH_RELAX \*ABS\*
+ dc: 28c00084 ld.d \$a0, \$a0, 0
+ dc: R_LARCH_GOT_PC_LO12 .L1
+ dc: R_LARCH_RELAX \*ABS\*
+ e0: 1a000004 pcalau12i \$a0, 0
+ e0: R_LARCH_GOT_PC_HI20 .L1
+ e4: 02c00005 li.d \$a1, 0
+ e4: R_LARCH_GOT_PC_LO12 .L1
+ e8: 16000005 lu32i.d \$a1, 0
+ e8: R_LARCH_GOT64_PC_LO20 .L1
+ ec: 030000a5 lu52i.d \$a1, \$a1, 0
+ ec: R_LARCH_GOT64_PC_HI12 .L1
+ f0: 380c1484 ldx.d \$a0, \$a0, \$a1
+ f4: 14000004 lu12i.w \$a0, 0
+ f4: R_LARCH_TLS_LE_HI20 TLS1
+ f4: R_LARCH_RELAX \*ABS\*
+ f8: 03800084 ori \$a0, \$a0, 0x0
+ f8: R_LARCH_TLS_LE_LO12 TLS1
+ f8: R_LARCH_RELAX \*ABS\*
+ fc: 1a000004 pcalau12i \$a0, 0
+ fc: R_LARCH_TLS_IE_PC_HI20 TLS1
+ fc: R_LARCH_RELAX \*ABS\*
+ 100: 28c00084 ld.d \$a0, \$a0, 0
+ 100: R_LARCH_TLS_IE_PC_LO12 TLS1
+ 100: R_LARCH_RELAX \*ABS\*
+ 104: 1a000004 pcalau12i \$a0, 0
+ 104: R_LARCH_TLS_IE_PC_HI20 TLS1
+ 108: 02c00005 li.d \$a1, 0
+ 108: R_LARCH_TLS_IE_PC_LO12 TLS1
+ 10c: 16000005 lu32i.d \$a1, 0
+ 10c: R_LARCH_TLS_IE64_PC_LO20 TLS1
+ 110: 030000a5 lu52i.d \$a1, \$a1, 0
+ 110: R_LARCH_TLS_IE64_PC_HI12 TLS1
+ 114: 380c1484 ldx.d \$a0, \$a0, \$a1
+ 118: 1a000004 pcalau12i \$a0, 0
+ 118: R_LARCH_TLS_LD_PC_HI20 TLS1
+ 118: R_LARCH_RELAX \*ABS\*
+ 11c: 02c00084 addi.d \$a0, \$a0, 0
+ 11c: R_LARCH_GOT_PC_LO12 TLS1
+ 11c: R_LARCH_RELAX \*ABS\*
+ 120: 1a000004 pcalau12i \$a0, 0
+ 120: R_LARCH_TLS_LD_PC_HI20 TLS1
+ 124: 02c00005 li.d \$a1, 0
+ 124: R_LARCH_GOT_PC_LO12 TLS1
+ 128: 16000005 lu32i.d \$a1, 0
+ 128: R_LARCH_GOT64_PC_LO20 TLS1
+ 12c: 030000a5 lu52i.d \$a1, \$a1, 0
+ 12c: R_LARCH_GOT64_PC_HI12 TLS1
+ 130: 00109484 add.d \$a0, \$a0, \$a1
+ 134: 1a000004 pcalau12i \$a0, 0
+ 134: R_LARCH_TLS_GD_PC_HI20 TLS1
+ 134: R_LARCH_RELAX \*ABS\*
+ 138: 02c00084 addi.d \$a0, \$a0, 0
+ 138: R_LARCH_GOT_PC_LO12 TLS1
+ 138: R_LARCH_RELAX \*ABS\*
+ 13c: 1a000004 pcalau12i \$a0, 0
+ 13c: R_LARCH_TLS_GD_PC_HI20 TLS1
+ 140: 02c00005 li.d \$a1, 0
+ 140: R_LARCH_GOT_PC_LO12 TLS1
+ 144: 16000005 lu32i.d \$a1, 0
+ 144: R_LARCH_GOT64_PC_LO20 TLS1
+ 148: 030000a5 lu52i.d \$a1, \$a1, 0
+ 148: R_LARCH_GOT64_PC_HI12 TLS1
+ 14c: 00109484 add.d \$a0, \$a0, \$a1
diff --git a/ld/testsuite/ld-loongarch-elf/relax.exp b/ld/testsuite/ld-loongarch-elf/relax.exp
index f421e8af8dd..8d4abd581cc 100644
--- a/ld/testsuite/ld-loongarch-elf/relax.exp
+++ b/ld/testsuite/ld-loongarch-elf/relax.exp
@@ -137,7 +137,7 @@ if [istarget loongarch64-*-*] {
[list \
[list \
"loongarch old tls le .exe build" \
- "" "" \
+ "" "--no-relax" \
"" \
{old-tls-le.s} \
{} \
@@ -158,7 +158,7 @@ if [istarget loongarch64-*-*] {
[list \
[list \
"loongarch tls le realx compatible .exe build" \
- "" "" \
+ "" "--no-relax" \
"" \
{tls-relax-compatible-check-new.s tls-relax-compatible-check-old.s} \
{} \
@@ -201,7 +201,7 @@ if [istarget loongarch64-*-*] {
[list \
[list \
"loongarch tls le realx bound-check .exe build" \
- "" "" \
+ "" "--no-relax" \
"" \
{relax-bound-check-tls-le.s} \
{} \
diff --git a/ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d b/ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d
index 453902d1622..40ffba8c14f 100644
--- a/ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d
+++ b/ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d
@@ -8,49 +8,45 @@
Disassembly of section .text:
-0+418 <fun_gl1>:
- 418: 180214c4 pcaddi \$a0, 4262
- 41c: 1a000084 pcalau12i \$a0, 4
- 420: 28db0084 ld.d \$a0, \$a0, 1728
- 424: 180212a4 pcaddi \$a0, 4245
- 428: 18021304 pcaddi \$a0, 4248
- 42c: 28c00081 ld.d \$ra, \$a0, 0
- 430: 4c000021 jirl \$ra, \$ra, 0
- 434: 1a000084 pcalau12i \$a0, 4
- 438: 28d9c084 ld.d \$a0, \$a0, 1648
- 43c: 03400000 nop.*
- 440: 03400000 nop.*
- 444: 1a000084 pcalau12i \$a0, 4
- 448: 28d9c084 ld.d \$a0, \$a0, 1648
- 44c: 18021264 pcaddi \$a0, 4243
- 450: 18021244 pcaddi \$a0, 4242
- 454: 28c00081 ld.d \$ra, \$a0, 0
- 458: 4c000021 jirl \$ra, \$ra, 0
- 45c: 1a000084 pcalau12i \$a0, 4
- 460: 28daa084 ld.d \$a0, \$a0, 1704
+[0-9a-f]+ <fun_gl1>:
+ +[0-9a-f]+: 18021444 pcaddi \$a0, .*
+ +[0-9a-f]+: 1a000084 pcalau12i \$a0, .*
+ +[0-9a-f]+: 28dac084 ld.d \$a0, \$a0, .*
+ +[0-9a-f]+: 18021224 pcaddi \$a0, .*
+ +[0-9a-f]+: 18021284 pcaddi \$a0, .*
+ +[0-9a-f]+: 28c00081 ld.d \$ra, \$a0, 0
+ +[0-9a-f]+: 4c000021 jirl \$ra, \$ra, 0
+ +[0-9a-f]+: 1a000084 pcalau12i \$a0, .*
+ +[0-9a-f]+: 28d98084 ld.d \$a0, \$a0, .*
+ +[0-9a-f]+: 1a000084 pcalau12i \$a0, .*
+ +[0-9a-f]+: 28d98084 ld.d \$a0, \$a0, .*
+ +[0-9a-f]+: 18021224 pcaddi \$a0, .*
+ +[0-9a-f]+: 18021204 pcaddi \$a0, .*
+ +[0-9a-f]+: 28c00081 ld.d \$ra, \$a0, 0
+ +[0-9a-f]+: 4c000021 jirl \$ra, \$ra, 0
+ +[0-9a-f]+: 1a000084 pcalau12i \$a0, .*
+ +[0-9a-f]+: 28da6084 ld.d \$a0, \$a0, .*
-0+464 <fun_lo>:
- 464: 1a000084 pcalau12i \$a0, 4
- 468: 28d86084 ld.d \$a0, \$a0, 1560
- 46c: 18020ce4 pcaddi \$a0, 4199
- 470: 18020e04 pcaddi \$a0, 4208
- 474: 28c00081 ld.d \$ra, \$a0, 0
- 478: 4c000021 jirl \$ra, \$ra, 0
- 47c: 18020d24 pcaddi \$a0, 4201
- 480: 1a000084 pcalau12i \$a0, 4
- 484: 28d90084 ld.d \$a0, \$a0, 1600
- 488: 03400000 nop.*
- 48c: 03400000 nop.*
- 490: 1a000084 pcalau12i \$a0, 4
- 494: 28d90084 ld.d \$a0, \$a0, 1600
- 498: 18020d84 pcaddi \$a0, 4204
- 49c: 28c00081 ld.d \$ra, \$a0, 0
- 4a0: 4c000021 jirl \$ra, \$ra, 0
- 4a4: 18020d24 pcaddi \$a0, 4201
- 4a8: 1a000084 pcalau12i \$a0, 4
- 4ac: 28d96084 ld.d \$a0, \$a0, 1624
+[0-9a-f]+ <fun_lo>:
+ +[0-9a-f]+: 1a000084 pcalau12i \$a0, .*
+ +[0-9a-f]+: 28d82084 ld.d \$a0, \$a0, .*
+ +[0-9a-f]+: 18020ca4 pcaddi \$a0, .*
+ +[0-9a-f]+: 18020dc4 pcaddi \$a0, .*
+ +[0-9a-f]+: 28c00081 ld.d \$ra, \$a0, 0
+ +[0-9a-f]+: 4c000021 jirl \$ra, \$ra, 0
+ +[0-9a-f]+: 18020ce4 pcaddi \$a0, .*
+ +[0-9a-f]+: 1a000084 pcalau12i \$a0, .*
+ +[0-9a-f]+: 28d8c084 ld.d \$a0, \$a0, .*
+ +[0-9a-f]+: 1a000084 pcalau12i \$a0, .*
+ +[0-9a-f]+: 28d8c084 ld.d \$a0, \$a0, .*
+ +[0-9a-f]+: 18020d84 pcaddi \$a0, .*
+ +[0-9a-f]+: 28c00081 ld.d \$ra, \$a0, 0
+ +[0-9a-f]+: 4c000021 jirl \$ra, \$ra, 0
+ +[0-9a-f]+: 18020d24 pcaddi \$a0, .*
+ +[0-9a-f]+: 1a000084 pcalau12i \$a0, .*
+ +[0-9a-f]+: 28d92084 ld.d \$a0, \$a0, .*
-0+4b0 <fun_external>:
- 4b0: 18020d84 pcaddi \$a0, 4204
- 4b4: 28c00081 ld.d \$ra, \$a0, 0
- 4b8: 4c000021 jirl \$ra, \$ra, 0
+[0-9a-f]+ <fun_external>:
+ +[0-9a-f]+: 18020d84 pcaddi \$a0, .*
+ +[0-9a-f]+: 28c00081 ld.d \$ra, \$a0, 0
+ +[0-9a-f]+: 4c000021 jirl \$ra, \$ra, 0
--
2.36.0
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 1/2] LoongArch: Delete extra instructions when TLS type transition
2024-01-26 13:55 [PATCH 1/2] LoongArch: Delete extra instructions when TLS type transition Lulu Cai
2024-01-26 13:55 ` [PATCH 2/2] LoongArch: Fix some test cases for TLS transition and relax Lulu Cai
@ 2024-01-26 18:22 ` Xi Ruoyao
2024-01-27 2:06 ` Lulu Cai
1 sibling, 1 reply; 4+ messages in thread
From: Xi Ruoyao @ 2024-01-26 18:22 UTC (permalink / raw)
To: Lulu Cai, binutils
Cc: xuchenghua, chenglulu, liuzhensong, mengqinggang, i.swmail,
maskray, luweining, wanglei, hejinyang
On Fri, 2024-01-26 at 21:55 +0800, Lulu Cai wrote:
> This modification mainly changes the timing of type transition,
> adds relaxation to the old LE instruction sequence, and fixes
> bugs in extreme code models.
I'd suggest to separate the bug fixes (requiring R_LARCH_RELAX for DESC
and IE transition) out into one separate commit and apply it for 2.42.
And the old LE relaxation & instruction deletion should be only applied
for trunk (2.43). We are just toooooo close to the 2.42 release, and
deleting instructions is always "dangerous" even if we do it very
carefully.
/* snip */
> +loongarch_can_trans_tls (bfd *input_bfd,
> + struct bfd_link_info *info,
> + struct elf_link_hash_entry *h,
> + const Elf_Internal_Rela *rel,
> + unsigned int r_type)
> {
> char symbol_tls_type;
> unsigned int reloc_got_type;
> + unsigned int r_symndx = ELFNN_R_SYM (rel->r_info);
>
> - if (! (IS_LOONGARCH_TLS_DESC_RELOC (r_type)
> - || IS_LOONGARCH_TLS_IE_RELOC (r_type)))
> + /* Only TLS DESC/IE in normal code mode will perform type
> + transition. */
> + if (! (IS_LOONGARCH_TLS_TRANS_RELOC (r_type)
> + && ELFNN_R_TYPE ((rel + 1)->r_info) == R_LARCH_RELAX))
We need to check if rel is the last relocation of the section, or rel +
1 may be an OOB read.
> static bool
> loongarch_relax_tls_le (bfd *abfd, asection *sec,
> @@ -4165,31 +4198,56 @@ loongarch_relax_tls_le (bfd *abfd, asection *sec,
> uint32_t insn = bfd_get (32, abfd, contents + rel->r_offset);
> static uint32_t insn_rj,insn_rd;
> symval = symval - elf_hash_table (link_info)->tls_sec->vma;
> - /* Whether the symbol offset is in the interval (offset < 0x800). */
> - if (ELFNN_R_TYPE ((rel + 1)->r_info == R_LARCH_RELAX) && (symval < 0x800))
> + /* The old LE instruction sequence can be relaxed when the symbol offset
> + is smaller than the 12-bit range. */
> + if (ELFNN_R_TYPE ((rel + 1)->r_info) == R_LARCH_RELAX && (symval <= 0xfff))
Likewise.
--
Xi Ruoyao <xry111@xry111.site>
School of Aerospace Science and Technology, Xidian University
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 1/2] LoongArch: Delete extra instructions when TLS type transition
2024-01-26 18:22 ` [PATCH 1/2] LoongArch: Delete extra instructions when TLS type transition Xi Ruoyao
@ 2024-01-27 2:06 ` Lulu Cai
0 siblings, 0 replies; 4+ messages in thread
From: Lulu Cai @ 2024-01-27 2:06 UTC (permalink / raw)
To: Xi Ruoyao, binutils
Cc: xuchenghua, chenglulu, liuzhensong, mengqinggang, i.swmail,
maskray, luweining, wanglei, hejinyang
On 1/27/24 2:22 AM, Xi Ruoyao wrote:
> On Fri, 2024-01-26 at 21:55 +0800, Lulu Cai wrote:
>> This modification mainly changes the timing of type transition,
>> adds relaxation to the old LE instruction sequence, and fixes
>> bugs in extreme code models.
> I'd suggest to separate the bug fixes (requiring R_LARCH_RELAX for DESC
> and IE transition) out into one separate commit and apply it for 2.42.
> And the old LE relaxation & instruction deletion should be only applied
> for trunk (2.43). We are just toooooo close to the 2.42 release, and
> deleting instructions is always "dangerous" even if we do it very
> carefully.
>
> /* snip */
Thanks for reminding. I will send a new patch with a separate bug fix later.
>> +loongarch_can_trans_tls (bfd *input_bfd,
>> + struct bfd_link_info *info,
>> + struct elf_link_hash_entry *h,
>> + const Elf_Internal_Rela *rel,
>> + unsigned int r_type)
>> {
>> char symbol_tls_type;
>> unsigned int reloc_got_type;
>> + unsigned int r_symndx = ELFNN_R_SYM (rel->r_info);
>>
>> - if (! (IS_LOONGARCH_TLS_DESC_RELOC (r_type)
>> - || IS_LOONGARCH_TLS_IE_RELOC (r_type)))
>> + /* Only TLS DESC/IE in normal code mode will perform type
>> + transition. */
>> + if (! (IS_LOONGARCH_TLS_TRANS_RELOC (r_type)
>> + && ELFNN_R_TYPE ((rel + 1)->r_info) == R_LARCH_RELAX))
> We need to check if rel is the last relocation of the section, or rel +
> 1 may be an OOB read.
>
Agreed, I will pay attention to these later.
>> static bool
>> loongarch_relax_tls_le (bfd *abfd, asection *sec,
>> @@ -4165,31 +4198,56 @@ loongarch_relax_tls_le (bfd *abfd, asection *sec,
>> uint32_t insn = bfd_get (32, abfd, contents + rel->r_offset);
>> static uint32_t insn_rj,insn_rd;
>> symval = symval - elf_hash_table (link_info)->tls_sec->vma;
>> - /* Whether the symbol offset is in the interval (offset < 0x800). */
>> - if (ELFNN_R_TYPE ((rel + 1)->r_info == R_LARCH_RELAX) && (symval < 0x800))
>> + /* The old LE instruction sequence can be relaxed when the symbol offset
>> + is smaller than the 12-bit range. */
>> + if (ELFNN_R_TYPE ((rel + 1)->r_info) == R_LARCH_RELAX && (symval <= 0xfff))
> Likewise.
>
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2024-01-27 2:07 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-01-26 13:55 [PATCH 1/2] LoongArch: Delete extra instructions when TLS type transition Lulu Cai
2024-01-26 13:55 ` [PATCH 2/2] LoongArch: Fix some test cases for TLS transition and relax Lulu Cai
2024-01-26 18:22 ` [PATCH 1/2] LoongArch: Delete extra instructions when TLS type transition Xi Ruoyao
2024-01-27 2:06 ` Lulu Cai
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