* [PATCH v2 1/2] LoongArch: Delete extra instructions when TLS type transition
2024-02-04 3:11 [PATCH v2 0/2] LoongArch: TLS type transition instruction removal and old LE rela Lulu Cai
@ 2024-02-04 3:11 ` Lulu Cai
2024-02-04 3:11 ` [PATCH v2 2/2] LoongArch: Fix some test cases for TLS transition and relax Lulu Cai
1 sibling, 0 replies; 3+ messages in thread
From: Lulu Cai @ 2024-02-04 3:11 UTC (permalink / raw)
To: binutils
Cc: xuchenghua, chenglulu, liuzhensong, mengqinggang, xry111,
i.swmail, maskray, luweining, wanglei, hejinyang, Lulu Cai
This modification mainly changes the timing of type transition,
adds relaxation to the old LE instruction sequence, and fixes
bugs in extreme code models.
We strictly distinguish between type transition and relaxation.
Type transition is from one type to another, while relaxation
is the removal of instructions under the same TLS type. Detailed
instructions are as follows:
1. For type transition, only the normal code model of DESC/IE
does type transition, and each relocation is accompanied by a
RELAX relocation. Neither abs nor extreme will do type transition,
and no RELAX relocation will be generated.
The extra instructions when DESC transitions to other TLS types
will be deleted during the type transition.
2. Implemented relaxation for the old LE instruction sequence.
The first two instructions of LE's 32-bit and 64-bit models
use the same relocations and cannot be distinguished based on
relocations. Therefore, for LE's instruction sequence, any code
model will try to relax.
3. Some function names have been adjusted to facilitate understanding,
parameters have been adjusted, and unused macros have been deleted.
---
bfd/elfnn-loongarch.c | 420 +++++++++++++++++++++++---------------
gas/config/tc-loongarch.c | 31 ++-
2 files changed, 279 insertions(+), 172 deletions(-)
diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c
index 1895699af06..12ca68a361c 100644
--- a/bfd/elfnn-loongarch.c
+++ b/bfd/elfnn-loongarch.c
@@ -145,16 +145,20 @@ struct loongarch_elf_link_hash_table
#define elf_backend_rela_normal 1
#define elf_backend_default_execstack 0
-#define IS_LOONGARCH_TLS_DESC_RELOC(R_TYPE) \
- ((R_TYPE) == R_LARCH_TLS_DESC_PC_HI20 \
- || (R_TYPE) == R_LARCH_TLS_DESC_PC_LO12 \
- || (R_TYPE) == R_LARCH_TLS_DESC_LD \
- || (R_TYPE) == R_LARCH_TLS_DESC_CALL)
-
-#define IS_LOONGARCH_TLS_IE_RELOC(R_TYPE) \
- ((R_TYPE) == R_LARCH_TLS_IE_PC_HI20 \
+#define IS_LOONGARCH_TLS_TRANS_RELOC(R_TYPE) \
+ ((R_TYPE) == R_LARCH_TLS_DESC_PC_HI20 \
+ || (R_TYPE) == R_LARCH_TLS_DESC_PC_LO12 \
+ || (R_TYPE) == R_LARCH_TLS_DESC_LD \
+ || (R_TYPE) == R_LARCH_TLS_DESC_CALL \
+ || (R_TYPE) == R_LARCH_TLS_IE_PC_HI20 \
|| (R_TYPE) == R_LARCH_TLS_IE_PC_LO12)
+#define IS_OUTDATED_TLS_LE_RELOC(R_TYPE) \
+ ((R_TYPE) == R_LARCH_TLS_LE_HI20 \
+ || (R_TYPE) == R_LARCH_TLS_LE_LO12 \
+ || (R_TYPE) == R_LARCH_TLS_LE64_LO20 \
+ || (R_TYPE) == R_LARCH_TLS_LE64_HI12)
+
/* Generate a PLT header. */
static bool
@@ -642,15 +646,18 @@ loongarch_reloc_got_type (unsigned int r_type)
/* Return true if tls type transition can be performed. */
static bool
-loongarch_can_relax_tls (struct bfd_link_info *info, unsigned int r_type,
- struct elf_link_hash_entry *h, bfd *input_bfd,
- unsigned long r_symndx)
+loongarch_can_trans_tls (bfd *input_bfd,
+ struct bfd_link_info *info,
+ struct elf_link_hash_entry *h,
+ unsigned int r_symndx,
+ unsigned int r_type)
{
char symbol_tls_type;
unsigned int reloc_got_type;
- if (! (IS_LOONGARCH_TLS_DESC_RELOC (r_type)
- || IS_LOONGARCH_TLS_IE_RELOC (r_type)))
+ /* Only TLS DESC/IE in normal code mode will perform type
+ transition. */
+ if (! IS_LOONGARCH_TLS_TRANS_RELOC (r_type))
return false;
symbol_tls_type = _bfd_loongarch_elf_tls_type (input_bfd, h, r_symndx);
@@ -707,11 +714,13 @@ loongarch_tls_transition_without_check (struct bfd_link_info *info,
}
static unsigned int
-loongarch_tls_transition (struct bfd_link_info *info, unsigned int r_type,
- struct elf_link_hash_entry *h, bfd *input_bfd,
- unsigned long r_symndx)
+loongarch_tls_transition (bfd *input_bfd,
+ struct bfd_link_info *info,
+ struct elf_link_hash_entry *h,
+ unsigned int r_symndx,
+ unsigned int r_type)
{
- if (! loongarch_can_relax_tls (info, r_type, h, input_bfd,r_symndx))
+ if (! loongarch_can_trans_tls (input_bfd, info, h, r_symndx, r_type))
return r_type;
return loongarch_tls_transition_without_check (info, r_type, h);
@@ -818,7 +827,11 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info,
int need_dynreloc = 0;
int only_need_pcrel = 0;
- r_type = loongarch_tls_transition (info, r_type, h, abfd, r_symndx);
+ /* Type transitions are only possible with relocations accompanied
+ by R_LARCH_RELAX. */
+ if (rel + 1 != relocs + sec->reloc_count
+ && ELFNN_R_TYPE (rel[1].r_info) == R_LARCH_RELAX)
+ r_type = loongarch_tls_transition (abfd, info, h, r_symndx, r_type);
switch (r_type)
{
case R_LARCH_GOT_PC_HI20:
@@ -2534,95 +2547,6 @@ loongarch_reloc_is_fatal (struct bfd_link_info *info,
relocation += 0x100000000; \
})
-/* Transition instruction sequence to relax instruction sequence. */
-static bool
-loongarch_tls_relax (bfd *abfd, asection *sec, Elf_Internal_Rela *rel,
- int r_type, struct elf_link_hash_entry *h,
- struct bfd_link_info *info)
-{
- bool local_exec = bfd_link_executable (info)
- && SYMBOL_REFERENCES_LOCAL (info, h);
- bfd_byte *contents = elf_section_data (sec)->this_hdr.contents;
- unsigned long insn;
-
- switch (r_type)
- {
- case R_LARCH_TLS_DESC_PC_HI20:
- if (local_exec)
- /* DESC -> LE relaxation:
- pcalalau12i $a0,%desc_pc_hi20(var) =>
- lu12i.w $a0,%le_hi20(var)
- */
- bfd_put (32, abfd, LARCH_LU12I_W | LARCH_RD_A0,
- contents + rel->r_offset);
-
- /* DESC -> IE relaxation:
- pcalalau12i $a0,%desc_pc_hi20(var) =>
- pcalalau12i $a0,%ie_pc_hi20(var)
- */
- return true;
-
- case R_LARCH_TLS_DESC_PC_LO12:
- if (local_exec)
- {
- /* DESC -> LE relaxation:
- addi.d $a0,$a0,%desc_pc_lo12(var) =>
- ori $a0,$a0,le_lo12(var)
- */
- insn = LARCH_ORI | LARCH_RD_RJ_A0;
- bfd_put (32, abfd, LARCH_ORI | LARCH_RD_RJ_A0,
- contents + rel->r_offset);
- }
- else
- {
- /* DESC -> IE relaxation:
- addi.d $a0,$a0,%desc_pc_lo12(var) =>
- ld.d $a0,$a0,%%ie_pc_lo12
- */
- bfd_put (32, abfd, LARCH_LD_D | LARCH_RD_RJ_A0,
- contents + rel->r_offset);
- }
- return true;
-
- case R_LARCH_TLS_DESC_LD:
- case R_LARCH_TLS_DESC_CALL:
- /* DESC -> LE/IE relaxation:
- ld.d $ra,$a0,%desc_ld(var) => NOP
- jirl $ra,$ra,%desc_call(var) => NOP
- */
- bfd_put (32, abfd, LARCH_NOP, contents + rel->r_offset);
- return true;
-
- case R_LARCH_TLS_IE_PC_HI20:
- if (local_exec)
- {
- /* IE -> LE relaxation:
- pcalalau12i $rd,%ie_pc_hi20(var) =>
- lu12i.w $rd,%le_hi20(var)
- */
- insn = bfd_getl32 (contents + rel->r_offset);
- bfd_put (32, abfd, LARCH_LU12I_W | (insn & 0x1f),
- contents + rel->r_offset);
- }
- return true;
-
- case R_LARCH_TLS_IE_PC_LO12:
- if (local_exec)
- {
- /* IE -> LE relaxation:
- ld.d $rd,$rj,%%ie_pc_lo12 =>
- ori $rd,$rj,le_lo12(var)
- */
- insn = bfd_getl32 (contents + rel->r_offset);
- bfd_put (32, abfd, LARCH_ORI | (insn & 0x3ff),
- contents + rel->r_offset);
- }
- return true;
- }
-
- return false;
-}
-
static int
loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
@@ -2657,7 +2581,6 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
const char *name;
bfd_reloc_status_type r = bfd_reloc_ok;
bool is_ie, is_desc, is_undefweak, unresolved_reloc, defined_local;
- unsigned int relaxed_r_type;
bool resolved_local, resolved_dynly, resolved_to_const;
char tls_type;
bfd_vma relocation, off, ie_off, desc_off;
@@ -2789,16 +2712,6 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
BFD_ASSERT (!resolved_local || defined_local);
- relaxed_r_type = loongarch_tls_transition (info, r_type, h, input_bfd, r_symndx);
- if (relaxed_r_type != r_type)
- {
- howto = loongarch_elf_rtype_to_howto (input_bfd, relaxed_r_type);
- BFD_ASSERT (howto != NULL);
-
- if (loongarch_tls_relax (input_bfd, input_section, rel, r_type, h, info))
- r_type = relaxed_r_type;
- }
-
is_desc = false;
is_ie = false;
switch (r_type)
@@ -4117,6 +4030,116 @@ loongarch_relax_delete_bytes (bfd *abfd,
return true;
}
+
+/* Start perform TLS type transition.
+ Currently there are three cases of relocation handled here:
+ DESC -> IE, DEC -> LE and IE -> LE. */
+static bool
+loongarch_tls_perform_trans (bfd *abfd, asection *sec,
+ Elf_Internal_Rela *rel,
+ struct elf_link_hash_entry *h,
+ struct bfd_link_info *info)
+{
+ unsigned long insn;
+ bool local_exec = bfd_link_executable (info)
+ && SYMBOL_REFERENCES_LOCAL (info, h);
+ bfd_byte *contents = elf_section_data (sec)->this_hdr.contents;
+ unsigned long r_type = ELFNN_R_TYPE (rel->r_info);
+ unsigned long r_symndx = ELFNN_R_SYM (rel->r_info);
+
+ switch (r_type)
+ {
+ case R_LARCH_TLS_DESC_PC_HI20:
+ if (local_exec)
+ {
+ /* DESC -> LE relaxation:
+ pcalalau12i $a0,%desc_pc_hi20(var) =>
+ lu12i.w $a0,%le_hi20(var)
+ */
+ bfd_put (32, abfd, LARCH_LU12I_W | LARCH_RD_A0,
+ contents + rel->r_offset);
+ rel->r_info = ELFNN_R_INFO (r_symndx, R_LARCH_TLS_LE_HI20);
+ }
+ else
+ {
+ /* DESC -> IE relaxation:
+ pcalalau12i $a0,%desc_pc_hi20(var) =>
+ pcalalau12i $a0,%ie_pc_hi20(var)
+ */
+ rel->r_info = ELFNN_R_INFO (r_symndx, R_LARCH_TLS_IE_PC_HI20);
+ }
+ return true;
+
+ case R_LARCH_TLS_DESC_PC_LO12:
+ if (local_exec)
+ {
+ /* DESC -> LE relaxation:
+ addi.d $a0,$a0,%desc_pc_lo12(var) =>
+ ori $a0,$a0,le_lo12(var)
+ */
+ insn = LARCH_ORI | LARCH_RD_RJ_A0;
+ bfd_put (32, abfd, LARCH_ORI | LARCH_RD_RJ_A0,
+ contents + rel->r_offset);
+ rel->r_info = ELFNN_R_INFO (r_symndx, R_LARCH_TLS_LE_LO12);
+ }
+ else
+ {
+ /* DESC -> IE relaxation:
+ addi.d $a0,$a0,%desc_pc_lo12(var) =>
+ ld.d $a0,$a0,%ie_pc_lo12(var)
+ */
+ bfd_put (32, abfd, LARCH_LD_D | LARCH_RD_RJ_A0,
+ contents + rel->r_offset);
+ rel->r_info = ELFNN_R_INFO (r_symndx, R_LARCH_TLS_IE_PC_LO12);
+ }
+ return true;
+
+ case R_LARCH_TLS_DESC_LD:
+ case R_LARCH_TLS_DESC_CALL:
+ /* DESC -> LE/IE relaxation:
+ ld.d $ra,$a0,%desc_ld(var) => NOP
+ jirl $ra,$ra,%desc_call(var) => NOP
+ */
+ rel->r_info = ELFNN_R_INFO (0, R_LARCH_NONE);
+ bfd_put (32, abfd, LARCH_NOP, contents + rel->r_offset);
+ /*link with -relax option will delete NOP. */
+ if (!info->disable_target_specific_optimizations)
+ loongarch_relax_delete_bytes (abfd, sec, rel->r_offset, 4, info);
+ return true;
+
+ case R_LARCH_TLS_IE_PC_HI20:
+ if (local_exec)
+ {
+ /* IE -> LE relaxation:
+ pcalalau12i $rd,%ie_pc_hi20(var) =>
+ lu12i.w $rd,%le_hi20(var)
+ */
+ insn = bfd_getl32 (contents + rel->r_offset);
+ bfd_put (32, abfd, LARCH_LU12I_W | (insn & 0x1f),
+ contents + rel->r_offset);
+ rel->r_info = ELFNN_R_INFO (r_symndx, R_LARCH_TLS_LE_HI20);
+ }
+ return true;
+
+ case R_LARCH_TLS_IE_PC_LO12:
+ if (local_exec)
+ {
+ /* IE -> LE relaxation:
+ ld.d $rd,$rj,%%ie_pc_lo12(var) =>
+ ori $rd,$rj,le_lo12(var)
+ */
+ insn = bfd_getl32 (contents + rel->r_offset);
+ bfd_put (32, abfd, LARCH_ORI | (insn & 0x3ff),
+ contents + rel->r_offset);
+ rel->r_info = ELFNN_R_INFO (r_symndx, R_LARCH_TLS_LE_LO12);
+ }
+ return true;
+ }
+
+ return false;
+}
+
+
/* Relax tls le, mainly relax the process of getting TLS le symbolic addresses.
there are three situations in which an assembly instruction sequence needs to
be relaxed:
@@ -4153,6 +4176,21 @@ loongarch_relax_delete_bytes (bfd *abfd,
lu12i.w $rd,%le_hi20_r (sym) ==> (instruction deleted)
add.{w/d} $rd,$rd,$tp,%le_add_r (sym) ==> (instruction deleted)
addi.{w/d} $rs,$rd,%le_lo12_r (sym) ==> addi.{w/d} $rs,$tp,%le_lo12_r (sym)
+
+
+ For relocation of all old LE instruction sequences, whether it is
+ a normal code model or an extreme code model, relaxation will be
+ performed when the relaxation conditions are met.
+
+ nomal code model:
+ lu12i.w $rd,%le_hi20(sym) => (deleted)
+ ori $rd,$rd,le_lo12(sym) => ori $rd,$zero,le_lo12(sym)
+
+ extreme code model:
+ lu12i.w $rd,%le_hi20(sym) => (deleted)
+ ori $rd,$rd,%le_lo12(sym) => ori $rd,$zero,le_lo12(sym)
+ lu32i.d $rd,%le64_lo20(sym) => (deleted)
+ lu52i.d $rd,$rd,%le64_hi12(sym) => (deleted)
*/
static bool
loongarch_relax_tls_le (bfd *abfd, asection *sec,
@@ -4164,31 +4202,56 @@ loongarch_relax_tls_le (bfd *abfd, asection *sec,
uint32_t insn = bfd_get (32, abfd, contents + rel->r_offset);
static uint32_t insn_rj,insn_rd;
symval = symval - elf_hash_table (link_info)->tls_sec->vma;
- /* Whether the symbol offset is in the interval (offset < 0x800). */
- if (ELFNN_R_TYPE ((rel + 1)->r_info) == R_LARCH_RELAX && (symval < 0x800))
+ /* The old LE instruction sequence can be relaxed when the symbol offset
+ is smaller than the 12-bit range. */
+ if (ELFNN_R_TYPE ((rel + 1)->r_info) == R_LARCH_RELAX && (symval <= 0xfff))
{
switch (ELFNN_R_TYPE (rel->r_info))
{
- case R_LARCH_TLS_LE_HI20_R:
- case R_LARCH_TLS_LE_ADD_R:
- /* delete insn. */
- rel->r_info = ELFNN_R_INFO (0, R_LARCH_NONE);
- loongarch_relax_delete_bytes (abfd, sec, rel->r_offset, 4, link_info);
- break;
- case R_LARCH_TLS_LE_LO12_R:
- /* Change rj to $tp. */
- insn_rj = 0x2 << 5;
- /* Get rd register. */
- insn_rd = insn & 0x1f;
- /* Write symbol offset. */
- symval <<= 10;
- /* Writes the modified instruction. */
- insn = insn & 0xffc00000;
- insn = insn | symval | insn_rj | insn_rd;
- bfd_put (32, abfd, insn, contents + rel->r_offset);
- break;
- default:
- break;
+ /*if offset < 0x800, then perform the new le instruction
+ sequence relax. */
+ case R_LARCH_TLS_LE_HI20_R:
+ case R_LARCH_TLS_LE_ADD_R:
+ /* delete insn. */
+ if (symval < 0x800)
+ {
+ rel->r_info = ELFNN_R_INFO (0, R_LARCH_NONE);
+ loongarch_relax_delete_bytes (abfd, sec, rel->r_offset,
+ 4, link_info);
+ }
+ break;
+
+ case R_LARCH_TLS_LE_LO12_R:
+ if (symval < 0x800)
+ {
+ /* Change rj to $tp. */
+ insn_rj = 0x2 << 5;
+ /* Get rd register. */
+ insn_rd = insn & 0x1f;
+ /* Write symbol offset. */
+ symval <<= 10;
+ /* Writes the modified instruction. */
+ insn = insn & 0xffc00000;
+ insn = insn | symval | insn_rj | insn_rd;
+ bfd_put (32, abfd, insn, contents + rel->r_offset);
+ }
+ break;
+
+ case R_LARCH_TLS_LE_HI20:
+ case R_LARCH_TLS_LE64_LO20:
+ case R_LARCH_TLS_LE64_HI12:
+ rel->r_info = ELFNN_R_INFO (0, R_LARCH_NONE);
+ loongarch_relax_delete_bytes (abfd, sec, rel->r_offset,
+ 4, link_info);
+ break;
+
+ case R_LARCH_TLS_LE_LO12:
+ bfd_put (32, abfd, LARCH_ORI | (insn & 0x1f),
+ contents + rel->r_offset);
+ break;
+
+ default:
+ break;
}
}
return true;
@@ -4539,7 +4602,7 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec,
R_LARCH_CALL36: symval is the symbol address for local symbols,
or the PLT entry address of the symbol. (Todo)
R_LARCHL_TLS_LD/GD/DESC_PC_HI20: symval is the GOT entry address
- of the symbol. */
+ of the symbol if transition is not possible. */
if (r_symndx < symtab_hdr->sh_info)
{
Elf_Internal_Sym *sym = (Elf_Internal_Sym *)symtab_hdr->contents
@@ -4547,22 +4610,24 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec,
if (ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC)
continue;
+ /* Only TLS instruction sequences that are accompanied by
+ R_LARCH_RELAX and cannot perform type transition can be
+ relaxed. */
if (R_LARCH_TLS_LD_PC_HI20 == r_type
|| R_LARCH_TLS_GD_PC_HI20 == r_type
- || R_LARCH_TLS_DESC_PC_HI20 == r_type)
+ || (R_LARCH_TLS_DESC_PC_HI20 == r_type
+ && (i + 1 != sec->reloc_count)
+ && ELFNN_R_TYPE (rel[1].r_info) == R_LARCH_RELAX
+ && ! loongarch_can_trans_tls (abfd, info, h,
+ r_symndx, r_type)))
{
- if (loongarch_can_relax_tls (info, r_type, h, abfd, r_symndx))
- continue;
- else
- {
- sym_sec = htab->elf.sgot;
- symval = elf_local_got_offsets (abfd)[r_symndx];
- char tls_type = _bfd_loongarch_elf_tls_type (abfd, h,
- r_symndx);
- if (R_LARCH_TLS_DESC_PC_HI20 == r_type
- && GOT_TLS_GD_BOTH_P (tls_type))
- symval += 2 * GOT_ENTRY_SIZE;
- }
+ sym_sec = htab->elf.sgot;
+ symval = elf_local_got_offsets (abfd)[r_symndx];
+ char tls_type = _bfd_loongarch_elf_tls_type (abfd, h,
+ r_symndx);
+ if (R_LARCH_TLS_DESC_PC_HI20 == r_type
+ && GOT_TLS_GD_BOTH_P (tls_type))
+ symval += 2 * GOT_ENTRY_SIZE;
}
else if (sym->st_shndx == SHN_UNDEF || R_LARCH_ALIGN == r_type)
{
@@ -4593,20 +4658,19 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec,
shared object. */
if (R_LARCH_TLS_LD_PC_HI20 == r_type
|| R_LARCH_TLS_GD_PC_HI20 == r_type
- || R_LARCH_TLS_DESC_PC_HI20 == r_type)
+ || (R_LARCH_TLS_DESC_PC_HI20 == r_type
+ && (i + 1 != sec->reloc_count)
+ && ELFNN_R_TYPE (rel[1].r_info) == R_LARCH_RELAX
+ && !loongarch_can_trans_tls (abfd, info, h,
+ r_symndx, r_type)))
{
- if (loongarch_can_relax_tls (info, r_type, h, abfd, r_symndx))
- continue;
- else
- {
- sym_sec = htab->elf.sgot;
- symval = h->got.offset;
- char tls_type = _bfd_loongarch_elf_tls_type (abfd, h,
- r_symndx);
- if (R_LARCH_TLS_DESC_PC_HI20 == r_type
- && GOT_TLS_GD_BOTH_P (tls_type))
- symval += 2 * GOT_ENTRY_SIZE;
- }
+ sym_sec = htab->elf.sgot;
+ symval = h->got.offset;
+ char tls_type = _bfd_loongarch_elf_tls_type (abfd, h,
+ r_symndx);
+ if (R_LARCH_TLS_DESC_PC_HI20 == r_type
+ && GOT_TLS_GD_BOTH_P (tls_type))
+ symval += 2 * GOT_ENTRY_SIZE;
}
else if ((h->root.type == bfd_link_hash_defined
|| h->root.type == bfd_link_hash_defweak)
@@ -4651,6 +4715,24 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec,
symval += sec_addr (sym_sec);
+ /* If the conditions for tls type transition are met, type
+ transition is performed instead of relax.
+ During the transition from DESC->IE/LE, there are 2 situations
+ depending on the different configurations of the relax/norelax
+ option.
+ If the -relax option is used, the extra nops will be removed,
+ and this transition is performed on pass 0.
+ If the --no-relax option is used, nop will be retained, and
+ this transition is performed on pass 1. */
+ if (IS_LOONGARCH_TLS_TRANS_RELOC (r_type)
+ && (i + 1 != sec->reloc_count)
+ && ELFNN_R_TYPE (rel[1].r_info) == R_LARCH_RELAX
+ && loongarch_can_trans_tls (abfd, info, h, r_symndx, r_type))
+ {
+ loongarch_tls_perform_trans (abfd, sec, rel, h, info);
+ r_type = ELFNN_R_TYPE (rel->r_info);
+ }
+
switch (r_type)
{
case R_LARCH_ALIGN:
@@ -4669,6 +4751,10 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec,
case R_LARCH_TLS_LE_HI20_R:
case R_LARCH_TLS_LE_LO12_R:
case R_LARCH_TLS_LE_ADD_R:
+ case R_LARCH_TLS_LE_HI20:
+ case R_LARCH_TLS_LE_LO12:
+ case R_LARCH_TLS_LE64_LO20:
+ case R_LARCH_TLS_LE64_HI12:
if (0 == info->relax_pass && (i + 2) <= sec->reloc_count)
loongarch_relax_tls_le (abfd, sec, rel, info, symval);
break;
diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c
index e0aff36bbbb..71cdc2349f6 100644
--- a/gas/config/tc-loongarch.c
+++ b/gas/config/tc-loongarch.c
@@ -716,7 +716,11 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2,
if (LARCH_opts.relax
&& (BFD_RELOC_LARCH_TLS_LE_HI20_R == reloc_type
- || BFD_RELOC_LARCH_TLS_LE_LO12_R == reloc_type))
+ || BFD_RELOC_LARCH_TLS_LE_LO12_R == reloc_type
+ || BFD_RELOC_LARCH_TLS_LE_HI20 == reloc_type
+ || BFD_RELOC_LARCH_TLS_LE_LO12 == reloc_type
+ || BFD_RELOC_LARCH_TLS_LE64_LO20 == reloc_type
+ || BFD_RELOC_LARCH_TLS_LE64_HI12 == reloc_type))
{
ip->reloc_info[ip->reloc_num].type = BFD_RELOC_LARCH_RELAX;
ip->reloc_info[ip->reloc_num].value = const_0;
@@ -724,8 +728,12 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2,
}
/* Only one register macros (used in normal code model)
- emit R_LARCH_RELAX. */
+ emit R_LARCH_RELAX.
+ LARCH_opts.ase_labs and LARCH_opts.ase_gabs are used
+ to generate the code model of absolute addresses, and
+ we do not relax this code model. */
if (LARCH_opts.relax && (ip->expand_from_macro & 1)
+ && !(LARCH_opts.ase_labs | LARCH_opts.ase_gabs)
&& (BFD_RELOC_LARCH_PCALA_HI20 == reloc_type
|| BFD_RELOC_LARCH_PCALA_LO12 == reloc_type
|| BFD_RELOC_LARCH_GOT_PC_HI20 == reloc_type
@@ -733,7 +741,11 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2,
|| BFD_RELOC_LARCH_TLS_LD_PC_HI20 == reloc_type
|| BFD_RELOC_LARCH_TLS_GD_PC_HI20 == reloc_type
|| BFD_RELOC_LARCH_TLS_DESC_PC_HI20 == reloc_type
- || BFD_RELOC_LARCH_TLS_DESC_PC_LO12 == reloc_type))
+ || BFD_RELOC_LARCH_TLS_DESC_PC_LO12 == reloc_type
+ || BFD_RELOC_LARCH_TLS_DESC_LD == reloc_type
+ || BFD_RELOC_LARCH_TLS_DESC_CALL == reloc_type
+ || BFD_RELOC_LARCH_TLS_IE_PC_HI20 == reloc_type
+ || BFD_RELOC_LARCH_TLS_IE_PC_LO12 == reloc_type))
{
ip->reloc_info[ip->reloc_num].type = BFD_RELOC_LARCH_RELAX;
ip->reloc_info[ip->reloc_num].value = const_0;
@@ -1080,7 +1092,11 @@ append_fixp_and_insn (struct loongarch_cl_insn *ip)
if (symbol_get_frag (to) == symbol_get_frag (from)))
For macro instructions, only the first instruction expanded from macro
- need to start a new frag. */
+ need to start a new frag.
+ Since the relocations of the normal code model and the extreme code model
+ of the old LE instruction sequence are the same, it is impossible to
+ distinguish which code model it is based on relocation alone, so the
+ extreme code model has to be relaxed. */
if (LARCH_opts.relax
&& (BFD_RELOC_LARCH_PCALA_HI20 == reloc_info[0].type
|| BFD_RELOC_LARCH_GOT_PC_HI20 == reloc_info[0].type
@@ -1088,7 +1104,12 @@ append_fixp_and_insn (struct loongarch_cl_insn *ip)
|| BFD_RELOC_LARCH_TLS_LE_ADD_R == reloc_info[0].type
|| BFD_RELOC_LARCH_TLS_LD_PC_HI20 == reloc_info[0].type
|| BFD_RELOC_LARCH_TLS_GD_PC_HI20 == reloc_info[0].type
- || BFD_RELOC_LARCH_TLS_DESC_PC_HI20 == reloc_info[0].type))
+ || BFD_RELOC_LARCH_TLS_DESC_PC_HI20 == reloc_info[0].type
+ || BFD_RELOC_LARCH_TLS_IE_PC_HI20 == reloc_info[0].type
+ || BFD_RELOC_LARCH_TLS_LE_HI20 == reloc_info[0].type
+ || BFD_RELOC_LARCH_TLS_LE_LO12 == reloc_info[0].type
+ || BFD_RELOC_LARCH_TLS_LE64_LO20 == reloc_info[0].type
+ || BFD_RELOC_LARCH_TLS_LE64_HI12 == reloc_info[0].type))
{
frag_wane (frag_now);
frag_new (0);
--
2.36.0
^ permalink raw reply [flat|nested] 3+ messages in thread* [PATCH v2 2/2] LoongArch: Fix some test cases for TLS transition and relax
2024-02-04 3:11 [PATCH v2 0/2] LoongArch: TLS type transition instruction removal and old LE rela Lulu Cai
2024-02-04 3:11 ` [PATCH v2 1/2] LoongArch: Delete extra instructions when TLS type transition Lulu Cai
@ 2024-02-04 3:11 ` Lulu Cai
1 sibling, 0 replies; 3+ messages in thread
From: Lulu Cai @ 2024-02-04 3:11 UTC (permalink / raw)
To: binutils
Cc: xuchenghua, chenglulu, liuzhensong, mengqinggang, xry111,
i.swmail, maskray, luweining, wanglei, hejinyang, Lulu Cai
---
gas/testsuite/gas/loongarch/macro_op.d | 4 +
gas/testsuite/gas/loongarch/macro_op_32.d | 4 +
.../gas/loongarch/macro_op_extreme_abs.d | 4 +-
.../gas/loongarch/macro_op_extreme_pc.d | 2 +
.../relax-cfi-fde-DW_CFA_advance_loc.d | 16 ++--
.../relax-cfi-fde-DW_CFA_advance_loc.s | 8 ++
gas/testsuite/gas/loongarch/reloc.d | 8 ++
gas/testsuite/gas/loongarch/tlsdesc_32.d | 2 +
gas/testsuite/gas/loongarch/tlsdesc_64.d | 2 +
ld/testsuite/ld-loongarch-elf/desc-ie.d | 14 ++--
ld/testsuite/ld-loongarch-elf/desc-ie.s | 13 +--
.../ld-loongarch-elf/desc-le-norelax.d | 15 ++++
.../ld-loongarch-elf/desc-le-norelax.s | 11 +++
ld/testsuite/ld-loongarch-elf/desc-le-relax.d | 13 +++
ld/testsuite/ld-loongarch-elf/desc-le-relax.s | 14 ++++
ld/testsuite/ld-loongarch-elf/desc-le.d | 15 ----
ld/testsuite/ld-loongarch-elf/desc-le.s | 14 ----
ld/testsuite/ld-loongarch-elf/ie-le-norelax.d | 13 +++
.../{ie-le.s => ie-le-norelax.s} | 4 +-
ld/testsuite/ld-loongarch-elf/ie-le-relax.d | 13 +++
ld/testsuite/ld-loongarch-elf/ie-le-relax.s | 13 +++
ld/testsuite/ld-loongarch-elf/ie-le.d | 13 ---
.../ld-loongarch-elf/ld-loongarch-elf.exp | 9 +-
ld/testsuite/ld-loongarch-elf/macro_op.d | 4 +
ld/testsuite/ld-loongarch-elf/macro_op_32.d | 4 +
ld/testsuite/ld-loongarch-elf/relax.exp | 6 +-
.../ld-loongarch-elf/tls-le-norelax.d | 18 ++++
.../{tls-le.s => tls-le-norelax.s} | 4 +
ld/testsuite/ld-loongarch-elf/tls-le-relax.d | 13 +++
ld/testsuite/ld-loongarch-elf/tls-le-relax.s | 22 +++++
ld/testsuite/ld-loongarch-elf/tls-le.d | 14 ----
ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d | 84 +++++++++----------
32 files changed, 261 insertions(+), 132 deletions(-)
create mode 100644 ld/testsuite/ld-loongarch-elf/desc-le-norelax.d
create mode 100644 ld/testsuite/ld-loongarch-elf/desc-le-norelax.s
create mode 100644 ld/testsuite/ld-loongarch-elf/desc-le-relax.d
create mode 100644 ld/testsuite/ld-loongarch-elf/desc-le-relax.s
delete mode 100644 ld/testsuite/ld-loongarch-elf/desc-le.d
delete mode 100644 ld/testsuite/ld-loongarch-elf/desc-le.s
create mode 100644 ld/testsuite/ld-loongarch-elf/ie-le-norelax.d
rename ld/testsuite/ld-loongarch-elf/{ie-le.s => ie-le-norelax.s} (63%)
create mode 100644 ld/testsuite/ld-loongarch-elf/ie-le-relax.d
create mode 100644 ld/testsuite/ld-loongarch-elf/ie-le-relax.s
delete mode 100644 ld/testsuite/ld-loongarch-elf/ie-le.d
create mode 100644 ld/testsuite/ld-loongarch-elf/tls-le-norelax.d
rename ld/testsuite/ld-loongarch-elf/{tls-le.s => tls-le-norelax.s} (70%)
create mode 100644 ld/testsuite/ld-loongarch-elf/tls-le-relax.d
create mode 100644 ld/testsuite/ld-loongarch-elf/tls-le-relax.s
delete mode 100644 ld/testsuite/ld-loongarch-elf/tls-le.d
diff --git a/gas/testsuite/gas/loongarch/macro_op.d b/gas/testsuite/gas/loongarch/macro_op.d
index 47f8f45c663..106f619ef05 100644
--- a/gas/testsuite/gas/loongarch/macro_op.d
+++ b/gas/testsuite/gas/loongarch/macro_op.d
@@ -53,12 +53,16 @@ Disassembly of section .text:
44: R_LARCH_RELAX \*ABS\*
48: 14000004 lu12i.w \$a0, 0
48: R_LARCH_TLS_LE_HI20 TLS1
+ 48: R_LARCH_RELAX \*ABS\*
4c: 03800084 ori \$a0, \$a0, 0x0
4c: R_LARCH_TLS_LE_LO12 TLS1
+ 4c: R_LARCH_RELAX \*ABS\*
50: 1a000004 pcalau12i \$a0, 0
50: R_LARCH_TLS_IE_PC_HI20 TLS1
+ 50: R_LARCH_RELAX \*ABS\*
54: 28c00084 ld.d \$a0, \$a0, 0
54: R_LARCH_TLS_IE_PC_LO12 TLS1
+ 54: R_LARCH_RELAX \*ABS\*
58: 1a000004 pcalau12i \$a0, 0
58: R_LARCH_TLS_LD_PC_HI20 TLS1
58: R_LARCH_RELAX \*ABS\*
diff --git a/gas/testsuite/gas/loongarch/macro_op_32.d b/gas/testsuite/gas/loongarch/macro_op_32.d
index a7349aa8dc0..8fd69922c14 100644
--- a/gas/testsuite/gas/loongarch/macro_op_32.d
+++ b/gas/testsuite/gas/loongarch/macro_op_32.d
@@ -49,12 +49,16 @@ Disassembly of section .text:
3c: R_LARCH_RELAX \*ABS\*
40: 14000004 lu12i.w \$a0, 0
40: R_LARCH_TLS_LE_HI20 TLS1
+ 40: R_LARCH_RELAX \*ABS\*
44: 03800084 ori \$a0, \$a0, 0x0
44: R_LARCH_TLS_LE_LO12 TLS1
+ 44: R_LARCH_RELAX \*ABS\*
48: 1a000004 pcalau12i \$a0, 0
48: R_LARCH_TLS_IE_PC_HI20 TLS1
+ 48: R_LARCH_RELAX \*ABS\*
4c: 28800084 ld.w \$a0, \$a0, 0
4c: R_LARCH_TLS_IE_PC_LO12 TLS1
+ 4c: R_LARCH_RELAX \*ABS\*
50: 1a000004 pcalau12i \$a0, 0
50: R_LARCH_TLS_LD_PC_HI20 TLS1
50: R_LARCH_RELAX \*ABS\*
diff --git a/gas/testsuite/gas/loongarch/macro_op_extreme_abs.d b/gas/testsuite/gas/loongarch/macro_op_extreme_abs.d
index 5c823ba0302..8e3a2aa97e9 100644
--- a/gas/testsuite/gas/loongarch/macro_op_extreme_abs.d
+++ b/gas/testsuite/gas/loongarch/macro_op_extreme_abs.d
@@ -28,10 +28,8 @@ Disassembly of section .text:
1c: R_LARCH_ABS64_HI12 .L1
20: 1a000004 pcalau12i \$a0, 0
20: R_LARCH_PCALA_HI20 .L1
- 20: R_LARCH_RELAX \*ABS\*
24: 02c00084 addi.d \$a0, \$a0, 0
24: R_LARCH_PCALA_LO12 .L1
- 24: R_LARCH_RELAX \*ABS\*
28: 14000004 lu12i.w \$a0, 0
28: R_LARCH_GOT_HI20 .L1
2c: 03800084 ori \$a0, \$a0, 0x0
@@ -43,8 +41,10 @@ Disassembly of section .text:
38: 28c00084 ld.d \$a0, \$a0, 0
3c: 14000004 lu12i.w \$a0, 0
3c: R_LARCH_TLS_LE_HI20 TLS1
+ 3c: R_LARCH_RELAX \*ABS\*
40: 03800084 ori \$a0, \$a0, 0x0
40: R_LARCH_TLS_LE_LO12 TLS1
+ 40: R_LARCH_RELAX \*ABS\*
44: 14000004 lu12i.w \$a0, 0
44: R_LARCH_TLS_IE_HI20 TLS1
48: 03800084 ori \$a0, \$a0, 0x0
diff --git a/gas/testsuite/gas/loongarch/macro_op_extreme_pc.d b/gas/testsuite/gas/loongarch/macro_op_extreme_pc.d
index 68fbb338c36..21c5e5a05ed 100644
--- a/gas/testsuite/gas/loongarch/macro_op_extreme_pc.d
+++ b/gas/testsuite/gas/loongarch/macro_op_extreme_pc.d
@@ -46,8 +46,10 @@ Disassembly of section .text:
[ ]+4c:[ ]+380c1484[ ]+ldx.d[ ]+\$a0, \$a0, \$a1
[ ]+50:[ ]+14000004[ ]+lu12i.w[ ]+\$a0, 0
[ ]+50: R_LARCH_TLS_LE_HI20[ ]+TLS1
+[ ]+50: R_LARCH_RELAX[ ]+\*ABS\*
[ ]+54:[ ]+03800084[ ]+ori[ ]+\$a0, \$a0, 0x0
[ ]+54: R_LARCH_TLS_LE_LO12[ ]+TLS1
+[ ]+54: R_LARCH_RELAX[ ]+\*ABS\*
[ ]+58:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0
[ ]+58: R_LARCH_TLS_IE_PC_HI20[ ]+TLS1
[ ]+5c:[ ]+02c00005[ ]+li.d[ ]+\$a1, 0
diff --git a/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.d b/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.d
index 367039e1efa..6b164cfbf61 100644
--- a/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.d
+++ b/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.d
@@ -14,7 +14,7 @@ Disassembly of section .eh_frame:
[ ]+c:[ ]+01017c01[ ]+fadd.d[ ]+\$fa1, \$fa0, \$fs7
[ ]+10:[ ]+0c030d1b[ ]+.word[ ]+[ ]+0x0c030d1b
[ ]+14:[ ]+00000016[ ]+.word[ ]+[ ]+0x00000016
-[ ]+18:[ ]+00000034[ ]+.word[ ]+[ ]+0x00000034
+[ ]+18:[ ]+0000003c[ ]+.word[ ]+[ ]+0x0000003c
[ ]+1c:[ ]+0000001c[ ]+.word[ ]+[ ]+0x0000001c
[ ]+...
[ ]+20: R_LARCH_32_PCREL[ ]+L0\^A
@@ -26,7 +26,7 @@ Disassembly of section .eh_frame:
[ ]+2c:[ ]+d6400016[ ]+.word[ ]+[ ]+0xd6400016
[ ]+2e: R_LARCH_ADD6[ ]+L0\^A
[ ]+2e: R_LARCH_SUB6[ ]+L0\^A
-[ ]+30:[ ]+4000160c[ ]+beqz[ ]+\$t4, 3145748[ ]+# 300044 <L0\^A\+0x30000c>
+[ ]+30:[ ]+4000160c[ ]+beqz[ ]+\$t4, 3145748[ ]+# 300044 <L0\^A\+0x2ffffc>
[ ]+33: R_LARCH_ADD6[ ]+L0\^A
[ ]+33: R_LARCH_SUB6[ ]+L0\^A
[ ]+34:[ ]+00160cd6[ ]+orn[ ]+\$fp, \$a2, \$sp
@@ -39,8 +39,14 @@ Disassembly of section .eh_frame:
[ ]+40:[ ]+d6400016[ ]+.word[ ]+[ ]+0xd6400016
[ ]+42: R_LARCH_ADD6[ ]+L0\^A
[ ]+42: R_LARCH_SUB6[ ]+L0\^A
-[ ]+44:[ ]+4000160c[ ]+beqz[ ]+\$t4, 3145748[ ]+# 300058 <L0\^A\+0x300020>
+[ ]+44:[ ]+4000160c[ ]+beqz[ ]+\$t4, 3145748[ ]+# 300058 <L0\^A\+0x300010>
[ ]+47: R_LARCH_ADD6[ ]+L0\^A
[ ]+47: R_LARCH_SUB6[ ]+L0\^A
-[ ]+48:[ ]+000000d6[ ]+.word[ ]+[ ]+0x000000d6
-[ ]+4c:[ ]+00000000[ ]+.word[ ]+[ ]+0x00000000
+[ ]+48:[ ]+00160cd6[ ]+orn[ ]+\$fp, \$a2, \$sp
+[ ]+4c:[ ]+160cd640[ ]+lu32i.d[ ]+\$zero, 26290
+[ ]+4c: R_LARCH_ADD6[ ]+L0\^A
+[ ]+4c: R_LARCH_SUB6[ ]+L0\^A
+[ ]+50:[ ]+00d64000[ ]+bstrpick.d[ ]+\$zero, \$zero, 0x16, 0x10
+[ ]+51: R_LARCH_ADD6[ ]+L0\^A
+[ ]+51: R_LARCH_SUB6[ ]+L0\^A
+[ ]+54:[ ]+00000000[ ]+.word[ ]+[ ]+0x00000000
diff --git a/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.s b/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.s
index 6e4c9b8bb6e..2c67587b722 100644
--- a/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.s
+++ b/gas/testsuite/gas/loongarch/relax-cfi-fde-DW_CFA_advance_loc.s
@@ -30,4 +30,12 @@ pcalau12i $t0, %le_hi20_r(a)
add.d $t0, $tp, $t0, %le_add_r(a)
.cfi_restore 22
+.cfi_def_cfa 22, 0
+la.tls.ie $t0, a
+.cfi_restore 22
+
+.cfi_def_cfa 22, 0
+la.tls.le $t0, a
+.cfi_restore 22
+
.cfi_endproc
diff --git a/gas/testsuite/gas/loongarch/reloc.d b/gas/testsuite/gas/loongarch/reloc.d
index fa249c58fd5..6a8f0e1f5d9 100644
--- a/gas/testsuite/gas/loongarch/reloc.d
+++ b/gas/testsuite/gas/loongarch/reloc.d
@@ -81,12 +81,16 @@ Disassembly of section .text:
[ ]+8c:[ ]+R_LARCH_GOT64_HI12[ ]+.L1
[ ]+90:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0
[ ]+90:[ ]+R_LARCH_TLS_LE_HI20[ ]+TLSL1
+[ ]+90:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+94:[ ]+03800085[ ]+ori[ ]+\$a1,[ ]+\$a0,[ ]+0x0
[ ]+94:[ ]+R_LARCH_TLS_LE_LO12[ ]+TLSL1
+[ ]+94:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+98:[ ]+16000004[ ]+lu32i.d[ ]+\$a0,[ ]+0
[ ]+98:[ ]+R_LARCH_TLS_LE64_LO20[ ]+TLSL1
+[ ]+98:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+9c:[ ]+03000085[ ]+lu52i.d[ ]+\$a1,[ ]+\$a0,[ ]+0
[ ]+9c:[ ]+R_LARCH_TLS_LE64_HI12[ ]+TLSL1
+[ ]+9c:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+a0:[ ]+58000085[ ]+beq[ ]+\$a0,[ ]+\$a1,[ ]+0[ ]+#[ ]+0xa0
[ ]+a0:[ ]+R_LARCH_B16[ ]+.L1\+0x8
[ ]+a4:[ ]+5c000085[ ]+bne[ ]+\$a0,[ ]+\$a1,[ ]+0[ ]+#[ ]+0xa4
@@ -159,12 +163,16 @@ Disassembly of section .text:
[ ]+128:[ ]+R_LARCH_GOT64_HI12[ ]+.L1\+0x8
[ ]+12c:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0
[ ]+12c:[ ]+R_LARCH_TLS_LE_HI20[ ]+TLSL1\+0x8
+[ ]+12c:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+130:[ ]+03800085[ ]+ori[ ]+\$a1,[ ]+\$a0,[ ]+0x0
[ ]+130:[ ]+R_LARCH_TLS_LE_LO12[ ]+TLSL1\+0x8
+[ ]+130:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+134:[ ]+16000004[ ]+lu32i.d[ ]+\$a0,[ ]+0
[ ]+134:[ ]+R_LARCH_TLS_LE64_LO20[ ]+TLSL1\+0x8
+[ ]+134:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+138:[ ]+03000085[ ]+lu52i.d[ ]+\$a1,[ ]+\$a0,[ ]+0
[ ]+138:[ ]+R_LARCH_TLS_LE64_HI12[ ]+TLSL1\+0x8
+[ ]+138:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+13c:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0
[ ]+13c:[ ]+R_LARCH_TLS_LE_HI20_R[ ]+TLSL1
[ ]+13c:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
diff --git a/gas/testsuite/gas/loongarch/tlsdesc_32.d b/gas/testsuite/gas/loongarch/tlsdesc_32.d
index eddcc5ed0e8..6c9558d7454 100644
--- a/gas/testsuite/gas/loongarch/tlsdesc_32.d
+++ b/gas/testsuite/gas/loongarch/tlsdesc_32.d
@@ -23,5 +23,7 @@ Disassembly of section .text:
14: R_LARCH_RELAX \*ABS\*
18: 28800081 ld.w \$ra, \$a0, 0
18: R_LARCH_TLS_DESC_LD var
+ 18: R_LARCH_RELAX \*ABS\*
1c: 4c000021 jirl \$ra, \$ra, 0
1c: R_LARCH_TLS_DESC_CALL var
+ 1c: R_LARCH_RELAX \*ABS\*
diff --git a/gas/testsuite/gas/loongarch/tlsdesc_64.d b/gas/testsuite/gas/loongarch/tlsdesc_64.d
index 2a2829c9b44..8fc9e883a4a 100644
--- a/gas/testsuite/gas/loongarch/tlsdesc_64.d
+++ b/gas/testsuite/gas/loongarch/tlsdesc_64.d
@@ -24,5 +24,7 @@ Disassembly of section .text:
14: R_LARCH_RELAX \*ABS\*
18: 28c00081 ld.d \$ra, \$a0, 0
18: R_LARCH_TLS_DESC_LD var
+ 18: R_LARCH_RELAX \*ABS\*
1c: 4c000021 jirl \$ra, \$ra, 0
1c: R_LARCH_TLS_DESC_CALL var
+ 1c: R_LARCH_RELAX \*ABS\*
diff --git a/ld/testsuite/ld-loongarch-elf/desc-ie.d b/ld/testsuite/ld-loongarch-elf/desc-ie.d
index 32e350507db..e1f49e2d556 100644
--- a/ld/testsuite/ld-loongarch-elf/desc-ie.d
+++ b/ld/testsuite/ld-loongarch-elf/desc-ie.d
@@ -1,5 +1,5 @@
#as:
-#ld: -shared -z norelro -e 0x0 --hash-style=both
+#ld: -shared -z norelro --hash-style=both
#objdump: -dr
#skip: loongarch32-*-*
@@ -7,10 +7,8 @@
Disassembly of section .text:
-0+230 <fn1>:
- 230: 1a000084 pcalau12i \$a0, 4
- 234: 28cd6084 ld.d \$a0, \$a0, 856
- 238: 03400000 nop.*
- 23c: 03400000 nop.*
- 240: 1a000084 pcalau12i \$a0, 4
- 244: 28cd6081 ld.d \$ra, \$a0, 856
+[0-9a-f]+ <fn1>:
+ +[0-9a-f]+: 1a000084 pcalau12i \$a0, .*
+ +[0-9a-f]+: 28cca084 ld.d \$a0, \$a0, .*
+ +[0-9a-f]+: 1a000084 pcalau12i \$a0, .*
+ +[0-9a-f]+: 28cca084 ld.d \$a0, \$a0, .*
diff --git a/ld/testsuite/ld-loongarch-elf/desc-ie.s b/ld/testsuite/ld-loongarch-elf/desc-ie.s
index 7f5772bcf23..441080b64b3 100644
--- a/ld/testsuite/ld-loongarch-elf/desc-ie.s
+++ b/ld/testsuite/ld-loongarch-elf/desc-ie.s
@@ -1,6 +1,6 @@
- .global v1
+ .global var
.section .tdata,"awT",@progbits
-v1:
+var:
.word 1
.text
.global fn1
@@ -9,10 +9,5 @@ fn1:
# Use DESC and IE to access the same symbol,
# DESC will relax to IE.
- pcalau12i $a0,%desc_pc_hi20(var)
- addi.d $a0,$a0,%desc_pc_lo12(var)
- ld.d $ra,$a0,%desc_ld(var)
- jirl $ra,$ra,%desc_call(var)
-
- pcalau12i $a0,%ie_pc_hi20(var)
- ld.d $ra,$a0,%ie_pc_lo12(var)
+ la.tls.ie $a0,var
+ la.tls.desc $a0,var
diff --git a/ld/testsuite/ld-loongarch-elf/desc-le-norelax.d b/ld/testsuite/ld-loongarch-elf/desc-le-norelax.d
new file mode 100644
index 00000000000..5a53245ad7f
--- /dev/null
+++ b/ld/testsuite/ld-loongarch-elf/desc-le-norelax.d
@@ -0,0 +1,15 @@
+#as:
+#ld: -z norelro -e0 --no-relax
+#objdump: -dr
+#skip: loongarch32-*-*
+
+.*: file format .*
+
+
+Disassembly of section .text:
+
+[0-9a-f]+ <fn1>:
+ +[0-9a-f]+: 14000004 lu12i.w \$a0, .*
+ +[0-9a-f]+: 03800084 ori \$a0, \$a0, .*
+ +[0-9a-f]+: 03400000 nop
+ +[0-9a-f]+: 03400000 nop
diff --git a/ld/testsuite/ld-loongarch-elf/desc-le-norelax.s b/ld/testsuite/ld-loongarch-elf/desc-le-norelax.s
new file mode 100644
index 00000000000..c91f15dee5e
--- /dev/null
+++ b/ld/testsuite/ld-loongarch-elf/desc-le-norelax.s
@@ -0,0 +1,11 @@
+ .global var
+ .section .tdata,"awT",@progbits
+var:
+ .word 1
+ .text
+ .global fn1
+ .type fn1,@function
+fn1:
+
+ # DESC will relax to LE.
+ la.tls.desc $a0,var
diff --git a/ld/testsuite/ld-loongarch-elf/desc-le-relax.d b/ld/testsuite/ld-loongarch-elf/desc-le-relax.d
new file mode 100644
index 00000000000..03b5535edf8
--- /dev/null
+++ b/ld/testsuite/ld-loongarch-elf/desc-le-relax.d
@@ -0,0 +1,13 @@
+#as:
+#ld: -z norelro -e0
+#objdump: -dr -M no-aliases
+#skip: loongarch32-*-*
+
+.*: file format .*
+
+
+Disassembly of section .text:
+
+[0-9a-f]+ <fn1>:
+ +[0-9a-f]+: 03800004 ori \$a0, \$zero, 0x0
+ +[0-9a-f]+: 03801004 ori \$a0, \$zero, 0x4
diff --git a/ld/testsuite/ld-loongarch-elf/desc-le-relax.s b/ld/testsuite/ld-loongarch-elf/desc-le-relax.s
new file mode 100644
index 00000000000..d590299dd24
--- /dev/null
+++ b/ld/testsuite/ld-loongarch-elf/desc-le-relax.s
@@ -0,0 +1,14 @@
+ .global var
+ .section .tdata,"awT",@progbits
+var1:
+ .word 1
+var2:
+ .word 1
+ .text
+ .global fn1
+ .type fn1,@function
+fn1:
+
+ # DESC will relax to LE.
+ la.tls.desc $a0,var1
+ la.tls.desc $a0,var2
diff --git a/ld/testsuite/ld-loongarch-elf/desc-le.d b/ld/testsuite/ld-loongarch-elf/desc-le.d
deleted file mode 100644
index b4ca9f82eb3..00000000000
--- a/ld/testsuite/ld-loongarch-elf/desc-le.d
+++ /dev/null
@@ -1,15 +0,0 @@
-#as:
-#ld: -z norelro -e 0x0
-#objdump: -dr
-#skip: loongarch32-*-*
-
-.*: file format .*
-
-
-Disassembly of section .text:
-
-0+1200000e8 <fn1>:
- 1200000e8: 14000004 lu12i.w \$a0, 0
- 1200000ec: 03800084 ori \$a0, \$a0, 0x0
- 1200000f0: 03400000 nop.*
- 1200000f4: 03400000 nop.*
diff --git a/ld/testsuite/ld-loongarch-elf/desc-le.s b/ld/testsuite/ld-loongarch-elf/desc-le.s
deleted file mode 100644
index 9ffaa2d668d..00000000000
--- a/ld/testsuite/ld-loongarch-elf/desc-le.s
+++ /dev/null
@@ -1,14 +0,0 @@
- .global var
- .section .tdata,"awT",@progbits
-var:
- .word 1
- .text
- .global fn1
- .type fn1,@function
-fn1:
-
- # DESC will relax to LE.
- pcalau12i $a0,%desc_pc_hi20(var)
- addi.d $a0,$a0,%desc_pc_lo12(var)
- ld.d $ra,$a0,%desc_ld(var)
- jirl $ra,$ra,%desc_call(var)
diff --git a/ld/testsuite/ld-loongarch-elf/ie-le-norelax.d b/ld/testsuite/ld-loongarch-elf/ie-le-norelax.d
new file mode 100644
index 00000000000..81d78ca3245
--- /dev/null
+++ b/ld/testsuite/ld-loongarch-elf/ie-le-norelax.d
@@ -0,0 +1,13 @@
+#as:
+#ld: -z norelro -e0 --no-relax
+#objdump: -dr
+#skip: loongarch32-*-*
+
+.*: file format .*
+
+
+Disassembly of section .text:
+
+[0-9a-f]+ <.*>:
+ +[0-9a-f]+: 14000024 lu12i.w \$a0, .*
+ +[0-9a-f]+: 03800084 ori \$a0, \$a0, .*
diff --git a/ld/testsuite/ld-loongarch-elf/ie-le.s b/ld/testsuite/ld-loongarch-elf/ie-le-norelax.s
similarity index 63%
rename from ld/testsuite/ld-loongarch-elf/ie-le.s
rename to ld/testsuite/ld-loongarch-elf/ie-le-norelax.s
index 795c7ce49cf..db87a2d3a75 100644
--- a/ld/testsuite/ld-loongarch-elf/ie-le.s
+++ b/ld/testsuite/ld-loongarch-elf/ie-le-norelax.s
@@ -1,5 +1,6 @@
.data
.section .tdata,"awT",@progbits
+ .fill 0x1000,1,0
var:
.word 1
.text
@@ -7,5 +8,4 @@ var:
.type gn1,@function
fn1:
# expect IE to relax LE.
- pcalau12i $a0,%ie_pc_hi20(var)
- ld.d $a0,$a0,%ie_pc_lo12(var)
+ la.tls.ie $a0,var
diff --git a/ld/testsuite/ld-loongarch-elf/ie-le-relax.d b/ld/testsuite/ld-loongarch-elf/ie-le-relax.d
new file mode 100644
index 00000000000..03b5535edf8
--- /dev/null
+++ b/ld/testsuite/ld-loongarch-elf/ie-le-relax.d
@@ -0,0 +1,13 @@
+#as:
+#ld: -z norelro -e0
+#objdump: -dr -M no-aliases
+#skip: loongarch32-*-*
+
+.*: file format .*
+
+
+Disassembly of section .text:
+
+[0-9a-f]+ <fn1>:
+ +[0-9a-f]+: 03800004 ori \$a0, \$zero, 0x0
+ +[0-9a-f]+: 03801004 ori \$a0, \$zero, 0x4
diff --git a/ld/testsuite/ld-loongarch-elf/ie-le-relax.s b/ld/testsuite/ld-loongarch-elf/ie-le-relax.s
new file mode 100644
index 00000000000..08bc398745e
--- /dev/null
+++ b/ld/testsuite/ld-loongarch-elf/ie-le-relax.s
@@ -0,0 +1,13 @@
+ .data
+ .section .tdata,"awT",@progbits
+var1:
+ .word 1
+var2:
+ .word 2
+ .text
+ .global fn1
+ .type gn1,@function
+fn1:
+ # expect IE to relax LE
+ la.tls.ie $a0,var1
+ la.tls.ie $a0,var2
diff --git a/ld/testsuite/ld-loongarch-elf/ie-le.d b/ld/testsuite/ld-loongarch-elf/ie-le.d
deleted file mode 100644
index 42694d7f9f0..00000000000
--- a/ld/testsuite/ld-loongarch-elf/ie-le.d
+++ /dev/null
@@ -1,13 +0,0 @@
-#as:
-#ld: -z norelro -e 0x0
-#objdump: -dr
-#skip: loongarch32-*-*
-
-.*: file format .*
-
-
-Disassembly of section .text:
-
-0+1200000e8 <fn1>:
- 1200000e8: 14000004 lu12i.w \$a0, 0
- 1200000ec: 03800084 ori \$a0, \$a0, 0x0
diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp
index 3ae0d9df3b4..797d3e8ff42 100644
--- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp
+++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp
@@ -34,7 +34,8 @@ if [istarget "loongarch64-*-*"] {
run_dump_test "local-ifunc-reloc"
run_dump_test "anno-sym"
run_dump_test "pcala64"
- run_dump_test "tls-le"
+ run_dump_test "tls-le-norelax"
+ run_dump_test "tls-le-relax"
}
if [istarget "loongarch32-*-*"] {
@@ -101,8 +102,10 @@ if [istarget "loongarch64-*-*"] {
if [istarget "loongarch64-*-*"] {
if [check_shared_lib_support] {
run_dump_test "desc-ie"
- run_dump_test "desc-le"
- run_dump_test "ie-le"
+ run_dump_test "desc-le-norelax"
+ run_dump_test "desc-le-relax"
+ run_dump_test "ie-le-norelax"
+ run_dump_test "ie-le-relax"
run_dump_test "tlsdesc-dso"
run_dump_test "desc-norelax"
run_dump_test "desc-relax"
diff --git a/ld/testsuite/ld-loongarch-elf/macro_op.d b/ld/testsuite/ld-loongarch-elf/macro_op.d
index c9493918a93..6a886224a15 100644
--- a/ld/testsuite/ld-loongarch-elf/macro_op.d
+++ b/ld/testsuite/ld-loongarch-elf/macro_op.d
@@ -140,12 +140,16 @@ Disassembly of section .text:
[ ]+f0:[ ]+380c1484[ ]+ldx.d[ ]+\$a0, \$a0, \$a1
[ ]+f4:[ ]+14000004[ ]+lu12i.w[ ]+\$a0, 0
[ ]+f4: R_LARCH_TLS_LE_HI20[ ]+TLS1
+[ ]+f4: R_LARCH_RELAX[ ]+\*ABS\*
[ ]+f8:[ ]+03800084[ ]+ori[ ]+\$a0, \$a0, 0x0
[ ]+f8: R_LARCH_TLS_LE_LO12[ ]+TLS1
+[ ]+f8: R_LARCH_RELAX[ ]+\*ABS\*
[ ]+fc:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0
[ ]+fc: R_LARCH_TLS_IE_PC_HI20[ ]+TLS1
+[ ]+fc: R_LARCH_RELAX[ ]+\*ABS\*
[ ]+100:[ ]+28c00084[ ]+ld.d[ ]+\$a0, \$a0, 0
[ ]+100: R_LARCH_TLS_IE_PC_LO12[ ]+TLS1
+[ ]+100: R_LARCH_RELAX[ ]+\*ABS\*
[ ]+104:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0
[ ]+104: R_LARCH_TLS_IE_PC_HI20[ ]+TLS1
[ ]+108:[ ]+02c00005[ ]+li.d[ ]+\$a1, 0
diff --git a/ld/testsuite/ld-loongarch-elf/macro_op_32.d b/ld/testsuite/ld-loongarch-elf/macro_op_32.d
index a7349aa8dc0..8fd69922c14 100644
--- a/ld/testsuite/ld-loongarch-elf/macro_op_32.d
+++ b/ld/testsuite/ld-loongarch-elf/macro_op_32.d
@@ -49,12 +49,16 @@ Disassembly of section .text:
3c: R_LARCH_RELAX \*ABS\*
40: 14000004 lu12i.w \$a0, 0
40: R_LARCH_TLS_LE_HI20 TLS1
+ 40: R_LARCH_RELAX \*ABS\*
44: 03800084 ori \$a0, \$a0, 0x0
44: R_LARCH_TLS_LE_LO12 TLS1
+ 44: R_LARCH_RELAX \*ABS\*
48: 1a000004 pcalau12i \$a0, 0
48: R_LARCH_TLS_IE_PC_HI20 TLS1
+ 48: R_LARCH_RELAX \*ABS\*
4c: 28800084 ld.w \$a0, \$a0, 0
4c: R_LARCH_TLS_IE_PC_LO12 TLS1
+ 4c: R_LARCH_RELAX \*ABS\*
50: 1a000004 pcalau12i \$a0, 0
50: R_LARCH_TLS_LD_PC_HI20 TLS1
50: R_LARCH_RELAX \*ABS\*
diff --git a/ld/testsuite/ld-loongarch-elf/relax.exp b/ld/testsuite/ld-loongarch-elf/relax.exp
index f421e8af8dd..7d95a9ca41d 100644
--- a/ld/testsuite/ld-loongarch-elf/relax.exp
+++ b/ld/testsuite/ld-loongarch-elf/relax.exp
@@ -137,7 +137,7 @@ if [istarget loongarch64-*-*] {
[list \
[list \
"loongarch old tls le .exe build" \
- "" "" \
+ "--no-relax" "" \
"" \
{old-tls-le.s} \
{} \
@@ -158,7 +158,7 @@ if [istarget loongarch64-*-*] {
[list \
[list \
"loongarch tls le realx compatible .exe build" \
- "" "" \
+ "--no-relax" "" \
"" \
{tls-relax-compatible-check-new.s tls-relax-compatible-check-old.s} \
{} \
@@ -201,7 +201,7 @@ if [istarget loongarch64-*-*] {
[list \
[list \
"loongarch tls le realx bound-check .exe build" \
- "" "" \
+ "--no-relax" "" \
"" \
{relax-bound-check-tls-le.s} \
{} \
diff --git a/ld/testsuite/ld-loongarch-elf/tls-le-norelax.d b/ld/testsuite/ld-loongarch-elf/tls-le-norelax.d
new file mode 100644
index 00000000000..a53d81235d9
--- /dev/null
+++ b/ld/testsuite/ld-loongarch-elf/tls-le-norelax.d
@@ -0,0 +1,18 @@
+#ld: --no-relax
+#objdump: -d -M no-aliases
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+[0-9a-f]+ <_start>:
+ +[0-9a-f]+: 14000004 lu12i.w \$a0, 0
+ +[0-9a-f]+: 03802085 ori \$a1, \$a0, 0x8
+ +[0-9a-f]+: 14000004 lu12i.w \$a0, 0
+ +[0-9a-f]+: 02c02085 addi.d \$a1, \$a0, 8
+ +[0-9a-f]+: 14000004 lu12i.w \$a0, 0
+ +[0-9a-f]+: 03802084 ori \$a0, \$a0, 0x8
+ +[0-9a-f]+: 16000004 lu32i.d \$a0, 0
+ +[0-9a-f]+: 03000084 lu52i.d \$a0, \$a0, 0
+ +[0-9a-f]+: 4c000020 jirl \$zero, \$ra, 0
diff --git a/ld/testsuite/ld-loongarch-elf/tls-le.s b/ld/testsuite/ld-loongarch-elf/tls-le-norelax.s
similarity index 70%
rename from ld/testsuite/ld-loongarch-elf/tls-le.s
rename to ld/testsuite/ld-loongarch-elf/tls-le-norelax.s
index 2e6a9de42ac..80f87920647 100644
--- a/ld/testsuite/ld-loongarch-elf/tls-le.s
+++ b/ld/testsuite/ld-loongarch-elf/tls-le-norelax.s
@@ -15,4 +15,8 @@ _start:
ori $r5,$r4,%le_lo12(a + 0x8)
lu12i.w $r4,%le_hi20_r(a + 0x8)
addi.d $r5,$r4,%le_lo12_r(a + 0x8)
+ lu12i.w $r4,%le_hi20(a + 0x8)
+ ori $r4,$r4,%le_lo12(a + 0x8)
+ lu32i.d $r4,%le64_lo20(a + 0x8)
+ lu52i.d $r4,$r4,%le64_hi12(a + 0x8)
jr $ra
diff --git a/ld/testsuite/ld-loongarch-elf/tls-le-relax.d b/ld/testsuite/ld-loongarch-elf/tls-le-relax.d
new file mode 100644
index 00000000000..19e101c8141
--- /dev/null
+++ b/ld/testsuite/ld-loongarch-elf/tls-le-relax.d
@@ -0,0 +1,13 @@
+#ld:
+#objdump: -d -M no-aliases
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+[0-9a-f]+ <_start>:
+ +[0-9a-f]+: 03802005 ori \$a1, \$zero, 0x8
+ +[0-9a-f]+: 02c02045 addi.d \$a1, \$tp, 8
+ +[0-9a-f]+: 03802004 ori \$a0, \$zero, 0x8
+ +[0-9a-f]+: 4c000020 jirl \$zero, \$ra, 0
diff --git a/ld/testsuite/ld-loongarch-elf/tls-le-relax.s b/ld/testsuite/ld-loongarch-elf/tls-le-relax.s
new file mode 100644
index 00000000000..80f87920647
--- /dev/null
+++ b/ld/testsuite/ld-loongarch-elf/tls-le-relax.s
@@ -0,0 +1,22 @@
+# Support for TLS LE symbols with addend
+ .text
+ .globl a
+ .section .tdata,"awT",@progbits
+ .align 2
+ .type a, @object
+ .size a, 4
+a:
+ .word 123
+
+ .text
+ .global _start
+_start:
+ lu12i.w $r4,%le_hi20(a + 0x8)
+ ori $r5,$r4,%le_lo12(a + 0x8)
+ lu12i.w $r4,%le_hi20_r(a + 0x8)
+ addi.d $r5,$r4,%le_lo12_r(a + 0x8)
+ lu12i.w $r4,%le_hi20(a + 0x8)
+ ori $r4,$r4,%le_lo12(a + 0x8)
+ lu32i.d $r4,%le64_lo20(a + 0x8)
+ lu52i.d $r4,$r4,%le64_hi12(a + 0x8)
+ jr $ra
diff --git a/ld/testsuite/ld-loongarch-elf/tls-le.d b/ld/testsuite/ld-loongarch-elf/tls-le.d
deleted file mode 100644
index cbd6adb8b41..00000000000
--- a/ld/testsuite/ld-loongarch-elf/tls-le.d
+++ /dev/null
@@ -1,14 +0,0 @@
-#ld: --no-relax
-#objdump: -d
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-[ ]*00000001200000e8 <_start>:
-[ ]+1200000e8:[ ]+14000004[ ]+lu12i.w[ ]+\$a0, 0
-[ ]+1200000ec:[ ]+03802085[ ]+ori[ ]+\$a1, \$a0, 0x8
-[ ]+1200000f0:[ ]+14000004[ ]+lu12i.w[ ]+\$a0, 0
-[ ]+1200000f4:[ ]+02c02085[ ]+addi.d[ ]+\$a1, \$a0, 8
-[ ]+1200000f8:[ ]+4c000020[ ]+ret
diff --git a/ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d b/ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d
index 453902d1622..40ffba8c14f 100644
--- a/ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d
+++ b/ld/testsuite/ld-loongarch-elf/tlsdesc-dso.d
@@ -8,49 +8,45 @@
Disassembly of section .text:
-0+418 <fun_gl1>:
- 418: 180214c4 pcaddi \$a0, 4262
- 41c: 1a000084 pcalau12i \$a0, 4
- 420: 28db0084 ld.d \$a0, \$a0, 1728
- 424: 180212a4 pcaddi \$a0, 4245
- 428: 18021304 pcaddi \$a0, 4248
- 42c: 28c00081 ld.d \$ra, \$a0, 0
- 430: 4c000021 jirl \$ra, \$ra, 0
- 434: 1a000084 pcalau12i \$a0, 4
- 438: 28d9c084 ld.d \$a0, \$a0, 1648
- 43c: 03400000 nop.*
- 440: 03400000 nop.*
- 444: 1a000084 pcalau12i \$a0, 4
- 448: 28d9c084 ld.d \$a0, \$a0, 1648
- 44c: 18021264 pcaddi \$a0, 4243
- 450: 18021244 pcaddi \$a0, 4242
- 454: 28c00081 ld.d \$ra, \$a0, 0
- 458: 4c000021 jirl \$ra, \$ra, 0
- 45c: 1a000084 pcalau12i \$a0, 4
- 460: 28daa084 ld.d \$a0, \$a0, 1704
+[0-9a-f]+ <fun_gl1>:
+ +[0-9a-f]+: 18021444 pcaddi \$a0, .*
+ +[0-9a-f]+: 1a000084 pcalau12i \$a0, .*
+ +[0-9a-f]+: 28dac084 ld.d \$a0, \$a0, .*
+ +[0-9a-f]+: 18021224 pcaddi \$a0, .*
+ +[0-9a-f]+: 18021284 pcaddi \$a0, .*
+ +[0-9a-f]+: 28c00081 ld.d \$ra, \$a0, 0
+ +[0-9a-f]+: 4c000021 jirl \$ra, \$ra, 0
+ +[0-9a-f]+: 1a000084 pcalau12i \$a0, .*
+ +[0-9a-f]+: 28d98084 ld.d \$a0, \$a0, .*
+ +[0-9a-f]+: 1a000084 pcalau12i \$a0, .*
+ +[0-9a-f]+: 28d98084 ld.d \$a0, \$a0, .*
+ +[0-9a-f]+: 18021224 pcaddi \$a0, .*
+ +[0-9a-f]+: 18021204 pcaddi \$a0, .*
+ +[0-9a-f]+: 28c00081 ld.d \$ra, \$a0, 0
+ +[0-9a-f]+: 4c000021 jirl \$ra, \$ra, 0
+ +[0-9a-f]+: 1a000084 pcalau12i \$a0, .*
+ +[0-9a-f]+: 28da6084 ld.d \$a0, \$a0, .*
-0+464 <fun_lo>:
- 464: 1a000084 pcalau12i \$a0, 4
- 468: 28d86084 ld.d \$a0, \$a0, 1560
- 46c: 18020ce4 pcaddi \$a0, 4199
- 470: 18020e04 pcaddi \$a0, 4208
- 474: 28c00081 ld.d \$ra, \$a0, 0
- 478: 4c000021 jirl \$ra, \$ra, 0
- 47c: 18020d24 pcaddi \$a0, 4201
- 480: 1a000084 pcalau12i \$a0, 4
- 484: 28d90084 ld.d \$a0, \$a0, 1600
- 488: 03400000 nop.*
- 48c: 03400000 nop.*
- 490: 1a000084 pcalau12i \$a0, 4
- 494: 28d90084 ld.d \$a0, \$a0, 1600
- 498: 18020d84 pcaddi \$a0, 4204
- 49c: 28c00081 ld.d \$ra, \$a0, 0
- 4a0: 4c000021 jirl \$ra, \$ra, 0
- 4a4: 18020d24 pcaddi \$a0, 4201
- 4a8: 1a000084 pcalau12i \$a0, 4
- 4ac: 28d96084 ld.d \$a0, \$a0, 1624
+[0-9a-f]+ <fun_lo>:
+ +[0-9a-f]+: 1a000084 pcalau12i \$a0, .*
+ +[0-9a-f]+: 28d82084 ld.d \$a0, \$a0, .*
+ +[0-9a-f]+: 18020ca4 pcaddi \$a0, .*
+ +[0-9a-f]+: 18020dc4 pcaddi \$a0, .*
+ +[0-9a-f]+: 28c00081 ld.d \$ra, \$a0, 0
+ +[0-9a-f]+: 4c000021 jirl \$ra, \$ra, 0
+ +[0-9a-f]+: 18020ce4 pcaddi \$a0, .*
+ +[0-9a-f]+: 1a000084 pcalau12i \$a0, .*
+ +[0-9a-f]+: 28d8c084 ld.d \$a0, \$a0, .*
+ +[0-9a-f]+: 1a000084 pcalau12i \$a0, .*
+ +[0-9a-f]+: 28d8c084 ld.d \$a0, \$a0, .*
+ +[0-9a-f]+: 18020d84 pcaddi \$a0, .*
+ +[0-9a-f]+: 28c00081 ld.d \$ra, \$a0, 0
+ +[0-9a-f]+: 4c000021 jirl \$ra, \$ra, 0
+ +[0-9a-f]+: 18020d24 pcaddi \$a0, .*
+ +[0-9a-f]+: 1a000084 pcalau12i \$a0, .*
+ +[0-9a-f]+: 28d92084 ld.d \$a0, \$a0, .*
-0+4b0 <fun_external>:
- 4b0: 18020d84 pcaddi \$a0, 4204
- 4b4: 28c00081 ld.d \$ra, \$a0, 0
- 4b8: 4c000021 jirl \$ra, \$ra, 0
+[0-9a-f]+ <fun_external>:
+ +[0-9a-f]+: 18020d84 pcaddi \$a0, .*
+ +[0-9a-f]+: 28c00081 ld.d \$ra, \$a0, 0
+ +[0-9a-f]+: 4c000021 jirl \$ra, \$ra, 0
--
2.36.0
^ permalink raw reply [flat|nested] 3+ messages in thread