[PATCH 0/1] RISC-V: Support CORE-V XCVSIMD extension

[PATCH 0/1] RISC-V: Support CORE-V XCVSIMD extension

[mary.bennett682]

Thank you for reviewing this patch. I do not have merge permissions. If
all looks good, please merge on my behalf.

This patch series presents the comprehensive implementation of the SIMD
extension for CORE-V.

Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
ensure its correctness and compatibility with the existing codebase.
However, your input, reviews, and suggestions are invaluable in making this
extension even more robust.

The CORE-V instructions are described in the specification [1] and work can be
found in the OpenHW group's Github repository [2].

[1] docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html

[2] github.com/openhwgroup/corev-binutils-gdb

Contributors:
  Mary Bennett <mary.bennett@embecosm.com>
  Nandni Jamnadas <nandni.jamnadas@embecosm.com>
  Pietra Ferreira <pietra.ferreira@embecosm.com>
  Charlie Keaney
  Jessica Mills
  Craig Blackmore <craig.blackmore@embecosm.com>
  Simon Cook <simon.cook@embecosm.com>
  Jeremy Bennett <jeremy.bennett@embecosm.com>
  Helene Chelin <helene.chelin@embecosm.com>

RISC-V: Add support for XCVsimd extension in CV32E40Pv2

 bfd/elfxx-riscv.c                             |   5 +
 gas/config/tc-riscv.c                         |  96 +++-
 gas/doc/c-riscv.texi                          |   5 +
 gas/testsuite/gas/riscv/cv-simd-abs-b-fail.d  |   3 +
 gas/testsuite/gas/riscv/cv-simd-abs-b-fail.l  |   3 +
 gas/testsuite/gas/riscv/cv-simd-abs-b-fail.s  |   4 +
 gas/testsuite/gas/riscv/cv-simd-abs-b-pass.d  |  16 +
 gas/testsuite/gas/riscv/cv-simd-abs-b-pass.s  |   8 +
 gas/testsuite/gas/riscv/cv-simd-abs-h-fail.d  |   3 +
 gas/testsuite/gas/riscv/cv-simd-abs-h-fail.l  |   3 +
 gas/testsuite/gas/riscv/cv-simd-abs-h-fail.s  |   4 +
 gas/testsuite/gas/riscv/cv-simd-abs-h-pass.d  |  16 +
 gas/testsuite/gas/riscv/cv-simd-abs-h-pass.s  |   8 +
 gas/testsuite/gas/riscv/cv-simd-add-b-fail.d  |   3 +
 gas/testsuite/gas/riscv/cv-simd-add-b-fail.l  |   3 +
 gas/testsuite/gas/riscv/cv-simd-add-b-fail.s  |   4 +
 gas/testsuite/gas/riscv/cv-simd-add-b-pass.d  |  16 +
 gas/testsuite/gas/riscv/cv-simd-add-b-pass.s  |   8 +
 .../gas/riscv/cv-simd-add-div2-fail.d         |   3 +
 .../gas/riscv/cv-simd-add-div2-fail.l         |   3 +
 .../gas/riscv/cv-simd-add-div2-fail.s         |   4 +
 .../gas/riscv/cv-simd-add-div2-pass.d         |  16 +
 .../gas/riscv/cv-simd-add-div2-pass.s         |   8 +
 .../gas/riscv/cv-simd-add-div4-fail.d         |   3 +
 .../gas/riscv/cv-simd-add-div4-fail.l         |   3 +
 .../gas/riscv/cv-simd-add-div4-fail.s         |   4 +
 .../gas/riscv/cv-simd-add-div4-pass.d         |  16 +
 .../gas/riscv/cv-simd-add-div4-pass.s         |   8 +
 .../gas/riscv/cv-simd-add-div8-fail.d         |   3 +
 .../gas/riscv/cv-simd-add-div8-fail.l         |   3 +
 .../gas/riscv/cv-simd-add-div8-fail.s         |   4 +
 .../gas/riscv/cv-simd-add-div8-pass.d         |  16 +
 .../gas/riscv/cv-simd-add-div8-pass.s         |   8 +
 gas/testsuite/gas/riscv/cv-simd-add-h-fail.d  |   3 +
 gas/testsuite/gas/riscv/cv-simd-add-h-fail.l  |   3 +
 gas/testsuite/gas/riscv/cv-simd-add-h-fail.s  |   4 +
 gas/testsuite/gas/riscv/cv-simd-add-h-pass.d  |  15 +
 gas/testsuite/gas/riscv/cv-simd-add-h-pass.s  |   8 +
 .../gas/riscv/cv-simd-add-sc-b-fail.d         |   3 +
 .../gas/riscv/cv-simd-add-sc-b-fail.l         |   3 +
 .../gas/riscv/cv-simd-add-sc-b-fail.s         |   4 +
 .../gas/riscv/cv-simd-add-sc-b-pass.d         |  16 +
 .../gas/riscv/cv-simd-add-sc-b-pass.s         |   8 +
 .../gas/riscv/cv-simd-add-sc-h-fail.d         |   3 +
 .../gas/riscv/cv-simd-add-sc-h-fail.l         |   3 +
 .../gas/riscv/cv-simd-add-sc-h-fail.s         |   4 +
 .../gas/riscv/cv-simd-add-sc-h-pass.d         |  16 +
 .../gas/riscv/cv-simd-add-sc-h-pass.s         |   8 +
 .../gas/riscv/cv-simd-add-sci-b-fail.d        |   3 +
 .../gas/riscv/cv-simd-add-sci-b-fail.l        |   5 +
 .../gas/riscv/cv-simd-add-sci-b-fail.s        |   7 +
 .../gas/riscv/cv-simd-add-sci-b-pass.d        |  19 +
 .../gas/riscv/cv-simd-add-sci-b-pass.s        |  12 +
 .../gas/riscv/cv-simd-add-sci-h-fail.d        |   3 +
 .../gas/riscv/cv-simd-add-sci-h-fail.l        |   5 +
 .../gas/riscv/cv-simd-add-sci-h-fail.s        |   7 +
 .../gas/riscv/cv-simd-add-sci-h-pass.d        |  19 +
 .../gas/riscv/cv-simd-add-sci-h-pass.s        |  12 +
 gas/testsuite/gas/riscv/cv-simd-and-b-fail.d  |   3 +
 gas/testsuite/gas/riscv/cv-simd-and-b-fail.l  |   3 +
 gas/testsuite/gas/riscv/cv-simd-and-b-fail.s  |   4 +
 gas/testsuite/gas/riscv/cv-simd-and-b-pass.d  |  16 +
 gas/testsuite/gas/riscv/cv-simd-and-b-pass.s  |   8 +
 gas/testsuite/gas/riscv/cv-simd-and-h-fail.d  |   3 +
 gas/testsuite/gas/riscv/cv-simd-and-h-fail.l  |   3 +
 gas/testsuite/gas/riscv/cv-simd-and-h-fail.s  |   4 +
 gas/testsuite/gas/riscv/cv-simd-and-h-pass.d  |  16 +
 gas/testsuite/gas/riscv/cv-simd-and-h-pass.s  |   8 +
 .../gas/riscv/cv-simd-and-sc-b-fail.d         |   3 +
 .../gas/riscv/cv-simd-and-sc-b-fail.l         |   3 +
 .../gas/riscv/cv-simd-and-sc-b-fail.s         |   4 +
 .../gas/riscv/cv-simd-and-sc-b-pass.d         |  16 +
 .../gas/riscv/cv-simd-and-sc-b-pass.s         |   8 +
 .../gas/riscv/cv-simd-and-sc-h-fail.d         |   3 +
 .../gas/riscv/cv-simd-and-sc-h-fail.l         |   3 +
 .../gas/riscv/cv-simd-and-sc-h-fail.s         |   4 +
 .../gas/riscv/cv-simd-and-sc-h-pass.d         |  16 +
 .../gas/riscv/cv-simd-and-sc-h-pass.s         |   8 +
 .../gas/riscv/cv-simd-and-sci-b-fail.d        |   3 +
 .../gas/riscv/cv-simd-and-sci-b-fail.l        |   5 +
 .../gas/riscv/cv-simd-and-sci-b-fail.s        |   7 +
 .../gas/riscv/cv-simd-and-sci-b-pass.d        |  19 +
 .../gas/riscv/cv-simd-and-sci-b-pass.s        |  12 +
 .../gas/riscv/cv-simd-and-sci-h-fail.d        |   3 +
 .../gas/riscv/cv-simd-and-sci-h-fail.l        |   5 +
 .../gas/riscv/cv-simd-and-sci-h-fail.s        |   7 +
 .../gas/riscv/cv-simd-and-sci-h-pass.d        |  19 +
 .../gas/riscv/cv-simd-and-sci-h-pass.s        |  12 +
 gas/testsuite/gas/riscv/cv-simd-avg-b-fail.d  |   3 +
 gas/testsuite/gas/riscv/cv-simd-avg-b-fail.l  |   3 +
 gas/testsuite/gas/riscv/cv-simd-avg-b-fail.s  |   4 +
 gas/testsuite/gas/riscv/cv-simd-avg-b-pass.d  |  16 +
 gas/testsuite/gas/riscv/cv-simd-avg-b-pass.s  |   8 +
 gas/testsuite/gas/riscv/cv-simd-avg-h-fail.d  |   3 +
 gas/testsuite/gas/riscv/cv-simd-avg-h-fail.l  |   3 +
 gas/testsuite/gas/riscv/cv-simd-avg-h-fail.s  |   4 +
 gas/testsuite/gas/riscv/cv-simd-avg-h-pass.d  |  16 +
 gas/testsuite/gas/riscv/cv-simd-avg-h-pass.s  |   8 +
 .../gas/riscv/cv-simd-avg-sc-b-fail.d         |   3 +
 .../gas/riscv/cv-simd-avg-sc-b-fail.l         |   3 +
 .../gas/riscv/cv-simd-avg-sc-b-fail.s         |   4 +
 .../gas/riscv/cv-simd-avg-sc-b-pass.d         |  16 +
 .../gas/riscv/cv-simd-avg-sc-b-pass.s         |   8 +
 .../gas/riscv/cv-simd-avg-sc-h-fail.d         |   3 +
 .../gas/riscv/cv-simd-avg-sc-h-fail.l         |   3 +
 .../gas/riscv/cv-simd-avg-sc-h-fail.s         |   4 +
 .../gas/riscv/cv-simd-avg-sc-h-pass.d         |  16 +
 .../gas/riscv/cv-simd-avg-sc-h-pass.s         |   8 +
 .../gas/riscv/cv-simd-avg-sci-b-fail.d        |   3 +
 .../gas/riscv/cv-simd-avg-sci-b-fail.l        |   5 +
 .../gas/riscv/cv-simd-avg-sci-b-fail.s        |   7 +
 .../gas/riscv/cv-simd-avg-sci-b-pass.d        |  19 +
 .../gas/riscv/cv-simd-avg-sci-b-pass.s        |  12 +
 .../gas/riscv/cv-simd-avg-sci-h-fail.d        |   3 +
 .../gas/riscv/cv-simd-avg-sci-h-fail.l        |   5 +
 .../gas/riscv/cv-simd-avg-sci-h-fail.s        |   7 +
 .../gas/riscv/cv-simd-avg-sci-h-pass.d        |  19 +
 .../gas/riscv/cv-simd-avg-sci-h-pass.s        |  12 +
 gas/testsuite/gas/riscv/cv-simd-avgu-b-fail.d |   3 +
 gas/testsuite/gas/riscv/cv-simd-avgu-b-fail.l |   3 +
 gas/testsuite/gas/riscv/cv-simd-avgu-b-fail.s |   4 +
 gas/testsuite/gas/riscv/cv-simd-avgu-b-pass.d |  16 +
 gas/testsuite/gas/riscv/cv-simd-avgu-b-pass.s |   8 +
 gas/testsuite/gas/riscv/cv-simd-avgu-h-fail.d |   3 +
 gas/testsuite/gas/riscv/cv-simd-avgu-h-fail.l |   3 +
 gas/testsuite/gas/riscv/cv-simd-avgu-h-fail.s |   4 +
 gas/testsuite/gas/riscv/cv-simd-avgu-h-pass.d |  16 +
 gas/testsuite/gas/riscv/cv-simd-avgu-h-pass.s |   8 +
 .../gas/riscv/cv-simd-avgu-sc-b-fail.d        |   3 +
 .../gas/riscv/cv-simd-avgu-sc-b-fail.l        |   3 +
 .../gas/riscv/cv-simd-avgu-sc-b-fail.s        |   4 +
 .../gas/riscv/cv-simd-avgu-sc-b-pass.d        |  16 +
 .../gas/riscv/cv-simd-avgu-sc-b-pass.s        |   8 +
 .../gas/riscv/cv-simd-avgu-sc-h-fail.d        |   3 +
 .../gas/riscv/cv-simd-avgu-sc-h-fail.l        |   3 +
 .../gas/riscv/cv-simd-avgu-sc-h-fail.s        |   4 +
 .../gas/riscv/cv-simd-avgu-sc-h-pass.d        |  16 +
 .../gas/riscv/cv-simd-avgu-sc-h-pass.s        |   8 +
 .../gas/riscv/cv-simd-avgu-sci-b-fail.d       |   3 +
 .../gas/riscv/cv-simd-avgu-sci-b-fail.l       |   5 +
 .../gas/riscv/cv-simd-avgu-sci-b-fail.s       |   7 +
 .../gas/riscv/cv-simd-avgu-sci-b-pass.d       |  18 +
 .../gas/riscv/cv-simd-avgu-sci-b-pass.s       |  11 +
 .../gas/riscv/cv-simd-avgu-sci-h-fail.d       |   3 +
 .../gas/riscv/cv-simd-avgu-sci-h-fail.l       |   5 +
 .../gas/riscv/cv-simd-avgu-sci-h-fail.s       |   7 +
 .../gas/riscv/cv-simd-avgu-sci-h-pass.d       |  18 +
 .../gas/riscv/cv-simd-avgu-sci-h-pass.s       |  11 +
 .../gas/riscv/cv-simd-cmpeq-b-fail.d          |   3 +
 .../gas/riscv/cv-simd-cmpeq-b-fail.l          |   3 +
 .../gas/riscv/cv-simd-cmpeq-b-fail.s          |   4 +
 .../gas/riscv/cv-simd-cmpeq-b-pass.d          |  16 +
 .../gas/riscv/cv-simd-cmpeq-b-pass.s          |   8 +
 .../gas/riscv/cv-simd-cmpeq-h-fail.d          |   3 +
 .../gas/riscv/cv-simd-cmpeq-h-fail.l          |   3 +
 .../gas/riscv/cv-simd-cmpeq-h-fail.s          |   4 +
 .../gas/riscv/cv-simd-cmpeq-h-pass.d          |  16 +
 .../gas/riscv/cv-simd-cmpeq-h-pass.s          |   8 +
 .../gas/riscv/cv-simd-cmpeq-sc-b-fail.d       |   3 +
 .../gas/riscv/cv-simd-cmpeq-sc-b-fail.l       |   3 +
 .../gas/riscv/cv-simd-cmpeq-sc-b-fail.s       |   4 +
 .../gas/riscv/cv-simd-cmpeq-sc-b-pass.d       |  16 +
 .../gas/riscv/cv-simd-cmpeq-sc-b-pass.s       |   8 +
 .../gas/riscv/cv-simd-cmpeq-sc-h-fail.d       |   3 +
 .../gas/riscv/cv-simd-cmpeq-sc-h-fail.l       |   3 +
 .../gas/riscv/cv-simd-cmpeq-sc-h-fail.s       |   4 +
 .../gas/riscv/cv-simd-cmpeq-sc-h-pass.d       |  16 +
 .../gas/riscv/cv-simd-cmpeq-sc-h-pass.s       |   8 +
 .../gas/riscv/cv-simd-cmpeq-sci-b-fail.d      |   3 +
 .../gas/riscv/cv-simd-cmpeq-sci-b-fail.l      |   5 +
 .../gas/riscv/cv-simd-cmpeq-sci-b-fail.s      |   7 +
 .../gas/riscv/cv-simd-cmpeq-sci-b-pass.d      |  19 +
 .../gas/riscv/cv-simd-cmpeq-sci-b-pass.s      |  12 +
 .../gas/riscv/cv-simd-cmpeq-sci-h-fail.d      |   3 +
 .../gas/riscv/cv-simd-cmpeq-sci-h-fail.l      |   5 +
 .../gas/riscv/cv-simd-cmpeq-sci-h-fail.s      |   7 +
 .../gas/riscv/cv-simd-cmpeq-sci-h-pass.d      |  19 +
 .../gas/riscv/cv-simd-cmpeq-sci-h-pass.s      |  12 +
 .../gas/riscv/cv-simd-cmpge-b-fail.d          |   3 +
 .../gas/riscv/cv-simd-cmpge-b-fail.l          |   3 +
 .../gas/riscv/cv-simd-cmpge-b-fail.s          |   4 +
 .../gas/riscv/cv-simd-cmpge-b-pass.d          |  16 +
 .../gas/riscv/cv-simd-cmpge-b-pass.s          |   8 +
 .../gas/riscv/cv-simd-cmpge-h-fail.d          |   3 +
 .../gas/riscv/cv-simd-cmpge-h-fail.l          |   3 +
 .../gas/riscv/cv-simd-cmpge-h-fail.s          |   4 +
 .../gas/riscv/cv-simd-cmpge-h-pass.d          |  16 +
 .../gas/riscv/cv-simd-cmpge-h-pass.s          |   8 +
 .../gas/riscv/cv-simd-cmpge-sc-b-fail.d       |   3 +
 .../gas/riscv/cv-simd-cmpge-sc-b-fail.l       |   3 +
 .../gas/riscv/cv-simd-cmpge-sc-b-fail.s       |   4 +
 .../gas/riscv/cv-simd-cmpge-sc-b-pass.d       |  16 +
 .../gas/riscv/cv-simd-cmpge-sc-b-pass.s       |   8 +
 .../gas/riscv/cv-simd-cmpge-sc-h-fail.d       |   3 +
 .../gas/riscv/cv-simd-cmpge-sc-h-fail.l       |   3 +
 .../gas/riscv/cv-simd-cmpge-sc-h-fail.s       |   4 +
 .../gas/riscv/cv-simd-cmpge-sc-h-pass.d       |  16 +
 .../gas/riscv/cv-simd-cmpge-sc-h-pass.s       |   8 +
 .../gas/riscv/cv-simd-cmpge-sci-b-fail.d      |   3 +
 .../gas/riscv/cv-simd-cmpge-sci-b-fail.l      |   5 +
 .../gas/riscv/cv-simd-cmpge-sci-b-fail.s      |   7 +
 .../gas/riscv/cv-simd-cmpge-sci-b-pass.d      |  19 +
 .../gas/riscv/cv-simd-cmpge-sci-b-pass.s      |  12 +
 .../gas/riscv/cv-simd-cmpge-sci-h-fail.d      |   3 +
 .../gas/riscv/cv-simd-cmpge-sci-h-fail.l      |   5 +
 .../gas/riscv/cv-simd-cmpge-sci-h-fail.s      |   7 +
 .../gas/riscv/cv-simd-cmpge-sci-h-pass.d      |  19 +
 .../gas/riscv/cv-simd-cmpge-sci-h-pass.s      |  12 +
 .../gas/riscv/cv-simd-cmpgeu-b-fail.d         |   3 +
 .../gas/riscv/cv-simd-cmpgeu-b-fail.l         |   3 +
 .../gas/riscv/cv-simd-cmpgeu-b-fail.s         |   4 +
 .../gas/riscv/cv-simd-cmpgeu-b-pass.d         |  16 +
 .../gas/riscv/cv-simd-cmpgeu-b-pass.s         |   8 +
 .../gas/riscv/cv-simd-cmpgeu-h-fail.d         |   3 +
 .../gas/riscv/cv-simd-cmpgeu-h-fail.l         |   3 +
 .../gas/riscv/cv-simd-cmpgeu-h-fail.s         |   4 +
 .../gas/riscv/cv-simd-cmpgeu-h-pass.d         |  16 +
 .../gas/riscv/cv-simd-cmpgeu-h-pass.s         |   8 +
 .../gas/riscv/cv-simd-cmpgeu-sc-b-fail.d      |   3 +
 .../gas/riscv/cv-simd-cmpgeu-sc-b-fail.l      |   3 +
 .../gas/riscv/cv-simd-cmpgeu-sc-b-fail.s      |   4 +
 .../gas/riscv/cv-simd-cmpgeu-sc-b-pass.d      |  16 +
 .../gas/riscv/cv-simd-cmpgeu-sc-b-pass.s      |   8 +
 .../gas/riscv/cv-simd-cmpgeu-sc-h-fail.d      |   3 +
 .../gas/riscv/cv-simd-cmpgeu-sc-h-fail.l      |   3 +
 .../gas/riscv/cv-simd-cmpgeu-sc-h-fail.s      |   4 +
 .../gas/riscv/cv-simd-cmpgeu-sc-h-pass.d      |  16 +
 .../gas/riscv/cv-simd-cmpgeu-sc-h-pass.s      |   8 +
 .../gas/riscv/cv-simd-cmpgeu-sci-b-fail.d     |   3 +
 .../gas/riscv/cv-simd-cmpgeu-sci-b-fail.l     |   5 +
 .../gas/riscv/cv-simd-cmpgeu-sci-b-fail.s     |   7 +
 .../gas/riscv/cv-simd-cmpgeu-sci-b-pass.d     |  18 +
 .../gas/riscv/cv-simd-cmpgeu-sci-b-pass.s     |  11 +
 .../gas/riscv/cv-simd-cmpgeu-sci-h-fail.d     |   3 +
 .../gas/riscv/cv-simd-cmpgeu-sci-h-fail.l     |   5 +
 .../gas/riscv/cv-simd-cmpgeu-sci-h-fail.s     |   7 +
 .../gas/riscv/cv-simd-cmpgeu-sci-h-pass.d     |  18 +
 .../gas/riscv/cv-simd-cmpgeu-sci-h-pass.s     |  11 +
 .../gas/riscv/cv-simd-cmpgt-b-fail.d          |   3 +
 .../gas/riscv/cv-simd-cmpgt-b-fail.l          |   3 +
 .../gas/riscv/cv-simd-cmpgt-b-fail.s          |   4 +
 .../gas/riscv/cv-simd-cmpgt-b-pass.d          |  16 +
 .../gas/riscv/cv-simd-cmpgt-b-pass.s          |   8 +
 .../gas/riscv/cv-simd-cmpgt-h-fail.d          |   3 +
 .../gas/riscv/cv-simd-cmpgt-h-fail.l          |   3 +
 .../gas/riscv/cv-simd-cmpgt-h-fail.s          |   4 +
 .../gas/riscv/cv-simd-cmpgt-h-pass.d          |  16 +
 .../gas/riscv/cv-simd-cmpgt-h-pass.s          |   8 +
 .../gas/riscv/cv-simd-cmpgt-sc-b-fail.d       |   3 +
 .../gas/riscv/cv-simd-cmpgt-sc-b-fail.l       |   3 +
 .../gas/riscv/cv-simd-cmpgt-sc-b-fail.s       |   4 +
 .../gas/riscv/cv-simd-cmpgt-sc-b-pass.d       |  16 +
 .../gas/riscv/cv-simd-cmpgt-sc-b-pass.s       |   8 +
 .../gas/riscv/cv-simd-cmpgt-sc-h-fail.d       |   3 +
 .../gas/riscv/cv-simd-cmpgt-sc-h-fail.l       |   3 +
 .../gas/riscv/cv-simd-cmpgt-sc-h-fail.s       |   4 +
 .../gas/riscv/cv-simd-cmpgt-sc-h-pass.d       |  16 +
 .../gas/riscv/cv-simd-cmpgt-sc-h-pass.s       |   8 +
 .../gas/riscv/cv-simd-cmpgt-sci-b-fail.d      |   3 +
 .../gas/riscv/cv-simd-cmpgt-sci-b-fail.l      |   5 +
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 .../gas/riscv/cv-simd-xor-sc-b-fail.d         |   3 +
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 .../gas/riscv/cv-simd-xor-sci-h-pass.s        |  12 +
 include/opcode/riscv-opc.h                    | 443 ++++++++++++++++++
 include/opcode/riscv.h                        |  14 +
 opcodes/riscv-dis.c                           |  22 +
 opcodes/riscv-opc.c                           | 222 +++++++++
 1112 files changed, 9963 insertions(+), 1 deletion(-)
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 create mode 100644 gas/testsuite/gas/riscv/cv-simd-srl-sci-b-pass.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-srl-sci-h-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-srl-sci-h-fail.l
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-srl-sci-h-fail.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-srl-sci-h-pass.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-srl-sci-h-pass.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-b-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-b-fail.l
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 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-b-pass.d
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 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-div2-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-div2-fail.l
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-div2-fail.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-div2-pass.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-div2-pass.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-div4-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-div4-fail.l
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-div4-fail.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-div4-pass.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-div4-pass.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-div8-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-div8-fail.l
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-div8-fail.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-div8-pass.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-div8-pass.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-h-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-h-fail.l
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 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-h-pass.d
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 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-sc-b-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-sc-b-fail.l
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 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-sc-h-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-sc-h-fail.l
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 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-sci-b-fail.d
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 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-sci-h-fail.d
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 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-sci-h-pass.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-sci-h-pass.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-subrotmj-div2-fail.d
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 create mode 100644 gas/testsuite/gas/riscv/cv-simd-subrotmj-fail.d
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 create mode 100644 gas/testsuite/gas/riscv/cv-simd-subrotmj-pass.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-subrotmj-pass.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-b-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-b-fail.l
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 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-b-pass.d
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 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-h-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-h-fail.l
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 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-h-pass.d
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 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sc-b-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sc-b-fail.l
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 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sc-b-pass.d
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 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sc-h-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sc-h-fail.l
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sc-h-fail.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sc-h-pass.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sc-h-pass.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sci-b-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sci-b-fail.l
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sci-b-fail.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sci-b-pass.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sci-b-pass.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sci-h-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sci-h-fail.l
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sci-h-fail.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sci-h-pass.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sci-h-pass.s

-- 
2.34.1

[PATCH 1/1] RISC-V: Add support for XCVsimd extension in CV32E40Pv2

[mary.bennett682]

Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html

Contributors:
  Mary Bennett <mary.bennett@embecosm.com>
  Nandni Jamnadas <nandni.jamnadas@embecosm.com>
  Pietra Ferreira <pietra.ferreira@embecosm.com>
  Charlie Keaney
  Jessica Mills
  Craig Blackmore <craig.blackmore@embecosm.com>
  Simon Cook <simon.cook@embecosm.com>
  Jeremy Bennett <jeremy.bennett@embecosm.com>
  Helene Chelin <helene.chelin@embecosm.com>

bfd/ChangeLog:

        * elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvsimd`
          instruction class.
        (riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

        * doc/c-riscv.texi: Note XCVsimd as an additional ISA extension
          for CORE-V.
	* config/tc-riscv.c: Add new operands b4, b5 and b8.
 	* testsuite/gas/riscv/cv-simd-abs-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-abs-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-abs-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-abs-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-abs-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-abs-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-abs-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-abs-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-abs-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-abs-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-add-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-add-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-add-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-add-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-add-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-add-div2-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-add-div2-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-add-div2-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-add-div2-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-add-div2-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-add-div4-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-add-div4-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-add-div4-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-add-div4-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-add-div4-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-add-div8-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-add-div8-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-add-div8-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-add-div8-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-add-div8-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-add-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-add-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-add-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-add-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-add-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-add-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-add-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-add-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-add-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-add-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-add-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-add-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-add-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-add-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-add-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-add-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-add-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-add-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-add-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-add-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-add-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-add-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-add-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-add-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-add-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-and-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-and-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-and-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-and-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-and-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-and-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-and-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-and-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-and-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-and-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-and-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-and-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-and-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-and-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-and-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-and-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-and-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-and-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-and-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-and-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-and-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-and-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-and-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-and-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-and-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-and-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-and-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-and-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-and-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-and-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-avg-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-avg-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-avg-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-avg-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-avg-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-avg-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-avg-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-avg-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-avg-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-avg-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-avg-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-avg-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-avg-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-avg-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-avg-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-avg-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-avg-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-avg-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-avg-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-avg-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-avg-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-avg-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-avg-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-avg-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-avg-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-avg-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-avg-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-avg-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-avg-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-avg-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cplxconj-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cplxconj-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cplxconj-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cplxconj-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cplxconj-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-i-div2-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-i-div2-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-i-div2-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-i-div2-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-i-div2-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-i-div4-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-i-div4-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-i-div4-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-i-div4-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-i-div4-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-i-div8-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-i-div8-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-i-div8-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-i-div8-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-i-div8-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-i-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-i-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-i-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-i-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-i-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-r-div2-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-r-div2-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-r-div2-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-r-div2-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-r-div2-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-r-div4-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-r-div4-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-r-div4-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-r-div4-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-r-div4-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-r-div8-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-r-div8-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-r-div8-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-r-div8-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-r-div8-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-r-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-r-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-r-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-r-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-r-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-extract-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-extract-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-extract-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-extract-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-extract-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-extract-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-extract-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-extract-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-extract-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-extract-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-extractu-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-extractu-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-extractu-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-extractu-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-extractu-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-extractu-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-extractu-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-extractu-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-extractu-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-extractu-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-insert-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-insert-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-insert-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-insert-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-insert-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-insert-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-insert-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-insert-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-insert-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-insert-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-march-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-march-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-march-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-march-xcvsimd.d
 	* testsuite/gas/riscv/cv-simd-march-xcvsimd.s
 	* testsuite/gas/riscv/cv-simd-max-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-max-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-max-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-max-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-max-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-max-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-max-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-max-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-max-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-max-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-max-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-max-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-max-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-max-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-max-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-max-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-max-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-max-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-max-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-max-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-max-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-max-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-max-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-max-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-max-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-max-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-max-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-max-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-max-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-max-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-min-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-min-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-min-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-min-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-min-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-min-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-min-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-min-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-min-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-min-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-min-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-min-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-min-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-min-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-min-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-min-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-min-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-min-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-min-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-min-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-min-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-min-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-min-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-min-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-min-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-min-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-min-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-min-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-min-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-min-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-minu-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-minu-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-minu-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-minu-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-minu-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-minu-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-minu-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-minu-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-minu-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-minu-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-minu-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-minu-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-minu-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-minu-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-minu-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-minu-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-minu-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-minu-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-minu-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-minu-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-minu-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-minu-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-minu-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-minu-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-minu-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-minu-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-minu-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-minu-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-minu-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-minu-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-or-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-or-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-or-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-or-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-or-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-or-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-or-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-or-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-or-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-or-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-or-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-or-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-or-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-or-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-or-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-or-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-or-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-or-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-or-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-or-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-or-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-or-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-or-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-or-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-or-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-or-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-or-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-or-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-or-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-or-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-pack-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-pack-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-pack-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-pack-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-pack-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-pack-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-pack-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-pack-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-pack-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-pack-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-packhi-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-packhi-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-packhi-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-packhi-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-packhi-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-packlo-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-packlo-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-packlo-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-packlo-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-packlo-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle2-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle2-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle2-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle2-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle2-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle2-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle2-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle2-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle2-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle2-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-shufflei0-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-shufflei0-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-shufflei0-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-shufflei0-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-shufflei0-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-shufflei1-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-shufflei1-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-shufflei1-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-shufflei1-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-shufflei1-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-shufflei2-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-shufflei2-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-shufflei2-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-shufflei2-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-shufflei2-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-shufflei3-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-shufflei3-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-shufflei3-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-shufflei3-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-shufflei3-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sll-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sll-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sll-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sll-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sll-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sll-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sll-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sll-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sll-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sll-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sll-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sll-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sll-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sll-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sll-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sll-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sll-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sll-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sll-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sll-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sll-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sll-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sll-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sll-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sll-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sll-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sll-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sll-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sll-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sll-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sra-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sra-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sra-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sra-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sra-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sra-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sra-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sra-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sra-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sra-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sra-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sra-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sra-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sra-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sra-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sra-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sra-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sra-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sra-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sra-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sra-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sra-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sra-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sra-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sra-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sra-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sra-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sra-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sra-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sra-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-srl-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-srl-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-srl-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-srl-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-srl-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-srl-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-srl-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-srl-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-srl-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-srl-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-srl-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-srl-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-srl-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-srl-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-srl-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-srl-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-srl-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-srl-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-srl-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-srl-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-srl-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-srl-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-srl-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-srl-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-srl-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-srl-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-srl-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-srl-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-srl-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-srl-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sub-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sub-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sub-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sub-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sub-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sub-div2-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sub-div2-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sub-div2-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sub-div2-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sub-div2-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sub-div4-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sub-div4-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sub-div4-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sub-div4-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sub-div4-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sub-div8-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sub-div8-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sub-div8-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sub-div8-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sub-div8-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sub-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sub-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sub-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sub-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sub-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sub-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sub-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sub-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sub-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sub-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sub-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sub-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sub-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sub-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sub-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sub-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sub-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sub-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sub-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sub-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sub-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sub-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sub-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sub-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sub-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-subrotmj-div2-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-subrotmj-div2-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-subrotmj-div2-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-subrotmj-div2-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-subrotmj-div2-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-subrotmj-div4-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-subrotmj-div4-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-subrotmj-div4-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-subrotmj-div4-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-subrotmj-div4-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-subrotmj-div8-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-subrotmj-div8-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-subrotmj-div8-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-subrotmj-div8-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-subrotmj-div8-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-subrotmj-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-subrotmj-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-subrotmj-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-subrotmj-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-subrotmj-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-xor-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-xor-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-xor-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-xor-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-xor-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-xor-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-xor-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-xor-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-xor-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-xor-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-xor-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-xor-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-xor-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-xor-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-xor-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-xor-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-xor-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-xor-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-xor-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-xor-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-xor-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-xor-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-xor-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-xor-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-xor-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-xor-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-xor-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-xor-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-xor-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-xor-sci-h-pass.s: New test.

include/ChangeLog:

        * opcode/riscv-opc.h: Add corresponding MATCH and MASK
          instruction opcode macros.
        * opcode/riscv.h (riscv_insn_class): Add INSN_CLASS_XCVSIMD.

opcodes/ChangeLog:

	* riscv-dis.c (print_insn_args): Add new operands.
        * riscv-opc.c (riscv_opcode): Add simd instructions.
---
 bfd/elfxx-riscv.c                             |   5 +
 gas/config/tc-riscv.c                         |  96 +++-
 gas/doc/c-riscv.texi                          |   5 +
 gas/testsuite/gas/riscv/cv-simd-abs-b-fail.d  |   3 +
 gas/testsuite/gas/riscv/cv-simd-abs-b-fail.l  |   3 +
 gas/testsuite/gas/riscv/cv-simd-abs-b-fail.s  |   4 +
 gas/testsuite/gas/riscv/cv-simd-abs-b-pass.d  |  16 +
 gas/testsuite/gas/riscv/cv-simd-abs-b-pass.s  |   8 +
 gas/testsuite/gas/riscv/cv-simd-abs-h-fail.d  |   3 +
 gas/testsuite/gas/riscv/cv-simd-abs-h-fail.l  |   3 +
 gas/testsuite/gas/riscv/cv-simd-abs-h-fail.s  |   4 +
 gas/testsuite/gas/riscv/cv-simd-abs-h-pass.d  |  16 +
 gas/testsuite/gas/riscv/cv-simd-abs-h-pass.s  |   8 +
 gas/testsuite/gas/riscv/cv-simd-add-b-fail.d  |   3 +
 gas/testsuite/gas/riscv/cv-simd-add-b-fail.l  |   3 +
 gas/testsuite/gas/riscv/cv-simd-add-b-fail.s  |   4 +
 gas/testsuite/gas/riscv/cv-simd-add-b-pass.d  |  16 +
 gas/testsuite/gas/riscv/cv-simd-add-b-pass.s  |   8 +
 .../gas/riscv/cv-simd-add-div2-fail.d         |   3 +
 .../gas/riscv/cv-simd-add-div2-fail.l         |   3 +
 .../gas/riscv/cv-simd-add-div2-fail.s         |   4 +
 .../gas/riscv/cv-simd-add-div2-pass.d         |  16 +
 .../gas/riscv/cv-simd-add-div2-pass.s         |   8 +
 .../gas/riscv/cv-simd-add-div4-fail.d         |   3 +
 .../gas/riscv/cv-simd-add-div4-fail.l         |   3 +
 .../gas/riscv/cv-simd-add-div4-fail.s         |   4 +
 .../gas/riscv/cv-simd-add-div4-pass.d         |  16 +
 .../gas/riscv/cv-simd-add-div4-pass.s         |   8 +
 .../gas/riscv/cv-simd-add-div8-fail.d         |   3 +
 .../gas/riscv/cv-simd-add-div8-fail.l         |   3 +
 .../gas/riscv/cv-simd-add-div8-fail.s         |   4 +
 .../gas/riscv/cv-simd-add-div8-pass.d         |  16 +
 .../gas/riscv/cv-simd-add-div8-pass.s         |   8 +
 gas/testsuite/gas/riscv/cv-simd-add-h-fail.d  |   3 +
 gas/testsuite/gas/riscv/cv-simd-add-h-fail.l  |   3 +
 gas/testsuite/gas/riscv/cv-simd-add-h-fail.s  |   4 +
 gas/testsuite/gas/riscv/cv-simd-add-h-pass.d  |  15 +
 gas/testsuite/gas/riscv/cv-simd-add-h-pass.s  |   8 +
 .../gas/riscv/cv-simd-add-sc-b-fail.d         |   3 +
 .../gas/riscv/cv-simd-add-sc-b-fail.l         |   3 +
 .../gas/riscv/cv-simd-add-sc-b-fail.s         |   4 +
 .../gas/riscv/cv-simd-add-sc-b-pass.d         |  16 +
 .../gas/riscv/cv-simd-add-sc-b-pass.s         |   8 +
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 include/opcode/riscv-opc.h                    | 443 ++++++++++++++++++
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 1112 files changed, 9963 insertions(+), 1 deletion(-)
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-abs-b-fail.d
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 create mode 100644 gas/testsuite/gas/riscv/cv-simd-subrotmj-div2-pass.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-subrotmj-div4-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-subrotmj-div4-fail.l
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-subrotmj-div4-fail.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-subrotmj-div4-pass.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-subrotmj-div4-pass.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-subrotmj-div8-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-subrotmj-div8-fail.l
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-subrotmj-div8-fail.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-subrotmj-div8-pass.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-subrotmj-div8-pass.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-subrotmj-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-subrotmj-fail.l
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-subrotmj-fail.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-subrotmj-pass.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-subrotmj-pass.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-b-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-b-fail.l
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-b-fail.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-b-pass.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-b-pass.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-h-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-h-fail.l
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-h-fail.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-h-pass.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-h-pass.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sc-b-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sc-b-fail.l
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sc-b-fail.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sc-b-pass.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sc-b-pass.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sc-h-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sc-h-fail.l
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sc-h-fail.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sc-h-pass.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sc-h-pass.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sci-b-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sci-b-fail.l
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sci-b-fail.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sci-b-pass.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sci-b-pass.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sci-h-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sci-h-fail.l
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sci-h-fail.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sci-h-pass.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sci-h-pass.s

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 9a121b47121..d0ecab02fed 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1369,6 +1369,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
 {
   {"xcvmac",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xcvalu",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
+  {"xcvsimd",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadba",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadbb",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadbs",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
@@ -2576,6 +2577,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "xcvmac");
     case INSN_CLASS_XCVALU:
       return riscv_subset_supports (rps, "xcvalu");
+    case INSN_CLASS_XCVSIMD:
+      return riscv_subset_supports (rps, "xcvsimd");
     case INSN_CLASS_XTHEADBA:
       return riscv_subset_supports (rps, "xtheadba");
     case INSN_CLASS_XTHEADBB:
@@ -2828,6 +2831,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return "xcvmac";
     case INSN_CLASS_XCVALU:
       return "xcvalu";
+    case INSN_CLASS_XCVSIMD:
+      return "xcvsimd";
     case INSN_CLASS_XTHEADBA:
       return "xtheadba";
     case INSN_CLASS_XTHEADBB:
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index a4161420128..ce55f46cdc5 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1373,6 +1373,24 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
 	case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
 	case 'A': break; /* Macro operand, must be symbol.  */
 	case 'B': break; /* Macro operand, must be symbol or constant.  */
+	case 'b': /* CORE-V Specific.  */
+	  if (oparg[1] == '4')
+	    {
+	      used_bits |= ENCODE_CV_UIMM5(-1U);
+	      ++oparg; break;
+	    }
+	  else if (oparg[1] == '5')
+	    {
+	      used_bits |= ENCODE_CV_SIMD_IMM6(-1U);
+	      ++oparg; break;
+	    }
+	  else if (oparg[1] == '8')
+	    {
+	      used_bits |= ENCODE_CV_SIMD_UIMM6(-1U);
+	      if (oparg[2] == '1' || oparg[2] == '2' || oparg[2] == '3' || oparg[2] == '4') ++oparg;
+	      ++oparg; break;
+	    }
+	  break;
 	case 'c': break; /* Macro operand, must be symbol or constant.  */
 	case 'I': break; /* Macro operand, must be constant.  */
 	case 'D': /* RD, floating point.  */
@@ -3361,7 +3379,83 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 	      *imm_reloc = BFD_RELOC_32;
 	      asarg = expr_parse_end;
 	      continue;
-
+	      /* CORE-V Specific.	 */
+	    case 'b':
+	      if (oparg[1] == '4')
+		{
+		  my_getExpression (imm_expr, asarg);
+		  check_absolute_expr (ip, imm_expr, FALSE);
+		  asarg = expr_parse_end;
+		  if (imm_expr->X_add_number<-16 || imm_expr->X_add_number>15)
+		  as_bad(_("immediate value must be 5-bit signed, %ld is out of range"),
+		  imm_expr->X_add_number);
+		  ip->insn_opcode |= ENCODE_CV_UIMM5 (imm_expr->X_add_number);
+		  ++oparg;
+		}
+	      else if (oparg[1] == '5')
+		// b5: imm6 bits signed immediate bits
+		{
+		  my_getExpression (imm_expr, asarg);
+		  check_absolute_expr (ip, imm_expr, FALSE);
+		  asarg = expr_parse_end;
+		  if (imm_expr->X_add_number<-32 || imm_expr->X_add_number>31)
+		  as_bad(_("immediate value must be 6-bit signed, %ld is out of range"),
+		  imm_expr->X_add_number);
+		  ip->insn_opcode |= ENCODE_CV_SIMD_IMM6 (imm_expr->X_add_number);
+		  ++oparg;
+		}
+	      else if (oparg[1] == '8')
+		// b8: uimm6 bits unsigned immediate bits
+		// b81: Imm6[0]
+		// b83: Imm6[2:0]
+		// b84: Imm6[3:0]
+		{
+		  my_getExpression (imm_expr, asarg);
+		  check_absolute_expr (ip, imm_expr, FALSE);
+		  asarg = expr_parse_end;
+		  if (oparg[2] == '1')
+		  {
+		    if (imm_expr->X_add_number<0 || imm_expr->X_add_number>1)
+		    as_bad(_("immediate value must be 1-bit unsigned, %ld is out of range"),
+		    imm_expr->X_add_number);
+		    ++oparg;
+		  }
+		  else if (oparg[2] == '2')
+		  {
+		    if (imm_expr->X_add_number<0 || imm_expr->X_add_number>3)
+		    as_bad(_("immediate value must be 2-bit unsigned, %ld is out of range"),
+		    imm_expr->X_add_number);
+		    ++oparg;
+		  }
+		  else if (oparg[2] == '3')
+		  {
+		    if (imm_expr->X_add_number<0 || imm_expr->X_add_number>7)
+		    as_bad(_("immediate value must be 3-bit unsigned, %ld is out of range"),
+		    imm_expr->X_add_number);
+		    ++oparg;
+		  }
+		  else if (oparg[2] == '4')
+		  {
+		    if (imm_expr->X_add_number<0 || imm_expr->X_add_number>15)
+		    as_bad(_("immediate value must be 4-bit unsigned, %ld is out of range"),
+		    imm_expr->X_add_number);
+		    ++oparg;
+		  }
+		  else
+		  {
+		    if (imm_expr->X_add_number<0 || imm_expr->X_add_number>63)
+		    as_bad(_("immediate value must be 6-bit unsigned, %ld is out of range"),
+		    imm_expr->X_add_number);
+		  }
+		  ip->insn_opcode |= ENCODE_CV_SIMD_UIMM6 (imm_expr->X_add_number);
+		  ++oparg;
+		}
+	      else
+		{
+		  my_getExpression (imm_expr, asarg);
+		  asarg = expr_parse_end;
+		}
+	      continue;
 	    case 'B':
 	      my_getExpression (imm_expr, asarg);
 	      normalize_constant_expr (imm_expr);
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 7484a71798a..f8c6bcd5f3d 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -750,6 +750,11 @@ The Xcvalu extension provides instructions for general ALU operations.
 
 It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
 
+@item Xcvsimd
+The Xcvsimd extension provides instructions for SIMD operations.
+
+It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
+
 @item XTheadBa
 The XTheadBa extension provides instructions for address calculations.
 
diff --git a/gas/testsuite/gas/riscv/cv-simd-abs-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-abs-b-fail.d
new file mode 100644
index 00000000000..d42b44dd49f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-abs-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-abs-b-fail.s
+#error_output: cv-simd-abs-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-abs-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-abs-b-fail.l
new file mode 100644
index 00000000000..93156ef3807
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-abs-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.abs.b x32,x32'
+.*: Error: illegal operands `cv.abs.b x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-abs-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-abs-b-fail.s
new file mode 100644
index 00000000000..77ae67f0daf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-abs-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.abs.b x32, x32
+    cv.abs.b x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-abs-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-abs-b-pass.d
new file mode 100644
index 00000000000..b50e9508bb4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-abs-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-abs-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	7000107b          	cv.abs.b	zero,zero
+   4:	700090fb          	cv.abs.b	ra,ra
+   8:	7001117b          	cv.abs.b	sp,sp
+   c:	7004147b          	cv.abs.b	s0,s0
+  10:	700a1a7b          	cv.abs.b	s4,s4
+  14:	700f9ffb          	cv.abs.b	t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-abs-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-abs-b-pass.s
new file mode 100644
index 00000000000..9e228305641
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-abs-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.abs.b x0, x0
+    cv.abs.b x1, x1
+    cv.abs.b x2, x2
+    cv.abs.b x8, x8
+    cv.abs.b x20, x20
+    cv.abs.b x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-abs-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-abs-h-fail.d
new file mode 100644
index 00000000000..b3938c89647
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-abs-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-abs-h-fail.s
+#error_output: cv-simd-abs-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-abs-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-abs-h-fail.l
new file mode 100644
index 00000000000..74867e1b611
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-abs-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.abs.h x32,x32'
+.*: Error: illegal operands `cv.abs.h x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-abs-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-abs-h-fail.s
new file mode 100644
index 00000000000..2e711546ce6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-abs-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.abs.h x32, x32
+    cv.abs.h x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-abs-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-abs-h-pass.d
new file mode 100644
index 00000000000..b8d09bb427f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-abs-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-abs-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	7000007b          	cv.abs.h	zero,zero
+   4:	700080fb          	cv.abs.h	ra,ra
+   8:	7001017b          	cv.abs.h	sp,sp
+   c:	7004047b          	cv.abs.h	s0,s0
+  10:	700a0a7b          	cv.abs.h	s4,s4
+  14:	700f8ffb          	cv.abs.h	t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-abs-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-abs-h-pass.s
new file mode 100644
index 00000000000..1d455699073
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-abs-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.abs.h x0, x0
+    cv.abs.h x1, x1
+    cv.abs.h x2, x2
+    cv.abs.h x8, x8
+    cv.abs.h x20, x20
+    cv.abs.h x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-add-b-fail.d
new file mode 100644
index 00000000000..1105a46a384
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-b-fail.s
+#error_output: cv-simd-add-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-add-b-fail.l
new file mode 100644
index 00000000000..e43a2c5536b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.add.b x32,x32,x32'
+.*: Error: illegal operands `cv.add.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-add-b-fail.s
new file mode 100644
index 00000000000..02b5c5d148f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.add.b x32, x32, x32
+    cv.add.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-add-b-pass.d
new file mode 100644
index 00000000000..371e0fb6af6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0000107b          	cv.add.b	zero,zero,zero
+   4:	001090fb          	cv.add.b	ra,ra,ra
+   8:	0021117b          	cv.add.b	sp,sp,sp
+   c:	0084147b          	cv.add.b	s0,s0,s0
+  10:	014a1a7b          	cv.add.b	s4,s4,s4
+  14:	01ff9ffb          	cv.add.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-add-b-pass.s
new file mode 100644
index 00000000000..77da5630aa8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.add.b x0, x0, x0
+    cv.add.b x1, x1, x1
+    cv.add.b x2, x2, x2
+    cv.add.b x8, x8, x8
+    cv.add.b x20, x20, x20
+    cv.add.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-div2-fail.d b/gas/testsuite/gas/riscv/cv-simd-add-div2-fail.d
new file mode 100644
index 00000000000..0430f5445d0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-div2-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-div2-fail.s
+#error_output: cv-simd-add-div2-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-div2-fail.l b/gas/testsuite/gas/riscv/cv-simd-add-div2-fail.l
new file mode 100644
index 00000000000..aaf581ef21d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-div2-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.add.div2 x32,x32,x32'
+.*: Error: illegal operands `cv.add.div2 x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-div2-fail.s b/gas/testsuite/gas/riscv/cv-simd-add-div2-fail.s
new file mode 100644
index 00000000000..ef37cafa2ae
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-div2-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.add.div2 x32, x32, x32
+    cv.add.div2 x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-div2-pass.d b/gas/testsuite/gas/riscv/cv-simd-add-div2-pass.d
new file mode 100644
index 00000000000..ec7c9478a2e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-div2-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-div2-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	6c00207b          	cv.add.div2	zero,zero,zero
+   4:	6c10a0fb          	cv.add.div2	ra,ra,ra
+   8:	6c21217b          	cv.add.div2	sp,sp,sp
+   c:	6c84247b          	cv.add.div2	s0,s0,s0
+  10:	6d4a2a7b          	cv.add.div2	s4,s4,s4
+  14:	6dffaffb          	cv.add.div2	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-div2-pass.s b/gas/testsuite/gas/riscv/cv-simd-add-div2-pass.s
new file mode 100644
index 00000000000..02bb555d39d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-div2-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.add.div2 x0, x0, x0
+    cv.add.div2 x1, x1, x1
+    cv.add.div2 x2, x2, x2
+    cv.add.div2 x8, x8, x8
+    cv.add.div2 x20, x20, x20
+    cv.add.div2 x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-div4-fail.d b/gas/testsuite/gas/riscv/cv-simd-add-div4-fail.d
new file mode 100644
index 00000000000..950e50f68f0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-div4-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-div4-fail.s
+#error_output: cv-simd-add-div4-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-div4-fail.l b/gas/testsuite/gas/riscv/cv-simd-add-div4-fail.l
new file mode 100644
index 00000000000..4f91c5031c8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-div4-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.add.div4 x32,x32,x32'
+.*: Error: illegal operands `cv.add.div4 x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-div4-fail.s b/gas/testsuite/gas/riscv/cv-simd-add-div4-fail.s
new file mode 100644
index 00000000000..94be2df60a5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-div4-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.add.div4 x32, x32, x32
+    cv.add.div4 x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-div4-pass.d b/gas/testsuite/gas/riscv/cv-simd-add-div4-pass.d
new file mode 100644
index 00000000000..b2ab67c3e46
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-div4-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-div4-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	6c00407b          	cv.add.div4	zero,zero,zero
+   4:	6c10c0fb          	cv.add.div4	ra,ra,ra
+   8:	6c21417b          	cv.add.div4	sp,sp,sp
+   c:	6c84447b          	cv.add.div4	s0,s0,s0
+  10:	6d4a4a7b          	cv.add.div4	s4,s4,s4
+  14:	6dffcffb          	cv.add.div4	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-div4-pass.s b/gas/testsuite/gas/riscv/cv-simd-add-div4-pass.s
new file mode 100644
index 00000000000..9f3afd2cbc0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-div4-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.add.div4 x0, x0, x0
+    cv.add.div4 x1, x1, x1
+    cv.add.div4 x2, x2, x2
+    cv.add.div4 x8, x8, x8
+    cv.add.div4 x20, x20, x20
+    cv.add.div4 x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-div8-fail.d b/gas/testsuite/gas/riscv/cv-simd-add-div8-fail.d
new file mode 100644
index 00000000000..dc238baf678
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-div8-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-div8-fail.s
+#error_output: cv-simd-add-div8-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-div8-fail.l b/gas/testsuite/gas/riscv/cv-simd-add-div8-fail.l
new file mode 100644
index 00000000000..b5628ada078
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-div8-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.add.div8 x32,x32,x32'
+.*: Error: illegal operands `cv.add.div8 x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-div8-fail.s b/gas/testsuite/gas/riscv/cv-simd-add-div8-fail.s
new file mode 100644
index 00000000000..d4c2c4afbfe
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-div8-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.add.div8 x32, x32, x32
+    cv.add.div8 x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-div8-pass.d b/gas/testsuite/gas/riscv/cv-simd-add-div8-pass.d
new file mode 100644
index 00000000000..df2687734a6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-div8-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-div8-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	6c00607b          	cv.add.div8	zero,zero,zero
+   4:	6c10e0fb          	cv.add.div8	ra,ra,ra
+   8:	6c21617b          	cv.add.div8	sp,sp,sp
+   c:	6c84647b          	cv.add.div8	s0,s0,s0
+  10:	6d4a6a7b          	cv.add.div8	s4,s4,s4
+  14:	6dffeffb          	cv.add.div8	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-div8-pass.s b/gas/testsuite/gas/riscv/cv-simd-add-div8-pass.s
new file mode 100644
index 00000000000..a0e33130eec
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-div8-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.add.div8 x0, x0, x0
+    cv.add.div8 x1, x1, x1
+    cv.add.div8 x2, x2, x2
+    cv.add.div8 x8, x8, x8
+    cv.add.div8 x20, x20, x20
+    cv.add.div8 x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-add-h-fail.d
new file mode 100644
index 00000000000..2955fadd135
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-h-fail.s
+#error_output: cv-simd-add-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-add-h-fail.l
new file mode 100644
index 00000000000..a82b28674ac
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.add.h x32,x32,x32'
+.*: Error: illegal operands `cv.add.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-add-h-fail.s
new file mode 100644
index 00000000000..2c9ffa090ca
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.add.h x32, x32, x32
+    cv.add.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-add-h-pass.d
new file mode 100644
index 00000000000..1a8515046a6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-h-pass.d
@@ -0,0 +1,15 @@
+#as: -march=rv32i_xcvsimd
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0000007b          	cv.add.h	zero,zero,zero
+   4:	001080fb          	cv.add.h	ra,ra,ra
+   8:	0021017b          	cv.add.h	sp,sp,sp
+   c:	0084047b          	cv.add.h	s0,s0,s0
+  10:	014a0a7b          	cv.add.h	s4,s4,s4
+  14:	01ff8ffb          	cv.add.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-add-h-pass.s
new file mode 100644
index 00000000000..46e91513932
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.add.h x0, x0, x0
+    cv.add.h x1, x1, x1
+    cv.add.h x2, x2, x2
+    cv.add.h x8, x8, x8
+    cv.add.h x20, x20, x20
+    cv.add.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-add-sc-b-fail.d
new file mode 100644
index 00000000000..5203f945385
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-sc-b-fail.s
+#error_output: cv-simd-add-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-add-sc-b-fail.l
new file mode 100644
index 00000000000..20b1f4fa1dd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.add.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.add.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-add-sc-b-fail.s
new file mode 100644
index 00000000000..9121fd4fefb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.add.sc.b x32, x32, x32
+    cv.add.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-add-sc-b-pass.d
new file mode 100644
index 00000000000..70c4d4d7a5f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0000507b          	cv.add.sc.b	zero,zero,zero
+   4:	0010d0fb          	cv.add.sc.b	ra,ra,ra
+   8:	0021517b          	cv.add.sc.b	sp,sp,sp
+   c:	0084547b          	cv.add.sc.b	s0,s0,s0
+  10:	014a5a7b          	cv.add.sc.b	s4,s4,s4
+  14:	01ffdffb          	cv.add.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-add-sc-b-pass.s
new file mode 100644
index 00000000000..e041df004cc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.add.sc.b x0, x0, x0
+    cv.add.sc.b x1, x1, x1
+    cv.add.sc.b x2, x2, x2
+    cv.add.sc.b x8, x8, x8
+    cv.add.sc.b x20, x20, x20
+    cv.add.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-add-sc-h-fail.d
new file mode 100644
index 00000000000..da90549036e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-sc-h-fail.s
+#error_output: cv-simd-add-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-add-sc-h-fail.l
new file mode 100644
index 00000000000..eaba711f44a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.add.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.add.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-add-sc-h-fail.s
new file mode 100644
index 00000000000..032270dc4e6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.add.sc.h x32, x32, x32
+    cv.add.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-add-sc-h-pass.d
new file mode 100644
index 00000000000..6292cead61a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0000407b          	cv.add.sc.h	zero,zero,zero
+   4:	0010c0fb          	cv.add.sc.h	ra,ra,ra
+   8:	0021417b          	cv.add.sc.h	sp,sp,sp
+   c:	0084447b          	cv.add.sc.h	s0,s0,s0
+  10:	014a4a7b          	cv.add.sc.h	s4,s4,s4
+  14:	01ffcffb          	cv.add.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-add-sc-h-pass.s
new file mode 100644
index 00000000000..27626c6af1a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.add.sc.h x0, x0, x0
+    cv.add.sc.h x1, x1, x1
+    cv.add.sc.h x2, x2, x2
+    cv.add.sc.h x8, x8, x8
+    cv.add.sc.h x20, x20, x20
+    cv.add.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-add-sci-b-fail.d
new file mode 100644
index 00000000000..4a887bf0b03
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-sci-b-fail.s
+#error_output: cv-simd-add-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-add-sci-b-fail.l
new file mode 100644
index 00000000000..c3f90cce759
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.add.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.add.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-add-sci-b-fail.s
new file mode 100644
index 00000000000..d3e2e2aae57
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.add.sci.b x32, x32, 20
+    cv.add.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.add.sci.b x6, x7, -33
+    cv.add.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-add-sci-b-pass.d
new file mode 100644
index 00000000000..a619e5c2a7e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	00a0707b          	cv.add.sci.b	zero,zero,20
+   4:	00a0f0fb          	cv.add.sci.b	ra,ra,20
+   8:	00a1717b          	cv.add.sci.b	sp,sp,20
+   c:	00a4747b          	cv.add.sci.b	s0,s0,20
+  10:	00aa7a7b          	cv.add.sci.b	s4,s4,20
+  14:	00affffb          	cv.add.sci.b	t6,t6,20
+  18:	0103f37b          	cv.add.sci.b	t1,t2,-32
+  1c:	0003f37b          	cv.add.sci.b	t1,t2,0
+  20:	02f3f37b          	cv.add.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-add-sci-b-pass.s
new file mode 100644
index 00000000000..3502bc197be
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sci-b-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.add.sci.b x0, x0, 20
+    cv.add.sci.b x1, x1, 20
+    cv.add.sci.b x2, x2, 20
+    cv.add.sci.b x8, x8, 20
+    cv.add.sci.b x20, x20, 20
+    cv.add.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.add.sci.b x6, x7, -32
+    cv.add.sci.b x6, x7, 0
+    cv.add.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-add-sci-h-fail.d
new file mode 100644
index 00000000000..0903b08b12a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-sci-h-fail.s
+#error_output: cv-simd-add-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-add-sci-h-fail.l
new file mode 100644
index 00000000000..2f0656f83a3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.add.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.add.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-add-sci-h-fail.s
new file mode 100644
index 00000000000..538864a7f48
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.add.sci.h x32, x32, 20
+    cv.add.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.add.sci.h x6, x7, -33
+    cv.add.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-add-sci-h-pass.d
new file mode 100644
index 00000000000..8feb432283e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	00a0607b          	cv.add.sci.h	zero,zero,20
+   4:	00a0e0fb          	cv.add.sci.h	ra,ra,20
+   8:	00a1617b          	cv.add.sci.h	sp,sp,20
+   c:	00a4647b          	cv.add.sci.h	s0,s0,20
+  10:	00aa6a7b          	cv.add.sci.h	s4,s4,20
+  14:	00afeffb          	cv.add.sci.h	t6,t6,20
+  18:	0103e37b          	cv.add.sci.h	t1,t2,-32
+  1c:	0003e37b          	cv.add.sci.h	t1,t2,0
+  20:	02f3e37b          	cv.add.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-add-sci-h-pass.s
new file mode 100644
index 00000000000..6ce7055482b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sci-h-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.add.sci.h x0, x0, 20
+    cv.add.sci.h x1, x1, 20
+    cv.add.sci.h x2, x2, 20
+    cv.add.sci.h x8, x8, 20
+    cv.add.sci.h x20, x20, 20
+    cv.add.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.add.sci.h x6, x7, -32
+    cv.add.sci.h x6, x7, 0
+    cv.add.sci.h x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-and-b-fail.d
new file mode 100644
index 00000000000..90dcc73303d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-and-b-fail.s
+#error_output: cv-simd-and-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-and-b-fail.l
new file mode 100644
index 00000000000..18102aad53f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.and.b x32,x32,x32'
+.*: Error: illegal operands `cv.and.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-and-b-fail.s
new file mode 100644
index 00000000000..576d7feecf6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.and.b x32, x32, x32
+    cv.and.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-and-b-pass.d
new file mode 100644
index 00000000000..3c04c58671c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-and-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	6800107b          	cv.and.b	zero,zero,zero
+   4:	681090fb          	cv.and.b	ra,ra,ra
+   8:	6821117b          	cv.and.b	sp,sp,sp
+   c:	6884147b          	cv.and.b	s0,s0,s0
+  10:	694a1a7b          	cv.and.b	s4,s4,s4
+  14:	69ff9ffb          	cv.and.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-and-b-pass.s
new file mode 100644
index 00000000000..84bd68710fa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.and.b x0, x0, x0
+    cv.and.b x1, x1, x1
+    cv.and.b x2, x2, x2
+    cv.and.b x8, x8, x8
+    cv.and.b x20, x20, x20
+    cv.and.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-and-h-fail.d
new file mode 100644
index 00000000000..8afc79a69b7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-and-h-fail.s
+#error_output: cv-simd-and-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-and-h-fail.l
new file mode 100644
index 00000000000..a12d6a349db
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.and.h x32,x32,x32'
+.*: Error: illegal operands `cv.and.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-and-h-fail.s
new file mode 100644
index 00000000000..f60f7afbcaf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.and.h x32, x32, x32
+    cv.and.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-and-h-pass.d
new file mode 100644
index 00000000000..543d22a8acc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-and-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	6800007b          	cv.and.h	zero,zero,zero
+   4:	681080fb          	cv.and.h	ra,ra,ra
+   8:	6821017b          	cv.and.h	sp,sp,sp
+   c:	6884047b          	cv.and.h	s0,s0,s0
+  10:	694a0a7b          	cv.and.h	s4,s4,s4
+  14:	69ff8ffb          	cv.and.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-and-h-pass.s
new file mode 100644
index 00000000000..776fce71297
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.and.h x0, x0, x0
+    cv.and.h x1, x1, x1
+    cv.and.h x2, x2, x2
+    cv.and.h x8, x8, x8
+    cv.and.h x20, x20, x20
+    cv.and.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-and-sc-b-fail.d
new file mode 100644
index 00000000000..6144978cf6c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-and-sc-b-fail.s
+#error_output: cv-simd-and-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-and-sc-b-fail.l
new file mode 100644
index 00000000000..cf9dd0e2935
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.and.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.and.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-and-sc-b-fail.s
new file mode 100644
index 00000000000..77e76d667b6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.and.sc.b x32, x32, x32
+    cv.and.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-and-sc-b-pass.d
new file mode 100644
index 00000000000..303b08034ef
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-and-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	6800507b          	cv.and.sc.b	zero,zero,zero
+   4:	6810d0fb          	cv.and.sc.b	ra,ra,ra
+   8:	6821517b          	cv.and.sc.b	sp,sp,sp
+   c:	6884547b          	cv.and.sc.b	s0,s0,s0
+  10:	694a5a7b          	cv.and.sc.b	s4,s4,s4
+  14:	69ffdffb          	cv.and.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-and-sc-b-pass.s
new file mode 100644
index 00000000000..d6b116a7bca
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.and.sc.b x0, x0, x0
+    cv.and.sc.b x1, x1, x1
+    cv.and.sc.b x2, x2, x2
+    cv.and.sc.b x8, x8, x8
+    cv.and.sc.b x20, x20, x20
+    cv.and.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-and-sc-h-fail.d
new file mode 100644
index 00000000000..c8bb0149d9a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-and-sc-h-fail.s
+#error_output: cv-simd-and-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-and-sc-h-fail.l
new file mode 100644
index 00000000000..cc0e3329db6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.and.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.and.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-and-sc-h-fail.s
new file mode 100644
index 00000000000..cfdc62d6512
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.and.sc.h x32, x32, x32
+    cv.and.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-and-sc-h-pass.d
new file mode 100644
index 00000000000..66eee81b941
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-and-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	6800407b          	cv.and.sc.h	zero,zero,zero
+   4:	6810c0fb          	cv.and.sc.h	ra,ra,ra
+   8:	6821417b          	cv.and.sc.h	sp,sp,sp
+   c:	6884447b          	cv.and.sc.h	s0,s0,s0
+  10:	694a4a7b          	cv.and.sc.h	s4,s4,s4
+  14:	69ffcffb          	cv.and.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-and-sc-h-pass.s
new file mode 100644
index 00000000000..a3ae1596c13
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.and.sc.h x0, x0, x0
+    cv.and.sc.h x1, x1, x1
+    cv.and.sc.h x2, x2, x2
+    cv.and.sc.h x8, x8, x8
+    cv.and.sc.h x20, x20, x20
+    cv.and.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-and-sci-b-fail.d
new file mode 100644
index 00000000000..f208bb9600e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-and-sci-b-fail.s
+#error_output: cv-simd-and-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-and-sci-b-fail.l
new file mode 100644
index 00000000000..a259452d78d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.and.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.and.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-and-sci-b-fail.s
new file mode 100644
index 00000000000..842278fb71f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.and.sci.b x32, x32, 20
+    cv.and.sci.b x33, x33, 20
+    #Boundary Ibmediate Values Test
+    cv.and.sci.b x6, x7, -33
+    cv.and.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-and-sci-b-pass.d
new file mode 100644
index 00000000000..df234b3bfe1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-and-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	68a0707b          	cv.and.sci.b	zero,zero,20
+   4:	68a0f0fb          	cv.and.sci.b	ra,ra,20
+   8:	68a1717b          	cv.and.sci.b	sp,sp,20
+   c:	68a4747b          	cv.and.sci.b	s0,s0,20
+  10:	68aa7a7b          	cv.and.sci.b	s4,s4,20
+  14:	68affffb          	cv.and.sci.b	t6,t6,20
+  18:	6903f37b          	cv.and.sci.b	t1,t2,-32
+  1c:	6803f37b          	cv.and.sci.b	t1,t2,0
+  20:	6af3f37b          	cv.and.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-and-sci-b-pass.s
new file mode 100644
index 00000000000..33aa654af1f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sci-b-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.and.sci.b x0, x0, 20
+    cv.and.sci.b x1, x1, 20
+    cv.and.sci.b x2, x2, 20
+    cv.and.sci.b x8, x8, 20
+    cv.and.sci.b x20, x20, 20
+    cv.and.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.and.sci.b x6, x7, -32
+    cv.and.sci.b x6, x7, 0
+    cv.and.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-and-sci-h-fail.d
new file mode 100644
index 00000000000..3f17a36db14
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-and-sci-h-fail.s
+#error_output: cv-simd-and-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-and-sci-h-fail.l
new file mode 100644
index 00000000000..3564a7fce86
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.and.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.and.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-and-sci-h-fail.s
new file mode 100644
index 00000000000..b510be5346a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.and.sci.h x32, x32, 20
+    cv.and.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.and.sci.h x6, x7, -33
+    cv.and.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-and-sci-h-pass.d
new file mode 100644
index 00000000000..e9f68737c8e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-and-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	68a0607b          	cv.and.sci.h	zero,zero,20
+   4:	68a0e0fb          	cv.and.sci.h	ra,ra,20
+   8:	68a1617b          	cv.and.sci.h	sp,sp,20
+   c:	68a4647b          	cv.and.sci.h	s0,s0,20
+  10:	68aa6a7b          	cv.and.sci.h	s4,s4,20
+  14:	68afeffb          	cv.and.sci.h	t6,t6,20
+  18:	6903e37b          	cv.and.sci.h	t1,t2,-32
+  1c:	6803e37b          	cv.and.sci.h	t1,t2,0
+  20:	6af3e37b          	cv.and.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-and-sci-h-pass.s
new file mode 100644
index 00000000000..5c06d000996
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sci-h-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.and.sci.h x0, x0, 20
+    cv.and.sci.h x1, x1, 20
+    cv.and.sci.h x2, x2, 20
+    cv.and.sci.h x8, x8, 20
+    cv.and.sci.h x20, x20, 20
+    cv.and.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.and.sci.h x6, x7, -32
+    cv.and.sci.h x6, x7, 0
+    cv.and.sci.h x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-avg-b-fail.d
new file mode 100644
index 00000000000..8e1fedc4f4b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avg-b-fail.s
+#error_output: cv-simd-avg-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-avg-b-fail.l
new file mode 100644
index 00000000000..7b693315d5e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.avg.b x32,x32,x32'
+.*: Error: illegal operands `cv.avg.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-avg-b-fail.s
new file mode 100644
index 00000000000..0488df691e2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.avg.b x32, x32, x32
+    cv.avg.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-avg-b-pass.d
new file mode 100644
index 00000000000..2f6b39e151a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avg-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1000107b          	cv.avg.b	zero,zero,zero
+   4:	101090fb          	cv.avg.b	ra,ra,ra
+   8:	1021117b          	cv.avg.b	sp,sp,sp
+   c:	1084147b          	cv.avg.b	s0,s0,s0
+  10:	114a1a7b          	cv.avg.b	s4,s4,s4
+  14:	11ff9ffb          	cv.avg.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-avg-b-pass.s
new file mode 100644
index 00000000000..bc299360a7d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.avg.b x0, x0, x0
+    cv.avg.b x1, x1, x1
+    cv.avg.b x2, x2, x2
+    cv.avg.b x8, x8, x8
+    cv.avg.b x20, x20, x20
+    cv.avg.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-avg-h-fail.d
new file mode 100644
index 00000000000..027118446fb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avg-h-fail.s
+#error_output: cv-simd-avg-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-avg-h-fail.l
new file mode 100644
index 00000000000..387e31e1f04
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.avg.h x32,x32,x32'
+.*: Error: illegal operands `cv.avg.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-avg-h-fail.s
new file mode 100644
index 00000000000..bd8f8bb5f40
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.avg.h x32, x32, x32
+    cv.avg.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-avg-h-pass.d
new file mode 100644
index 00000000000..044b292c450
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avg-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1000007b          	cv.avg.h	zero,zero,zero
+   4:	101080fb          	cv.avg.h	ra,ra,ra
+   8:	1021017b          	cv.avg.h	sp,sp,sp
+   c:	1084047b          	cv.avg.h	s0,s0,s0
+  10:	114a0a7b          	cv.avg.h	s4,s4,s4
+  14:	11ff8ffb          	cv.avg.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-avg-h-pass.s
new file mode 100644
index 00000000000..e2558e322d8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.avg.h x0, x0, x0
+    cv.avg.h x1, x1, x1
+    cv.avg.h x2, x2, x2
+    cv.avg.h x8, x8, x8
+    cv.avg.h x20, x20, x20
+    cv.avg.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-avg-sc-b-fail.d
new file mode 100644
index 00000000000..a452363f4d7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avg-sc-b-fail.s
+#error_output: cv-simd-avg-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-avg-sc-b-fail.l
new file mode 100644
index 00000000000..dd22457c92d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.avg.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.avg.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-avg-sc-b-fail.s
new file mode 100644
index 00000000000..b40ce82d61b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.avg.sc.b x32, x32, x32
+    cv.avg.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-avg-sc-b-pass.d
new file mode 100644
index 00000000000..24c9362fec0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avg-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1000507b          	cv.avg.sc.b	zero,zero,zero
+   4:	1010d0fb          	cv.avg.sc.b	ra,ra,ra
+   8:	1021517b          	cv.avg.sc.b	sp,sp,sp
+   c:	1084547b          	cv.avg.sc.b	s0,s0,s0
+  10:	114a5a7b          	cv.avg.sc.b	s4,s4,s4
+  14:	11ffdffb          	cv.avg.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-avg-sc-b-pass.s
new file mode 100644
index 00000000000..a78c7d56c1e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.avg.sc.b x0, x0, x0
+    cv.avg.sc.b x1, x1, x1
+    cv.avg.sc.b x2, x2, x2
+    cv.avg.sc.b x8, x8, x8
+    cv.avg.sc.b x20, x20, x20
+    cv.avg.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-avg-sc-h-fail.d
new file mode 100644
index 00000000000..5e48b003006
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avg-sc-h-fail.s
+#error_output: cv-simd-avg-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-avg-sc-h-fail.l
new file mode 100644
index 00000000000..3df6422a9d4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.avg.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.avg.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-avg-sc-h-fail.s
new file mode 100644
index 00000000000..fa3a4d2e700
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.avg.sc.h x32, x32, x32
+    cv.avg.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-avg-sc-h-pass.d
new file mode 100644
index 00000000000..f4cd1bcfe73
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avg-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1000407b          	cv.avg.sc.h	zero,zero,zero
+   4:	1010c0fb          	cv.avg.sc.h	ra,ra,ra
+   8:	1021417b          	cv.avg.sc.h	sp,sp,sp
+   c:	1084447b          	cv.avg.sc.h	s0,s0,s0
+  10:	114a4a7b          	cv.avg.sc.h	s4,s4,s4
+  14:	11ffcffb          	cv.avg.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-avg-sc-h-pass.s
new file mode 100644
index 00000000000..28bf8536fa3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.avg.sc.h x0, x0, x0
+    cv.avg.sc.h x1, x1, x1
+    cv.avg.sc.h x2, x2, x2
+    cv.avg.sc.h x8, x8, x8
+    cv.avg.sc.h x20, x20, x20
+    cv.avg.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-avg-sci-b-fail.d
new file mode 100644
index 00000000000..166015a1156
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avg-sci-b-fail.s
+#error_output: cv-simd-avg-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-avg-sci-b-fail.l
new file mode 100644
index 00000000000..1d66f52499b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.avg.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.avg.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-avg-sci-b-fail.s
new file mode 100644
index 00000000000..dd0eb100064
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.avg.sci.b x32, x32, 20
+    cv.avg.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.avg.sci.b x6, x7, -33
+    cv.avg.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-avg-sci-b-pass.d
new file mode 100644
index 00000000000..023b3201d14
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avg-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	10a0707b          	cv.avg.sci.b	zero,zero,20
+   4:	10a0f0fb          	cv.avg.sci.b	ra,ra,20
+   8:	10a1717b          	cv.avg.sci.b	sp,sp,20
+   c:	10a4747b          	cv.avg.sci.b	s0,s0,20
+  10:	10aa7a7b          	cv.avg.sci.b	s4,s4,20
+  14:	10affffb          	cv.avg.sci.b	t6,t6,20
+  18:	1103f37b          	cv.avg.sci.b	t1,t2,-32
+  1c:	1003f37b          	cv.avg.sci.b	t1,t2,0
+  20:	12f3f37b          	cv.avg.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-avg-sci-b-pass.s
new file mode 100644
index 00000000000..cef5caba22c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sci-b-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.avg.sci.b x0, x0, 20
+    cv.avg.sci.b x1, x1, 20
+    cv.avg.sci.b x2, x2, 20
+    cv.avg.sci.b x8, x8, 20
+    cv.avg.sci.b x20, x20, 20
+    cv.avg.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.avg.sci.b x6, x7, -32
+    cv.avg.sci.b x6, x7, 0
+    cv.avg.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-avg-sci-h-fail.d
new file mode 100644
index 00000000000..d995769504d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avg-sci-h-fail.s
+#error_output: cv-simd-avg-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-avg-sci-h-fail.l
new file mode 100644
index 00000000000..a5bc7a5cdb9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.avg.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.avg.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-avg-sci-h-fail.s
new file mode 100644
index 00000000000..41144e20d77
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.avg.sci.h x32, x32, 20
+    cv.avg.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.avg.sci.h x6, x7, -33
+    cv.avg.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-avg-sci-h-pass.d
new file mode 100644
index 00000000000..43e6089b2b9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avg-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	10a0607b          	cv.avg.sci.h	zero,zero,20
+   4:	10a0e0fb          	cv.avg.sci.h	ra,ra,20
+   8:	10a1617b          	cv.avg.sci.h	sp,sp,20
+   c:	10a4647b          	cv.avg.sci.h	s0,s0,20
+  10:	10aa6a7b          	cv.avg.sci.h	s4,s4,20
+  14:	10afeffb          	cv.avg.sci.h	t6,t6,20
+  18:	1103e37b          	cv.avg.sci.h	t1,t2,-32
+  1c:	1003e37b          	cv.avg.sci.h	t1,t2,0
+  20:	12f3e37b          	cv.avg.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-avg-sci-h-pass.s
new file mode 100644
index 00000000000..a489cbbdaac
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sci-h-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.avg.sci.h x0, x0, 20
+    cv.avg.sci.h x1, x1, 20
+    cv.avg.sci.h x2, x2, 20
+    cv.avg.sci.h x8, x8, 20
+    cv.avg.sci.h x20, x20, 20
+    cv.avg.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.avg.sci.h x6, x7, -32
+    cv.avg.sci.h x6, x7, 0
+    cv.avg.sci.h x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-avgu-b-fail.d
new file mode 100644
index 00000000000..af1ddbe83ca
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avgu-b-fail.s
+#error_output: cv-simd-avgu-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-avgu-b-fail.l
new file mode 100644
index 00000000000..945d5b11ad7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.avgu.b x32,x32,x32'
+.*: Error: illegal operands `cv.avgu.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-avgu-b-fail.s
new file mode 100644
index 00000000000..8401e7c18bc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.avgu.b x32, x32, x32
+    cv.avgu.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-avgu-b-pass.d
new file mode 100644
index 00000000000..f7e548a3ca2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avgu-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1800107b          	cv.avgu.b	zero,zero,zero
+   4:	181090fb          	cv.avgu.b	ra,ra,ra
+   8:	1821117b          	cv.avgu.b	sp,sp,sp
+   c:	1884147b          	cv.avgu.b	s0,s0,s0
+  10:	194a1a7b          	cv.avgu.b	s4,s4,s4
+  14:	19ff9ffb          	cv.avgu.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-avgu-b-pass.s
new file mode 100644
index 00000000000..afea2b753de
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.avgu.b x0, x0, x0
+    cv.avgu.b x1, x1, x1
+    cv.avgu.b x2, x2, x2
+    cv.avgu.b x8, x8, x8
+    cv.avgu.b x20, x20, x20
+    cv.avgu.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-avgu-h-fail.d
new file mode 100644
index 00000000000..caabe1b56af
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avgu-h-fail.s
+#error_output: cv-simd-avgu-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-avgu-h-fail.l
new file mode 100644
index 00000000000..7c8f1554713
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.avgu.h x32,x32,x32'
+.*: Error: illegal operands `cv.avgu.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-avgu-h-fail.s
new file mode 100644
index 00000000000..0d68904a760
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.avgu.h x32, x32, x32
+    cv.avgu.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-avgu-h-pass.d
new file mode 100644
index 00000000000..21d3e815119
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avgu-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1800007b          	cv.avgu.h	zero,zero,zero
+   4:	181080fb          	cv.avgu.h	ra,ra,ra
+   8:	1821017b          	cv.avgu.h	sp,sp,sp
+   c:	1884047b          	cv.avgu.h	s0,s0,s0
+  10:	194a0a7b          	cv.avgu.h	s4,s4,s4
+  14:	19ff8ffb          	cv.avgu.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-avgu-h-pass.s
new file mode 100644
index 00000000000..2bf5b99bcb4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.avgu.h x0, x0, x0
+    cv.avgu.h x1, x1, x1
+    cv.avgu.h x2, x2, x2
+    cv.avgu.h x8, x8, x8
+    cv.avgu.h x20, x20, x20
+    cv.avgu.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-b-fail.d
new file mode 100644
index 00000000000..9528a0ef082
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avgu-sc-b-fail.s
+#error_output: cv-simd-avgu-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-b-fail.l
new file mode 100644
index 00000000000..477e1703fd2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.avgu.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.avgu.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-b-fail.s
new file mode 100644
index 00000000000..6d6f0814829
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.avgu.sc.b x32, x32, x32
+    cv.avgu.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-b-pass.d
new file mode 100644
index 00000000000..4b7819c5705
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avgu-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1800507b          	cv.avgu.sc.b	zero,zero,zero
+   4:	1810d0fb          	cv.avgu.sc.b	ra,ra,ra
+   8:	1821517b          	cv.avgu.sc.b	sp,sp,sp
+   c:	1884547b          	cv.avgu.sc.b	s0,s0,s0
+  10:	194a5a7b          	cv.avgu.sc.b	s4,s4,s4
+  14:	19ffdffb          	cv.avgu.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-b-pass.s
new file mode 100644
index 00000000000..a22ee098d2b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.avgu.sc.b x0, x0, x0
+    cv.avgu.sc.b x1, x1, x1
+    cv.avgu.sc.b x2, x2, x2
+    cv.avgu.sc.b x8, x8, x8
+    cv.avgu.sc.b x20, x20, x20
+    cv.avgu.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-h-fail.d
new file mode 100644
index 00000000000..63ae30b9c62
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avgu-sc-h-fail.s
+#error_output: cv-simd-avgu-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-h-fail.l
new file mode 100644
index 00000000000..b4192d02b66
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.avgu.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.avgu.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-h-fail.s
new file mode 100644
index 00000000000..f42e01e2e2c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.avgu.sc.h x32, x32, x32
+    cv.avgu.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-h-pass.d
new file mode 100644
index 00000000000..c084dbd8aed
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avgu-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1800407b          	cv.avgu.sc.h	zero,zero,zero
+   4:	1810c0fb          	cv.avgu.sc.h	ra,ra,ra
+   8:	1821417b          	cv.avgu.sc.h	sp,sp,sp
+   c:	1884447b          	cv.avgu.sc.h	s0,s0,s0
+  10:	194a4a7b          	cv.avgu.sc.h	s4,s4,s4
+  14:	19ffcffb          	cv.avgu.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-h-pass.s
new file mode 100644
index 00000000000..ea6ad17c56e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.avgu.sc.h x0, x0, x0
+    cv.avgu.sc.h x1, x1, x1
+    cv.avgu.sc.h x2, x2, x2
+    cv.avgu.sc.h x8, x8, x8
+    cv.avgu.sc.h x20, x20, x20
+    cv.avgu.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-fail.d
new file mode 100644
index 00000000000..071985022d0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avgu-sci-b-fail.s
+#error_output: cv-simd-avgu-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-fail.l
new file mode 100644
index 00000000000..241f8ae1341
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.avgu.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.avgu.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-fail.s
new file mode 100644
index 00000000000..ddf40939b69
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.avgu.sci.b x32, x32, 20
+    cv.avgu.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.avgu.sci.b x6, x7, -1
+    cv.avgu.sci.b x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-pass.d
new file mode 100644
index 00000000000..0668fe1848d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avgu-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	18a0707b          	cv.avgu.sci.b	zero,zero,20
+   4:	18a0f0fb          	cv.avgu.sci.b	ra,ra,20
+   8:	18a1717b          	cv.avgu.sci.b	sp,sp,20
+   c:	18a4747b          	cv.avgu.sci.b	s0,s0,20
+  10:	18aa7a7b          	cv.avgu.sci.b	s4,s4,20
+  14:	18affffb          	cv.avgu.sci.b	t6,t6,20
+  18:	1803f37b          	cv.avgu.sci.b	t1,t2,0
+  1c:	1bf3f37b          	cv.avgu.sci.b	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-pass.s
new file mode 100644
index 00000000000..dc8073603cc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.avgu.sci.b x0, x0, 20
+    cv.avgu.sci.b x1, x1, 20
+    cv.avgu.sci.b x2, x2, 20
+    cv.avgu.sci.b x8, x8, 20
+    cv.avgu.sci.b x20, x20, 20
+    cv.avgu.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.avgu.sci.b x6, x7, 0
+    cv.avgu.sci.b x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-h-fail.d
new file mode 100644
index 00000000000..398239769ff
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avgu-sci-h-fail.s
+#error_output: cv-simd-avgu-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-h-fail.l
new file mode 100644
index 00000000000..ec018bdd1ef
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.avgu.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.avgu.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-h-fail.s
new file mode 100644
index 00000000000..cae50e2320d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.avgu.sci.h x32, x32, 20
+    cv.avgu.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.avgu.sci.h x6, x7, -1
+    cv.avgu.sci.h x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-h-pass.d
new file mode 100644
index 00000000000..1f9902d0dc4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-h-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avgu-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	18a0607b          	cv.avgu.sci.h	zero,zero,20
+   4:	18a0e0fb          	cv.avgu.sci.h	ra,ra,20
+   8:	18a1617b          	cv.avgu.sci.h	sp,sp,20
+   c:	18a4647b          	cv.avgu.sci.h	s0,s0,20
+  10:	18aa6a7b          	cv.avgu.sci.h	s4,s4,20
+  14:	18afeffb          	cv.avgu.sci.h	t6,t6,20
+  18:	1803e37b          	cv.avgu.sci.h	t1,t2,0
+  1c:	1bf3e37b          	cv.avgu.sci.h	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-h-pass.s
new file mode 100644
index 00000000000..f638387199b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-h-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.avgu.sci.h x0, x0, 20
+    cv.avgu.sci.h x1, x1, 20
+    cv.avgu.sci.h x2, x2, 20
+    cv.avgu.sci.h x8, x8, 20
+    cv.avgu.sci.h x20, x20, 20
+    cv.avgu.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.avgu.sci.h x6, x7, 0
+    cv.avgu.sci.h x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpeq-b-fail.d
new file mode 100644
index 00000000000..2a3318d5dfe
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpeq-b-fail.s
+#error_output: cv-simd-cmpeq-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpeq-b-fail.l
new file mode 100644
index 00000000000..4aac9f46da2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpeq.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpeq.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpeq-b-fail.s
new file mode 100644
index 00000000000..a0f528ad7c1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpeq.b x32, x32, x32
+    cv.cmpeq.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpeq-b-pass.d
new file mode 100644
index 00000000000..bd2b2f9b0a6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpeq-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0400107b          	cv.cmpeq.b	zero,zero,zero
+   4:	041090fb          	cv.cmpeq.b	ra,ra,ra
+   8:	0421117b          	cv.cmpeq.b	sp,sp,sp
+   c:	0484147b          	cv.cmpeq.b	s0,s0,s0
+  10:	054a1a7b          	cv.cmpeq.b	s4,s4,s4
+  14:	05ff9ffb          	cv.cmpeq.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpeq-b-pass.s
new file mode 100644
index 00000000000..a4875125eeb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpeq.b x0, x0, x0
+    cv.cmpeq.b x1, x1, x1
+    cv.cmpeq.b x2, x2, x2
+    cv.cmpeq.b x8, x8, x8
+    cv.cmpeq.b x20, x20, x20
+    cv.cmpeq.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpeq-h-fail.d
new file mode 100644
index 00000000000..b258f49d2ec
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpeq-h-fail.s
+#error_output: cv-simd-cmpeq-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpeq-h-fail.l
new file mode 100644
index 00000000000..a4a2d73299c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpeq.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpeq.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpeq-h-fail.s
new file mode 100644
index 00000000000..72008f735cd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpeq.h x32, x32, x32
+    cv.cmpeq.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpeq-h-pass.d
new file mode 100644
index 00000000000..f5e54008311
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpeq-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0400007b          	cv.cmpeq.h	zero,zero,zero
+   4:	041080fb          	cv.cmpeq.h	ra,ra,ra
+   8:	0421017b          	cv.cmpeq.h	sp,sp,sp
+   c:	0484047b          	cv.cmpeq.h	s0,s0,s0
+  10:	054a0a7b          	cv.cmpeq.h	s4,s4,s4
+  14:	05ff8ffb          	cv.cmpeq.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpeq-h-pass.s
new file mode 100644
index 00000000000..5bef92b2dbe
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpeq.h x0, x0, x0
+    cv.cmpeq.h x1, x1, x1
+    cv.cmpeq.h x2, x2, x2
+    cv.cmpeq.h x8, x8, x8
+    cv.cmpeq.h x20, x20, x20
+    cv.cmpeq.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-b-fail.d
new file mode 100644
index 00000000000..e2fe218cdd4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpeq-sc-b-fail.s
+#error_output: cv-simd-cmpeq-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-b-fail.l
new file mode 100644
index 00000000000..43c0f88c42b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpeq.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpeq.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-b-fail.s
new file mode 100644
index 00000000000..46edcf3b987
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpeq.sc.b x32, x32, x32
+    cv.cmpeq.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-b-pass.d
new file mode 100644
index 00000000000..81d4ee3964c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpeq-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0400507b          	cv.cmpeq.sc.b	zero,zero,zero
+   4:	0410d0fb          	cv.cmpeq.sc.b	ra,ra,ra
+   8:	0421517b          	cv.cmpeq.sc.b	sp,sp,sp
+   c:	0484547b          	cv.cmpeq.sc.b	s0,s0,s0
+  10:	054a5a7b          	cv.cmpeq.sc.b	s4,s4,s4
+  14:	05ffdffb          	cv.cmpeq.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-b-pass.s
new file mode 100644
index 00000000000..73808e038fa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpeq.sc.b x0, x0, x0
+    cv.cmpeq.sc.b x1, x1, x1
+    cv.cmpeq.sc.b x2, x2, x2
+    cv.cmpeq.sc.b x8, x8, x8
+    cv.cmpeq.sc.b x20, x20, x20
+    cv.cmpeq.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-h-fail.d
new file mode 100644
index 00000000000..cc28bad796d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpeq-sc-h-fail.s
+#error_output: cv-simd-cmpeq-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-h-fail.l
new file mode 100644
index 00000000000..13275a99112
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpeq.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpeq.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-h-fail.s
new file mode 100644
index 00000000000..24e211af754
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpeq.sc.h x32, x32, x32
+    cv.cmpeq.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-h-pass.d
new file mode 100644
index 00000000000..11a5774ebc9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpeq-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0400407b          	cv.cmpeq.sc.h	zero,zero,zero
+   4:	0410c0fb          	cv.cmpeq.sc.h	ra,ra,ra
+   8:	0421417b          	cv.cmpeq.sc.h	sp,sp,sp
+   c:	0484447b          	cv.cmpeq.sc.h	s0,s0,s0
+  10:	054a4a7b          	cv.cmpeq.sc.h	s4,s4,s4
+  14:	05ffcffb          	cv.cmpeq.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-h-pass.s
new file mode 100644
index 00000000000..fc8f7686695
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpeq.sc.h x0, x0, x0
+    cv.cmpeq.sc.h x1, x1, x1
+    cv.cmpeq.sc.h x2, x2, x2
+    cv.cmpeq.sc.h x8, x8, x8
+    cv.cmpeq.sc.h x20, x20, x20
+    cv.cmpeq.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-b-fail.d
new file mode 100644
index 00000000000..ee63eaa3a7c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpeq-sci-b-fail.s
+#error_output: cv-simd-cmpeq-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-b-fail.l
new file mode 100644
index 00000000000..0d488f66ce1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpeq.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.cmpeq.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-b-fail.s
new file mode 100644
index 00000000000..6cf4cb09612
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.cmpeq.sci.b x32, x32, 20
+    cv.cmpeq.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpeq.sci.b x6, x7, -33
+    cv.cmpeq.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-b-pass.d
new file mode 100644
index 00000000000..c0dead860d9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpeq-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	04a0707b          	cv.cmpeq.sci.b	zero,zero,20
+   4:	04a0f0fb          	cv.cmpeq.sci.b	ra,ra,20
+   8:	04a1717b          	cv.cmpeq.sci.b	sp,sp,20
+   c:	04a4747b          	cv.cmpeq.sci.b	s0,s0,20
+  10:	04aa7a7b          	cv.cmpeq.sci.b	s4,s4,20
+  14:	04affffb          	cv.cmpeq.sci.b	t6,t6,20
+  18:	0503f37b          	cv.cmpeq.sci.b	t1,t2,-32
+  1c:	0403f37b          	cv.cmpeq.sci.b	t1,t2,0
+  20:	06f3f37b          	cv.cmpeq.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-b-pass.s
new file mode 100644
index 00000000000..aa079a6780b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-b-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.cmpeq.sci.b x0, x0, 20
+    cv.cmpeq.sci.b x1, x1, 20
+    cv.cmpeq.sci.b x2, x2, 20
+    cv.cmpeq.sci.b x8, x8, 20
+    cv.cmpeq.sci.b x20, x20, 20
+    cv.cmpeq.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.cmpeq.sci.b x6, x7, -32
+    cv.cmpeq.sci.b x6, x7, 0
+    cv.cmpeq.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-h-fail.d
new file mode 100644
index 00000000000..878e99672f7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpeq-sci-h-fail.s
+#error_output: cv-simd-cmpeq-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-h-fail.l
new file mode 100644
index 00000000000..77a6cd56bf1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpeq.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.cmpeq.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-h-fail.s
new file mode 100644
index 00000000000..677b67ce279
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.cmpeq.sci.h x32, x32, 20
+    cv.cmpeq.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpeq.sci.h x6, x7, -33
+    cv.cmpeq.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-h-pass.d
new file mode 100644
index 00000000000..302d2f80cc3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpeq-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	04a0607b          	cv.cmpeq.sci.h	zero,zero,20
+   4:	04a0e0fb          	cv.cmpeq.sci.h	ra,ra,20
+   8:	04a1617b          	cv.cmpeq.sci.h	sp,sp,20
+   c:	04a4647b          	cv.cmpeq.sci.h	s0,s0,20
+  10:	04aa6a7b          	cv.cmpeq.sci.h	s4,s4,20
+  14:	04afeffb          	cv.cmpeq.sci.h	t6,t6,20
+  18:	0503e37b          	cv.cmpeq.sci.h	t1,t2,-32
+  1c:	0403e37b          	cv.cmpeq.sci.h	t1,t2,0
+  20:	06f3e37b          	cv.cmpeq.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-h-pass.s
new file mode 100644
index 00000000000..c5f00ca2070
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-h-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.cmpeq.sci.h x0, x0, 20
+    cv.cmpeq.sci.h x1, x1, 20
+    cv.cmpeq.sci.h x2, x2, 20
+    cv.cmpeq.sci.h x8, x8, 20
+    cv.cmpeq.sci.h x20, x20, 20
+    cv.cmpeq.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.cmpeq.sci.h x6, x7, -32
+    cv.cmpeq.sci.h x6, x7, 0
+    cv.cmpeq.sci.h x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpge-b-fail.d
new file mode 100644
index 00000000000..644f83b5692
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpge-b-fail.s
+#error_output: cv-simd-cmpge-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpge-b-fail.l
new file mode 100644
index 00000000000..a08e74fe104
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpge.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpge.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpge-b-fail.s
new file mode 100644
index 00000000000..a97fd9c1ac1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpge.b x32, x32, x32
+    cv.cmpge.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpge-b-pass.d
new file mode 100644
index 00000000000..029840c70d5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpge-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1c00107b          	cv.cmpge.b	zero,zero,zero
+   4:	1c1090fb          	cv.cmpge.b	ra,ra,ra
+   8:	1c21117b          	cv.cmpge.b	sp,sp,sp
+   c:	1c84147b          	cv.cmpge.b	s0,s0,s0
+  10:	1d4a1a7b          	cv.cmpge.b	s4,s4,s4
+  14:	1dff9ffb          	cv.cmpge.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpge-b-pass.s
new file mode 100644
index 00000000000..30f6576b832
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpge.b x0, x0, x0
+    cv.cmpge.b x1, x1, x1
+    cv.cmpge.b x2, x2, x2
+    cv.cmpge.b x8, x8, x8
+    cv.cmpge.b x20, x20, x20
+    cv.cmpge.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpge-h-fail.d
new file mode 100644
index 00000000000..7b7d123aa74
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpge-h-fail.s
+#error_output: cv-simd-cmpge-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpge-h-fail.l
new file mode 100644
index 00000000000..a9f0019ae95
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpge.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpge.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpge-h-fail.s
new file mode 100644
index 00000000000..04bd6e61f55
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpge.h x32, x32, x32
+    cv.cmpge.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpge-h-pass.d
new file mode 100644
index 00000000000..4ba0160c254
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpge-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1c00007b          	cv.cmpge.h	zero,zero,zero
+   4:	1c1080fb          	cv.cmpge.h	ra,ra,ra
+   8:	1c21017b          	cv.cmpge.h	sp,sp,sp
+   c:	1c84047b          	cv.cmpge.h	s0,s0,s0
+  10:	1d4a0a7b          	cv.cmpge.h	s4,s4,s4
+  14:	1dff8ffb          	cv.cmpge.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpge-h-pass.s
new file mode 100644
index 00000000000..83c9cbb7c5f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpge.h x0, x0, x0
+    cv.cmpge.h x1, x1, x1
+    cv.cmpge.h x2, x2, x2
+    cv.cmpge.h x8, x8, x8
+    cv.cmpge.h x20, x20, x20
+    cv.cmpge.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-b-fail.d
new file mode 100644
index 00000000000..996cd49af15
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpge-sc-b-fail.s
+#error_output: cv-simd-cmpge-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-b-fail.l
new file mode 100644
index 00000000000..2d73720e32c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpge.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpge.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-b-fail.s
new file mode 100644
index 00000000000..2282d53a132
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpge.sc.b x32, x32, x32
+    cv.cmpge.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-b-pass.d
new file mode 100644
index 00000000000..f00943ab68e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpge-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1c00507b          	cv.cmpge.sc.b	zero,zero,zero
+   4:	1c10d0fb          	cv.cmpge.sc.b	ra,ra,ra
+   8:	1c21517b          	cv.cmpge.sc.b	sp,sp,sp
+   c:	1c84547b          	cv.cmpge.sc.b	s0,s0,s0
+  10:	1d4a5a7b          	cv.cmpge.sc.b	s4,s4,s4
+  14:	1dffdffb          	cv.cmpge.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-b-pass.s
new file mode 100644
index 00000000000..d70ff7dbadb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpge.sc.b x0, x0, x0
+    cv.cmpge.sc.b x1, x1, x1
+    cv.cmpge.sc.b x2, x2, x2
+    cv.cmpge.sc.b x8, x8, x8
+    cv.cmpge.sc.b x20, x20, x20
+    cv.cmpge.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-h-fail.d
new file mode 100644
index 00000000000..e74c232991a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpge-sc-h-fail.s
+#error_output: cv-simd-cmpge-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-h-fail.l
new file mode 100644
index 00000000000..97c55e41c90
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpge.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpge.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-h-fail.s
new file mode 100644
index 00000000000..a753d789c82
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpge.sc.h x32, x32, x32
+    cv.cmpge.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-h-pass.d
new file mode 100644
index 00000000000..d44d2258a42
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpge-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1c00407b          	cv.cmpge.sc.h	zero,zero,zero
+   4:	1c10c0fb          	cv.cmpge.sc.h	ra,ra,ra
+   8:	1c21417b          	cv.cmpge.sc.h	sp,sp,sp
+   c:	1c84447b          	cv.cmpge.sc.h	s0,s0,s0
+  10:	1d4a4a7b          	cv.cmpge.sc.h	s4,s4,s4
+  14:	1dffcffb          	cv.cmpge.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-h-pass.s
new file mode 100644
index 00000000000..7013748e8ec
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpge.sc.h x0, x0, x0
+    cv.cmpge.sc.h x1, x1, x1
+    cv.cmpge.sc.h x2, x2, x2
+    cv.cmpge.sc.h x8, x8, x8
+    cv.cmpge.sc.h x20, x20, x20
+    cv.cmpge.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-b-fail.d
new file mode 100644
index 00000000000..80122bf062d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpge-sci-b-fail.s
+#error_output: cv-simd-cmpge-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-b-fail.l
new file mode 100644
index 00000000000..cfebdde1262
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpge.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.cmpge.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-b-fail.s
new file mode 100644
index 00000000000..3a1cda683e4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.cmpge.sci.b x32, x32, 20
+    cv.cmpge.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpge.sci.b x6, x7, -33
+    cv.cmpge.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-b-pass.d
new file mode 100644
index 00000000000..c7c0838d69e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpge-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1ca0707b          	cv.cmpge.sci.b	zero,zero,20
+   4:	1ca0f0fb          	cv.cmpge.sci.b	ra,ra,20
+   8:	1ca1717b          	cv.cmpge.sci.b	sp,sp,20
+   c:	1ca4747b          	cv.cmpge.sci.b	s0,s0,20
+  10:	1caa7a7b          	cv.cmpge.sci.b	s4,s4,20
+  14:	1caffffb          	cv.cmpge.sci.b	t6,t6,20
+  18:	1d03f37b          	cv.cmpge.sci.b	t1,t2,-32
+  1c:	1c03f37b          	cv.cmpge.sci.b	t1,t2,0
+  20:	1ef3f37b          	cv.cmpge.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-b-pass.s
new file mode 100644
index 00000000000..34a141f45fe
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-b-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.cmpge.sci.b x0, x0, 20
+    cv.cmpge.sci.b x1, x1, 20
+    cv.cmpge.sci.b x2, x2, 20
+    cv.cmpge.sci.b x8, x8, 20
+    cv.cmpge.sci.b x20, x20, 20
+    cv.cmpge.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.cmpge.sci.b x6, x7, -32
+    cv.cmpge.sci.b x6, x7, 0
+    cv.cmpge.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-h-fail.d
new file mode 100644
index 00000000000..b5a66ffd965
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpge-sci-h-fail.s
+#error_output: cv-simd-cmpge-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-h-fail.l
new file mode 100644
index 00000000000..b29956b0d6c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpge.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.cmpge.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-h-fail.s
new file mode 100644
index 00000000000..67c61e70c2b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.cmpge.sci.h x32, x32, 20
+    cv.cmpge.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpge.sci.h x6, x7, -33
+    cv.cmpge.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-h-pass.d
new file mode 100644
index 00000000000..4651c97bf4c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpge-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1ca0607b          	cv.cmpge.sci.h	zero,zero,20
+   4:	1ca0e0fb          	cv.cmpge.sci.h	ra,ra,20
+   8:	1ca1617b          	cv.cmpge.sci.h	sp,sp,20
+   c:	1ca4647b          	cv.cmpge.sci.h	s0,s0,20
+  10:	1caa6a7b          	cv.cmpge.sci.h	s4,s4,20
+  14:	1cafeffb          	cv.cmpge.sci.h	t6,t6,20
+  18:	1d03e37b          	cv.cmpge.sci.h	t1,t2,-32
+  1c:	1c03e37b          	cv.cmpge.sci.h	t1,t2,0
+  20:	1ef3e37b          	cv.cmpge.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-h-pass.s
new file mode 100644
index 00000000000..1ac8e796e6c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-h-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.cmpge.sci.h x0, x0, 20
+    cv.cmpge.sci.h x1, x1, 20
+    cv.cmpge.sci.h x2, x2, 20
+    cv.cmpge.sci.h x8, x8, 20
+    cv.cmpge.sci.h x20, x20, 20
+    cv.cmpge.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.cmpge.sci.h x6, x7, -32
+    cv.cmpge.sci.h x6, x7, 0
+    cv.cmpge.sci.h x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-b-fail.d
new file mode 100644
index 00000000000..52fbe0058e4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgeu-b-fail.s
+#error_output: cv-simd-cmpgeu-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-b-fail.l
new file mode 100644
index 00000000000..a5765fd2abb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgeu.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpgeu.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-b-fail.s
new file mode 100644
index 00000000000..73f313280cf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpgeu.b x32, x32, x32
+    cv.cmpgeu.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-b-pass.d
new file mode 100644
index 00000000000..755a62d7636
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgeu-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3c00107b          	cv.cmpgeu.b	zero,zero,zero
+   4:	3c1090fb          	cv.cmpgeu.b	ra,ra,ra
+   8:	3c21117b          	cv.cmpgeu.b	sp,sp,sp
+   c:	3c84147b          	cv.cmpgeu.b	s0,s0,s0
+  10:	3d4a1a7b          	cv.cmpgeu.b	s4,s4,s4
+  14:	3dff9ffb          	cv.cmpgeu.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-b-pass.s
new file mode 100644
index 00000000000..9d134a5f9c9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpgeu.b x0, x0, x0
+    cv.cmpgeu.b x1, x1, x1
+    cv.cmpgeu.b x2, x2, x2
+    cv.cmpgeu.b x8, x8, x8
+    cv.cmpgeu.b x20, x20, x20
+    cv.cmpgeu.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-h-fail.d
new file mode 100644
index 00000000000..b026ee73432
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgeu-h-fail.s
+#error_output: cv-simd-cmpgeu-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-h-fail.l
new file mode 100644
index 00000000000..237d1505e05
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgeu.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpgeu.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-h-fail.s
new file mode 100644
index 00000000000..6c58cc8c466
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpgeu.h x32, x32, x32
+    cv.cmpgeu.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-h-pass.d
new file mode 100644
index 00000000000..ba0f05878ed
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgeu-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3c00007b          	cv.cmpgeu.h	zero,zero,zero
+   4:	3c1080fb          	cv.cmpgeu.h	ra,ra,ra
+   8:	3c21017b          	cv.cmpgeu.h	sp,sp,sp
+   c:	3c84047b          	cv.cmpgeu.h	s0,s0,s0
+  10:	3d4a0a7b          	cv.cmpgeu.h	s4,s4,s4
+  14:	3dff8ffb          	cv.cmpgeu.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-h-pass.s
new file mode 100644
index 00000000000..6981d4bf05e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpgeu.h x0, x0, x0
+    cv.cmpgeu.h x1, x1, x1
+    cv.cmpgeu.h x2, x2, x2
+    cv.cmpgeu.h x8, x8, x8
+    cv.cmpgeu.h x20, x20, x20
+    cv.cmpgeu.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-fail.d
new file mode 100644
index 00000000000..92885ecc5a7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgeu-sc-b-fail.s
+#error_output: cv-simd-cmpgeu-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-fail.l
new file mode 100644
index 00000000000..d80803402ba
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgeu.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpgeu.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-fail.s
new file mode 100644
index 00000000000..59641fd93ca
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpgeu.sc.b x32, x32, x32
+    cv.cmpgeu.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-pass.d
new file mode 100644
index 00000000000..11cf81d6cce
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgeu-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3c00507b          	cv.cmpgeu.sc.b	zero,zero,zero
+   4:	3c10d0fb          	cv.cmpgeu.sc.b	ra,ra,ra
+   8:	3c21517b          	cv.cmpgeu.sc.b	sp,sp,sp
+   c:	3c84547b          	cv.cmpgeu.sc.b	s0,s0,s0
+  10:	3d4a5a7b          	cv.cmpgeu.sc.b	s4,s4,s4
+  14:	3dffdffb          	cv.cmpgeu.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-pass.s
new file mode 100644
index 00000000000..bad8aad78b4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpgeu.sc.b x0, x0, x0
+    cv.cmpgeu.sc.b x1, x1, x1
+    cv.cmpgeu.sc.b x2, x2, x2
+    cv.cmpgeu.sc.b x8, x8, x8
+    cv.cmpgeu.sc.b x20, x20, x20
+    cv.cmpgeu.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-fail.d
new file mode 100644
index 00000000000..e8e302d2f86
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgeu-sc-h-fail.s
+#error_output: cv-simd-cmpgeu-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-fail.l
new file mode 100644
index 00000000000..711b5fd0a4f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgeu.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpgeu.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-fail.s
new file mode 100644
index 00000000000..f3e9c164cdc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpgeu.sc.h x32, x32, x32
+    cv.cmpgeu.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-pass.d
new file mode 100644
index 00000000000..145bff760d6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgeu-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3c00407b          	cv.cmpgeu.sc.h	zero,zero,zero
+   4:	3c10c0fb          	cv.cmpgeu.sc.h	ra,ra,ra
+   8:	3c21417b          	cv.cmpgeu.sc.h	sp,sp,sp
+   c:	3c84447b          	cv.cmpgeu.sc.h	s0,s0,s0
+  10:	3d4a4a7b          	cv.cmpgeu.sc.h	s4,s4,s4
+  14:	3dffcffb          	cv.cmpgeu.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-pass.s
new file mode 100644
index 00000000000..78dcb5d7faa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpgeu.sc.h x0, x0, x0
+    cv.cmpgeu.sc.h x1, x1, x1
+    cv.cmpgeu.sc.h x2, x2, x2
+    cv.cmpgeu.sc.h x8, x8, x8
+    cv.cmpgeu.sc.h x20, x20, x20
+    cv.cmpgeu.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-fail.d
new file mode 100644
index 00000000000..6f30fc63775
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgeu-sci-b-fail.s
+#error_output: cv-simd-cmpgeu-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-fail.l
new file mode 100644
index 00000000000..199cf8e2677
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgeu.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.cmpgeu.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-fail.s
new file mode 100644
index 00000000000..5ad2b6b2926
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.cmpgeu.sci.b x32, x32, 20
+    cv.cmpgeu.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpgeu.sci.b x6, x7, -1
+    cv.cmpgeu.sci.b x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-pass.d
new file mode 100644
index 00000000000..23bad539c54
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgeu-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3ca0707b          	cv.cmpgeu.sci.b	zero,zero,20
+   4:	3ca0f0fb          	cv.cmpgeu.sci.b	ra,ra,20
+   8:	3ca1717b          	cv.cmpgeu.sci.b	sp,sp,20
+   c:	3ca4747b          	cv.cmpgeu.sci.b	s0,s0,20
+  10:	3caa7a7b          	cv.cmpgeu.sci.b	s4,s4,20
+  14:	3caffffb          	cv.cmpgeu.sci.b	t6,t6,20
+  18:	3c03f37b          	cv.cmpgeu.sci.b	t1,t2,0
+  1c:	3ff3f37b          	cv.cmpgeu.sci.b	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-pass.s
new file mode 100644
index 00000000000..86db54973e1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.cmpgeu.sci.b x0, x0, 20
+    cv.cmpgeu.sci.b x1, x1, 20
+    cv.cmpgeu.sci.b x2, x2, 20
+    cv.cmpgeu.sci.b x8, x8, 20
+    cv.cmpgeu.sci.b x20, x20, 20
+    cv.cmpgeu.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.cmpgeu.sci.b x6, x7, 0
+    cv.cmpgeu.sci.b x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-fail.d
new file mode 100644
index 00000000000..850860ea855
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgeu-sci-h-fail.s
+#error_output: cv-simd-cmpgeu-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-fail.l
new file mode 100644
index 00000000000..81243bb67d0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgeu.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.cmpgeu.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-fail.s
new file mode 100644
index 00000000000..0efe6080655
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.cmpgeu.sci.h x32, x32, 20
+    cv.cmpgeu.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpgeu.sci.h x6, x7, -1
+    cv.cmpgeu.sci.h x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-pass.d
new file mode 100644
index 00000000000..8cfd2a47298
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgeu-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3ca0607b          	cv.cmpgeu.sci.h	zero,zero,20
+   4:	3ca0e0fb          	cv.cmpgeu.sci.h	ra,ra,20
+   8:	3ca1617b          	cv.cmpgeu.sci.h	sp,sp,20
+   c:	3ca4647b          	cv.cmpgeu.sci.h	s0,s0,20
+  10:	3caa6a7b          	cv.cmpgeu.sci.h	s4,s4,20
+  14:	3cafeffb          	cv.cmpgeu.sci.h	t6,t6,20
+  18:	3c03e37b          	cv.cmpgeu.sci.h	t1,t2,0
+  1c:	3ff3e37b          	cv.cmpgeu.sci.h	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-pass.s
new file mode 100644
index 00000000000..7272c7b4c68
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.cmpgeu.sci.h x0, x0, 20
+    cv.cmpgeu.sci.h x1, x1, 20
+    cv.cmpgeu.sci.h x2, x2, 20
+    cv.cmpgeu.sci.h x8, x8, 20
+    cv.cmpgeu.sci.h x20, x20, 20
+    cv.cmpgeu.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.cmpgeu.sci.h x6, x7, 0
+    cv.cmpgeu.sci.h x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgt-b-fail.d
new file mode 100644
index 00000000000..06713e63512
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgt-b-fail.s
+#error_output: cv-simd-cmpgt-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgt-b-fail.l
new file mode 100644
index 00000000000..4e68125dad4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgt.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpgt.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgt-b-fail.s
new file mode 100644
index 00000000000..378c6ece39b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpgt.b x32, x32, x32
+    cv.cmpgt.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgt-b-pass.d
new file mode 100644
index 00000000000..daf50430a15
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgt-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1400107b          	cv.cmpgt.b	zero,zero,zero
+   4:	141090fb          	cv.cmpgt.b	ra,ra,ra
+   8:	1421117b          	cv.cmpgt.b	sp,sp,sp
+   c:	1484147b          	cv.cmpgt.b	s0,s0,s0
+  10:	154a1a7b          	cv.cmpgt.b	s4,s4,s4
+  14:	15ff9ffb          	cv.cmpgt.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgt-b-pass.s
new file mode 100644
index 00000000000..eb895c512f6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpgt.b x0, x0, x0
+    cv.cmpgt.b x1, x1, x1
+    cv.cmpgt.b x2, x2, x2
+    cv.cmpgt.b x8, x8, x8
+    cv.cmpgt.b x20, x20, x20
+    cv.cmpgt.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgt-h-fail.d
new file mode 100644
index 00000000000..b1f8f066bb7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgt-h-fail.s
+#error_output: cv-simd-cmpgt-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgt-h-fail.l
new file mode 100644
index 00000000000..9237078e20a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgt.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpgt.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgt-h-fail.s
new file mode 100644
index 00000000000..d0c6cec4fed
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpgt.h x32, x32, x32
+    cv.cmpgt.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgt-h-pass.d
new file mode 100644
index 00000000000..74de9d8d350
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgt-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1400007b          	cv.cmpgt.h	zero,zero,zero
+   4:	141080fb          	cv.cmpgt.h	ra,ra,ra
+   8:	1421017b          	cv.cmpgt.h	sp,sp,sp
+   c:	1484047b          	cv.cmpgt.h	s0,s0,s0
+  10:	154a0a7b          	cv.cmpgt.h	s4,s4,s4
+  14:	15ff8ffb          	cv.cmpgt.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgt-h-pass.s
new file mode 100644
index 00000000000..721f9e7cc15
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpgt.h x0, x0, x0
+    cv.cmpgt.h x1, x1, x1
+    cv.cmpgt.h x2, x2, x2
+    cv.cmpgt.h x8, x8, x8
+    cv.cmpgt.h x20, x20, x20
+    cv.cmpgt.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-b-fail.d
new file mode 100644
index 00000000000..8bf0da8cbe0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgt-sc-b-fail.s
+#error_output: cv-simd-cmpgt-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-b-fail.l
new file mode 100644
index 00000000000..526c0b90ba9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgt.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpgt.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-b-fail.s
new file mode 100644
index 00000000000..d90150fdca5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpgt.sc.b x32, x32, x32
+    cv.cmpgt.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-b-pass.d
new file mode 100644
index 00000000000..a724df267d7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgt-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1400507b          	cv.cmpgt.sc.b	zero,zero,zero
+   4:	1410d0fb          	cv.cmpgt.sc.b	ra,ra,ra
+   8:	1421517b          	cv.cmpgt.sc.b	sp,sp,sp
+   c:	1484547b          	cv.cmpgt.sc.b	s0,s0,s0
+  10:	154a5a7b          	cv.cmpgt.sc.b	s4,s4,s4
+  14:	15ffdffb          	cv.cmpgt.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-b-pass.s
new file mode 100644
index 00000000000..bf0a2317a09
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpgt.sc.b x0, x0, x0
+    cv.cmpgt.sc.b x1, x1, x1
+    cv.cmpgt.sc.b x2, x2, x2
+    cv.cmpgt.sc.b x8, x8, x8
+    cv.cmpgt.sc.b x20, x20, x20
+    cv.cmpgt.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-h-fail.d
new file mode 100644
index 00000000000..03744bfd706
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgt-sc-h-fail.s
+#error_output: cv-simd-cmpgt-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-h-fail.l
new file mode 100644
index 00000000000..e13663d6149
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgt.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpgt.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-h-fail.s
new file mode 100644
index 00000000000..a69ec47ce84
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpgt.sc.h x32, x32, x32
+    cv.cmpgt.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-h-pass.d
new file mode 100644
index 00000000000..ea7792b1411
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgt-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1400407b          	cv.cmpgt.sc.h	zero,zero,zero
+   4:	1410c0fb          	cv.cmpgt.sc.h	ra,ra,ra
+   8:	1421417b          	cv.cmpgt.sc.h	sp,sp,sp
+   c:	1484447b          	cv.cmpgt.sc.h	s0,s0,s0
+  10:	154a4a7b          	cv.cmpgt.sc.h	s4,s4,s4
+  14:	15ffcffb          	cv.cmpgt.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-h-pass.s
new file mode 100644
index 00000000000..4d9d07011d7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpgt.sc.h x0, x0, x0
+    cv.cmpgt.sc.h x1, x1, x1
+    cv.cmpgt.sc.h x2, x2, x2
+    cv.cmpgt.sc.h x8, x8, x8
+    cv.cmpgt.sc.h x20, x20, x20
+    cv.cmpgt.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-b-fail.d
new file mode 100644
index 00000000000..2919d4bb629
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgt-sci-b-fail.s
+#error_output: cv-simd-cmpgt-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-b-fail.l
new file mode 100644
index 00000000000..0afcded817f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgt.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.cmpgt.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-b-fail.s
new file mode 100644
index 00000000000..6afc6cfa887
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.cmpgt.sci.b x32, x32, 20
+    cv.cmpgt.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpgt.sci.b x6, x7, -33
+    cv.cmpgt.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-b-pass.d
new file mode 100644
index 00000000000..da3734fc1dc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgt-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	14a0707b          	cv.cmpgt.sci.b	zero,zero,20
+   4:	14a0f0fb          	cv.cmpgt.sci.b	ra,ra,20
+   8:	14a1717b          	cv.cmpgt.sci.b	sp,sp,20
+   c:	14a4747b          	cv.cmpgt.sci.b	s0,s0,20
+  10:	14aa7a7b          	cv.cmpgt.sci.b	s4,s4,20
+  14:	14affffb          	cv.cmpgt.sci.b	t6,t6,20
+  18:	1503f37b          	cv.cmpgt.sci.b	t1,t2,-32
+  1c:	1403f37b          	cv.cmpgt.sci.b	t1,t2,0
+  20:	16f3f37b          	cv.cmpgt.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-b-pass.s
new file mode 100644
index 00000000000..be38ddfe800
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-b-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.cmpgt.sci.b x0, x0, 20
+    cv.cmpgt.sci.b x1, x1, 20
+    cv.cmpgt.sci.b x2, x2, 20
+    cv.cmpgt.sci.b x8, x8, 20
+    cv.cmpgt.sci.b x20, x20, 20
+    cv.cmpgt.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.cmpgt.sci.b x6, x7, -32
+    cv.cmpgt.sci.b x6, x7, 0
+    cv.cmpgt.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-h-fail.d
new file mode 100644
index 00000000000..c90370a2788
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgt-sci-h-fail.s
+#error_output: cv-simd-cmpgt-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-h-fail.l
new file mode 100644
index 00000000000..cb3234ffa5d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgt.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.cmpgt.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-h-fail.s
new file mode 100644
index 00000000000..50e9975caf8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.cmpgt.sci.h x32, x32, 20
+    cv.cmpgt.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpgt.sci.h x6, x7, -33
+    cv.cmpgt.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-h-pass.d
new file mode 100644
index 00000000000..844dc76a020
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgt-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	14a0607b          	cv.cmpgt.sci.h	zero,zero,20
+   4:	14a0e0fb          	cv.cmpgt.sci.h	ra,ra,20
+   8:	14a1617b          	cv.cmpgt.sci.h	sp,sp,20
+   c:	14a4647b          	cv.cmpgt.sci.h	s0,s0,20
+  10:	14aa6a7b          	cv.cmpgt.sci.h	s4,s4,20
+  14:	14afeffb          	cv.cmpgt.sci.h	t6,t6,20
+  18:	1503e37b          	cv.cmpgt.sci.h	t1,t2,-32
+  1c:	1403e37b          	cv.cmpgt.sci.h	t1,t2,0
+  20:	16f3e37b          	cv.cmpgt.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-h-pass.s
new file mode 100644
index 00000000000..128e103f033
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-h-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.cmpgt.sci.h x0, x0, 20
+    cv.cmpgt.sci.h x1, x1, 20
+    cv.cmpgt.sci.h x2, x2, 20
+    cv.cmpgt.sci.h x8, x8, 20
+    cv.cmpgt.sci.h x20, x20, 20
+    cv.cmpgt.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.cmpgt.sci.h x6, x7, -32
+    cv.cmpgt.sci.h x6, x7, 0
+    cv.cmpgt.sci.h x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-b-fail.d
new file mode 100644
index 00000000000..63ee1bdc4bd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgtu-b-fail.s
+#error_output: cv-simd-cmpgtu-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-b-fail.l
new file mode 100644
index 00000000000..dec5965c148
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgtu.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpgtu.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-b-fail.s
new file mode 100644
index 00000000000..42aa8c5611a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpgtu.b x32, x32, x32
+    cv.cmpgtu.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-b-pass.d
new file mode 100644
index 00000000000..5d3aa8d7ff5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgtu-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3400107b          	cv.cmpgtu.b	zero,zero,zero
+   4:	341090fb          	cv.cmpgtu.b	ra,ra,ra
+   8:	3421117b          	cv.cmpgtu.b	sp,sp,sp
+   c:	3484147b          	cv.cmpgtu.b	s0,s0,s0
+  10:	354a1a7b          	cv.cmpgtu.b	s4,s4,s4
+  14:	35ff9ffb          	cv.cmpgtu.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-b-pass.s
new file mode 100644
index 00000000000..d086aafd4f7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpgtu.b x0, x0, x0
+    cv.cmpgtu.b x1, x1, x1
+    cv.cmpgtu.b x2, x2, x2
+    cv.cmpgtu.b x8, x8, x8
+    cv.cmpgtu.b x20, x20, x20
+    cv.cmpgtu.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-h-fail.d
new file mode 100644
index 00000000000..fb528c57508
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgtu-h-fail.s
+#error_output: cv-simd-cmpgtu-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-h-fail.l
new file mode 100644
index 00000000000..09b6b0c67fb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgtu.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpgtu.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-h-fail.s
new file mode 100644
index 00000000000..3ddcd7aba97
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpgtu.h x32, x32, x32
+    cv.cmpgtu.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-h-pass.d
new file mode 100644
index 00000000000..a08da4ff5b2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgtu-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3400007b          	cv.cmpgtu.h	zero,zero,zero
+   4:	341080fb          	cv.cmpgtu.h	ra,ra,ra
+   8:	3421017b          	cv.cmpgtu.h	sp,sp,sp
+   c:	3484047b          	cv.cmpgtu.h	s0,s0,s0
+  10:	354a0a7b          	cv.cmpgtu.h	s4,s4,s4
+  14:	35ff8ffb          	cv.cmpgtu.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-h-pass.s
new file mode 100644
index 00000000000..5487c53a4c9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpgtu.h x0, x0, x0
+    cv.cmpgtu.h x1, x1, x1
+    cv.cmpgtu.h x2, x2, x2
+    cv.cmpgtu.h x8, x8, x8
+    cv.cmpgtu.h x20, x20, x20
+    cv.cmpgtu.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-fail.d
new file mode 100644
index 00000000000..cebe6125b5c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgtu-sc-b-fail.s
+#error_output: cv-simd-cmpgtu-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-fail.l
new file mode 100644
index 00000000000..8e61b4687f9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgtu.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpgtu.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-fail.s
new file mode 100644
index 00000000000..995f3d9f7ab
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpgtu.sc.b x32, x32, x32
+    cv.cmpgtu.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-pass.d
new file mode 100644
index 00000000000..cfbe16753df
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgtu-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3400507b          	cv.cmpgtu.sc.b	zero,zero,zero
+   4:	3410d0fb          	cv.cmpgtu.sc.b	ra,ra,ra
+   8:	3421517b          	cv.cmpgtu.sc.b	sp,sp,sp
+   c:	3484547b          	cv.cmpgtu.sc.b	s0,s0,s0
+  10:	354a5a7b          	cv.cmpgtu.sc.b	s4,s4,s4
+  14:	35ffdffb          	cv.cmpgtu.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-pass.s
new file mode 100644
index 00000000000..7433324f6fa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpgtu.sc.b x0, x0, x0
+    cv.cmpgtu.sc.b x1, x1, x1
+    cv.cmpgtu.sc.b x2, x2, x2
+    cv.cmpgtu.sc.b x8, x8, x8
+    cv.cmpgtu.sc.b x20, x20, x20
+    cv.cmpgtu.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-fail.d
new file mode 100644
index 00000000000..3dfb1d87383
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgtu-sc-h-fail.s
+#error_output: cv-simd-cmpgtu-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-fail.l
new file mode 100644
index 00000000000..db82748d2ab
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgtu.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpgtu.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-fail.s
new file mode 100644
index 00000000000..bc6a47abb5f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpgtu.sc.h x32, x32, x32
+    cv.cmpgtu.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-pass.d
new file mode 100644
index 00000000000..46f600935f6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgtu-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3400407b          	cv.cmpgtu.sc.h	zero,zero,zero
+   4:	3410c0fb          	cv.cmpgtu.sc.h	ra,ra,ra
+   8:	3421417b          	cv.cmpgtu.sc.h	sp,sp,sp
+   c:	3484447b          	cv.cmpgtu.sc.h	s0,s0,s0
+  10:	354a4a7b          	cv.cmpgtu.sc.h	s4,s4,s4
+  14:	35ffcffb          	cv.cmpgtu.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-pass.s
new file mode 100644
index 00000000000..6f9e70effb3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpgtu.sc.h x0, x0, x0
+    cv.cmpgtu.sc.h x1, x1, x1
+    cv.cmpgtu.sc.h x2, x2, x2
+    cv.cmpgtu.sc.h x8, x8, x8
+    cv.cmpgtu.sc.h x20, x20, x20
+    cv.cmpgtu.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-fail.d
new file mode 100644
index 00000000000..511d8b71653
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgtu-sci-b-fail.s
+#error_output: cv-simd-cmpgtu-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-fail.l
new file mode 100644
index 00000000000..765eb803d77
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgtu.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.cmpgtu.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-fail.s
new file mode 100644
index 00000000000..aacb26b1159
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.cmpgtu.sci.b x32, x32, 20
+    cv.cmpgtu.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpgtu.sci.b x6, x7, -1
+    cv.cmpgtu.sci.b x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-pass.d
new file mode 100644
index 00000000000..8e230445944
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgtu-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	34a0707b          	cv.cmpgtu.sci.b	zero,zero,20
+   4:	34a0f0fb          	cv.cmpgtu.sci.b	ra,ra,20
+   8:	34a1717b          	cv.cmpgtu.sci.b	sp,sp,20
+   c:	34a4747b          	cv.cmpgtu.sci.b	s0,s0,20
+  10:	34aa7a7b          	cv.cmpgtu.sci.b	s4,s4,20
+  14:	34affffb          	cv.cmpgtu.sci.b	t6,t6,20
+  18:	3403f37b          	cv.cmpgtu.sci.b	t1,t2,0
+  1c:	37f3f37b          	cv.cmpgtu.sci.b	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-pass.s
new file mode 100644
index 00000000000..0d60dbd2792
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.cmpgtu.sci.b x0, x0, 20
+    cv.cmpgtu.sci.b x1, x1, 20
+    cv.cmpgtu.sci.b x2, x2, 20
+    cv.cmpgtu.sci.b x8, x8, 20
+    cv.cmpgtu.sci.b x20, x20, 20
+    cv.cmpgtu.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.cmpgtu.sci.b x6, x7, 0
+    cv.cmpgtu.sci.b x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-fail.d
new file mode 100644
index 00000000000..7813fc68442
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgtu-sci-h-fail.s
+#error_output: cv-simd-cmpgtu-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-fail.l
new file mode 100644
index 00000000000..424630562ee
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgtu.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.cmpgtu.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-fail.s
new file mode 100644
index 00000000000..a3c6ae574c3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.cmpgtu.sci.h x32, x32, 20
+    cv.cmpgtu.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpgtu.sci.h x6, x7, -1
+    cv.cmpgtu.sci.h x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-pass.d
new file mode 100644
index 00000000000..9f7ea98e3fa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgtu-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	34a0607b          	cv.cmpgtu.sci.h	zero,zero,20
+   4:	34a0e0fb          	cv.cmpgtu.sci.h	ra,ra,20
+   8:	34a1617b          	cv.cmpgtu.sci.h	sp,sp,20
+   c:	34a4647b          	cv.cmpgtu.sci.h	s0,s0,20
+  10:	34aa6a7b          	cv.cmpgtu.sci.h	s4,s4,20
+  14:	34afeffb          	cv.cmpgtu.sci.h	t6,t6,20
+  18:	3403e37b          	cv.cmpgtu.sci.h	t1,t2,0
+  1c:	37f3e37b          	cv.cmpgtu.sci.h	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-pass.s
new file mode 100644
index 00000000000..2a9d34ebfec
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.cmpgtu.sci.h x0, x0, 20
+    cv.cmpgtu.sci.h x1, x1, 20
+    cv.cmpgtu.sci.h x2, x2, 20
+    cv.cmpgtu.sci.h x8, x8, 20
+    cv.cmpgtu.sci.h x20, x20, 20
+    cv.cmpgtu.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.cmpgtu.sci.h x6, x7, 0
+    cv.cmpgtu.sci.h x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmple-b-fail.d
new file mode 100644
index 00000000000..a6907dd5a95
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmple-b-fail.s
+#error_output: cv-simd-cmple-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmple-b-fail.l
new file mode 100644
index 00000000000..c1ce1e95e57
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmple.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmple.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmple-b-fail.s
new file mode 100644
index 00000000000..9c8aae64d55
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmple.b x32, x32, x32
+    cv.cmple.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmple-b-pass.d
new file mode 100644
index 00000000000..927374db6cf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmple-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2c00107b          	cv.cmple.b	zero,zero,zero
+   4:	2c1090fb          	cv.cmple.b	ra,ra,ra
+   8:	2c21117b          	cv.cmple.b	sp,sp,sp
+   c:	2c84147b          	cv.cmple.b	s0,s0,s0
+  10:	2d4a1a7b          	cv.cmple.b	s4,s4,s4
+  14:	2dff9ffb          	cv.cmple.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmple-b-pass.s
new file mode 100644
index 00000000000..5fab1cd9124
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmple.b x0, x0, x0
+    cv.cmple.b x1, x1, x1
+    cv.cmple.b x2, x2, x2
+    cv.cmple.b x8, x8, x8
+    cv.cmple.b x20, x20, x20
+    cv.cmple.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmple-h-fail.d
new file mode 100644
index 00000000000..bbc68c94565
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmple-h-fail.s
+#error_output: cv-simd-cmple-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmple-h-fail.l
new file mode 100644
index 00000000000..90dc4e90829
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmple.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmple.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmple-h-fail.s
new file mode 100644
index 00000000000..d80043ebde5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmple.h x32, x32, x32
+    cv.cmple.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmple-h-pass.d
new file mode 100644
index 00000000000..b98c0094d42
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmple-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2c00007b          	cv.cmple.h	zero,zero,zero
+   4:	2c1080fb          	cv.cmple.h	ra,ra,ra
+   8:	2c21017b          	cv.cmple.h	sp,sp,sp
+   c:	2c84047b          	cv.cmple.h	s0,s0,s0
+  10:	2d4a0a7b          	cv.cmple.h	s4,s4,s4
+  14:	2dff8ffb          	cv.cmple.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmple-h-pass.s
new file mode 100644
index 00000000000..afcf7435a36
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmple.h x0, x0, x0
+    cv.cmple.h x1, x1, x1
+    cv.cmple.h x2, x2, x2
+    cv.cmple.h x8, x8, x8
+    cv.cmple.h x20, x20, x20
+    cv.cmple.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-b-fail.d
new file mode 100644
index 00000000000..74c37e5f187
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmple-sc-b-fail.s
+#error_output: cv-simd-cmple-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-b-fail.l
new file mode 100644
index 00000000000..74b287452ea
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmple.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmple.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-b-fail.s
new file mode 100644
index 00000000000..6c2a2b3cf38
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmple.sc.b x32, x32, x32
+    cv.cmple.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-b-pass.d
new file mode 100644
index 00000000000..00120c97862
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmple-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2c00507b          	cv.cmple.sc.b	zero,zero,zero
+   4:	2c10d0fb          	cv.cmple.sc.b	ra,ra,ra
+   8:	2c21517b          	cv.cmple.sc.b	sp,sp,sp
+   c:	2c84547b          	cv.cmple.sc.b	s0,s0,s0
+  10:	2d4a5a7b          	cv.cmple.sc.b	s4,s4,s4
+  14:	2dffdffb          	cv.cmple.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-b-pass.s
new file mode 100644
index 00000000000..90d8115fb15
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmple.sc.b x0, x0, x0
+    cv.cmple.sc.b x1, x1, x1
+    cv.cmple.sc.b x2, x2, x2
+    cv.cmple.sc.b x8, x8, x8
+    cv.cmple.sc.b x20, x20, x20
+    cv.cmple.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-h-fail.d
new file mode 100644
index 00000000000..86ba75fde12
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmple-sc-h-fail.s
+#error_output: cv-simd-cmple-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-h-fail.l
new file mode 100644
index 00000000000..781dcb28e9a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmple.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmple.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-h-fail.s
new file mode 100644
index 00000000000..f88621036ca
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmple.sc.h x32, x32, x32
+    cv.cmple.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-h-pass.d
new file mode 100644
index 00000000000..750cf51f0fd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmple-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2c00407b          	cv.cmple.sc.h	zero,zero,zero
+   4:	2c10c0fb          	cv.cmple.sc.h	ra,ra,ra
+   8:	2c21417b          	cv.cmple.sc.h	sp,sp,sp
+   c:	2c84447b          	cv.cmple.sc.h	s0,s0,s0
+  10:	2d4a4a7b          	cv.cmple.sc.h	s4,s4,s4
+  14:	2dffcffb          	cv.cmple.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-h-pass.s
new file mode 100644
index 00000000000..94a4f5ea19d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmple.sc.h x0, x0, x0
+    cv.cmple.sc.h x1, x1, x1
+    cv.cmple.sc.h x2, x2, x2
+    cv.cmple.sc.h x8, x8, x8
+    cv.cmple.sc.h x20, x20, x20
+    cv.cmple.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-b-fail.d
new file mode 100644
index 00000000000..92aaddd59ff
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmple-sci-b-fail.s
+#error_output: cv-simd-cmple-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-b-fail.l
new file mode 100644
index 00000000000..6fbc895b3ea
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmple.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.cmple.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-b-fail.s
new file mode 100644
index 00000000000..76927d84bd6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.cmple.sci.b x32, x32, 20
+    cv.cmple.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmple.sci.b x6, x7, -33
+    cv.cmple.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-b-pass.d
new file mode 100644
index 00000000000..c9851df4ad5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmple-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2ca0707b          	cv.cmple.sci.b	zero,zero,20
+   4:	2ca0f0fb          	cv.cmple.sci.b	ra,ra,20
+   8:	2ca1717b          	cv.cmple.sci.b	sp,sp,20
+   c:	2ca4747b          	cv.cmple.sci.b	s0,s0,20
+  10:	2caa7a7b          	cv.cmple.sci.b	s4,s4,20
+  14:	2caffffb          	cv.cmple.sci.b	t6,t6,20
+  18:	2d03f37b          	cv.cmple.sci.b	t1,t2,-32
+  1c:	2c03f37b          	cv.cmple.sci.b	t1,t2,0
+  20:	2ef3f37b          	cv.cmple.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-b-pass.s
new file mode 100644
index 00000000000..472cda7f1de
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-b-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.cmple.sci.b x0, x0, 20
+    cv.cmple.sci.b x1, x1, 20
+    cv.cmple.sci.b x2, x2, 20
+    cv.cmple.sci.b x8, x8, 20
+    cv.cmple.sci.b x20, x20, 20
+    cv.cmple.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.cmple.sci.b x6, x7, -32
+    cv.cmple.sci.b x6, x7, 0
+    cv.cmple.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-h-fail.d
new file mode 100644
index 00000000000..30002602360
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmple-sci-h-fail.s
+#error_output: cv-simd-cmple-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-h-fail.l
new file mode 100644
index 00000000000..ccbf473dbd3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmple.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.cmple.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-h-fail.s
new file mode 100644
index 00000000000..fb4620a024f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.cmple.sci.h x32, x32, 20
+    cv.cmple.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmple.sci.h x6, x7, -33
+    cv.cmple.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-h-pass.d
new file mode 100644
index 00000000000..0a10894d659
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmple-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2ca0607b          	cv.cmple.sci.h	zero,zero,20
+   4:	2ca0e0fb          	cv.cmple.sci.h	ra,ra,20
+   8:	2ca1617b          	cv.cmple.sci.h	sp,sp,20
+   c:	2ca4647b          	cv.cmple.sci.h	s0,s0,20
+  10:	2caa6a7b          	cv.cmple.sci.h	s4,s4,20
+  14:	2cafeffb          	cv.cmple.sci.h	t6,t6,20
+  18:	2d03e37b          	cv.cmple.sci.h	t1,t2,-32
+  1c:	2c03e37b          	cv.cmple.sci.h	t1,t2,0
+  20:	2ef3e37b          	cv.cmple.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-h-pass.s
new file mode 100644
index 00000000000..fcfe70449b6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-h-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.cmple.sci.h x0, x0, 20
+    cv.cmple.sci.h x1, x1, 20
+    cv.cmple.sci.h x2, x2, 20
+    cv.cmple.sci.h x8, x8, 20
+    cv.cmple.sci.h x20, x20, 20
+    cv.cmple.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.cmple.sci.h x6, x7, -32
+    cv.cmple.sci.h x6, x7, 0
+    cv.cmple.sci.h x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpleu-b-fail.d
new file mode 100644
index 00000000000..635991b6097
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpleu-b-fail.s
+#error_output: cv-simd-cmpleu-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpleu-b-fail.l
new file mode 100644
index 00000000000..906bb044ca7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpleu.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpleu.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpleu-b-fail.s
new file mode 100644
index 00000000000..4e44ba9c39c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpleu.b x32, x32, x32
+    cv.cmpleu.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpleu-b-pass.d
new file mode 100644
index 00000000000..8cb04f5a11a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpleu-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4c00107b          	cv.cmpleu.b	zero,zero,zero
+   4:	4c1090fb          	cv.cmpleu.b	ra,ra,ra
+   8:	4c21117b          	cv.cmpleu.b	sp,sp,sp
+   c:	4c84147b          	cv.cmpleu.b	s0,s0,s0
+  10:	4d4a1a7b          	cv.cmpleu.b	s4,s4,s4
+  14:	4dff9ffb          	cv.cmpleu.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpleu-b-pass.s
new file mode 100644
index 00000000000..f8026b29065
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpleu.b x0, x0, x0
+    cv.cmpleu.b x1, x1, x1
+    cv.cmpleu.b x2, x2, x2
+    cv.cmpleu.b x8, x8, x8
+    cv.cmpleu.b x20, x20, x20
+    cv.cmpleu.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpleu-h-fail.d
new file mode 100644
index 00000000000..f2a3d69363c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpleu-h-fail.s
+#error_output: cv-simd-cmpleu-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpleu-h-fail.l
new file mode 100644
index 00000000000..1bcab7179eb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpleu.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpleu.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpleu-h-fail.s
new file mode 100644
index 00000000000..93b039a8f10
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpleu.h x32, x32, x32
+    cv.cmpleu.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpleu-h-pass.d
new file mode 100644
index 00000000000..88510d9e822
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpleu-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4c00007b          	cv.cmpleu.h	zero,zero,zero
+   4:	4c1080fb          	cv.cmpleu.h	ra,ra,ra
+   8:	4c21017b          	cv.cmpleu.h	sp,sp,sp
+   c:	4c84047b          	cv.cmpleu.h	s0,s0,s0
+  10:	4d4a0a7b          	cv.cmpleu.h	s4,s4,s4
+  14:	4dff8ffb          	cv.cmpleu.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpleu-h-pass.s
new file mode 100644
index 00000000000..ce120275cdf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpleu.h x0, x0, x0
+    cv.cmpleu.h x1, x1, x1
+    cv.cmpleu.h x2, x2, x2
+    cv.cmpleu.h x8, x8, x8
+    cv.cmpleu.h x20, x20, x20
+    cv.cmpleu.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-b-fail.d
new file mode 100644
index 00000000000..3dbb3317678
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpleu-sc-b-fail.s
+#error_output: cv-simd-cmpleu-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-b-fail.l
new file mode 100644
index 00000000000..5fde1fae238
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpleu.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpleu.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-b-fail.s
new file mode 100644
index 00000000000..b0eb2333f24
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpleu.sc.b x32, x32, x32
+    cv.cmpleu.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-b-pass.d
new file mode 100644
index 00000000000..25200479d35
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpleu-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4c00507b          	cv.cmpleu.sc.b	zero,zero,zero
+   4:	4c10d0fb          	cv.cmpleu.sc.b	ra,ra,ra
+   8:	4c21517b          	cv.cmpleu.sc.b	sp,sp,sp
+   c:	4c84547b          	cv.cmpleu.sc.b	s0,s0,s0
+  10:	4d4a5a7b          	cv.cmpleu.sc.b	s4,s4,s4
+  14:	4dffdffb          	cv.cmpleu.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-b-pass.s
new file mode 100644
index 00000000000..3f2ecfd7e67
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpleu.sc.b x0, x0, x0
+    cv.cmpleu.sc.b x1, x1, x1
+    cv.cmpleu.sc.b x2, x2, x2
+    cv.cmpleu.sc.b x8, x8, x8
+    cv.cmpleu.sc.b x20, x20, x20
+    cv.cmpleu.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-h-fail.d
new file mode 100644
index 00000000000..9ddd9d42c7b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpleu-sc-h-fail.s
+#error_output: cv-simd-cmpleu-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-h-fail.l
new file mode 100644
index 00000000000..11438240a92
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpleu.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpleu.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-h-fail.s
new file mode 100644
index 00000000000..8265fb20add
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpleu.sc.h x32, x32, x32
+    cv.cmpleu.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-h-pass.d
new file mode 100644
index 00000000000..acbfa417945
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpleu-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4c00407b          	cv.cmpleu.sc.h	zero,zero,zero
+   4:	4c10c0fb          	cv.cmpleu.sc.h	ra,ra,ra
+   8:	4c21417b          	cv.cmpleu.sc.h	sp,sp,sp
+   c:	4c84447b          	cv.cmpleu.sc.h	s0,s0,s0
+  10:	4d4a4a7b          	cv.cmpleu.sc.h	s4,s4,s4
+  14:	4dffcffb          	cv.cmpleu.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-h-pass.s
new file mode 100644
index 00000000000..3860ae1122e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpleu.sc.h x0, x0, x0
+    cv.cmpleu.sc.h x1, x1, x1
+    cv.cmpleu.sc.h x2, x2, x2
+    cv.cmpleu.sc.h x8, x8, x8
+    cv.cmpleu.sc.h x20, x20, x20
+    cv.cmpleu.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-b-fail.d
new file mode 100644
index 00000000000..81a56d4c797
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpleu-sci-b-fail.s
+#error_output: cv-simd-cmpleu-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-b-fail.l
new file mode 100644
index 00000000000..589af59d74e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpleu.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.cmpleu.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-b-fail.s
new file mode 100644
index 00000000000..5efddc4e080
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.cmpleu.sci.b x32, x32, 20
+    cv.cmpleu.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpleu.sci.b x6, x7, -1
+    cv.cmpleu.sci.b x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-b-pass.d
new file mode 100644
index 00000000000..8a0ac6cbdfc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-b-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpleu-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4ca0707b          	cv.cmpleu.sci.b	zero,zero,20
+   4:	4ca0f0fb          	cv.cmpleu.sci.b	ra,ra,20
+   8:	4ca1717b          	cv.cmpleu.sci.b	sp,sp,20
+   c:	4ca4747b          	cv.cmpleu.sci.b	s0,s0,20
+  10:	4caa7a7b          	cv.cmpleu.sci.b	s4,s4,20
+  14:	4caffffb          	cv.cmpleu.sci.b	t6,t6,20
+  18:	4c03f37b          	cv.cmpleu.sci.b	t1,t2,0
+  1c:	4ff3f37b          	cv.cmpleu.sci.b	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-b-pass.s
new file mode 100644
index 00000000000..a5c4b273c62
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-b-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.cmpleu.sci.b x0, x0, 20
+    cv.cmpleu.sci.b x1, x1, 20
+    cv.cmpleu.sci.b x2, x2, 20
+    cv.cmpleu.sci.b x8, x8, 20
+    cv.cmpleu.sci.b x20, x20, 20
+    cv.cmpleu.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.cmpleu.sci.b x6, x7, 0
+    cv.cmpleu.sci.b x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-h-fail.d
new file mode 100644
index 00000000000..34a81b5cd8a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpleu-sci-h-fail.s
+#error_output: cv-simd-cmpleu-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-h-fail.l
new file mode 100644
index 00000000000..a7969bb4db2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpleu.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.cmpleu.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
\ No newline at end of file
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-h-fail.s
new file mode 100644
index 00000000000..a4dbd6fcb8f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.cmpleu.sci.h x32, x32, 20
+    cv.cmpleu.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpleu.sci.h x6, x7, -1
+    cv.cmpleu.sci.h x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-h-pass.d
new file mode 100644
index 00000000000..83ca67a305e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-h-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpleu-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4ca0607b          	cv.cmpleu.sci.h	zero,zero,20
+   4:	4ca0e0fb          	cv.cmpleu.sci.h	ra,ra,20
+   8:	4ca1617b          	cv.cmpleu.sci.h	sp,sp,20
+   c:	4ca4647b          	cv.cmpleu.sci.h	s0,s0,20
+  10:	4caa6a7b          	cv.cmpleu.sci.h	s4,s4,20
+  14:	4cafeffb          	cv.cmpleu.sci.h	t6,t6,20
+  18:	4c03e37b          	cv.cmpleu.sci.h	t1,t2,0
+  1c:	4ff3e37b          	cv.cmpleu.sci.h	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-h-pass.s
new file mode 100644
index 00000000000..a090b350010
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-h-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.cmpleu.sci.h x0, x0, 20
+    cv.cmpleu.sci.h x1, x1, 20
+    cv.cmpleu.sci.h x2, x2, 20
+    cv.cmpleu.sci.h x8, x8, 20
+    cv.cmpleu.sci.h x20, x20, 20
+    cv.cmpleu.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.cmpleu.sci.h x6, x7, 0
+    cv.cmpleu.sci.h x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmplt-b-fail.d
new file mode 100644
index 00000000000..242b75786d6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmplt-b-fail.s
+#error_output: cv-simd-cmplt-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmplt-b-fail.l
new file mode 100644
index 00000000000..0f98b08b92e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmplt.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmplt.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmplt-b-fail.s
new file mode 100644
index 00000000000..0c67c18560f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmplt.b x32, x32, x32
+    cv.cmplt.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmplt-b-pass.d
new file mode 100644
index 00000000000..90d4f22903e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmplt-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2400107b          	cv.cmplt.b	zero,zero,zero
+   4:	241090fb          	cv.cmplt.b	ra,ra,ra
+   8:	2421117b          	cv.cmplt.b	sp,sp,sp
+   c:	2484147b          	cv.cmplt.b	s0,s0,s0
+  10:	254a1a7b          	cv.cmplt.b	s4,s4,s4
+  14:	25ff9ffb          	cv.cmplt.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmplt-b-pass.s
new file mode 100644
index 00000000000..a511a83ff14
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmplt.b x0, x0, x0
+    cv.cmplt.b x1, x1, x1
+    cv.cmplt.b x2, x2, x2
+    cv.cmplt.b x8, x8, x8
+    cv.cmplt.b x20, x20, x20
+    cv.cmplt.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmplt-h-fail.d
new file mode 100644
index 00000000000..fddea37a26f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmplt-h-fail.s
+#error_output: cv-simd-cmplt-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmplt-h-fail.l
new file mode 100644
index 00000000000..b2c5298e1e3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmplt.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmplt.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmplt-h-fail.s
new file mode 100644
index 00000000000..3d47de30ab4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmplt.h x32, x32, x32
+    cv.cmplt.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmplt-h-pass.d
new file mode 100644
index 00000000000..42b980e670e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmplt-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2400007b          	cv.cmplt.h	zero,zero,zero
+   4:	241080fb          	cv.cmplt.h	ra,ra,ra
+   8:	2421017b          	cv.cmplt.h	sp,sp,sp
+   c:	2484047b          	cv.cmplt.h	s0,s0,s0
+  10:	254a0a7b          	cv.cmplt.h	s4,s4,s4
+  14:	25ff8ffb          	cv.cmplt.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmplt-h-pass.s
new file mode 100644
index 00000000000..85bcb8970a4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmplt.h x0, x0, x0
+    cv.cmplt.h x1, x1, x1
+    cv.cmplt.h x2, x2, x2
+    cv.cmplt.h x8, x8, x8
+    cv.cmplt.h x20, x20, x20
+    cv.cmplt.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-b-fail.d
new file mode 100644
index 00000000000..20491b47b11
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmplt-sc-b-fail.s
+#error_output: cv-simd-cmplt-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-b-fail.l
new file mode 100644
index 00000000000..bc8340f218b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmplt.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmplt.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-b-fail.s
new file mode 100644
index 00000000000..2fbc6c49ecc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmplt.sc.b x32, x32, x32
+    cv.cmplt.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-b-pass.d
new file mode 100644
index 00000000000..58dc2cc2458
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmplt-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2400507b          	cv.cmplt.sc.b	zero,zero,zero
+   4:	2410d0fb          	cv.cmplt.sc.b	ra,ra,ra
+   8:	2421517b          	cv.cmplt.sc.b	sp,sp,sp
+   c:	2484547b          	cv.cmplt.sc.b	s0,s0,s0
+  10:	254a5a7b          	cv.cmplt.sc.b	s4,s4,s4
+  14:	25ffdffb          	cv.cmplt.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-b-pass.s
new file mode 100644
index 00000000000..0909cd18619
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmplt.sc.b x0, x0, x0
+    cv.cmplt.sc.b x1, x1, x1
+    cv.cmplt.sc.b x2, x2, x2
+    cv.cmplt.sc.b x8, x8, x8
+    cv.cmplt.sc.b x20, x20, x20
+    cv.cmplt.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-h-fail.d
new file mode 100644
index 00000000000..9aa9ab6b6ee
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmplt-sc-h-fail.s
+#error_output: cv-simd-cmplt-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-h-fail.l
new file mode 100644
index 00000000000..9d7c9e05479
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmplt.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmplt.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-h-fail.s
new file mode 100644
index 00000000000..ffc1d9f5b98
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmplt.sc.h x32, x32, x32
+    cv.cmplt.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-h-pass.d
new file mode 100644
index 00000000000..c3a5de547e3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmplt-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2400407b          	cv.cmplt.sc.h	zero,zero,zero
+   4:	2410c0fb          	cv.cmplt.sc.h	ra,ra,ra
+   8:	2421417b          	cv.cmplt.sc.h	sp,sp,sp
+   c:	2484447b          	cv.cmplt.sc.h	s0,s0,s0
+  10:	254a4a7b          	cv.cmplt.sc.h	s4,s4,s4
+  14:	25ffcffb          	cv.cmplt.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-h-pass.s
new file mode 100644
index 00000000000..4278bf94e05
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmplt.sc.h x0, x0, x0
+    cv.cmplt.sc.h x1, x1, x1
+    cv.cmplt.sc.h x2, x2, x2
+    cv.cmplt.sc.h x8, x8, x8
+    cv.cmplt.sc.h x20, x20, x20
+    cv.cmplt.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-b-fail.d
new file mode 100644
index 00000000000..f678f979ab3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmplt-sci-b-fail.s
+#error_output: cv-simd-cmplt-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-b-fail.l
new file mode 100644
index 00000000000..2d5cdad6b80
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmplt.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.cmplt.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-b-fail.s
new file mode 100644
index 00000000000..e1fb4dd0887
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.cmplt.sci.b x32, x32, 20
+    cv.cmplt.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmplt.sci.b x6, x7, -33
+    cv.cmplt.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-b-pass.d
new file mode 100644
index 00000000000..7ff96089553
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmplt-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	24a0707b          	cv.cmplt.sci.b	zero,zero,20
+   4:	24a0f0fb          	cv.cmplt.sci.b	ra,ra,20
+   8:	24a1717b          	cv.cmplt.sci.b	sp,sp,20
+   c:	24a4747b          	cv.cmplt.sci.b	s0,s0,20
+  10:	24aa7a7b          	cv.cmplt.sci.b	s4,s4,20
+  14:	24affffb          	cv.cmplt.sci.b	t6,t6,20
+  18:	2503f37b          	cv.cmplt.sci.b	t1,t2,-32
+  1c:	2403f37b          	cv.cmplt.sci.b	t1,t2,0
+  20:	26f3f37b          	cv.cmplt.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-b-pass.s
new file mode 100644
index 00000000000..83bcbda6b9a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-b-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.cmplt.sci.b x0, x0, 20
+    cv.cmplt.sci.b x1, x1, 20
+    cv.cmplt.sci.b x2, x2, 20
+    cv.cmplt.sci.b x8, x8, 20
+    cv.cmplt.sci.b x20, x20, 20
+    cv.cmplt.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.cmplt.sci.b x6, x7, -32
+    cv.cmplt.sci.b x6, x7, 0
+    cv.cmplt.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-h-fail.d
new file mode 100644
index 00000000000..094b86805e4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmplt-sci-h-fail.s
+#error_output: cv-simd-cmplt-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-h-fail.l
new file mode 100644
index 00000000000..6be7bcaf461
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmplt.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.cmplt.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-h-fail.s
new file mode 100644
index 00000000000..5ce5511612c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.cmplt.sci.h x32, x32, 20
+    cv.cmplt.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmplt.sci.h x6, x7, -33
+    cv.cmplt.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-h-pass.d
new file mode 100644
index 00000000000..74831942dc1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmplt-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	24a0607b          	cv.cmplt.sci.h	zero,zero,20
+   4:	24a0e0fb          	cv.cmplt.sci.h	ra,ra,20
+   8:	24a1617b          	cv.cmplt.sci.h	sp,sp,20
+   c:	24a4647b          	cv.cmplt.sci.h	s0,s0,20
+  10:	24aa6a7b          	cv.cmplt.sci.h	s4,s4,20
+  14:	24afeffb          	cv.cmplt.sci.h	t6,t6,20
+  18:	2503e37b          	cv.cmplt.sci.h	t1,t2,-32
+  1c:	2403e37b          	cv.cmplt.sci.h	t1,t2,0
+  20:	26f3e37b          	cv.cmplt.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-h-pass.s
new file mode 100644
index 00000000000..fd1d4e4a20a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-h-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.cmplt.sci.h x0, x0, 20
+    cv.cmplt.sci.h x1, x1, 20
+    cv.cmplt.sci.h x2, x2, 20
+    cv.cmplt.sci.h x8, x8, 20
+    cv.cmplt.sci.h x20, x20, 20
+    cv.cmplt.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.cmplt.sci.h x6, x7, -32
+    cv.cmplt.sci.h x6, x7, 0
+    cv.cmplt.sci.h x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpltu-b-fail.d
new file mode 100644
index 00000000000..0050c0dfcbc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpltu-b-fail.s
+#error_output: cv-simd-cmpltu-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpltu-b-fail.l
new file mode 100644
index 00000000000..199b24d2c5e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpltu.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpltu.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpltu-b-fail.s
new file mode 100644
index 00000000000..b2c0b184925
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpltu.b x32, x32, x32
+    cv.cmpltu.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpltu-b-pass.d
new file mode 100644
index 00000000000..ae5e5d804c4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpltu-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4400107b          	cv.cmpltu.b	zero,zero,zero
+   4:	441090fb          	cv.cmpltu.b	ra,ra,ra
+   8:	4421117b          	cv.cmpltu.b	sp,sp,sp
+   c:	4484147b          	cv.cmpltu.b	s0,s0,s0
+  10:	454a1a7b          	cv.cmpltu.b	s4,s4,s4
+  14:	45ff9ffb          	cv.cmpltu.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpltu-b-pass.s
new file mode 100644
index 00000000000..c8478657052
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpltu.b x0, x0, x0
+    cv.cmpltu.b x1, x1, x1
+    cv.cmpltu.b x2, x2, x2
+    cv.cmpltu.b x8, x8, x8
+    cv.cmpltu.b x20, x20, x20
+    cv.cmpltu.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpltu-h-fail.d
new file mode 100644
index 00000000000..b37c94721ee
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpltu-h-fail.s
+#error_output: cv-simd-cmpltu-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpltu-h-fail.l
new file mode 100644
index 00000000000..7ec17d16181
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpltu.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpltu.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpltu-h-fail.s
new file mode 100644
index 00000000000..4153184c5fb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpltu.h x32, x32, x32
+    cv.cmpltu.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpltu-h-pass.d
new file mode 100644
index 00000000000..4c15ec5cc45
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpltu-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4400007b          	cv.cmpltu.h	zero,zero,zero
+   4:	441080fb          	cv.cmpltu.h	ra,ra,ra
+   8:	4421017b          	cv.cmpltu.h	sp,sp,sp
+   c:	4484047b          	cv.cmpltu.h	s0,s0,s0
+  10:	454a0a7b          	cv.cmpltu.h	s4,s4,s4
+  14:	45ff8ffb          	cv.cmpltu.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpltu-h-pass.s
new file mode 100644
index 00000000000..de032838e09
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpltu.h x0, x0, x0
+    cv.cmpltu.h x1, x1, x1
+    cv.cmpltu.h x2, x2, x2
+    cv.cmpltu.h x8, x8, x8
+    cv.cmpltu.h x20, x20, x20
+    cv.cmpltu.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-b-fail.d
new file mode 100644
index 00000000000..50bab346eec
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpltu-sc-b-fail.s
+#error_output: cv-simd-cmpltu-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-b-fail.l
new file mode 100644
index 00000000000..0b4c9992e7f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpltu.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpltu.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-b-fail.s
new file mode 100644
index 00000000000..6541d12e631
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpltu.sc.b x32, x32, x32
+    cv.cmpltu.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-b-pass.d
new file mode 100644
index 00000000000..3aa01db8faa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpltu-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4400507b          	cv.cmpltu.sc.b	zero,zero,zero
+   4:	4410d0fb          	cv.cmpltu.sc.b	ra,ra,ra
+   8:	4421517b          	cv.cmpltu.sc.b	sp,sp,sp
+   c:	4484547b          	cv.cmpltu.sc.b	s0,s0,s0
+  10:	454a5a7b          	cv.cmpltu.sc.b	s4,s4,s4
+  14:	45ffdffb          	cv.cmpltu.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-b-pass.s
new file mode 100644
index 00000000000..9c2647130e6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpltu.sc.b x0, x0, x0
+    cv.cmpltu.sc.b x1, x1, x1
+    cv.cmpltu.sc.b x2, x2, x2
+    cv.cmpltu.sc.b x8, x8, x8
+    cv.cmpltu.sc.b x20, x20, x20
+    cv.cmpltu.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-h-fail.d
new file mode 100644
index 00000000000..8422ac02345
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpltu-sc-h-fail.s
+#error_output: cv-simd-cmpltu-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-h-fail.l
new file mode 100644
index 00000000000..aa73e2dd5e1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpltu.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpltu.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-h-fail.s
new file mode 100644
index 00000000000..af03693e229
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpltu.sc.h x32, x32, x32
+    cv.cmpltu.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-h-pass.d
new file mode 100644
index 00000000000..6437841a4fa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpltu-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4400407b          	cv.cmpltu.sc.h	zero,zero,zero
+   4:	4410c0fb          	cv.cmpltu.sc.h	ra,ra,ra
+   8:	4421417b          	cv.cmpltu.sc.h	sp,sp,sp
+   c:	4484447b          	cv.cmpltu.sc.h	s0,s0,s0
+  10:	454a4a7b          	cv.cmpltu.sc.h	s4,s4,s4
+  14:	45ffcffb          	cv.cmpltu.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-h-pass.s
new file mode 100644
index 00000000000..9b658a00bcd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpltu.sc.h x0, x0, x0
+    cv.cmpltu.sc.h x1, x1, x1
+    cv.cmpltu.sc.h x2, x2, x2
+    cv.cmpltu.sc.h x8, x8, x8
+    cv.cmpltu.sc.h x20, x20, x20
+    cv.cmpltu.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-b-fail.d
new file mode 100644
index 00000000000..ed3751de479
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpltu-sci-b-fail.s
+#error_output: cv-simd-cmpltu-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-b-fail.l
new file mode 100644
index 00000000000..810a82147fa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpltu.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.cmpltu.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
\ No newline at end of file
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-b-fail.s
new file mode 100644
index 00000000000..54736a9389f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.cmpltu.sci.b x32, x32, 20
+    cv.cmpltu.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpltu.sci.b x6, x7, -1
+    cv.cmpltu.sci.b x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-b-pass.d
new file mode 100644
index 00000000000..2ff3f7dc5fa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-b-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpltu-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	44a0707b          	cv.cmpltu.sci.b	zero,zero,20
+   4:	44a0f0fb          	cv.cmpltu.sci.b	ra,ra,20
+   8:	44a1717b          	cv.cmpltu.sci.b	sp,sp,20
+   c:	44a4747b          	cv.cmpltu.sci.b	s0,s0,20
+  10:	44aa7a7b          	cv.cmpltu.sci.b	s4,s4,20
+  14:	44affffb          	cv.cmpltu.sci.b	t6,t6,20
+  18:	4403f37b          	cv.cmpltu.sci.b	t1,t2,0
+  1c:	47f3f37b          	cv.cmpltu.sci.b	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-b-pass.s
new file mode 100644
index 00000000000..b72b4ca49ff
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-b-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.cmpltu.sci.b x0, x0, 20
+    cv.cmpltu.sci.b x1, x1, 20
+    cv.cmpltu.sci.b x2, x2, 20
+    cv.cmpltu.sci.b x8, x8, 20
+    cv.cmpltu.sci.b x20, x20, 20
+    cv.cmpltu.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.cmpltu.sci.b x6, x7, 0
+    cv.cmpltu.sci.b x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-h-fail.d
new file mode 100644
index 00000000000..4b4a7bee880
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpltu-sci-h-fail.s
+#error_output: cv-simd-cmpltu-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-h-fail.l
new file mode 100644
index 00000000000..73a451bfccc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpltu.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.cmpltu.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
\ No newline at end of file
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-h-fail.s
new file mode 100644
index 00000000000..d32c317e769
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.cmpltu.sci.h x32, x32, 20
+    cv.cmpltu.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpltu.sci.h x6, x7, -1
+    cv.cmpltu.sci.h x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-h-pass.d
new file mode 100644
index 00000000000..5c59dce3e54
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-h-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpltu-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	44a0607b          	cv.cmpltu.sci.h	zero,zero,20
+   4:	44a0e0fb          	cv.cmpltu.sci.h	ra,ra,20
+   8:	44a1617b          	cv.cmpltu.sci.h	sp,sp,20
+   c:	44a4647b          	cv.cmpltu.sci.h	s0,s0,20
+  10:	44aa6a7b          	cv.cmpltu.sci.h	s4,s4,20
+  14:	44afeffb          	cv.cmpltu.sci.h	t6,t6,20
+  18:	4403e37b          	cv.cmpltu.sci.h	t1,t2,0
+  1c:	47f3e37b          	cv.cmpltu.sci.h	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-h-pass.s
new file mode 100644
index 00000000000..092aead3d03
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-h-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.cmpltu.sci.h x0, x0, 20
+    cv.cmpltu.sci.h x1, x1, 20
+    cv.cmpltu.sci.h x2, x2, 20
+    cv.cmpltu.sci.h x8, x8, 20
+    cv.cmpltu.sci.h x20, x20, 20
+    cv.cmpltu.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.cmpltu.sci.h x6, x7, 0
+    cv.cmpltu.sci.h x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpne-b-fail.d
new file mode 100644
index 00000000000..51af5dec963
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpne-b-fail.s
+#error_output: cv-simd-cmpne-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpne-b-fail.l
new file mode 100644
index 00000000000..17dd8aad0d5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpne.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpne.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpne-b-fail.s
new file mode 100644
index 00000000000..996216864f7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpne.b x32, x32, x32
+    cv.cmpne.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpne-b-pass.d
new file mode 100644
index 00000000000..8d034c7e505
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpne-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0c00107b          	cv.cmpne.b	zero,zero,zero
+   4:	0c1090fb          	cv.cmpne.b	ra,ra,ra
+   8:	0c21117b          	cv.cmpne.b	sp,sp,sp
+   c:	0c84147b          	cv.cmpne.b	s0,s0,s0
+  10:	0d4a1a7b          	cv.cmpne.b	s4,s4,s4
+  14:	0dff9ffb          	cv.cmpne.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpne-b-pass.s
new file mode 100644
index 00000000000..cec97fd1411
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpne.b x0, x0, x0
+    cv.cmpne.b x1, x1, x1
+    cv.cmpne.b x2, x2, x2
+    cv.cmpne.b x8, x8, x8
+    cv.cmpne.b x20, x20, x20
+    cv.cmpne.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpne-h-fail.d
new file mode 100644
index 00000000000..624ccd8aaaa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpne-h-fail.s
+#error_output: cv-simd-cmpne-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpne-h-fail.l
new file mode 100644
index 00000000000..0b53e8f593c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpne.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpne.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpne-h-fail.s
new file mode 100644
index 00000000000..530f083631f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpne.h x32, x32, x32
+    cv.cmpne.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpne-h-pass.d
new file mode 100644
index 00000000000..029e561a41e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpne-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0c00007b          	cv.cmpne.h	zero,zero,zero
+   4:	0c1080fb          	cv.cmpne.h	ra,ra,ra
+   8:	0c21017b          	cv.cmpne.h	sp,sp,sp
+   c:	0c84047b          	cv.cmpne.h	s0,s0,s0
+  10:	0d4a0a7b          	cv.cmpne.h	s4,s4,s4
+  14:	0dff8ffb          	cv.cmpne.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpne-h-pass.s
new file mode 100644
index 00000000000..4394e5dc22c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpne.h x0, x0, x0
+    cv.cmpne.h x1, x1, x1
+    cv.cmpne.h x2, x2, x2
+    cv.cmpne.h x8, x8, x8
+    cv.cmpne.h x20, x20, x20
+    cv.cmpne.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-b-fail.d
new file mode 100644
index 00000000000..aff55fbae53
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpne-sc-b-fail.s
+#error_output: cv-simd-cmpne-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-b-fail.l
new file mode 100644
index 00000000000..24afd896558
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpne.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpne.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-b-fail.s
new file mode 100644
index 00000000000..3aaa6d53445
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpne.sc.b x32, x32, x32
+    cv.cmpne.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-b-pass.d
new file mode 100644
index 00000000000..503ca16c0e5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpne-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0c00507b          	cv.cmpne.sc.b	zero,zero,zero
+   4:	0c10d0fb          	cv.cmpne.sc.b	ra,ra,ra
+   8:	0c21517b          	cv.cmpne.sc.b	sp,sp,sp
+   c:	0c84547b          	cv.cmpne.sc.b	s0,s0,s0
+  10:	0d4a5a7b          	cv.cmpne.sc.b	s4,s4,s4
+  14:	0dffdffb          	cv.cmpne.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-b-pass.s
new file mode 100644
index 00000000000..d08bd7b5d59
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpne.sc.b x0, x0, x0
+    cv.cmpne.sc.b x1, x1, x1
+    cv.cmpne.sc.b x2, x2, x2
+    cv.cmpne.sc.b x8, x8, x8
+    cv.cmpne.sc.b x20, x20, x20
+    cv.cmpne.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-h-fail.d
new file mode 100644
index 00000000000..fc715061d72
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpne-sc-h-fail.s
+#error_output: cv-simd-cmpne-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-h-fail.l
new file mode 100644
index 00000000000..34854ac8eee
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpne.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpne.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-h-fail.s
new file mode 100644
index 00000000000..f1c84c3c95f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpne.sc.h x32, x32, x32
+    cv.cmpne.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-h-pass.d
new file mode 100644
index 00000000000..5d36594c891
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpne-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0c00407b          	cv.cmpne.sc.h	zero,zero,zero
+   4:	0c10c0fb          	cv.cmpne.sc.h	ra,ra,ra
+   8:	0c21417b          	cv.cmpne.sc.h	sp,sp,sp
+   c:	0c84447b          	cv.cmpne.sc.h	s0,s0,s0
+  10:	0d4a4a7b          	cv.cmpne.sc.h	s4,s4,s4
+  14:	0dffcffb          	cv.cmpne.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-h-pass.s
new file mode 100644
index 00000000000..f699512ba07
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpne.sc.h x0, x0, x0
+    cv.cmpne.sc.h x1, x1, x1
+    cv.cmpne.sc.h x2, x2, x2
+    cv.cmpne.sc.h x8, x8, x8
+    cv.cmpne.sc.h x20, x20, x20
+    cv.cmpne.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-b-fail.d
new file mode 100644
index 00000000000..83e37b66793
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpne-sci-b-fail.s
+#error_output: cv-simd-cmpne-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-b-fail.l
new file mode 100644
index 00000000000..9ad1b198f54
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpne.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.cmpne.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-b-fail.s
new file mode 100644
index 00000000000..bd2e550e544
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.cmpne.sci.b x32, x32, 20
+    cv.cmpne.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpne.sci.b x6, x7, -33
+    cv.cmpne.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-b-pass.d
new file mode 100644
index 00000000000..0c20249d25e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpne-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0ca0707b          	cv.cmpne.sci.b	zero,zero,20
+   4:	0ca0f0fb          	cv.cmpne.sci.b	ra,ra,20
+   8:	0ca1717b          	cv.cmpne.sci.b	sp,sp,20
+   c:	0ca4747b          	cv.cmpne.sci.b	s0,s0,20
+  10:	0caa7a7b          	cv.cmpne.sci.b	s4,s4,20
+  14:	0caffffb          	cv.cmpne.sci.b	t6,t6,20
+  18:	0d03f37b          	cv.cmpne.sci.b	t1,t2,-32
+  1c:	0c03f37b          	cv.cmpne.sci.b	t1,t2,0
+  20:	0ef3f37b          	cv.cmpne.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-b-pass.s
new file mode 100644
index 00000000000..465a42d3c79
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-b-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.cmpne.sci.b x0, x0, 20
+    cv.cmpne.sci.b x1, x1, 20
+    cv.cmpne.sci.b x2, x2, 20
+    cv.cmpne.sci.b x8, x8, 20
+    cv.cmpne.sci.b x20, x20, 20
+    cv.cmpne.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.cmpne.sci.b x6, x7, -32
+    cv.cmpne.sci.b x6, x7, 0
+    cv.cmpne.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-h-fail.d
new file mode 100644
index 00000000000..0a2f50e59c4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpne-sci-h-fail.s
+#error_output: cv-simd-cmpne-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-h-fail.l
new file mode 100644
index 00000000000..eba861843c8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpne.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.cmpne.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-h-fail.s
new file mode 100644
index 00000000000..10b9d4d8aa8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.cmpne.sci.h x32, x32, 20
+    cv.cmpne.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpne.sci.h x6, x7, -33
+    cv.cmpne.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-h-pass.d
new file mode 100644
index 00000000000..19a3e4cfe73
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpne-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0ca0607b          	cv.cmpne.sci.h	zero,zero,20
+   4:	0ca0e0fb          	cv.cmpne.sci.h	ra,ra,20
+   8:	0ca1617b          	cv.cmpne.sci.h	sp,sp,20
+   c:	0ca4647b          	cv.cmpne.sci.h	s0,s0,20
+  10:	0caa6a7b          	cv.cmpne.sci.h	s4,s4,20
+  14:	0cafeffb          	cv.cmpne.sci.h	t6,t6,20
+  18:	0d03e37b          	cv.cmpne.sci.h	t1,t2,-32
+  1c:	0c03e37b          	cv.cmpne.sci.h	t1,t2,0
+  20:	0ef3e37b          	cv.cmpne.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-h-pass.s
new file mode 100644
index 00000000000..93cdf3af6cb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-h-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.cmpne.sci.h x0, x0, 20
+    cv.cmpne.sci.h x1, x1, 20
+    cv.cmpne.sci.h x2, x2, 20
+    cv.cmpne.sci.h x8, x8, 20
+    cv.cmpne.sci.h x20, x20, 20
+    cv.cmpne.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.cmpne.sci.h x6, x7, -32
+    cv.cmpne.sci.h x6, x7, 0
+    cv.cmpne.sci.h x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxconj-fail.d b/gas/testsuite/gas/riscv/cv-simd-cplxconj-fail.d
new file mode 100644
index 00000000000..a0605a09309
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxconj-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxconj-fail.s
+#error_output: cv-simd-cplxconj-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxconj-fail.l b/gas/testsuite/gas/riscv/cv-simd-cplxconj-fail.l
new file mode 100644
index 00000000000..ed0844fae23
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxconj-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cplxconj x32,x32'
+.*: Error: illegal operands `cv.cplxconj x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxconj-fail.s b/gas/testsuite/gas/riscv/cv-simd-cplxconj-fail.s
new file mode 100644
index 00000000000..186e85f8ea0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxconj-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cplxconj x32, x32
+    cv.cplxconj x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxconj-pass.d b/gas/testsuite/gas/riscv/cv-simd-cplxconj-pass.d
new file mode 100644
index 00000000000..c380f769cf8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxconj-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxconj-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	5c00007b          	cv.cplxconj	zero,zero
+   4:	5c0080fb          	cv.cplxconj	ra,ra
+   8:	5c01017b          	cv.cplxconj	sp,sp
+   c:	5c04047b          	cv.cplxconj	s0,s0
+  10:	5c0a0a7b          	cv.cplxconj	s4,s4
+  14:	5c0f8ffb          	cv.cplxconj	t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxconj-pass.s b/gas/testsuite/gas/riscv/cv-simd-cplxconj-pass.s
new file mode 100644
index 00000000000..7c1fc017ef7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxconj-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cplxconj x0, x0
+    cv.cplxconj x1, x1
+    cv.cplxconj x2, x2
+    cv.cplxconj x8, x8
+    cv.cplxconj x20, x20
+    cv.cplxconj x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div2-fail.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div2-fail.d
new file mode 100644
index 00000000000..7fb7a62b8a0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div2-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-i-div2-fail.s
+#error_output: cv-simd-cplxmul-i-div2-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div2-fail.l b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div2-fail.l
new file mode 100644
index 00000000000..9af5157824d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div2-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cplxmul.i.div2 x32,x32,x32'
+.*: Error: illegal operands `cv.cplxmul.i.div2 x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div2-fail.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div2-fail.s
new file mode 100644
index 00000000000..cdd5b8f1379
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div2-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cplxmul.i.div2 x32, x32, x32
+    cv.cplxmul.i.div2 x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div2-pass.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div2-pass.d
new file mode 100644
index 00000000000..582b2c63c1e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div2-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-i-div2-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	5600207b          	cv.cplxmul.i.div2	zero,zero,zero
+   4:	5610a0fb          	cv.cplxmul.i.div2	ra,ra,ra
+   8:	5621217b          	cv.cplxmul.i.div2	sp,sp,sp
+   c:	5684247b          	cv.cplxmul.i.div2	s0,s0,s0
+  10:	574a2a7b          	cv.cplxmul.i.div2	s4,s4,s4
+  14:	57ffaffb          	cv.cplxmul.i.div2	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div2-pass.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div2-pass.s
new file mode 100644
index 00000000000..c90292dbdd9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div2-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cplxmul.i.div2 x0, x0, x0
+    cv.cplxmul.i.div2 x1, x1, x1
+    cv.cplxmul.i.div2 x2, x2, x2
+    cv.cplxmul.i.div2 x8, x8, x8
+    cv.cplxmul.i.div2 x20, x20, x20
+    cv.cplxmul.i.div2 x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div4-fail.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div4-fail.d
new file mode 100644
index 00000000000..e9b9062f17e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div4-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-i-div4-fail.s
+#error_output: cv-simd-cplxmul-i-div4-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div4-fail.l b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div4-fail.l
new file mode 100644
index 00000000000..c3efbe053eb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div4-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cplxmul.i.div4 x32,x32,x32'
+.*: Error: illegal operands `cv.cplxmul.i.div4 x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div4-fail.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div4-fail.s
new file mode 100644
index 00000000000..e5464864280
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div4-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cplxmul.i.div4 x32, x32, x32
+    cv.cplxmul.i.div4 x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div4-pass.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div4-pass.d
new file mode 100644
index 00000000000..1091785e951
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div4-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-i-div4-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	5600407b          	cv.cplxmul.i.div4	zero,zero,zero
+   4:	5610c0fb          	cv.cplxmul.i.div4	ra,ra,ra
+   8:	5621417b          	cv.cplxmul.i.div4	sp,sp,sp
+   c:	5684447b          	cv.cplxmul.i.div4	s0,s0,s0
+  10:	574a4a7b          	cv.cplxmul.i.div4	s4,s4,s4
+  14:	57ffcffb          	cv.cplxmul.i.div4	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div4-pass.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div4-pass.s
new file mode 100644
index 00000000000..95c840436b1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div4-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cplxmul.i.div4 x0, x0, x0
+    cv.cplxmul.i.div4 x1, x1, x1
+    cv.cplxmul.i.div4 x2, x2, x2
+    cv.cplxmul.i.div4 x8, x8, x8
+    cv.cplxmul.i.div4 x20, x20, x20
+    cv.cplxmul.i.div4 x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div8-fail.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div8-fail.d
new file mode 100644
index 00000000000..a5959794dfe
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div8-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-i-div8-fail.s
+#error_output: cv-simd-cplxmul-i-div8-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div8-fail.l b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div8-fail.l
new file mode 100644
index 00000000000..cc52645bf80
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div8-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cplxmul.i.div8 x32,x32,x32'
+.*: Error: illegal operands `cv.cplxmul.i.div8 x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div8-fail.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div8-fail.s
new file mode 100644
index 00000000000..04b7b4688d6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div8-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cplxmul.i.div8 x32, x32, x32
+    cv.cplxmul.i.div8 x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div8-pass.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div8-pass.d
new file mode 100644
index 00000000000..c81a1dc7c8e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div8-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-i-div8-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	5600607b          	cv.cplxmul.i.div8	zero,zero,zero
+   4:	5610e0fb          	cv.cplxmul.i.div8	ra,ra,ra
+   8:	5621617b          	cv.cplxmul.i.div8	sp,sp,sp
+   c:	5684647b          	cv.cplxmul.i.div8	s0,s0,s0
+  10:	574a6a7b          	cv.cplxmul.i.div8	s4,s4,s4
+  14:	57ffeffb          	cv.cplxmul.i.div8	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div8-pass.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div8-pass.s
new file mode 100644
index 00000000000..5a265cc97fe
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div8-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cplxmul.i.div8 x0, x0, x0
+    cv.cplxmul.i.div8 x1, x1, x1
+    cv.cplxmul.i.div8 x2, x2, x2
+    cv.cplxmul.i.div8 x8, x8, x8
+    cv.cplxmul.i.div8 x20, x20, x20
+    cv.cplxmul.i.div8 x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-fail.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-fail.d
new file mode 100644
index 00000000000..5a1f3f4025b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-i-fail.s
+#error_output: cv-simd-cplxmul-i-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-fail.l b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-fail.l
new file mode 100644
index 00000000000..4d63c3d02b5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cplxmul.i x32,x32,x32'
+.*: Error: illegal operands `cv.cplxmul.i x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-fail.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-fail.s
new file mode 100644
index 00000000000..de8deac97b9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cplxmul.i x32, x32, x32
+    cv.cplxmul.i x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-pass.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-pass.d
new file mode 100644
index 00000000000..4c346bde03d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-i-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	5600007b          	cv.cplxmul.i	zero,zero,zero
+   4:	561080fb          	cv.cplxmul.i	ra,ra,ra
+   8:	5621017b          	cv.cplxmul.i	sp,sp,sp
+   c:	5684047b          	cv.cplxmul.i	s0,s0,s0
+  10:	574a0a7b          	cv.cplxmul.i	s4,s4,s4
+  14:	57ff8ffb          	cv.cplxmul.i	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-pass.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-pass.s
new file mode 100644
index 00000000000..f3a20c71259
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cplxmul.i x0, x0, x0
+    cv.cplxmul.i x1, x1, x1
+    cv.cplxmul.i x2, x2, x2
+    cv.cplxmul.i x8, x8, x8
+    cv.cplxmul.i x20, x20, x20
+    cv.cplxmul.i x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div2-fail.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div2-fail.d
new file mode 100644
index 00000000000..329cfbdf65e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div2-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-r-div2-fail.s
+#error_output: cv-simd-cplxmul-r-div2-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div2-fail.l b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div2-fail.l
new file mode 100644
index 00000000000..0f6c70cbaa1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div2-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cplxmul.r.div2 x32,x32,x32'
+.*: Error: illegal operands `cv.cplxmul.r.div2 x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div2-fail.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div2-fail.s
new file mode 100644
index 00000000000..f37d2ebba3d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div2-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cplxmul.r.div2 x32, x32, x32
+    cv.cplxmul.r.div2 x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div2-pass.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div2-pass.d
new file mode 100644
index 00000000000..c8e8e61b55e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div2-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-r-div2-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	5400207b          	cv.cplxmul.r.div2	zero,zero,zero
+   4:	5410a0fb          	cv.cplxmul.r.div2	ra,ra,ra
+   8:	5421217b          	cv.cplxmul.r.div2	sp,sp,sp
+   c:	5484247b          	cv.cplxmul.r.div2	s0,s0,s0
+  10:	554a2a7b          	cv.cplxmul.r.div2	s4,s4,s4
+  14:	55ffaffb          	cv.cplxmul.r.div2	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div2-pass.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div2-pass.s
new file mode 100644
index 00000000000..12af3c2e772
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div2-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cplxmul.r.div2 x0, x0, x0
+    cv.cplxmul.r.div2 x1, x1, x1
+    cv.cplxmul.r.div2 x2, x2, x2
+    cv.cplxmul.r.div2 x8, x8, x8
+    cv.cplxmul.r.div2 x20, x20, x20
+    cv.cplxmul.r.div2 x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div4-fail.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div4-fail.d
new file mode 100644
index 00000000000..e1dd762124d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div4-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-r-div4-fail.s
+#error_output: cv-simd-cplxmul-r-div4-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div4-fail.l b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div4-fail.l
new file mode 100644
index 00000000000..3fa875f7a3c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div4-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cplxmul.r.div4 x32,x32,x32'
+.*: Error: illegal operands `cv.cplxmul.r.div4 x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div4-fail.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div4-fail.s
new file mode 100644
index 00000000000..15bd239d8ce
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div4-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cplxmul.r.div4 x32, x32, x32
+    cv.cplxmul.r.div4 x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div4-pass.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div4-pass.d
new file mode 100644
index 00000000000..3f99541f5bd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div4-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-r-div4-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	5400407b          	cv.cplxmul.r.div4	zero,zero,zero
+   4:	5410c0fb          	cv.cplxmul.r.div4	ra,ra,ra
+   8:	5421417b          	cv.cplxmul.r.div4	sp,sp,sp
+   c:	5484447b          	cv.cplxmul.r.div4	s0,s0,s0
+  10:	554a4a7b          	cv.cplxmul.r.div4	s4,s4,s4
+  14:	55ffcffb          	cv.cplxmul.r.div4	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div4-pass.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div4-pass.s
new file mode 100644
index 00000000000..d14f98520ea
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div4-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cplxmul.r.div4 x0, x0, x0
+    cv.cplxmul.r.div4 x1, x1, x1
+    cv.cplxmul.r.div4 x2, x2, x2
+    cv.cplxmul.r.div4 x8, x8, x8
+    cv.cplxmul.r.div4 x20, x20, x20
+    cv.cplxmul.r.div4 x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div8-fail.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div8-fail.d
new file mode 100644
index 00000000000..02b11f31228
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div8-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-r-div8-fail.s
+#error_output: cv-simd-cplxmul-r-div8-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div8-fail.l b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div8-fail.l
new file mode 100644
index 00000000000..ba8c9752dad
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div8-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cplxmul.r.div8 x32,x32,x32'
+.*: Error: illegal operands `cv.cplxmul.r.div8 x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div8-fail.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div8-fail.s
new file mode 100644
index 00000000000..62e66c984e0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div8-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cplxmul.r.div8 x32, x32, x32
+    cv.cplxmul.r.div8 x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div8-pass.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div8-pass.d
new file mode 100644
index 00000000000..cdc13e64fcd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div8-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-r-div8-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	5400607b          	cv.cplxmul.r.div8	zero,zero,zero
+   4:	5410e0fb          	cv.cplxmul.r.div8	ra,ra,ra
+   8:	5421617b          	cv.cplxmul.r.div8	sp,sp,sp
+   c:	5484647b          	cv.cplxmul.r.div8	s0,s0,s0
+  10:	554a6a7b          	cv.cplxmul.r.div8	s4,s4,s4
+  14:	55ffeffb          	cv.cplxmul.r.div8	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div8-pass.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div8-pass.s
new file mode 100644
index 00000000000..cee5c7bbbe2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div8-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cplxmul.r.div8 x0, x0, x0
+    cv.cplxmul.r.div8 x1, x1, x1
+    cv.cplxmul.r.div8 x2, x2, x2
+    cv.cplxmul.r.div8 x8, x8, x8
+    cv.cplxmul.r.div8 x20, x20, x20
+    cv.cplxmul.r.div8 x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-fail.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-fail.d
new file mode 100644
index 00000000000..ee4480a46e7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-r-fail.s
+#error_output: cv-simd-cplxmul-r-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-fail.l b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-fail.l
new file mode 100644
index 00000000000..f3f3a9cc542
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cplxmul.r x32,x32,x32'
+.*: Error: illegal operands `cv.cplxmul.r x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-fail.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-fail.s
new file mode 100644
index 00000000000..b21557bb80a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cplxmul.r x32, x32, x32
+    cv.cplxmul.r x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-pass.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-pass.d
new file mode 100644
index 00000000000..d8f8c7ab0d8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-r-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	5400007b          	cv.cplxmul.r	zero,zero,zero
+   4:	541080fb          	cv.cplxmul.r	ra,ra,ra
+   8:	5421017b          	cv.cplxmul.r	sp,sp,sp
+   c:	5484047b          	cv.cplxmul.r	s0,s0,s0
+  10:	554a0a7b          	cv.cplxmul.r	s4,s4,s4
+  14:	55ff8ffb          	cv.cplxmul.r	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-pass.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-pass.s
new file mode 100644
index 00000000000..e2c929a485e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cplxmul.r x0, x0, x0
+    cv.cplxmul.r x1, x1, x1
+    cv.cplxmul.r x2, x2, x2
+    cv.cplxmul.r x8, x8, x8
+    cv.cplxmul.r x20, x20, x20
+    cv.cplxmul.r x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotsp-b-fail.d
new file mode 100644
index 00000000000..78a375e025f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotsp-b-fail.s
+#error_output: cv-simd-dotsp-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotsp-b-fail.l
new file mode 100644
index 00000000000..05e06134148
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotsp.b x32,x32,x32'
+.*: Error: illegal operands `cv.dotsp.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotsp-b-fail.s
new file mode 100644
index 00000000000..fea262538e2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.dotsp.b x32, x32, x32
+    cv.dotsp.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotsp-b-pass.d
new file mode 100644
index 00000000000..43fb568fe05
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotsp-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	9000107b          	cv.dotsp.b	zero,zero,zero
+   4:	901090fb          	cv.dotsp.b	ra,ra,ra
+   8:	9021117b          	cv.dotsp.b	sp,sp,sp
+   c:	9084147b          	cv.dotsp.b	s0,s0,s0
+  10:	914a1a7b          	cv.dotsp.b	s4,s4,s4
+  14:	91ff9ffb          	cv.dotsp.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotsp-b-pass.s
new file mode 100644
index 00000000000..c9c1070f479
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.dotsp.b x0, x0, x0
+    cv.dotsp.b x1, x1, x1
+    cv.dotsp.b x2, x2, x2
+    cv.dotsp.b x8, x8, x8
+    cv.dotsp.b x20, x20, x20
+    cv.dotsp.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotsp-h-fail.d
new file mode 100644
index 00000000000..cb8ba2656fb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotsp-h-fail.s
+#error_output: cv-simd-dotsp-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotsp-h-fail.l
new file mode 100644
index 00000000000..9a4969c3e92
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotsp.h x32,x32,x32'
+.*: Error: illegal operands `cv.dotsp.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotsp-h-fail.s
new file mode 100644
index 00000000000..09ccb4898c3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.dotsp.h x32, x32, x32
+    cv.dotsp.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotsp-h-pass.d
new file mode 100644
index 00000000000..b6ee73a3f15
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotsp-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	9000007b          	cv.dotsp.h	zero,zero,zero
+   4:	901080fb          	cv.dotsp.h	ra,ra,ra
+   8:	9021017b          	cv.dotsp.h	sp,sp,sp
+   c:	9084047b          	cv.dotsp.h	s0,s0,s0
+  10:	914a0a7b          	cv.dotsp.h	s4,s4,s4
+  14:	91ff8ffb          	cv.dotsp.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotsp-h-pass.s
new file mode 100644
index 00000000000..5d651502c62
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.dotsp.h x0, x0, x0
+    cv.dotsp.h x1, x1, x1
+    cv.dotsp.h x2, x2, x2
+    cv.dotsp.h x8, x8, x8
+    cv.dotsp.h x20, x20, x20
+    cv.dotsp.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-b-fail.d
new file mode 100644
index 00000000000..cd9ffacc679
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotsp-sc-b-fail.s
+#error_output: cv-simd-dotsp-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-b-fail.l
new file mode 100644
index 00000000000..f08b9016d62
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotsp.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.dotsp.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-b-fail.s
new file mode 100644
index 00000000000..594a6f54983
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.dotsp.sc.b x32, x32, x32
+    cv.dotsp.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-b-pass.d
new file mode 100644
index 00000000000..d318e9030eb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotsp-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	9000507b          	cv.dotsp.sc.b	zero,zero,zero
+   4:	9010d0fb          	cv.dotsp.sc.b	ra,ra,ra
+   8:	9021517b          	cv.dotsp.sc.b	sp,sp,sp
+   c:	9084547b          	cv.dotsp.sc.b	s0,s0,s0
+  10:	914a5a7b          	cv.dotsp.sc.b	s4,s4,s4
+  14:	91ffdffb          	cv.dotsp.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-b-pass.s
new file mode 100644
index 00000000000..2a498253989
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.dotsp.sc.b x0, x0, x0
+    cv.dotsp.sc.b x1, x1, x1
+    cv.dotsp.sc.b x2, x2, x2
+    cv.dotsp.sc.b x8, x8, x8
+    cv.dotsp.sc.b x20, x20, x20
+    cv.dotsp.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-h-fail.d
new file mode 100644
index 00000000000..6760134f668
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotsp-sc-h-fail.s
+#error_output: cv-simd-dotsp-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-h-fail.l
new file mode 100644
index 00000000000..16aa43d60bd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotsp.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.dotsp.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-h-fail.s
new file mode 100644
index 00000000000..6873a449870
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.dotsp.sc.h x32, x32, x32
+    cv.dotsp.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-h-pass.d
new file mode 100644
index 00000000000..418ccea6343
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotsp-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	9000407b          	cv.dotsp.sc.h	zero,zero,zero
+   4:	9010c0fb          	cv.dotsp.sc.h	ra,ra,ra
+   8:	9021417b          	cv.dotsp.sc.h	sp,sp,sp
+   c:	9084447b          	cv.dotsp.sc.h	s0,s0,s0
+  10:	914a4a7b          	cv.dotsp.sc.h	s4,s4,s4
+  14:	91ffcffb          	cv.dotsp.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-h-pass.s
new file mode 100644
index 00000000000..a70c8278b67
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.dotsp.sc.h x0, x0, x0
+    cv.dotsp.sc.h x1, x1, x1
+    cv.dotsp.sc.h x2, x2, x2
+    cv.dotsp.sc.h x8, x8, x8
+    cv.dotsp.sc.h x20, x20, x20
+    cv.dotsp.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-b-fail.d
new file mode 100644
index 00000000000..57ec9b6093b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotsp-sci-b-fail.s
+#error_output: cv-simd-dotsp-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-b-fail.l
new file mode 100644
index 00000000000..76fff08f39b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotsp.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.dotsp.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-b-fail.s
new file mode 100644
index 00000000000..4d6307e1a7d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.dotsp.sci.b x32, x32, 20
+    cv.dotsp.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.dotsp.sci.b x6, x7, -33
+    cv.dotsp.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-b-pass.d
new file mode 100644
index 00000000000..f89184af378
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotsp-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	90a0707b          	cv.dotsp.sci.b	zero,zero,20
+   4:	90a0f0fb          	cv.dotsp.sci.b	ra,ra,20
+   8:	90a1717b          	cv.dotsp.sci.b	sp,sp,20
+   c:	90a4747b          	cv.dotsp.sci.b	s0,s0,20
+  10:	90aa7a7b          	cv.dotsp.sci.b	s4,s4,20
+  14:	90affffb          	cv.dotsp.sci.b	t6,t6,20
+  18:	9103f37b          	cv.dotsp.sci.b	t1,t2,-32
+  1c:	9003f37b          	cv.dotsp.sci.b	t1,t2,0
+  20:	92f3f37b          	cv.dotsp.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-b-pass.s
new file mode 100644
index 00000000000..e98e027903c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-b-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.dotsp.sci.b x0, x0, 20
+    cv.dotsp.sci.b x1, x1, 20
+    cv.dotsp.sci.b x2, x2, 20
+    cv.dotsp.sci.b x8, x8, 20
+    cv.dotsp.sci.b x20, x20, 20
+    cv.dotsp.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.dotsp.sci.b x6, x7, -32
+    cv.dotsp.sci.b x6, x7, 0
+    cv.dotsp.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-h-fail.d
new file mode 100644
index 00000000000..3aba92e6349
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotsp-sci-h-fail.s
+#error_output: cv-simd-dotsp-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-h-fail.l
new file mode 100644
index 00000000000..9410a24e1c9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotsp.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.dotsp.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-h-fail.s
new file mode 100644
index 00000000000..bc7fb62d76d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.dotsp.sci.h x32, x32, 20
+    cv.dotsp.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.dotsp.sci.h x6, x7, -33
+    cv.dotsp.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-h-pass.d
new file mode 100644
index 00000000000..330dcdadab0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotsp-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	90a0607b          	cv.dotsp.sci.h	zero,zero,20
+   4:	90a0e0fb          	cv.dotsp.sci.h	ra,ra,20
+   8:	90a1617b          	cv.dotsp.sci.h	sp,sp,20
+   c:	90a4647b          	cv.dotsp.sci.h	s0,s0,20
+  10:	90aa6a7b          	cv.dotsp.sci.h	s4,s4,20
+  14:	90afeffb          	cv.dotsp.sci.h	t6,t6,20
+  18:	9103e37b          	cv.dotsp.sci.h	t1,t2,-32
+  1c:	9003e37b          	cv.dotsp.sci.h	t1,t2,0
+  20:	92f3e37b          	cv.dotsp.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-h-pass.s
new file mode 100644
index 00000000000..d0bcf39c3ff
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-h-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.dotsp.sci.h x0, x0, 20
+    cv.dotsp.sci.h x1, x1, 20
+    cv.dotsp.sci.h x2, x2, 20
+    cv.dotsp.sci.h x8, x8, 20
+    cv.dotsp.sci.h x20, x20, 20
+    cv.dotsp.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.dotsp.sci.h x6, x7, -32
+    cv.dotsp.sci.h x6, x7, 0
+    cv.dotsp.sci.h x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotup-b-fail.d
new file mode 100644
index 00000000000..a1acd2d00d0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotup-b-fail.s
+#error_output: cv-simd-dotup-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotup-b-fail.l
new file mode 100644
index 00000000000..7a3964aece1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotup.b x32,x32,x32'
+.*: Error: illegal operands `cv.dotup.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotup-b-fail.s
new file mode 100644
index 00000000000..858ee2aac83
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.dotup.b x32, x32, x32
+    cv.dotup.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotup-b-pass.d
new file mode 100644
index 00000000000..baee7940f2e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotup-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	8000107b          	cv.dotup.b	zero,zero,zero
+   4:	801090fb          	cv.dotup.b	ra,ra,ra
+   8:	8021117b          	cv.dotup.b	sp,sp,sp
+   c:	8084147b          	cv.dotup.b	s0,s0,s0
+  10:	814a1a7b          	cv.dotup.b	s4,s4,s4
+  14:	81ff9ffb          	cv.dotup.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotup-b-pass.s
new file mode 100644
index 00000000000..f689f8f1225
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.dotup.b x0, x0, x0
+    cv.dotup.b x1, x1, x1
+    cv.dotup.b x2, x2, x2
+    cv.dotup.b x8, x8, x8
+    cv.dotup.b x20, x20, x20
+    cv.dotup.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotup-h-fail.d
new file mode 100644
index 00000000000..744f55d56c3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotup-h-fail.s
+#error_output: cv-simd-dotup-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotup-h-fail.l
new file mode 100644
index 00000000000..3bc820e3e8b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotup.h x32,x32,x32'
+.*: Error: illegal operands `cv.dotup.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotup-h-fail.s
new file mode 100644
index 00000000000..8148e5f9a17
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.dotup.h x32, x32, x32
+    cv.dotup.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotup-h-pass.d
new file mode 100644
index 00000000000..44f9c9c7e3c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotup-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	8000007b          	cv.dotup.h	zero,zero,zero
+   4:	801080fb          	cv.dotup.h	ra,ra,ra
+   8:	8021017b          	cv.dotup.h	sp,sp,sp
+   c:	8084047b          	cv.dotup.h	s0,s0,s0
+  10:	814a0a7b          	cv.dotup.h	s4,s4,s4
+  14:	81ff8ffb          	cv.dotup.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotup-h-pass.s
new file mode 100644
index 00000000000..bf8ac6d64ad
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.dotup.h x0, x0, x0
+    cv.dotup.h x1, x1, x1
+    cv.dotup.h x2, x2, x2
+    cv.dotup.h x8, x8, x8
+    cv.dotup.h x20, x20, x20
+    cv.dotup.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-b-fail.d
new file mode 100644
index 00000000000..b43265562a7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotup-sc-b-fail.s
+#error_output: cv-simd-dotup-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-b-fail.l
new file mode 100644
index 00000000000..86044aeac47
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotup.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.dotup.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-b-fail.s
new file mode 100644
index 00000000000..c050e02c185
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.dotup.sc.b x32, x32, x32
+    cv.dotup.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-b-pass.d
new file mode 100644
index 00000000000..305d5ec70c4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotup-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	8000507b          	cv.dotup.sc.b	zero,zero,zero
+   4:	8010d0fb          	cv.dotup.sc.b	ra,ra,ra
+   8:	8021517b          	cv.dotup.sc.b	sp,sp,sp
+   c:	8084547b          	cv.dotup.sc.b	s0,s0,s0
+  10:	814a5a7b          	cv.dotup.sc.b	s4,s4,s4
+  14:	81ffdffb          	cv.dotup.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-b-pass.s
new file mode 100644
index 00000000000..332c0abd010
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.dotup.sc.b x0, x0, x0
+    cv.dotup.sc.b x1, x1, x1
+    cv.dotup.sc.b x2, x2, x2
+    cv.dotup.sc.b x8, x8, x8
+    cv.dotup.sc.b x20, x20, x20
+    cv.dotup.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-h-fail.d
new file mode 100644
index 00000000000..5f2978f4bbe
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotup-sc-h-fail.s
+#error_output: cv-simd-dotup-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-h-fail.l
new file mode 100644
index 00000000000..c2264dcdb7c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotup.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.dotup.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-h-fail.s
new file mode 100644
index 00000000000..f60879dcefc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.dotup.sc.h x32, x32, x32
+    cv.dotup.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-h-pass.d
new file mode 100644
index 00000000000..72ce17d933b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotup-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	8000407b          	cv.dotup.sc.h	zero,zero,zero
+   4:	8010c0fb          	cv.dotup.sc.h	ra,ra,ra
+   8:	8021417b          	cv.dotup.sc.h	sp,sp,sp
+   c:	8084447b          	cv.dotup.sc.h	s0,s0,s0
+  10:	814a4a7b          	cv.dotup.sc.h	s4,s4,s4
+  14:	81ffcffb          	cv.dotup.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-h-pass.s
new file mode 100644
index 00000000000..305442c7bcc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.dotup.sc.h x0, x0, x0
+    cv.dotup.sc.h x1, x1, x1
+    cv.dotup.sc.h x2, x2, x2
+    cv.dotup.sc.h x8, x8, x8
+    cv.dotup.sc.h x20, x20, x20
+    cv.dotup.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-b-fail.d
new file mode 100644
index 00000000000..1e1d17b7df2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotup-sci-b-fail.s
+#error_output: cv-simd-dotup-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-b-fail.l
new file mode 100644
index 00000000000..06ab6ad68c9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotup.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.dotup.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-b-fail.s
new file mode 100644
index 00000000000..94e34518ccf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.dotup.sci.b x32, x32, 20
+    cv.dotup.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.dotup.sci.b x6, x7, -1
+    cv.dotup.sci.b x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-b-pass.d
new file mode 100644
index 00000000000..e730b7157e8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-b-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotup-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	80a0707b          	cv.dotup.sci.b	zero,zero,20
+   4:	80a0f0fb          	cv.dotup.sci.b	ra,ra,20
+   8:	80a1717b          	cv.dotup.sci.b	sp,sp,20
+   c:	80a4747b          	cv.dotup.sci.b	s0,s0,20
+  10:	80aa7a7b          	cv.dotup.sci.b	s4,s4,20
+  14:	80affffb          	cv.dotup.sci.b	t6,t6,20
+  18:	8003f37b          	cv.dotup.sci.b	t1,t2,0
+  1c:	83f3f37b          	cv.dotup.sci.b	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-b-pass.s
new file mode 100644
index 00000000000..9dcb63433f1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-b-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.dotup.sci.b x0, x0, 20
+    cv.dotup.sci.b x1, x1, 20
+    cv.dotup.sci.b x2, x2, 20
+    cv.dotup.sci.b x8, x8, 20
+    cv.dotup.sci.b x20, x20, 20
+    cv.dotup.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.dotup.sci.b x6, x7, 0
+    cv.dotup.sci.b x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-h-fail.d
new file mode 100644
index 00000000000..b2d54310161
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotup-sci-h-fail.s
+#error_output: cv-simd-dotup-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-h-fail.l
new file mode 100644
index 00000000000..f62408540de
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotup.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.dotup.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-h-fail.s
new file mode 100644
index 00000000000..5e08fc7a4ad
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.dotup.sci.h x32, x32, 20
+    cv.dotup.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.dotup.sci.h x6, x7, -1
+    cv.dotup.sci.h x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-h-pass.d
new file mode 100644
index 00000000000..fed5c6b5b8c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-h-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotup-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	80a0607b          	cv.dotup.sci.h	zero,zero,20
+   4:	80a0e0fb          	cv.dotup.sci.h	ra,ra,20
+   8:	80a1617b          	cv.dotup.sci.h	sp,sp,20
+   c:	80a4647b          	cv.dotup.sci.h	s0,s0,20
+  10:	80aa6a7b          	cv.dotup.sci.h	s4,s4,20
+  14:	80afeffb          	cv.dotup.sci.h	t6,t6,20
+  18:	8003e37b          	cv.dotup.sci.h	t1,t2,0
+  1c:	83f3e37b          	cv.dotup.sci.h	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-h-pass.s
new file mode 100644
index 00000000000..3ea446ded09
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-h-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.dotup.sci.h x0, x0, 20
+    cv.dotup.sci.h x1, x1, 20
+    cv.dotup.sci.h x2, x2, 20
+    cv.dotup.sci.h x8, x8, 20
+    cv.dotup.sci.h x20, x20, 20
+    cv.dotup.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.dotup.sci.h x6, x7, 0
+    cv.dotup.sci.h x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotusp-b-fail.d
new file mode 100644
index 00000000000..cefd5542193
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotusp-b-fail.s
+#error_output: cv-simd-dotusp-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotusp-b-fail.l
new file mode 100644
index 00000000000..da8dcc44589
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotusp.b x32,x32,x32'
+.*: Error: illegal operands `cv.dotusp.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotusp-b-fail.s
new file mode 100644
index 00000000000..f7a1dfa2415
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.dotusp.b x32, x32, x32
+    cv.dotusp.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotusp-b-pass.d
new file mode 100644
index 00000000000..adb512c1d6d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotusp-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	8800107b          	cv.dotusp.b	zero,zero,zero
+   4:	881090fb          	cv.dotusp.b	ra,ra,ra
+   8:	8821117b          	cv.dotusp.b	sp,sp,sp
+   c:	8884147b          	cv.dotusp.b	s0,s0,s0
+  10:	894a1a7b          	cv.dotusp.b	s4,s4,s4
+  14:	89ff9ffb          	cv.dotusp.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotusp-b-pass.s
new file mode 100644
index 00000000000..50d191e0053
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.dotusp.b x0, x0, x0
+    cv.dotusp.b x1, x1, x1
+    cv.dotusp.b x2, x2, x2
+    cv.dotusp.b x8, x8, x8
+    cv.dotusp.b x20, x20, x20
+    cv.dotusp.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotusp-h-fail.d
new file mode 100644
index 00000000000..fdede84e736
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotusp-h-fail.s
+#error_output: cv-simd-dotusp-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotusp-h-fail.l
new file mode 100644
index 00000000000..3b025c9b718
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotusp.h x32,x32,x32'
+.*: Error: illegal operands `cv.dotusp.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotusp-h-fail.s
new file mode 100644
index 00000000000..69fd8c4b4f4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.dotusp.h x32, x32, x32
+    cv.dotusp.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotusp-h-pass.d
new file mode 100644
index 00000000000..4727622b959
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotusp-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	8800007b          	cv.dotusp.h	zero,zero,zero
+   4:	881080fb          	cv.dotusp.h	ra,ra,ra
+   8:	8821017b          	cv.dotusp.h	sp,sp,sp
+   c:	8884047b          	cv.dotusp.h	s0,s0,s0
+  10:	894a0a7b          	cv.dotusp.h	s4,s4,s4
+  14:	89ff8ffb          	cv.dotusp.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotusp-h-pass.s
new file mode 100644
index 00000000000..77e58734be0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.dotusp.h x0, x0, x0
+    cv.dotusp.h x1, x1, x1
+    cv.dotusp.h x2, x2, x2
+    cv.dotusp.h x8, x8, x8
+    cv.dotusp.h x20, x20, x20
+    cv.dotusp.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-b-fail.d
new file mode 100644
index 00000000000..dc763469da8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotusp-sc-b-fail.s
+#error_output: cv-simd-dotusp-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-b-fail.l
new file mode 100644
index 00000000000..c1c7d325c99
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotusp.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.dotusp.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-b-fail.s
new file mode 100644
index 00000000000..7a2863a5679
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.dotusp.sc.b x32, x32, x32
+    cv.dotusp.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-b-pass.d
new file mode 100644
index 00000000000..a8c2408e753
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotusp-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	8800507b          	cv.dotusp.sc.b	zero,zero,zero
+   4:	8810d0fb          	cv.dotusp.sc.b	ra,ra,ra
+   8:	8821517b          	cv.dotusp.sc.b	sp,sp,sp
+   c:	8884547b          	cv.dotusp.sc.b	s0,s0,s0
+  10:	894a5a7b          	cv.dotusp.sc.b	s4,s4,s4
+  14:	89ffdffb          	cv.dotusp.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-b-pass.s
new file mode 100644
index 00000000000..6318c733d95
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.dotusp.sc.b x0, x0, x0
+    cv.dotusp.sc.b x1, x1, x1
+    cv.dotusp.sc.b x2, x2, x2
+    cv.dotusp.sc.b x8, x8, x8
+    cv.dotusp.sc.b x20, x20, x20
+    cv.dotusp.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-h-fail.d
new file mode 100644
index 00000000000..aa166ddc6e7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotusp-sc-h-fail.s
+#error_output: cv-simd-dotusp-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-h-fail.l
new file mode 100644
index 00000000000..48e1819aa53
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotusp.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.dotusp.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-h-fail.s
new file mode 100644
index 00000000000..1ef27353cdf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.dotusp.sc.h x32, x32, x32
+    cv.dotusp.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-h-pass.d
new file mode 100644
index 00000000000..a3afc79157e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotusp-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	8800407b          	cv.dotusp.sc.h	zero,zero,zero
+   4:	8810c0fb          	cv.dotusp.sc.h	ra,ra,ra
+   8:	8821417b          	cv.dotusp.sc.h	sp,sp,sp
+   c:	8884447b          	cv.dotusp.sc.h	s0,s0,s0
+  10:	894a4a7b          	cv.dotusp.sc.h	s4,s4,s4
+  14:	89ffcffb          	cv.dotusp.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-h-pass.s
new file mode 100644
index 00000000000..04e69bc7c6d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.dotusp.sc.h x0, x0, x0
+    cv.dotusp.sc.h x1, x1, x1
+    cv.dotusp.sc.h x2, x2, x2
+    cv.dotusp.sc.h x8, x8, x8
+    cv.dotusp.sc.h x20, x20, x20
+    cv.dotusp.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-b-fail.d
new file mode 100644
index 00000000000..0ea3d54f7c7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotusp-sci-b-fail.s
+#error_output: cv-simd-dotusp-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-b-fail.l
new file mode 100644
index 00000000000..6e3e7bf28de
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotusp.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.dotusp.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-b-fail.s
new file mode 100644
index 00000000000..78198cf290d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.dotusp.sci.b x32, x32, 20
+    cv.dotusp.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.dotusp.sci.b x6, x7, -33
+    cv.dotusp.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-b-pass.d
new file mode 100644
index 00000000000..e9f956ad384
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotusp-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	88a0707b          	cv.dotusp.sci.b	zero,zero,20
+   4:	88a0f0fb          	cv.dotusp.sci.b	ra,ra,20
+   8:	88a1717b          	cv.dotusp.sci.b	sp,sp,20
+   c:	88a4747b          	cv.dotusp.sci.b	s0,s0,20
+  10:	88aa7a7b          	cv.dotusp.sci.b	s4,s4,20
+  14:	88affffb          	cv.dotusp.sci.b	t6,t6,20
+  18:	8903f37b          	cv.dotusp.sci.b	t1,t2,-32
+  1c:	8803f37b          	cv.dotusp.sci.b	t1,t2,0
+  20:	8af3f37b          	cv.dotusp.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-b-pass.s
new file mode 100644
index 00000000000..618abbb88cb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-b-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.dotusp.sci.b x0, x0, 20
+    cv.dotusp.sci.b x1, x1, 20
+    cv.dotusp.sci.b x2, x2, 20
+    cv.dotusp.sci.b x8, x8, 20
+    cv.dotusp.sci.b x20, x20, 20
+    cv.dotusp.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.dotusp.sci.b x6, x7, -32
+    cv.dotusp.sci.b x6, x7, 0
+    cv.dotusp.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-h-fail.d
new file mode 100644
index 00000000000..89ed824b8a6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotusp-sci-h-fail.s
+#error_output: cv-simd-dotusp-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-h-fail.l
new file mode 100644
index 00000000000..99f14c09c12
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotusp.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.dotusp.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-h-fail.s
new file mode 100644
index 00000000000..b5ae531aa6f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.dotusp.sci.h x32, x32, 20
+    cv.dotusp.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.dotusp.sci.h x6, x7, -33
+    cv.dotusp.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-h-pass.d
new file mode 100644
index 00000000000..cb5e2aeca57
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotusp-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	88a0607b          	cv.dotusp.sci.h	zero,zero,20
+   4:	88a0e0fb          	cv.dotusp.sci.h	ra,ra,20
+   8:	88a1617b          	cv.dotusp.sci.h	sp,sp,20
+   c:	88a4647b          	cv.dotusp.sci.h	s0,s0,20
+  10:	88aa6a7b          	cv.dotusp.sci.h	s4,s4,20
+  14:	88afeffb          	cv.dotusp.sci.h	t6,t6,20
+  18:	8903e37b          	cv.dotusp.sci.h	t1,t2,-32
+  1c:	8803e37b          	cv.dotusp.sci.h	t1,t2,0
+  20:	8af3e37b          	cv.dotusp.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-h-pass.s
new file mode 100644
index 00000000000..991095197f0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-h-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.dotusp.sci.h x0, x0, 20
+    cv.dotusp.sci.h x1, x1, 20
+    cv.dotusp.sci.h x2, x2, 20
+    cv.dotusp.sci.h x8, x8, 20
+    cv.dotusp.sci.h x20, x20, 20
+    cv.dotusp.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.dotusp.sci.h x6, x7, -32
+    cv.dotusp.sci.h x6, x7, 0
+    cv.dotusp.sci.h x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-extract-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-extract-b-fail.d
new file mode 100644
index 00000000000..dc987eef71c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extract-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-extract-b-fail.s
+#error_output: cv-simd-extract-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-extract-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-extract-b-fail.l
new file mode 100644
index 00000000000..8bd2af78338
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extract-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.extract.b x32,x32,2'
+.*: Error: illegal operands `cv.extract.b x33,x33,2'
+.*: Error: immediate value must be 2-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 2-bit unsigned, 4 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-extract-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-extract-b-fail.s
new file mode 100644
index 00000000000..bb5fc63e2b3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extract-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.extract.b x32, x32, 2
+    cv.extract.b x33, x33, 2
+    #Boundary Immediate Values Test
+    cv.extract.b x6, x7, -1
+    cv.extract.b x6, x7, 4
diff --git a/gas/testsuite/gas/riscv/cv-simd-extract-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-extract-b-pass.d
new file mode 100644
index 00000000000..4e66cffd156
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extract-b-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-extract-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	b810107b          	cv.extract.b	zero,zero,2
+   4:	b81090fb          	cv.extract.b	ra,ra,2
+   8:	b811117b          	cv.extract.b	sp,sp,2
+   c:	b814147b          	cv.extract.b	s0,s0,2
+  10:	b81a1a7b          	cv.extract.b	s4,s4,2
+  14:	b81f9ffb          	cv.extract.b	t6,t6,2
+  18:	b803937b          	cv.extract.b	t1,t2,0
+  1c:	ba13937b          	cv.extract.b	t1,t2,3
diff --git a/gas/testsuite/gas/riscv/cv-simd-extract-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-extract-b-pass.s
new file mode 100644
index 00000000000..04e87dbb847
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extract-b-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.extract.b x0, x0, 2
+    cv.extract.b x1, x1, 2
+    cv.extract.b x2, x2, 2
+    cv.extract.b x8, x8, 2
+    cv.extract.b x20, x20, 2
+    cv.extract.b x31, x31, 2
+    #Immediate Values Test
+    cv.extract.b x6, x7, 0
+    cv.extract.b x6, x7, 3
diff --git a/gas/testsuite/gas/riscv/cv-simd-extract-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-extract-h-fail.d
new file mode 100644
index 00000000000..b6f94bfb620
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extract-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-extract-h-fail.s
+#error_output: cv-simd-extract-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-extract-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-extract-h-fail.l
new file mode 100644
index 00000000000..efea5128201
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extract-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.extract.h x32,x32,1'
+.*: Error: illegal operands `cv.extract.h x33,x33,1'
+.*: Error: immediate value must be 1-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 1-bit unsigned, 2 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-extract-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-extract-h-fail.s
new file mode 100644
index 00000000000..bed9dc60b29
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extract-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.extract.h x32, x32, 1
+    cv.extract.h x33, x33, 1
+    #Boundary Immediate Values Test
+    cv.extract.h x6, x7, -1
+    cv.extract.h x6, x7, 2
diff --git a/gas/testsuite/gas/riscv/cv-simd-extract-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-extract-h-pass.d
new file mode 100644
index 00000000000..3655538f19f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extract-h-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-extract-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	ba00007b          	cv.extract.h	zero,zero,1
+   4:	ba0080fb          	cv.extract.h	ra,ra,1
+   8:	ba01017b          	cv.extract.h	sp,sp,1
+   c:	ba04047b          	cv.extract.h	s0,s0,1
+  10:	ba0a0a7b          	cv.extract.h	s4,s4,1
+  14:	ba0f8ffb          	cv.extract.h	t6,t6,1
+  18:	b803837b          	cv.extract.h	t1,t2,0
+  1c:	ba03837b          	cv.extract.h	t1,t2,1
diff --git a/gas/testsuite/gas/riscv/cv-simd-extract-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-extract-h-pass.s
new file mode 100644
index 00000000000..d2373baced4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extract-h-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.extract.h x0, x0, 1
+    cv.extract.h x1, x1, 1
+    cv.extract.h x2, x2, 1
+    cv.extract.h x8, x8, 1
+    cv.extract.h x20, x20, 1
+    cv.extract.h x31, x31, 1
+    #Immediate Values Test
+    cv.extract.h x6, x7, 0
+    cv.extract.h x6, x7, 1
diff --git a/gas/testsuite/gas/riscv/cv-simd-extractu-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-extractu-b-fail.d
new file mode 100644
index 00000000000..a591c64c8d1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extractu-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-extractu-b-fail.s
+#error_output: cv-simd-extractu-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-extractu-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-extractu-b-fail.l
new file mode 100644
index 00000000000..5015a59f857
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extractu-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.extractu.b x32,x32,2'
+.*: Error: illegal operands `cv.extractu.b x33,x33,2'
+.*: Error: immediate value must be 2-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 2-bit unsigned, 4 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-extractu-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-extractu-b-fail.s
new file mode 100644
index 00000000000..8d9a8653e76
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extractu-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.extractu.b x32, x32, 2
+    cv.extractu.b x33, x33, 2
+    #Boundary Immediate Values Test
+    cv.extractu.b x6, x7, -1
+    cv.extractu.b x6, x7, 4
diff --git a/gas/testsuite/gas/riscv/cv-simd-extractu-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-extractu-b-pass.d
new file mode 100644
index 00000000000..ac17efa88fa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extractu-b-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-extractu-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	b810307b          	cv.extractu.b	zero,zero,2
+   4:	b810b0fb          	cv.extractu.b	ra,ra,2
+   8:	b811317b          	cv.extractu.b	sp,sp,2
+   c:	b814347b          	cv.extractu.b	s0,s0,2
+  10:	b81a3a7b          	cv.extractu.b	s4,s4,2
+  14:	b81fbffb          	cv.extractu.b	t6,t6,2
+  18:	b803b37b          	cv.extractu.b	t1,t2,0
+  1c:	ba13b37b          	cv.extractu.b	t1,t2,3
diff --git a/gas/testsuite/gas/riscv/cv-simd-extractu-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-extractu-b-pass.s
new file mode 100644
index 00000000000..adcc064acfd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extractu-b-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.extractu.b x0, x0, 2
+    cv.extractu.b x1, x1, 2
+    cv.extractu.b x2, x2, 2
+    cv.extractu.b x8, x8, 2
+    cv.extractu.b x20, x20, 2
+    cv.extractu.b x31, x31, 2
+    #Immediate Values Test
+    cv.extractu.b x6, x7, 0
+    cv.extractu.b x6, x7, 3
diff --git a/gas/testsuite/gas/riscv/cv-simd-extractu-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-extractu-h-fail.d
new file mode 100644
index 00000000000..fb23af44fec
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extractu-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-extractu-h-fail.s
+#error_output: cv-simd-extractu-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-extractu-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-extractu-h-fail.l
new file mode 100644
index 00000000000..47a7cc955b9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extractu-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.extractu.h x32,x32,1'
+.*: Error: illegal operands `cv.extractu.h x33,x33,1'
+.*: Error: immediate value must be 1-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 1-bit unsigned, 2 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-extractu-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-extractu-h-fail.s
new file mode 100644
index 00000000000..69401f5df2e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extractu-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.extractu.h x32, x32, 1
+    cv.extractu.h x33, x33, 1
+    #Boundary Immediate Values Test
+    cv.extractu.h x6, x7, -1
+    cv.extractu.h x6, x7, 2
diff --git a/gas/testsuite/gas/riscv/cv-simd-extractu-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-extractu-h-pass.d
new file mode 100644
index 00000000000..748cb8ba6a1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extractu-h-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-extractu-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	ba00207b          	cv.extractu.h	zero,zero,1
+   4:	ba00a0fb          	cv.extractu.h	ra,ra,1
+   8:	ba01217b          	cv.extractu.h	sp,sp,1
+   c:	ba04247b          	cv.extractu.h	s0,s0,1
+  10:	ba0a2a7b          	cv.extractu.h	s4,s4,1
+  14:	ba0faffb          	cv.extractu.h	t6,t6,1
+  18:	b803a37b          	cv.extractu.h	t1,t2,0
+  1c:	ba03a37b          	cv.extractu.h	t1,t2,1
diff --git a/gas/testsuite/gas/riscv/cv-simd-extractu-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-extractu-h-pass.s
new file mode 100644
index 00000000000..05d631ea6f6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extractu-h-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.extractu.h x0, x0, 1
+    cv.extractu.h x1, x1, 1
+    cv.extractu.h x2, x2, 1
+    cv.extractu.h x8, x8, 1
+    cv.extractu.h x20, x20, 1
+    cv.extractu.h x31, x31, 1
+    #Immediate Values Test
+    cv.extractu.h x6, x7, 0
+    cv.extractu.h x6, x7, 1
diff --git a/gas/testsuite/gas/riscv/cv-simd-insert-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-insert-b-fail.d
new file mode 100644
index 00000000000..1b367d2a8ee
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-insert-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-insert-b-fail.s
+#error_output: cv-simd-insert-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-insert-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-insert-b-fail.l
new file mode 100644
index 00000000000..f1249a06471
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-insert-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.insert.b x32,x32,2'
+.*: Error: illegal operands `cv.insert.b x33,x33,2'
+.*: Error: immediate value must be 2-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 2-bit unsigned, 4 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-insert-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-insert-b-fail.s
new file mode 100644
index 00000000000..3df296f0e5f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-insert-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.insert.b x32, x32, 2
+    cv.insert.b x33, x33, 2
+    #Boundary Immediate Values Test
+    cv.insert.b x6, x7, -1
+    cv.insert.b x6, x7, 4
diff --git a/gas/testsuite/gas/riscv/cv-simd-insert-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-insert-b-pass.d
new file mode 100644
index 00000000000..83f7b98b1ee
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-insert-b-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-insert-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	b810507b          	cv.insert.b	zero,zero,2
+   4:	b810d0fb          	cv.insert.b	ra,ra,2
+   8:	b811517b          	cv.insert.b	sp,sp,2
+   c:	b814547b          	cv.insert.b	s0,s0,2
+  10:	b81a5a7b          	cv.insert.b	s4,s4,2
+  14:	b81fdffb          	cv.insert.b	t6,t6,2
+  18:	b803d37b          	cv.insert.b	t1,t2,0
+  1c:	ba13d37b          	cv.insert.b	t1,t2,3
diff --git a/gas/testsuite/gas/riscv/cv-simd-insert-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-insert-b-pass.s
new file mode 100644
index 00000000000..edc68280ed7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-insert-b-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.insert.b x0, x0, 2
+    cv.insert.b x1, x1, 2
+    cv.insert.b x2, x2, 2
+    cv.insert.b x8, x8, 2
+    cv.insert.b x20, x20, 2
+    cv.insert.b x31, x31, 2
+    #Immediate Values Test
+    cv.insert.b x6, x7, 0
+    cv.insert.b x6, x7, 3
diff --git a/gas/testsuite/gas/riscv/cv-simd-insert-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-insert-h-fail.d
new file mode 100644
index 00000000000..8b7a2f097cd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-insert-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-insert-h-fail.s
+#error_output: cv-simd-insert-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-insert-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-insert-h-fail.l
new file mode 100644
index 00000000000..04e261e08bf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-insert-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.insert.h x32,x32,1'
+.*: Error: illegal operands `cv.insert.h x33,x33,1'
+.*: Error: immediate value must be 1-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 1-bit unsigned, 2 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-insert-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-insert-h-fail.s
new file mode 100644
index 00000000000..bd441601f2c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-insert-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.insert.h x32, x32, 1
+    cv.insert.h x33, x33, 1
+    #Boundary Immediate Values Test
+    cv.insert.h x6, x7, -1
+    cv.insert.h x6, x7, 2
diff --git a/gas/testsuite/gas/riscv/cv-simd-insert-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-insert-h-pass.d
new file mode 100644
index 00000000000..3a13221d14a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-insert-h-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-insert-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	ba00407b          	cv.insert.h	zero,zero,1
+   4:	ba00c0fb          	cv.insert.h	ra,ra,1
+   8:	ba01417b          	cv.insert.h	sp,sp,1
+   c:	ba04447b          	cv.insert.h	s0,s0,1
+  10:	ba0a4a7b          	cv.insert.h	s4,s4,1
+  14:	ba0fcffb          	cv.insert.h	t6,t6,1
+  18:	b803c37b          	cv.insert.h	t1,t2,0
+  1c:	ba03c37b          	cv.insert.h	t1,t2,1
diff --git a/gas/testsuite/gas/riscv/cv-simd-insert-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-insert-h-pass.s
new file mode 100644
index 00000000000..6f3a035f256
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-insert-h-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.insert.h x0, x0, 1
+    cv.insert.h x1, x1, 1
+    cv.insert.h x2, x2, 1
+    cv.insert.h x8, x8, 1
+    cv.insert.h x20, x20, 1
+    cv.insert.h x31, x31, 1
+    #Immediate Values Test
+    cv.insert.h x6, x7, 0
+    cv.insert.h x6, x7, 1
diff --git a/gas/testsuite/gas/riscv/cv-simd-march-fail.d b/gas/testsuite/gas/riscv/cv-simd-march-fail.d
new file mode 100644
index 00000000000..4ae0a97b4ce
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-march-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i
+#source: cv-simd-march-fail.s
+#error_output: cv-simd-march-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-march-fail.l b/gas/testsuite/gas/riscv/cv-simd-march-fail.l
new file mode 100644
index 00000000000..dc9eef29026
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-march-fail.l
@@ -0,0 +1,221 @@
+.*: Assembler messages:
+.*: Error: unrecognized opcode `cv.add.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.add.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.add.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.add.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.add.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.add.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sub.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sub.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sub.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sub.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sub.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sub.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.avg.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.avg.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.avg.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.avg.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.avg.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.avg.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.avgu.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.avgu.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.avgu.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.avgu.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.avgu.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.avgu.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.min.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.min.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.min.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.min.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.min.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.min.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.minu.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.minu.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.minu.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.minu.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.minu.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.minu.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.max.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.max.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.max.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.max.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.max.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.max.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.maxu.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.maxu.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.maxu.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.maxu.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.maxu.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.maxu.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.srl.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.srl.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.srl.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.srl.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.srl.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.srl.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sra.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sra.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sra.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sra.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sra.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sra.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sll.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sll.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sll.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sll.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sll.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sll.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.or.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.or.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.or.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.or.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.or.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.or.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.xor.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.xor.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.xor.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.xor.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.xor.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.xor.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.and.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.and.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.and.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.and.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.and.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.and.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.abs.h x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.abs.b x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.dotup.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.dotup.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.dotup.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.dotup.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.dotup.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.dotup.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.dotusp.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.dotusp.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.dotusp.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.dotusp.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.dotusp.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.dotusp.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.dotsp.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.dotsp.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.dotsp.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.dotsp.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.dotsp.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.dotsp.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sdotup.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sdotup.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sdotup.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sdotup.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sdotup.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sdotup.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sdotusp.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sdotusp.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sdotusp.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sdotusp.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sdotusp.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sdotusp.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sdotsp.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sdotsp.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sdotsp.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sdotsp.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sdotsp.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sdotsp.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.extract.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.extract.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.extractu.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.extractu.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.insert.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.insert.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.shuffle.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.shuffle.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.shuffle.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.shufflei0.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.shufflei1.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.shufflei2.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.shufflei3.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.shuffle2.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.shuffle2.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.pack x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.pack.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.packhi.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.packlo.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpeq.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpeq.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpeq.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpeq.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpeq.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpeq.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpne.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpne.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpne.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpne.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpne.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpne.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpgt.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpgt.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpgt.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpgt.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpgt.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpgt.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpge.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpge.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpge.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpge.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpge.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpge.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmplt.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmplt.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmplt.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmplt.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmplt.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmplt.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmple.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmple.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmple.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmple.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmple.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmple.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpgtu.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpgtu.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpgtu.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpgtu.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpgtu.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpgtu.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpgeu.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpgeu.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpgeu.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpgeu.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpgeu.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpgeu.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpltu.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpltu.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpltu.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpltu.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpltu.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpltu.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpleu.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpleu.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpleu.sc.h x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpleu.sc.b x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpleu.sci.h x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cmpleu.sci.b x6,x7,20', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cplxmul.r x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cplxmul.i x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cplxmul.r.div2 x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cplxmul.i.div2 x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cplxmul.r.div4 x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cplxmul.i.div4 x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cplxmul.r.div8 x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cplxmul.i.div8 x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.cplxconj x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.subrotmj x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.subrotmj.div2 x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.subrotmj.div4 x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.subrotmj.div8 x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.add.div2 x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.add.div4 x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.add.div8 x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sub.div2 x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sub.div4 x5,x6,x7', extension `xcvsimd' required
+.*: Error: unrecognized opcode `cv.sub.div8 x5,x6,x7', extension `xcvsimd' required
diff --git a/gas/testsuite/gas/riscv/cv-simd-march-fail.s b/gas/testsuite/gas/riscv/cv-simd-march-fail.s
new file mode 100644
index 00000000000..046bbfece6f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-march-fail.s
@@ -0,0 +1,221 @@
+target:
+    cv.add.h x5, x6, x7
+    cv.add.b x5, x6, x7
+    cv.add.sc.h x5, x6, x7
+    cv.add.sc.b x5, x6, x7
+    cv.add.sci.h x6, x7, 20
+    cv.add.sci.b x6, x7, 20
+    cv.sub.h x5, x6, x7
+    cv.sub.b x5, x6, x7
+    cv.sub.sc.h x5, x6, x7
+    cv.sub.sc.b x5, x6, x7
+    cv.sub.sci.h x6, x7, 20
+    cv.sub.sci.b x6, x7, 20
+    cv.avg.h x5, x6, x7
+    cv.avg.b x5, x6, x7
+    cv.avg.sc.h x5, x6, x7
+    cv.avg.sc.b x5, x6, x7
+    cv.avg.sci.h x6, x7, 20
+    cv.avg.sci.b x6, x7, 20
+    cv.avgu.h x5, x6, x7
+    cv.avgu.b x5, x6, x7
+    cv.avgu.sc.h x5, x6, x7
+    cv.avgu.sc.b x5, x6, x7
+    cv.avgu.sci.h x6, x7, 20
+    cv.avgu.sci.b x6, x7, 20
+    cv.min.h x5, x6, x7
+    cv.min.b x5, x6, x7
+    cv.min.sc.h x5, x6, x7
+    cv.min.sc.b x5, x6, x7
+    cv.min.sci.h x6, x7, 20
+    cv.min.sci.b x6, x7, 20
+    cv.minu.h x5, x6, x7
+    cv.minu.b x5, x6, x7
+    cv.minu.sc.h x5, x6, x7
+    cv.minu.sc.b x5, x6, x7
+    cv.minu.sci.h x6, x7, 20
+    cv.minu.sci.b x6, x7, 20
+    cv.max.h x5, x6, x7
+    cv.max.b x5, x6, x7
+    cv.max.sc.h x5, x6, x7
+    cv.max.sc.b x5, x6, x7
+    cv.max.sci.h x6, x7, 20
+    cv.max.sci.b x6, x7, 20
+    cv.maxu.h x5, x6, x7
+    cv.maxu.b x5, x6, x7
+    cv.maxu.sc.h x5, x6, x7
+    cv.maxu.sc.b x5, x6, x7
+    cv.maxu.sci.h x6, x7, 20
+    cv.maxu.sci.b x6, x7, 20
+    cv.srl.h x5, x6, x7
+    cv.srl.b x5, x6, x7
+    cv.srl.sc.h x5, x6, x7
+    cv.srl.sc.b x5, x6, x7
+    cv.srl.sci.h x6, x7, 20
+    cv.srl.sci.b x6, x7, 20
+    cv.sra.h x5, x6, x7
+    cv.sra.b x5, x6, x7
+    cv.sra.sc.h x5, x6, x7
+    cv.sra.sc.b x5, x6, x7
+    cv.sra.sci.h x6, x7, 20
+    cv.sra.sci.b x6, x7, 20
+    cv.sll.h x5, x6, x7
+    cv.sll.b x5, x6, x7
+    cv.sll.sc.h x5, x6, x7
+    cv.sll.sc.b x5, x6, x7
+    cv.sll.sci.h x6, x7, 20
+    cv.sll.sci.b x6, x7, 20
+    cv.or.h x5, x6, x7
+    cv.or.b x5, x6, x7
+    cv.or.sc.h x5, x6, x7
+    cv.or.sc.b x5, x6, x7
+    cv.or.sci.h x6, x7, 20
+    cv.or.sci.b x6, x7, 20
+    cv.xor.h x5, x6, x7
+    cv.xor.b x5, x6, x7
+    cv.xor.sc.h x5, x6, x7
+    cv.xor.sc.b x5, x6, x7
+    cv.xor.sci.h x6, x7, 20
+    cv.xor.sci.b x6, x7, 20
+    cv.and.h x5, x6, x7
+    cv.and.b x5, x6, x7
+    cv.and.sc.h x5, x6, x7
+    cv.and.sc.b x5, x6, x7
+    cv.and.sci.h x6, x7, 20
+    cv.and.sci.b x6, x7, 20
+    cv.abs.h x6, x7
+    cv.abs.b x6, x7
+    cv.dotup.h x5, x6, x7
+    cv.dotup.b x5, x6, x7
+    cv.dotup.sc.h x5, x6, x7
+    cv.dotup.sc.b x5, x6, x7
+    cv.dotup.sci.h x6, x7, 20
+    cv.dotup.sci.b x6, x7, 20
+    cv.dotusp.h x5, x6, x7
+    cv.dotusp.b x5, x6, x7
+    cv.dotusp.sc.h x5, x6, x7
+    cv.dotusp.sc.b x5, x6, x7
+    cv.dotusp.sci.h x6, x7, 20
+    cv.dotusp.sci.b x6, x7, 20
+    cv.dotsp.h x5, x6, x7
+    cv.dotsp.b x5, x6, x7
+    cv.dotsp.sc.h x5, x6, x7
+    cv.dotsp.sc.b x5, x6, x7
+    cv.dotsp.sci.h x6, x7, 20
+    cv.dotsp.sci.b x6, x7, 20
+    cv.sdotup.h x5, x6, x7
+    cv.sdotup.b x5, x6, x7
+    cv.sdotup.sc.h x5, x6, x7
+    cv.sdotup.sc.b x5, x6, x7
+    cv.sdotup.sci.h x6, x7, 20
+    cv.sdotup.sci.b x6, x7, 20
+    cv.sdotusp.h x5, x6, x7
+    cv.sdotusp.b x5, x6, x7
+    cv.sdotusp.sc.h x5, x6, x7
+    cv.sdotusp.sc.b x5, x6, x7
+    cv.sdotusp.sci.h x6, x7, 20
+    cv.sdotusp.sci.b x6, x7, 20
+    cv.sdotsp.h x5, x6, x7
+    cv.sdotsp.b x5, x6, x7
+    cv.sdotsp.sc.h x5, x6, x7
+    cv.sdotsp.sc.b x5, x6, x7
+    cv.sdotsp.sci.h x6, x7, 20
+    cv.sdotsp.sci.b x6, x7, 20
+    cv.extract.h x6, x7, 20
+    cv.extract.b x6, x7, 20
+    cv.extractu.h x6, x7, 20
+    cv.extractu.b x6, x7, 20
+    cv.insert.h x6, x7, 20
+    cv.insert.b x6, x7, 20
+    cv.shuffle.h x5, x6, x7
+    cv.shuffle.b x5, x6, x7
+    cv.shuffle.sci.h x6, x7, 20
+    cv.shufflei0.sci.b x6, x7, 20
+    cv.shufflei1.sci.b x6, x7, 20
+    cv.shufflei2.sci.b x6, x7, 20
+    cv.shufflei3.sci.b x6, x7, 20
+    cv.shuffle2.h x5, x6, x7
+    cv.shuffle2.b x5, x6, x7
+    cv.pack x5, x6, x7
+    cv.pack.h x5, x6, x7
+    cv.packhi.b x5, x6, x7
+    cv.packlo.b x5, x6, x7
+    cv.cmpeq.h x5, x6, x7
+    cv.cmpeq.b x5, x6, x7
+    cv.cmpeq.sc.h x5, x6, x7
+    cv.cmpeq.sc.b x5, x6, x7
+    cv.cmpeq.sci.h x6, x7, 20
+    cv.cmpeq.sci.b x6, x7, 20
+    cv.cmpne.h x5, x6, x7
+    cv.cmpne.b x5, x6, x7
+    cv.cmpne.sc.h x5, x6, x7
+    cv.cmpne.sc.b x5, x6, x7
+    cv.cmpne.sci.h x6, x7, 20
+    cv.cmpne.sci.b x6, x7, 20
+    cv.cmpgt.h x5, x6, x7
+    cv.cmpgt.b x5, x6, x7
+    cv.cmpgt.sc.h x5, x6, x7
+    cv.cmpgt.sc.b x5, x6, x7
+    cv.cmpgt.sci.h x6, x7, 20
+    cv.cmpgt.sci.b x6, x7, 20
+    cv.cmpge.h x5, x6, x7
+    cv.cmpge.b x5, x6, x7
+    cv.cmpge.sc.h x5, x6, x7
+    cv.cmpge.sc.b x5, x6, x7
+    cv.cmpge.sci.h x6, x7, 20
+    cv.cmpge.sci.b x6, x7, 20
+    cv.cmplt.h x5, x6, x7
+    cv.cmplt.b x5, x6, x7
+    cv.cmplt.sc.h x5, x6, x7
+    cv.cmplt.sc.b x5, x6, x7
+    cv.cmplt.sci.h x6, x7, 20
+    cv.cmplt.sci.b x6, x7, 20
+    cv.cmple.h x5, x6, x7
+    cv.cmple.b x5, x6, x7
+    cv.cmple.sc.h x5, x6, x7
+    cv.cmple.sc.b x5, x6, x7
+    cv.cmple.sci.h x6, x7, 20
+    cv.cmple.sci.b x6, x7, 20
+    cv.cmpgtu.h x5, x6, x7
+    cv.cmpgtu.b x5, x6, x7
+    cv.cmpgtu.sc.h x5, x6, x7
+    cv.cmpgtu.sc.b x5, x6, x7
+    cv.cmpgtu.sci.h x6, x7, 20
+    cv.cmpgtu.sci.b x6, x7, 20
+    cv.cmpgeu.h x5, x6, x7
+    cv.cmpgeu.b x5, x6, x7
+    cv.cmpgeu.sc.h x5, x6, x7
+    cv.cmpgeu.sc.b x5, x6, x7
+    cv.cmpgeu.sci.h x6, x7, 20
+    cv.cmpgeu.sci.b x6, x7, 20
+    cv.cmpltu.h x5, x6, x7
+    cv.cmpltu.b x5, x6, x7
+    cv.cmpltu.sc.h x5, x6, x7
+    cv.cmpltu.sc.b x5, x6, x7
+    cv.cmpltu.sci.h x6, x7, 20
+    cv.cmpltu.sci.b x6, x7, 20
+    cv.cmpleu.h x5, x6, x7
+    cv.cmpleu.b x5, x6, x7
+    cv.cmpleu.sc.h x5, x6, x7
+    cv.cmpleu.sc.b x5, x6, x7
+    cv.cmpleu.sci.h x6, x7, 20
+    cv.cmpleu.sci.b x6, x7, 20
+    cv.cplxmul.r x5, x6, x7
+    cv.cplxmul.i x5, x6, x7
+    cv.cplxmul.r.div2 x5, x6, x7
+    cv.cplxmul.i.div2 x5, x6, x7
+    cv.cplxmul.r.div4 x5, x6, x7
+    cv.cplxmul.i.div4 x5, x6, x7
+    cv.cplxmul.r.div8 x5, x6, x7
+    cv.cplxmul.i.div8 x5, x6, x7
+    cv.cplxconj x6, x7
+    cv.subrotmj x5, x6, x7
+    cv.subrotmj.div2 x5, x6, x7
+    cv.subrotmj.div4 x5, x6, x7
+    cv.subrotmj.div8 x5, x6, x7
+    cv.add.div2 x5, x6, x7
+    cv.add.div4 x5, x6, x7
+    cv.add.div8 x5, x6, x7
+    cv.sub.div2 x5, x6, x7
+    cv.sub.div4 x5, x6, x7
+    cv.sub.div8 x5, x6, x7
diff --git a/gas/testsuite/gas/riscv/cv-simd-march-xcvsimd.d b/gas/testsuite/gas/riscv/cv-simd-march-xcvsimd.d
new file mode 100644
index 00000000000..f93175e780b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-march-xcvsimd.d
@@ -0,0 +1,230 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-march-xcvsimd.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[  ]+0:[ 	]+007302fb[ 	]+cv.add.h	t0,t1,t2
+[  ]+4:[ 	]+007312fb[ 	]+cv.add.b	t0,t1,t2
+[  ]+8:[ 	]+007342fb[ 	]+cv.add.sc.h	t0,t1,t2
+[  ]+c:[ 	]+007352fb[ 	]+cv.add.sc.b	t0,t1,t2
+[  ]+10:[ 	]+00a3e37b[ 	]+cv.add.sci.h	t1,t2,20
+[  ]+14:[ 	]+00a3f37b[ 	]+cv.add.sci.b	t1,t2,20
+[  ]+18:[ 	]+087302fb[ 	]+cv.sub.h	t0,t1,t2
+[  ]+1c:[ 	]+087312fb[ 	]+cv.sub.b	t0,t1,t2
+[  ]+20:[ 	]+087342fb[ 	]+cv.sub.sc.h	t0,t1,t2
+[  ]+24:[ 	]+087352fb[ 	]+cv.sub.sc.b	t0,t1,t2
+[  ]+28:[ 	]+08a3e37b[ 	]+cv.sub.sci.h	t1,t2,20
+[  ]+2c:[ 	]+08a3f37b[ 	]+cv.sub.sci.b	t1,t2,20
+[  ]+30:[ 	]+107302fb[ 	]+cv.avg.h	t0,t1,t2
+[  ]+34:[ 	]+107312fb[ 	]+cv.avg.b	t0,t1,t2
+[  ]+38:[ 	]+107342fb[ 	]+cv.avg.sc.h	t0,t1,t2
+[  ]+3c:[ 	]+107352fb[ 	]+cv.avg.sc.b	t0,t1,t2
+[  ]+40:[ 	]+10a3e37b[ 	]+cv.avg.sci.h	t1,t2,20
+[  ]+44:[ 	]+10a3f37b[ 	]+cv.avg.sci.b	t1,t2,20
+[  ]+48:[ 	]+187302fb[ 	]+cv.avgu.h	t0,t1,t2
+[  ]+4c:[ 	]+187312fb[ 	]+cv.avgu.b	t0,t1,t2
+[  ]+50:[ 	]+187342fb[ 	]+cv.avgu.sc.h	t0,t1,t2
+[  ]+54:[ 	]+187352fb[ 	]+cv.avgu.sc.b	t0,t1,t2
+[  ]+58:[ 	]+18a3e37b[ 	]+cv.avgu.sci.h	t1,t2,20
+[  ]+5c:[ 	]+18a3f37b[ 	]+cv.avgu.sci.b	t1,t2,20
+[  ]+60:[ 	]+207302fb[ 	]+cv.min.h	t0,t1,t2
+[  ]+64:[ 	]+207312fb[ 	]+cv.min.b	t0,t1,t2
+[  ]+68:[ 	]+207342fb[ 	]+cv.min.sc.h	t0,t1,t2
+[  ]+6c:[ 	]+207352fb[ 	]+cv.min.sc.b	t0,t1,t2
+[  ]+70:[ 	]+20a3e37b[ 	]+cv.min.sci.h	t1,t2,20
+[  ]+74:[ 	]+20a3f37b[ 	]+cv.min.sci.b	t1,t2,20
+[  ]+78:[ 	]+287302fb[ 	]+cv.minu.h	t0,t1,t2
+[  ]+7c:[ 	]+287312fb[ 	]+cv.minu.b	t0,t1,t2
+[  ]+80:[ 	]+287342fb[ 	]+cv.minu.sc.h	t0,t1,t2
+[  ]+84:[ 	]+287352fb[ 	]+cv.minu.sc.b	t0,t1,t2
+[  ]+88:[ 	]+28a3e37b[ 	]+cv.minu.sci.h	t1,t2,20
+[  ]+8c:[ 	]+28a3f37b[ 	]+cv.minu.sci.b	t1,t2,20
+[  ]+90:[ 	]+307302fb[ 	]+cv.max.h	t0,t1,t2
+[  ]+94:[ 	]+307312fb[ 	]+cv.max.b	t0,t1,t2
+[  ]+98:[ 	]+307342fb[ 	]+cv.max.sc.h	t0,t1,t2
+[  ]+9c:[ 	]+307352fb[ 	]+cv.max.sc.b	t0,t1,t2
+[  ]+a0:[ 	]+30a3e37b[ 	]+cv.max.sci.h	t1,t2,20
+[  ]+a4:[ 	]+30a3f37b[ 	]+cv.max.sci.b	t1,t2,20
+[  ]+a8:[ 	]+387302fb[ 	]+cv.maxu.h	t0,t1,t2
+[  ]+ac:[ 	]+387312fb[ 	]+cv.maxu.b	t0,t1,t2
+[  ]+b0:[ 	]+387342fb[ 	]+cv.maxu.sc.h	t0,t1,t2
+[  ]+b4:[ 	]+387352fb[ 	]+cv.maxu.sc.b	t0,t1,t2
+[  ]+b8:[ 	]+38a3e37b[ 	]+cv.maxu.sci.h	t1,t2,20
+[  ]+bc:[ 	]+38a3f37b[ 	]+cv.maxu.sci.b	t1,t2,20
+[  ]+c0:[ 	]+407302fb[ 	]+cv.srl.h	t0,t1,t2
+[  ]+c4:[ 	]+407312fb[ 	]+cv.srl.b	t0,t1,t2
+[  ]+c8:[ 	]+407342fb[ 	]+cv.srl.sc.h	t0,t1,t2
+[  ]+cc:[ 	]+407352fb[ 	]+cv.srl.sc.b	t0,t1,t2
+[  ]+d0:[ 	]+4063e37b[ 	]+cv.srl.sci.h	t1,t2,12
+[  ]+d4:[ 	]+4023f37b[ 	]+cv.srl.sci.b	t1,t2,4
+[  ]+d8:[ 	]+487302fb[ 	]+cv.sra.h	t0,t1,t2
+[  ]+dc:[ 	]+487312fb[ 	]+cv.sra.b	t0,t1,t2
+[  ]+e0:[ 	]+487342fb[ 	]+cv.sra.sc.h	t0,t1,t2
+[  ]+e4:[ 	]+487352fb[ 	]+cv.sra.sc.b	t0,t1,t2
+[  ]+e8:[ 	]+4863e37b[ 	]+cv.sra.sci.h	t1,t2,12
+[  ]+ec:[ 	]+4823f37b[ 	]+cv.sra.sci.b	t1,t2,4
+[  ]+f0:[ 	]+507302fb[ 	]+cv.sll.h	t0,t1,t2
+[  ]+f4:[ 	]+507312fb[ 	]+cv.sll.b	t0,t1,t2
+[  ]+f8:[ 	]+507342fb[ 	]+cv.sll.sc.h	t0,t1,t2
+[  ]+fc:[ 	]+507352fb[ 	]+cv.sll.sc.b	t0,t1,t2
+[  ]+100:[ 	]+5063e37b[ 	]+cv.sll.sci.h	t1,t2,12
+[  ]+104:[ 	]+5023f37b[ 	]+cv.sll.sci.b	t1,t2,4
+[  ]+108:[ 	]+587302fb[ 	]+cv.or.h	t0,t1,t2
+[  ]+10c:[ 	]+587312fb[ 	]+cv.or.b	t0,t1,t2
+[  ]+110:[ 	]+587342fb[ 	]+cv.or.sc.h	t0,t1,t2
+[  ]+114:[ 	]+587352fb[ 	]+cv.or.sc.b	t0,t1,t2
+[  ]+118:[ 	]+58a3e37b[ 	]+cv.or.sci.h	t1,t2,20
+[  ]+11c:[ 	]+58a3f37b[ 	]+cv.or.sci.b	t1,t2,20
+[  ]+120:[ 	]+607302fb[ 	]+cv.xor.h	t0,t1,t2
+[  ]+124:[ 	]+607312fb[ 	]+cv.xor.b	t0,t1,t2
+[  ]+128:[ 	]+607342fb[ 	]+cv.xor.sc.h	t0,t1,t2
+[  ]+12c:[ 	]+607352fb[ 	]+cv.xor.sc.b	t0,t1,t2
+[  ]+130:[ 	]+60a3e37b[ 	]+cv.xor.sci.h	t1,t2,20
+[  ]+134:[ 	]+60a3f37b[ 	]+cv.xor.sci.b	t1,t2,20
+[  ]+138:[ 	]+687302fb[ 	]+cv.and.h	t0,t1,t2
+[  ]+13c:[ 	]+687312fb[ 	]+cv.and.b	t0,t1,t2
+[  ]+140:[ 	]+687342fb[ 	]+cv.and.sc.h	t0,t1,t2
+[  ]+144:[ 	]+687352fb[ 	]+cv.and.sc.b	t0,t1,t2
+[  ]+148:[ 	]+68a3e37b[ 	]+cv.and.sci.h	t1,t2,20
+[  ]+14c:[ 	]+68a3f37b[ 	]+cv.and.sci.b	t1,t2,20
+[  ]+150:[ 	]+7003837b[ 	]+cv.abs.h	t1,t2
+[  ]+154:[ 	]+7003937b[ 	]+cv.abs.b	t1,t2
+[  ]+158:[ 	]+807302fb[ 	]+cv.dotup.h	t0,t1,t2
+[  ]+15c:[ 	]+807312fb[ 	]+cv.dotup.b	t0,t1,t2
+[  ]+160:[ 	]+807342fb[ 	]+cv.dotup.sc.h	t0,t1,t2
+[  ]+164:[ 	]+807352fb[ 	]+cv.dotup.sc.b	t0,t1,t2
+[  ]+168:[ 	]+80a3e37b[ 	]+cv.dotup.sci.h	t1,t2,20
+[  ]+16c:[ 	]+80a3f37b[ 	]+cv.dotup.sci.b	t1,t2,20
+[  ]+170:[ 	]+887302fb[ 	]+cv.dotusp.h	t0,t1,t2
+[  ]+174:[ 	]+887312fb[ 	]+cv.dotusp.b	t0,t1,t2
+[  ]+178:[ 	]+887342fb[ 	]+cv.dotusp.sc.h	t0,t1,t2
+[  ]+17c:[ 	]+887352fb[ 	]+cv.dotusp.sc.b	t0,t1,t2
+[  ]+180:[ 	]+88a3e37b[ 	]+cv.dotusp.sci.h	t1,t2,20
+[  ]+184:[ 	]+88a3f37b[ 	]+cv.dotusp.sci.b	t1,t2,20
+[  ]+188:[ 	]+907302fb[ 	]+cv.dotsp.h	t0,t1,t2
+[  ]+18c:[ 	]+907312fb[ 	]+cv.dotsp.b	t0,t1,t2
+[  ]+190:[ 	]+907342fb[ 	]+cv.dotsp.sc.h	t0,t1,t2
+[  ]+194:[ 	]+907352fb[ 	]+cv.dotsp.sc.b	t0,t1,t2
+[  ]+198:[ 	]+90a3e37b[ 	]+cv.dotsp.sci.h	t1,t2,20
+[  ]+19c:[ 	]+90a3f37b[ 	]+cv.dotsp.sci.b	t1,t2,20
+[  ]+1a0:[ 	]+987302fb[ 	]+cv.sdotup.h	t0,t1,t2
+[  ]+1a4:[ 	]+987312fb[ 	]+cv.sdotup.b	t0,t1,t2
+[  ]+1a8:[ 	]+987342fb[ 	]+cv.sdotup.sc.h	t0,t1,t2
+[  ]+1ac:[ 	]+987352fb[ 	]+cv.sdotup.sc.b	t0,t1,t2
+[  ]+1b0:[ 	]+98a3e37b[ 	]+cv.sdotup.sci.h	t1,t2,20
+[  ]+1b4:[ 	]+98a3f37b[ 	]+cv.sdotup.sci.b	t1,t2,20
+[  ]+1b8:[ 	]+a07302fb[ 	]+cv.sdotusp.h	t0,t1,t2
+[  ]+1bc:[ 	]+a07312fb[ 	]+cv.sdotusp.b	t0,t1,t2
+[  ]+1c0:[ 	]+a07342fb[ 	]+cv.sdotusp.sc.h	t0,t1,t2
+[  ]+1c4:[ 	]+a07352fb[ 	]+cv.sdotusp.sc.b	t0,t1,t2
+[  ]+1c8:[ 	]+a0a3e37b[ 	]+cv.sdotusp.sci.h	t1,t2,20
+[  ]+1cc:[ 	]+a0a3f37b[ 	]+cv.sdotusp.sci.b	t1,t2,20
+[  ]+1d0:[ 	]+a87302fb[ 	]+cv.sdotsp.h	t0,t1,t2
+[  ]+1d4:[ 	]+a87312fb[ 	]+cv.sdotsp.b	t0,t1,t2
+[  ]+1d8:[ 	]+a87342fb[ 	]+cv.sdotsp.sc.h	t0,t1,t2
+[  ]+1dc:[ 	]+a87352fb[ 	]+cv.sdotsp.sc.b	t0,t1,t2
+[  ]+1e0:[ 	]+a8a3e37b[ 	]+cv.sdotsp.sci.h	t1,t2,20
+[  ]+1e4:[ 	]+a8a3f37b[ 	]+cv.sdotsp.sci.b	t1,t2,20
+[  ]+1e8:[ 	]+ba03837b[ 	]+cv.extract.h	t1,t2,1
+[  ]+1ec:[ 	]+b813937b[ 	]+cv.extract.b	t1,t2,2
+[  ]+1f0:[ 	]+ba03a37b[ 	]+cv.extractu.h	t1,t2,1
+[  ]+1f4:[ 	]+b813b37b[ 	]+cv.extractu.b	t1,t2,2
+[  ]+1f8:[ 	]+ba03c37b[ 	]+cv.insert.h	t1,t2,1
+[  ]+1fc:[ 	]+b813d37b[ 	]+cv.insert.b	t1,t2,2
+[  ]+200:[ 	]+c07302fb[ 	]+cv.shuffle.h	t0,t1,t2
+[  ]+204:[ 	]+c07312fb[ 	]+cv.shuffle.b	t0,t1,t2
+[  ]+208:[ 	]+c0a3e37b[ 	]+cv.shuffle.sci.h	t1,t2,20
+[  ]+20c:[ 	]+c0a3f37b[ 	]+cv.shufflei0.sci.b	t1,t2,20
+[  ]+210:[ 	]+c8a3f37b[ 	]+cv.shufflei1.sci.b	t1,t2,20
+[  ]+214:[ 	]+d0a3f37b[ 	]+cv.shufflei2.sci.b	t1,t2,20
+[  ]+218:[ 	]+d8a3f37b[ 	]+cv.shufflei3.sci.b	t1,t2,20
+[  ]+21c:[ 	]+e07302fb[ 	]+cv.shuffle2.h	t0,t1,t2
+[  ]+220:[ 	]+e07312fb[ 	]+cv.shuffle2.b	t0,t1,t2
+[  ]+224:[ 	]+f07302fb[ 	]+cv.pack	t0,t1,t2
+[  ]+228:[ 	]+f27302fb[ 	]+cv.pack.h	t0,t1,t2
+[  ]+22c:[ 	]+fa7312fb[ 	]+cv.packhi.b	t0,t1,t2
+[  ]+230:[ 	]+f87312fb[ 	]+cv.packlo.b	t0,t1,t2
+[  ]+234:[ 	]+047302fb[ 	]+cv.cmpeq.h	t0,t1,t2
+[  ]+238:[ 	]+047312fb[ 	]+cv.cmpeq.b	t0,t1,t2
+[  ]+23c:[ 	]+047342fb[ 	]+cv.cmpeq.sc.h	t0,t1,t2
+[  ]+240:[ 	]+047352fb[ 	]+cv.cmpeq.sc.b	t0,t1,t2
+[  ]+244:[ 	]+04a3e37b[ 	]+cv.cmpeq.sci.h	t1,t2,20
+[  ]+248:[ 	]+04a3f37b[ 	]+cv.cmpeq.sci.b	t1,t2,20
+[  ]+24c:[ 	]+0c7302fb[ 	]+cv.cmpne.h	t0,t1,t2
+[  ]+250:[ 	]+0c7312fb[ 	]+cv.cmpne.b	t0,t1,t2
+[  ]+254:[ 	]+0c7342fb[ 	]+cv.cmpne.sc.h	t0,t1,t2
+[  ]+258:[ 	]+0c7352fb[ 	]+cv.cmpne.sc.b	t0,t1,t2
+[  ]+25c:[ 	]+0ca3e37b[ 	]+cv.cmpne.sci.h	t1,t2,20
+[  ]+260:[ 	]+0ca3f37b[ 	]+cv.cmpne.sci.b	t1,t2,20
+[  ]+264:[ 	]+147302fb[ 	]+cv.cmpgt.h	t0,t1,t2
+[  ]+268:[ 	]+147312fb[ 	]+cv.cmpgt.b	t0,t1,t2
+[  ]+26c:[ 	]+147342fb[ 	]+cv.cmpgt.sc.h	t0,t1,t2
+[  ]+270:[ 	]+147352fb[ 	]+cv.cmpgt.sc.b	t0,t1,t2
+[  ]+274:[ 	]+14a3e37b[ 	]+cv.cmpgt.sci.h	t1,t2,20
+[  ]+278:[ 	]+14a3f37b[ 	]+cv.cmpgt.sci.b	t1,t2,20
+[  ]+27c:[ 	]+1c7302fb[ 	]+cv.cmpge.h	t0,t1,t2
+[  ]+280:[ 	]+1c7312fb[ 	]+cv.cmpge.b	t0,t1,t2
+[  ]+284:[ 	]+1c7342fb[ 	]+cv.cmpge.sc.h	t0,t1,t2
+[  ]+288:[ 	]+1c7352fb[ 	]+cv.cmpge.sc.b	t0,t1,t2
+[  ]+28c:[ 	]+1ca3e37b[ 	]+cv.cmpge.sci.h	t1,t2,20
+[  ]+290:[ 	]+1ca3f37b[ 	]+cv.cmpge.sci.b	t1,t2,20
+[  ]+294:[ 	]+247302fb[ 	]+cv.cmplt.h	t0,t1,t2
+[  ]+298:[ 	]+247312fb[ 	]+cv.cmplt.b	t0,t1,t2
+[  ]+29c:[ 	]+247342fb[ 	]+cv.cmplt.sc.h	t0,t1,t2
+[  ]+2a0:[ 	]+247352fb[ 	]+cv.cmplt.sc.b	t0,t1,t2
+[  ]+2a4:[ 	]+24a3e37b[ 	]+cv.cmplt.sci.h	t1,t2,20
+[  ]+2a8:[ 	]+24a3f37b[ 	]+cv.cmplt.sci.b	t1,t2,20
+[  ]+2ac:[ 	]+2c7302fb[ 	]+cv.cmple.h	t0,t1,t2
+[  ]+2b0:[ 	]+2c7312fb[ 	]+cv.cmple.b	t0,t1,t2
+[  ]+2b4:[ 	]+2c7342fb[ 	]+cv.cmple.sc.h	t0,t1,t2
+[  ]+2b8:[ 	]+2c7352fb[ 	]+cv.cmple.sc.b	t0,t1,t2
+[  ]+2bc:[ 	]+2ca3e37b[ 	]+cv.cmple.sci.h	t1,t2,20
+[  ]+2c0:[ 	]+2ca3f37b[ 	]+cv.cmple.sci.b	t1,t2,20
+[  ]+2c4:[ 	]+347302fb[ 	]+cv.cmpgtu.h	t0,t1,t2
+[  ]+2c8:[ 	]+347312fb[ 	]+cv.cmpgtu.b	t0,t1,t2
+[  ]+2cc:[ 	]+347342fb[ 	]+cv.cmpgtu.sc.h	t0,t1,t2
+[  ]+2d0:[ 	]+347352fb[ 	]+cv.cmpgtu.sc.b	t0,t1,t2
+[  ]+2d4:[ 	]+34a3e37b[ 	]+cv.cmpgtu.sci.h	t1,t2,20
+[  ]+2d8:[ 	]+34a3f37b[ 	]+cv.cmpgtu.sci.b	t1,t2,20
+[  ]+2dc:[ 	]+3c7302fb[ 	]+cv.cmpgeu.h	t0,t1,t2
+[  ]+2e0:[ 	]+3c7312fb[ 	]+cv.cmpgeu.b	t0,t1,t2
+[  ]+2e4:[ 	]+3c7342fb[ 	]+cv.cmpgeu.sc.h	t0,t1,t2
+[  ]+2e8:[ 	]+3c7352fb[ 	]+cv.cmpgeu.sc.b	t0,t1,t2
+[  ]+2ec:[ 	]+3ca3e37b[ 	]+cv.cmpgeu.sci.h	t1,t2,20
+[  ]+2f0:[ 	]+3ca3f37b[ 	]+cv.cmpgeu.sci.b	t1,t2,20
+[  ]+2f4:[ 	]+447302fb[ 	]+cv.cmpltu.h	t0,t1,t2
+[  ]+2f8:[ 	]+447312fb[ 	]+cv.cmpltu.b	t0,t1,t2
+[  ]+2fc:[ 	]+447342fb[ 	]+cv.cmpltu.sc.h	t0,t1,t2
+[  ]+300:[ 	]+447352fb[ 	]+cv.cmpltu.sc.b	t0,t1,t2
+[  ]+304:[ 	]+44a3e37b[ 	]+cv.cmpltu.sci.h	t1,t2,20
+[  ]+308:[ 	]+44a3f37b[ 	]+cv.cmpltu.sci.b	t1,t2,20
+[  ]+30c:[ 	]+4c7302fb[ 	]+cv.cmpleu.h	t0,t1,t2
+[  ]+310:[ 	]+4c7312fb[ 	]+cv.cmpleu.b	t0,t1,t2
+[  ]+314:[ 	]+4c7342fb[ 	]+cv.cmpleu.sc.h	t0,t1,t2
+[  ]+318:[ 	]+4c7352fb[ 	]+cv.cmpleu.sc.b	t0,t1,t2
+[  ]+31c:[ 	]+4ca3e37b[ 	]+cv.cmpleu.sci.h	t1,t2,20
+[  ]+320:[ 	]+4ca3f37b[ 	]+cv.cmpleu.sci.b	t1,t2,20
+[  ]+324:[ 	]+547302fb[ 	]+cv.cplxmul.r	t0,t1,t2
+[  ]+328:[ 	]+567302fb[ 	]+cv.cplxmul.i	t0,t1,t2
+[  ]+32c:[ 	]+547322fb[ 	]+cv.cplxmul.r.div2	t0,t1,t2
+[  ]+330:[ 	]+567322fb[ 	]+cv.cplxmul.i.div2	t0,t1,t2
+[  ]+334:[ 	]+547342fb[ 	]+cv.cplxmul.r.div4	t0,t1,t2
+[  ]+338:[ 	]+567342fb[ 	]+cv.cplxmul.i.div4	t0,t1,t2
+[  ]+33c:[ 	]+547362fb[ 	]+cv.cplxmul.r.div8	t0,t1,t2
+[  ]+340:[ 	]+567362fb[ 	]+cv.cplxmul.i.div8	t0,t1,t2
+[  ]+344:[ 	]+5c03837b[ 	]+cv.cplxconj	t1,t2
+[  ]+348:[ 	]+647302fb[ 	]+cv.subrotmj	t0,t1,t2
+[  ]+34c:[ 	]+647322fb[ 	]+cv.subrotmj.div2	t0,t1,t2
+[  ]+350:[ 	]+647342fb[ 	]+cv.subrotmj.div4	t0,t1,t2
+[  ]+354:[ 	]+647362fb[ 	]+cv.subrotmj.div8	t0,t1,t2
+[  ]+358:[ 	]+6c7322fb[ 	]+cv.add.div2	t0,t1,t2
+[  ]+35c:[ 	]+6c7342fb[ 	]+cv.add.div4	t0,t1,t2
+[  ]+360:[ 	]+6c7362fb[ 	]+cv.add.div8	t0,t1,t2
+[  ]+364:[ 	]+747322fb[ 	]+cv.sub.div2	t0,t1,t2
+[  ]+368:[ 	]+747342fb[ 	]+cv.sub.div4	t0,t1,t2
+[  ]+36c:[ 	]+747362fb[ 	]+cv.sub.div8	t0,t1,t2
diff --git a/gas/testsuite/gas/riscv/cv-simd-march-xcvsimd.s b/gas/testsuite/gas/riscv/cv-simd-march-xcvsimd.s
new file mode 100644
index 00000000000..e53b0e4419d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-march-xcvsimd.s
@@ -0,0 +1,221 @@
+target:
+    cv.add.h x5, x6, x7
+    cv.add.b x5, x6, x7
+    cv.add.sc.h x5, x6, x7
+    cv.add.sc.b x5, x6, x7
+    cv.add.sci.h x6, x7, 20
+    cv.add.sci.b x6, x7, 20
+    cv.sub.h x5, x6, x7
+    cv.sub.b x5, x6, x7
+    cv.sub.sc.h x5, x6, x7
+    cv.sub.sc.b x5, x6, x7
+    cv.sub.sci.h x6, x7, 20
+    cv.sub.sci.b x6, x7, 20
+    cv.avg.h x5, x6, x7
+    cv.avg.b x5, x6, x7
+    cv.avg.sc.h x5, x6, x7
+    cv.avg.sc.b x5, x6, x7
+    cv.avg.sci.h x6, x7, 20
+    cv.avg.sci.b x6, x7, 20
+    cv.avgu.h x5, x6, x7
+    cv.avgu.b x5, x6, x7
+    cv.avgu.sc.h x5, x6, x7
+    cv.avgu.sc.b x5, x6, x7
+    cv.avgu.sci.h x6, x7, 20
+    cv.avgu.sci.b x6, x7, 20
+    cv.min.h x5, x6, x7
+    cv.min.b x5, x6, x7
+    cv.min.sc.h x5, x6, x7
+    cv.min.sc.b x5, x6, x7
+    cv.min.sci.h x6, x7, 20
+    cv.min.sci.b x6, x7, 20
+    cv.minu.h x5, x6, x7
+    cv.minu.b x5, x6, x7
+    cv.minu.sc.h x5, x6, x7
+    cv.minu.sc.b x5, x6, x7
+    cv.minu.sci.h x6, x7, 20
+    cv.minu.sci.b x6, x7, 20
+    cv.max.h x5, x6, x7
+    cv.max.b x5, x6, x7
+    cv.max.sc.h x5, x6, x7
+    cv.max.sc.b x5, x6, x7
+    cv.max.sci.h x6, x7, 20
+    cv.max.sci.b x6, x7, 20
+    cv.maxu.h x5, x6, x7
+    cv.maxu.b x5, x6, x7
+    cv.maxu.sc.h x5, x6, x7
+    cv.maxu.sc.b x5, x6, x7
+    cv.maxu.sci.h x6, x7, 20
+    cv.maxu.sci.b x6, x7, 20
+    cv.srl.h x5, x6, x7
+    cv.srl.b x5, x6, x7
+    cv.srl.sc.h x5, x6, x7
+    cv.srl.sc.b x5, x6, x7
+    cv.srl.sci.h x6, x7, 12
+    cv.srl.sci.b x6, x7, 4
+    cv.sra.h x5, x6, x7
+    cv.sra.b x5, x6, x7
+    cv.sra.sc.h x5, x6, x7
+    cv.sra.sc.b x5, x6, x7
+    cv.sra.sci.h x6, x7, 12
+    cv.sra.sci.b x6, x7, 4
+    cv.sll.h x5, x6, x7
+    cv.sll.b x5, x6, x7
+    cv.sll.sc.h x5, x6, x7
+    cv.sll.sc.b x5, x6, x7
+    cv.sll.sci.h x6, x7, 12
+    cv.sll.sci.b x6, x7, 4
+    cv.or.h x5, x6, x7
+    cv.or.b x5, x6, x7
+    cv.or.sc.h x5, x6, x7
+    cv.or.sc.b x5, x6, x7
+    cv.or.sci.h x6, x7, 20
+    cv.or.sci.b x6, x7, 20
+    cv.xor.h x5, x6, x7
+    cv.xor.b x5, x6, x7
+    cv.xor.sc.h x5, x6, x7
+    cv.xor.sc.b x5, x6, x7
+    cv.xor.sci.h x6, x7, 20
+    cv.xor.sci.b x6, x7, 20
+    cv.and.h x5, x6, x7
+    cv.and.b x5, x6, x7
+    cv.and.sc.h x5, x6, x7
+    cv.and.sc.b x5, x6, x7
+    cv.and.sci.h x6, x7, 20
+    cv.and.sci.b x6, x7, 20
+    cv.abs.h x6, x7
+    cv.abs.b x6, x7
+    cv.dotup.h x5, x6, x7
+    cv.dotup.b x5, x6, x7
+    cv.dotup.sc.h x5, x6, x7
+    cv.dotup.sc.b x5, x6, x7
+    cv.dotup.sci.h x6, x7, 20
+    cv.dotup.sci.b x6, x7, 20
+    cv.dotusp.h x5, x6, x7
+    cv.dotusp.b x5, x6, x7
+    cv.dotusp.sc.h x5, x6, x7
+    cv.dotusp.sc.b x5, x6, x7
+    cv.dotusp.sci.h x6, x7, 20
+    cv.dotusp.sci.b x6, x7, 20
+    cv.dotsp.h x5, x6, x7
+    cv.dotsp.b x5, x6, x7
+    cv.dotsp.sc.h x5, x6, x7
+    cv.dotsp.sc.b x5, x6, x7
+    cv.dotsp.sci.h x6, x7, 20
+    cv.dotsp.sci.b x6, x7, 20
+    cv.sdotup.h x5, x6, x7
+    cv.sdotup.b x5, x6, x7
+    cv.sdotup.sc.h x5, x6, x7
+    cv.sdotup.sc.b x5, x6, x7
+    cv.sdotup.sci.h x6, x7, 20
+    cv.sdotup.sci.b x6, x7, 20
+    cv.sdotusp.h x5, x6, x7
+    cv.sdotusp.b x5, x6, x7
+    cv.sdotusp.sc.h x5, x6, x7
+    cv.sdotusp.sc.b x5, x6, x7
+    cv.sdotusp.sci.h x6, x7, 20
+    cv.sdotusp.sci.b x6, x7, 20
+    cv.sdotsp.h x5, x6, x7
+    cv.sdotsp.b x5, x6, x7
+    cv.sdotsp.sc.h x5, x6, x7
+    cv.sdotsp.sc.b x5, x6, x7
+    cv.sdotsp.sci.h x6, x7, 20
+    cv.sdotsp.sci.b x6, x7, 20
+    cv.extract.h x6, x7, 1
+    cv.extract.b x6, x7, 2
+    cv.extractu.h x6, x7, 1
+    cv.extractu.b x6, x7, 2
+    cv.insert.h x6, x7, 1
+    cv.insert.b x6, x7, 2
+    cv.shuffle.h x5, x6, x7
+    cv.shuffle.b x5, x6, x7
+    cv.shuffle.sci.h x6, x7, 20
+    cv.shufflei0.sci.b x6, x7, 20
+    cv.shufflei1.sci.b x6, x7, 20
+    cv.shufflei2.sci.b x6, x7, 20
+    cv.shufflei3.sci.b x6, x7, 20
+    cv.shuffle2.h x5, x6, x7
+    cv.shuffle2.b x5, x6, x7
+    cv.pack x5, x6, x7
+    cv.pack.h x5, x6, x7
+    cv.packhi.b x5, x6, x7
+    cv.packlo.b x5, x6, x7
+    cv.cmpeq.h x5, x6, x7
+    cv.cmpeq.b x5, x6, x7
+    cv.cmpeq.sc.h x5, x6, x7
+    cv.cmpeq.sc.b x5, x6, x7
+    cv.cmpeq.sci.h x6, x7, 20
+    cv.cmpeq.sci.b x6, x7, 20
+    cv.cmpne.h x5, x6, x7
+    cv.cmpne.b x5, x6, x7
+    cv.cmpne.sc.h x5, x6, x7
+    cv.cmpne.sc.b x5, x6, x7
+    cv.cmpne.sci.h x6, x7, 20
+    cv.cmpne.sci.b x6, x7, 20
+    cv.cmpgt.h x5, x6, x7
+    cv.cmpgt.b x5, x6, x7
+    cv.cmpgt.sc.h x5, x6, x7
+    cv.cmpgt.sc.b x5, x6, x7
+    cv.cmpgt.sci.h x6, x7, 20
+    cv.cmpgt.sci.b x6, x7, 20
+    cv.cmpge.h x5, x6, x7
+    cv.cmpge.b x5, x6, x7
+    cv.cmpge.sc.h x5, x6, x7
+    cv.cmpge.sc.b x5, x6, x7
+    cv.cmpge.sci.h x6, x7, 20
+    cv.cmpge.sci.b x6, x7, 20
+    cv.cmplt.h x5, x6, x7
+    cv.cmplt.b x5, x6, x7
+    cv.cmplt.sc.h x5, x6, x7
+    cv.cmplt.sc.b x5, x6, x7
+    cv.cmplt.sci.h x6, x7, 20
+    cv.cmplt.sci.b x6, x7, 20
+    cv.cmple.h x5, x6, x7
+    cv.cmple.b x5, x6, x7
+    cv.cmple.sc.h x5, x6, x7
+    cv.cmple.sc.b x5, x6, x7
+    cv.cmple.sci.h x6, x7, 20
+    cv.cmple.sci.b x6, x7, 20
+    cv.cmpgtu.h x5, x6, x7
+    cv.cmpgtu.b x5, x6, x7
+    cv.cmpgtu.sc.h x5, x6, x7
+    cv.cmpgtu.sc.b x5, x6, x7
+    cv.cmpgtu.sci.h x6, x7, 20
+    cv.cmpgtu.sci.b x6, x7, 20
+    cv.cmpgeu.h x5, x6, x7
+    cv.cmpgeu.b x5, x6, x7
+    cv.cmpgeu.sc.h x5, x6, x7
+    cv.cmpgeu.sc.b x5, x6, x7
+    cv.cmpgeu.sci.h x6, x7, 20
+    cv.cmpgeu.sci.b x6, x7, 20
+    cv.cmpltu.h x5, x6, x7
+    cv.cmpltu.b x5, x6, x7
+    cv.cmpltu.sc.h x5, x6, x7
+    cv.cmpltu.sc.b x5, x6, x7
+    cv.cmpltu.sci.h x6, x7, 20
+    cv.cmpltu.sci.b x6, x7, 20
+    cv.cmpleu.h x5, x6, x7
+    cv.cmpleu.b x5, x6, x7
+    cv.cmpleu.sc.h x5, x6, x7
+    cv.cmpleu.sc.b x5, x6, x7
+    cv.cmpleu.sci.h x6, x7, 20
+    cv.cmpleu.sci.b x6, x7, 20
+    cv.cplxmul.r x5, x6, x7
+    cv.cplxmul.i x5, x6, x7
+    cv.cplxmul.r.div2 x5, x6, x7
+    cv.cplxmul.i.div2 x5, x6, x7
+    cv.cplxmul.r.div4 x5, x6, x7
+    cv.cplxmul.i.div4 x5, x6, x7
+    cv.cplxmul.r.div8 x5, x6, x7
+    cv.cplxmul.i.div8 x5, x6, x7
+    cv.cplxconj x6, x7
+    cv.subrotmj x5, x6, x7
+    cv.subrotmj.div2 x5, x6, x7
+    cv.subrotmj.div4 x5, x6, x7
+    cv.subrotmj.div8 x5, x6, x7
+    cv.add.div2 x5, x6, x7
+    cv.add.div4 x5, x6, x7
+    cv.add.div8 x5, x6, x7
+    cv.sub.div2 x5, x6, x7
+    cv.sub.div4 x5, x6, x7
+    cv.sub.div8 x5, x6, x7
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-max-b-fail.d
new file mode 100644
index 00000000000..7adfdf10d87
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-max-b-fail.s
+#error_output: cv-simd-max-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-max-b-fail.l
new file mode 100644
index 00000000000..ffa9db5ce2e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.max.b x32,x32,x32'
+.*: Error: illegal operands `cv.max.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-max-b-fail.s
new file mode 100644
index 00000000000..1f635f4599c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.max.b x32, x32, x32
+    cv.max.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-max-b-pass.d
new file mode 100644
index 00000000000..994a4c89222
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-max-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3000107b          	cv.max.b	zero,zero,zero
+   4:	301090fb          	cv.max.b	ra,ra,ra
+   8:	3021117b          	cv.max.b	sp,sp,sp
+   c:	3084147b          	cv.max.b	s0,s0,s0
+  10:	314a1a7b          	cv.max.b	s4,s4,s4
+  14:	31ff9ffb          	cv.max.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-max-b-pass.s
new file mode 100644
index 00000000000..fa8e090e21c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.max.b x0, x0, x0
+    cv.max.b x1, x1, x1
+    cv.max.b x2, x2, x2
+    cv.max.b x8, x8, x8
+    cv.max.b x20, x20, x20
+    cv.max.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-max-h-fail.d
new file mode 100644
index 00000000000..2902f67e7c2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-max-h-fail.s
+#error_output: cv-simd-max-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-max-h-fail.l
new file mode 100644
index 00000000000..e99ba005a12
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.max.h x32,x32,x32'
+.*: Error: illegal operands `cv.max.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-max-h-fail.s
new file mode 100644
index 00000000000..6f6a9e7f71f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.max.h x32, x32, x32
+    cv.max.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-max-h-pass.d
new file mode 100644
index 00000000000..296f9e597db
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-max-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3000007b          	cv.max.h	zero,zero,zero
+   4:	301080fb          	cv.max.h	ra,ra,ra
+   8:	3021017b          	cv.max.h	sp,sp,sp
+   c:	3084047b          	cv.max.h	s0,s0,s0
+  10:	314a0a7b          	cv.max.h	s4,s4,s4
+  14:	31ff8ffb          	cv.max.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-max-h-pass.s
new file mode 100644
index 00000000000..921d44e81f9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.max.h x0, x0, x0
+    cv.max.h x1, x1, x1
+    cv.max.h x2, x2, x2
+    cv.max.h x8, x8, x8
+    cv.max.h x20, x20, x20
+    cv.max.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-max-sc-b-fail.d
new file mode 100644
index 00000000000..200aebfe5b8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-max-sc-b-fail.s
+#error_output: cv-simd-max-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-max-sc-b-fail.l
new file mode 100644
index 00000000000..62bb8033164
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.max.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.max.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-max-sc-b-fail.s
new file mode 100644
index 00000000000..7f33e07dbd3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.max.sc.b x32, x32, x32
+    cv.max.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-max-sc-b-pass.d
new file mode 100644
index 00000000000..f986253741c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-max-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3000507b          	cv.max.sc.b	zero,zero,zero
+   4:	3010d0fb          	cv.max.sc.b	ra,ra,ra
+   8:	3021517b          	cv.max.sc.b	sp,sp,sp
+   c:	3084547b          	cv.max.sc.b	s0,s0,s0
+  10:	314a5a7b          	cv.max.sc.b	s4,s4,s4
+  14:	31ffdffb          	cv.max.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-max-sc-b-pass.s
new file mode 100644
index 00000000000..2d6740beec8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.max.sc.b x0, x0, x0
+    cv.max.sc.b x1, x1, x1
+    cv.max.sc.b x2, x2, x2
+    cv.max.sc.b x8, x8, x8
+    cv.max.sc.b x20, x20, x20
+    cv.max.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-max-sc-h-fail.d
new file mode 100644
index 00000000000..4c79df34eac
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-max-sc-h-fail.s
+#error_output: cv-simd-max-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-max-sc-h-fail.l
new file mode 100644
index 00000000000..1b60f1d2a9b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.max.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.max.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-max-sc-h-fail.s
new file mode 100644
index 00000000000..ca7df25011f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.max.sc.h x32, x32, x32
+    cv.max.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-max-sc-h-pass.d
new file mode 100644
index 00000000000..bfecf4ece42
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-max-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3000407b          	cv.max.sc.h	zero,zero,zero
+   4:	3010c0fb          	cv.max.sc.h	ra,ra,ra
+   8:	3021417b          	cv.max.sc.h	sp,sp,sp
+   c:	3084447b          	cv.max.sc.h	s0,s0,s0
+  10:	314a4a7b          	cv.max.sc.h	s4,s4,s4
+  14:	31ffcffb          	cv.max.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-max-sc-h-pass.s
new file mode 100644
index 00000000000..316745d47bf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.max.sc.h x0, x0, x0
+    cv.max.sc.h x1, x1, x1
+    cv.max.sc.h x2, x2, x2
+    cv.max.sc.h x8, x8, x8
+    cv.max.sc.h x20, x20, x20
+    cv.max.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-max-sci-b-fail.d
new file mode 100644
index 00000000000..2c1fdd0fae4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-max-sci-b-fail.s
+#error_output: cv-simd-max-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-max-sci-b-fail.l
new file mode 100644
index 00000000000..27fd4658b42
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.max.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.max.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-max-sci-b-fail.s
new file mode 100644
index 00000000000..6032d61f607
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.max.sci.b x32, x32, 20
+    cv.max.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.max.sci.b x6, x7, -33
+    cv.max.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-max-sci-b-pass.d
new file mode 100644
index 00000000000..bd6d549cff1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-max-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	30a0707b          	cv.max.sci.b	zero,zero,20
+   4:	30a0f0fb          	cv.max.sci.b	ra,ra,20
+   8:	30a1717b          	cv.max.sci.b	sp,sp,20
+   c:	30a4747b          	cv.max.sci.b	s0,s0,20
+  10:	30aa7a7b          	cv.max.sci.b	s4,s4,20
+  14:	30affffb          	cv.max.sci.b	t6,t6,20
+  18:	3103f37b          	cv.max.sci.b	t1,t2,-32
+  1c:	3003f37b          	cv.max.sci.b	t1,t2,0
+  20:	32f3f37b          	cv.max.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-max-sci-b-pass.s
new file mode 100644
index 00000000000..d8d77d998c9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-sci-b-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.max.sci.b x0, x0, 20
+    cv.max.sci.b x1, x1, 20
+    cv.max.sci.b x2, x2, 20
+    cv.max.sci.b x8, x8, 20
+    cv.max.sci.b x20, x20, 20
+    cv.max.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.max.sci.b x6, x7, -32
+    cv.max.sci.b x6, x7, 0
+    cv.max.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-max-sci-h-fail.d
new file mode 100644
index 00000000000..2230bd4ed6d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-max-sci-h-fail.s
+#error_output: cv-simd-max-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-max-sci-h-fail.l
new file mode 100644
index 00000000000..de60c07a756
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.max.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.max.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-max-sci-h-fail.s
new file mode 100644
index 00000000000..fa0a4f04737
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.max.sci.h x32, x32, 20
+    cv.max.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.max.sci.h x6, x7, -33
+    cv.max.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-max-sci-h-pass.d
new file mode 100644
index 00000000000..022f13aedd5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-max-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	30a0607b          	cv.max.sci.h	zero,zero,20
+   4:	30a0e0fb          	cv.max.sci.h	ra,ra,20
+   8:	30a1617b          	cv.max.sci.h	sp,sp,20
+   c:	30a4647b          	cv.max.sci.h	s0,s0,20
+  10:	30aa6a7b          	cv.max.sci.h	s4,s4,20
+  14:	30afeffb          	cv.max.sci.h	t6,t6,20
+  18:	3103e37b          	cv.max.sci.h	t1,t2,-32
+  1c:	3003e37b          	cv.max.sci.h	t1,t2,0
+  20:	32f3e37b          	cv.max.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-max-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-max-sci-h-pass.s
new file mode 100644
index 00000000000..96fb0f76b3d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-max-sci-h-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.max.sci.h x0, x0, 20
+    cv.max.sci.h x1, x1, 20
+    cv.max.sci.h x2, x2, 20
+    cv.max.sci.h x8, x8, 20
+    cv.max.sci.h x20, x20, 20
+    cv.max.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.max.sci.h x6, x7, -32
+    cv.max.sci.h x6, x7, 0
+    cv.max.sci.h x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-maxu-b-fail.d
new file mode 100644
index 00000000000..ece0eb491ce
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-maxu-b-fail.s
+#error_output: cv-simd-maxu-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-maxu-b-fail.l
new file mode 100644
index 00000000000..ac57a2f9361
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.maxu.b x32,x32,x32'
+.*: Error: illegal operands `cv.maxu.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-maxu-b-fail.s
new file mode 100644
index 00000000000..6b3ba6cd3f0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.maxu.b x32, x32, x32
+    cv.maxu.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-maxu-b-pass.d
new file mode 100644
index 00000000000..4d7a1e8ac05
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-maxu-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3800107b          	cv.maxu.b	zero,zero,zero
+   4:	381090fb          	cv.maxu.b	ra,ra,ra
+   8:	3821117b          	cv.maxu.b	sp,sp,sp
+   c:	3884147b          	cv.maxu.b	s0,s0,s0
+  10:	394a1a7b          	cv.maxu.b	s4,s4,s4
+  14:	39ff9ffb          	cv.maxu.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-maxu-b-pass.s
new file mode 100644
index 00000000000..e37d0c77304
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.maxu.b x0, x0, x0
+    cv.maxu.b x1, x1, x1
+    cv.maxu.b x2, x2, x2
+    cv.maxu.b x8, x8, x8
+    cv.maxu.b x20, x20, x20
+    cv.maxu.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-maxu-h-fail.d
new file mode 100644
index 00000000000..60114f2669a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-maxu-h-fail.s
+#error_output: cv-simd-maxu-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-maxu-h-fail.l
new file mode 100644
index 00000000000..1d530582eaa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.maxu.h x32,x32,x32'
+.*: Error: illegal operands `cv.maxu.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-maxu-h-fail.s
new file mode 100644
index 00000000000..ff67ae4fa88
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.maxu.h x32, x32, x32
+    cv.maxu.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-maxu-h-pass.d
new file mode 100644
index 00000000000..ebc70e75647
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-maxu-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3800007b          	cv.maxu.h	zero,zero,zero
+   4:	381080fb          	cv.maxu.h	ra,ra,ra
+   8:	3821017b          	cv.maxu.h	sp,sp,sp
+   c:	3884047b          	cv.maxu.h	s0,s0,s0
+  10:	394a0a7b          	cv.maxu.h	s4,s4,s4
+  14:	39ff8ffb          	cv.maxu.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-maxu-h-pass.s
new file mode 100644
index 00000000000..b58ba27aa6a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.maxu.h x0, x0, x0
+    cv.maxu.h x1, x1, x1
+    cv.maxu.h x2, x2, x2
+    cv.maxu.h x8, x8, x8
+    cv.maxu.h x20, x20, x20
+    cv.maxu.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-maxu-sc-b-fail.d
new file mode 100644
index 00000000000..a1da7306139
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-maxu-sc-b-fail.s
+#error_output: cv-simd-maxu-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-maxu-sc-b-fail.l
new file mode 100644
index 00000000000..7f1928d30bd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.maxu.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.maxu.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-maxu-sc-b-fail.s
new file mode 100644
index 00000000000..2717beabedf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.maxu.sc.b x32, x32, x32
+    cv.maxu.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-maxu-sc-b-pass.d
new file mode 100644
index 00000000000..5e18aca58ac
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-maxu-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3800507b          	cv.maxu.sc.b	zero,zero,zero
+   4:	3810d0fb          	cv.maxu.sc.b	ra,ra,ra
+   8:	3821517b          	cv.maxu.sc.b	sp,sp,sp
+   c:	3884547b          	cv.maxu.sc.b	s0,s0,s0
+  10:	394a5a7b          	cv.maxu.sc.b	s4,s4,s4
+  14:	39ffdffb          	cv.maxu.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-maxu-sc-b-pass.s
new file mode 100644
index 00000000000..8cf477b3524
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.maxu.sc.b x0, x0, x0
+    cv.maxu.sc.b x1, x1, x1
+    cv.maxu.sc.b x2, x2, x2
+    cv.maxu.sc.b x8, x8, x8
+    cv.maxu.sc.b x20, x20, x20
+    cv.maxu.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-maxu-sc-h-fail.d
new file mode 100644
index 00000000000..91c8ef5f879
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-maxu-sc-h-fail.s
+#error_output: cv-simd-maxu-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-maxu-sc-h-fail.l
new file mode 100644
index 00000000000..1fc68d46428
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.maxu.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.maxu.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-maxu-sc-h-fail.s
new file mode 100644
index 00000000000..4c9c385b004
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.maxu.sc.h x32, x32, x32
+    cv.maxu.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-maxu-sc-h-pass.d
new file mode 100644
index 00000000000..451224eea82
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-maxu-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3800407b          	cv.maxu.sc.h	zero,zero,zero
+   4:	3810c0fb          	cv.maxu.sc.h	ra,ra,ra
+   8:	3821417b          	cv.maxu.sc.h	sp,sp,sp
+   c:	3884447b          	cv.maxu.sc.h	s0,s0,s0
+  10:	394a4a7b          	cv.maxu.sc.h	s4,s4,s4
+  14:	39ffcffb          	cv.maxu.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-maxu-sc-h-pass.s
new file mode 100644
index 00000000000..e19266ebec7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.maxu.sc.h x0, x0, x0
+    cv.maxu.sc.h x1, x1, x1
+    cv.maxu.sc.h x2, x2, x2
+    cv.maxu.sc.h x8, x8, x8
+    cv.maxu.sc.h x20, x20, x20
+    cv.maxu.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-maxu-sci-b-fail.d
new file mode 100644
index 00000000000..260b58a43b8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-maxu-sci-b-fail.s
+#error_output: cv-simd-maxu-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-maxu-sci-b-fail.l
new file mode 100644
index 00000000000..c1429c0b23c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.maxu.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.maxu.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-maxu-sci-b-fail.s
new file mode 100644
index 00000000000..982160ed302
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.maxu.sci.b x32, x32, 20
+    cv.maxu.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.maxu.sci.b x6, x7, -1
+    cv.maxu.sci.b x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-maxu-sci-b-pass.d
new file mode 100644
index 00000000000..f7e9be756a1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-sci-b-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-maxu-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	38a0707b          	cv.maxu.sci.b	zero,zero,20
+   4:	38a0f0fb          	cv.maxu.sci.b	ra,ra,20
+   8:	38a1717b          	cv.maxu.sci.b	sp,sp,20
+   c:	38a4747b          	cv.maxu.sci.b	s0,s0,20
+  10:	38aa7a7b          	cv.maxu.sci.b	s4,s4,20
+  14:	38affffb          	cv.maxu.sci.b	t6,t6,20
+  18:	3803f37b          	cv.maxu.sci.b	t1,t2,0
+  1c:	3bf3f37b          	cv.maxu.sci.b	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-maxu-sci-b-pass.s
new file mode 100644
index 00000000000..c1332ebe8ff
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-sci-b-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.maxu.sci.b x0, x0, 20
+    cv.maxu.sci.b x1, x1, 20
+    cv.maxu.sci.b x2, x2, 20
+    cv.maxu.sci.b x8, x8, 20
+    cv.maxu.sci.b x20, x20, 20
+    cv.maxu.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.maxu.sci.b x6, x7, 0
+    cv.maxu.sci.b x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-maxu-sci-h-fail.d
new file mode 100644
index 00000000000..b1841b44de2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-maxu-sci-h-fail.s
+#error_output: cv-simd-maxu-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-maxu-sci-h-fail.l
new file mode 100644
index 00000000000..444a3b52c41
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.maxu.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.maxu.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-maxu-sci-h-fail.s
new file mode 100644
index 00000000000..762754680b8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.maxu.sci.h x32, x32, 20
+    cv.maxu.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.maxu.sci.h x6, x7, -1
+    cv.maxu.sci.h x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-maxu-sci-h-pass.d
new file mode 100644
index 00000000000..1510bec98f5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-sci-h-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-maxu-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	38a0607b          	cv.maxu.sci.h	zero,zero,20
+   4:	38a0e0fb          	cv.maxu.sci.h	ra,ra,20
+   8:	38a1617b          	cv.maxu.sci.h	sp,sp,20
+   c:	38a4647b          	cv.maxu.sci.h	s0,s0,20
+  10:	38aa6a7b          	cv.maxu.sci.h	s4,s4,20
+  14:	38afeffb          	cv.maxu.sci.h	t6,t6,20
+  18:	3803e37b          	cv.maxu.sci.h	t1,t2,0
+  1c:	3bf3e37b          	cv.maxu.sci.h	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-maxu-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-maxu-sci-h-pass.s
new file mode 100644
index 00000000000..af87bde6e0b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-maxu-sci-h-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.maxu.sci.h x0, x0, 20
+    cv.maxu.sci.h x1, x1, 20
+    cv.maxu.sci.h x2, x2, 20
+    cv.maxu.sci.h x8, x8, 20
+    cv.maxu.sci.h x20, x20, 20
+    cv.maxu.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.maxu.sci.h x6, x7, 0
+    cv.maxu.sci.h x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-min-b-fail.d
new file mode 100644
index 00000000000..8757fdd74bd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-min-b-fail.s
+#error_output: cv-simd-min-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-min-b-fail.l
new file mode 100644
index 00000000000..3d78d2d91b8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.min.b x32,x32,x32'
+.*: Error: illegal operands `cv.min.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-min-b-fail.s
new file mode 100644
index 00000000000..8082360d286
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.min.b x32, x32, x32
+    cv.min.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-min-b-pass.d
new file mode 100644
index 00000000000..cb238cbc7dd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-min-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2000107b          	cv.min.b	zero,zero,zero
+   4:	201090fb          	cv.min.b	ra,ra,ra
+   8:	2021117b          	cv.min.b	sp,sp,sp
+   c:	2084147b          	cv.min.b	s0,s0,s0
+  10:	214a1a7b          	cv.min.b	s4,s4,s4
+  14:	21ff9ffb          	cv.min.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-min-b-pass.s
new file mode 100644
index 00000000000..c84fbe1dab1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.min.b x0, x0, x0
+    cv.min.b x1, x1, x1
+    cv.min.b x2, x2, x2
+    cv.min.b x8, x8, x8
+    cv.min.b x20, x20, x20
+    cv.min.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-min-h-fail.d
new file mode 100644
index 00000000000..fc20e7ebb77
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-min-h-fail.s
+#error_output: cv-simd-min-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-min-h-fail.l
new file mode 100644
index 00000000000..0f959466de8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.min.h x32,x32,x32'
+.*: Error: illegal operands `cv.min.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-min-h-fail.s
new file mode 100644
index 00000000000..78716687dc0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.min.h x32, x32, x32
+    cv.min.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-min-h-pass.d
new file mode 100644
index 00000000000..d3a67463904
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-min-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2000007b          	cv.min.h	zero,zero,zero
+   4:	201080fb          	cv.min.h	ra,ra,ra
+   8:	2021017b          	cv.min.h	sp,sp,sp
+   c:	2084047b          	cv.min.h	s0,s0,s0
+  10:	214a0a7b          	cv.min.h	s4,s4,s4
+  14:	21ff8ffb          	cv.min.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-min-h-pass.s
new file mode 100644
index 00000000000..5e4fea6541a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.min.h x0, x0, x0
+    cv.min.h x1, x1, x1
+    cv.min.h x2, x2, x2
+    cv.min.h x8, x8, x8
+    cv.min.h x20, x20, x20
+    cv.min.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-min-sc-b-fail.d
new file mode 100644
index 00000000000..1fc40b59be6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-min-sc-b-fail.s
+#error_output: cv-simd-min-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-min-sc-b-fail.l
new file mode 100644
index 00000000000..7f31ec02691
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.min.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.min.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-min-sc-b-fail.s
new file mode 100644
index 00000000000..72640b42a10
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.min.sc.b x32, x32, x32
+    cv.min.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-min-sc-b-pass.d
new file mode 100644
index 00000000000..739164a5872
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-min-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2000507b          	cv.min.sc.b	zero,zero,zero
+   4:	2010d0fb          	cv.min.sc.b	ra,ra,ra
+   8:	2021517b          	cv.min.sc.b	sp,sp,sp
+   c:	2084547b          	cv.min.sc.b	s0,s0,s0
+  10:	214a5a7b          	cv.min.sc.b	s4,s4,s4
+  14:	21ffdffb          	cv.min.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-min-sc-b-pass.s
new file mode 100644
index 00000000000..10c7c478891
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.min.sc.b x0, x0, x0
+    cv.min.sc.b x1, x1, x1
+    cv.min.sc.b x2, x2, x2
+    cv.min.sc.b x8, x8, x8
+    cv.min.sc.b x20, x20, x20
+    cv.min.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-min-sc-h-fail.d
new file mode 100644
index 00000000000..600b3b9b3ff
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-min-sc-h-fail.s
+#error_output: cv-simd-min-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-min-sc-h-fail.l
new file mode 100644
index 00000000000..72ce1e76a29
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.min.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.min.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-min-sc-h-fail.s
new file mode 100644
index 00000000000..43f9d10eaf7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.min.sc.h x32, x32, x32
+    cv.min.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-min-sc-h-pass.d
new file mode 100644
index 00000000000..c6361bed1fa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-min-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2000407b          	cv.min.sc.h	zero,zero,zero
+   4:	2010c0fb          	cv.min.sc.h	ra,ra,ra
+   8:	2021417b          	cv.min.sc.h	sp,sp,sp
+   c:	2084447b          	cv.min.sc.h	s0,s0,s0
+  10:	214a4a7b          	cv.min.sc.h	s4,s4,s4
+  14:	21ffcffb          	cv.min.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-min-sc-h-pass.s
new file mode 100644
index 00000000000..3f814f48d64
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.min.sc.h x0, x0, x0
+    cv.min.sc.h x1, x1, x1
+    cv.min.sc.h x2, x2, x2
+    cv.min.sc.h x8, x8, x8
+    cv.min.sc.h x20, x20, x20
+    cv.min.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-min-sci-b-fail.d
new file mode 100644
index 00000000000..62b171d7856
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-min-sci-b-fail.s
+#error_output: cv-simd-min-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-min-sci-b-fail.l
new file mode 100644
index 00000000000..204cae31c6a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.min.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.min.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-min-sci-b-fail.s
new file mode 100644
index 00000000000..c413ec1f281
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.min.sci.b x32, x32, 20
+    cv.min.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.min.sci.b x6, x7, -33
+    cv.min.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-min-sci-b-pass.d
new file mode 100644
index 00000000000..6c367a19365
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-min-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	20a0707b          	cv.min.sci.b	zero,zero,20
+   4:	20a0f0fb          	cv.min.sci.b	ra,ra,20
+   8:	20a1717b          	cv.min.sci.b	sp,sp,20
+   c:	20a4747b          	cv.min.sci.b	s0,s0,20
+  10:	20aa7a7b          	cv.min.sci.b	s4,s4,20
+  14:	20affffb          	cv.min.sci.b	t6,t6,20
+  18:	2103f37b          	cv.min.sci.b	t1,t2,-32
+  1c:	2003f37b          	cv.min.sci.b	t1,t2,0
+  20:	22f3f37b          	cv.min.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-min-sci-b-pass.s
new file mode 100644
index 00000000000..ce44fcea9f6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-sci-b-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.min.sci.b x0, x0, 20
+    cv.min.sci.b x1, x1, 20
+    cv.min.sci.b x2, x2, 20
+    cv.min.sci.b x8, x8, 20
+    cv.min.sci.b x20, x20, 20
+    cv.min.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.min.sci.b x6, x7, -32
+    cv.min.sci.b x6, x7, 0
+    cv.min.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-min-sci-h-fail.d
new file mode 100644
index 00000000000..3af7fe1f912
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-min-sci-h-fail.s
+#error_output: cv-simd-min-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-min-sci-h-fail.l
new file mode 100644
index 00000000000..1179f306663
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.min.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.min.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-min-sci-h-fail.s
new file mode 100644
index 00000000000..813b3cc6e1d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.min.sci.h x32, x32, 20
+    cv.min.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.min.sci.h x6, x7, -33
+    cv.min.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-min-sci-h-pass.d
new file mode 100644
index 00000000000..8d6d6006314
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-min-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	20a0607b          	cv.min.sci.h	zero,zero,20
+   4:	20a0e0fb          	cv.min.sci.h	ra,ra,20
+   8:	20a1617b          	cv.min.sci.h	sp,sp,20
+   c:	20a4647b          	cv.min.sci.h	s0,s0,20
+  10:	20aa6a7b          	cv.min.sci.h	s4,s4,20
+  14:	20afeffb          	cv.min.sci.h	t6,t6,20
+  18:	2103e37b          	cv.min.sci.h	t1,t2,-32
+  1c:	2003e37b          	cv.min.sci.h	t1,t2,0
+  20:	22f3e37b          	cv.min.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-min-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-min-sci-h-pass.s
new file mode 100644
index 00000000000..2a49a1c1d74
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-min-sci-h-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.min.sci.h x0, x0, 20
+    cv.min.sci.h x1, x1, 20
+    cv.min.sci.h x2, x2, 20
+    cv.min.sci.h x8, x8, 20
+    cv.min.sci.h x20, x20, 20
+    cv.min.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.min.sci.h x6, x7, -32
+    cv.min.sci.h x6, x7, 0
+    cv.min.sci.h x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-minu-b-fail.d
new file mode 100644
index 00000000000..1849d1e58d9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-minu-b-fail.s
+#error_output: cv-simd-minu-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-minu-b-fail.l
new file mode 100644
index 00000000000..9971ea8223e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.minu.b x32,x32,x32'
+.*: Error: illegal operands `cv.minu.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-minu-b-fail.s
new file mode 100644
index 00000000000..1a0a37ab006
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.minu.b x32, x32, x32
+    cv.minu.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-minu-b-pass.d
new file mode 100644
index 00000000000..8447639c467
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-minu-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2800107b          	cv.minu.b	zero,zero,zero
+   4:	281090fb          	cv.minu.b	ra,ra,ra
+   8:	2821117b          	cv.minu.b	sp,sp,sp
+   c:	2884147b          	cv.minu.b	s0,s0,s0
+  10:	294a1a7b          	cv.minu.b	s4,s4,s4
+  14:	29ff9ffb          	cv.minu.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-minu-b-pass.s
new file mode 100644
index 00000000000..40c2358227c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.minu.b x0, x0, x0
+    cv.minu.b x1, x1, x1
+    cv.minu.b x2, x2, x2
+    cv.minu.b x8, x8, x8
+    cv.minu.b x20, x20, x20
+    cv.minu.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-minu-h-fail.d
new file mode 100644
index 00000000000..f10a6c20d8e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-minu-h-fail.s
+#error_output: cv-simd-minu-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-minu-h-fail.l
new file mode 100644
index 00000000000..8916337969a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.minu.h x32,x32,x32'
+.*: Error: illegal operands `cv.minu.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-minu-h-fail.s
new file mode 100644
index 00000000000..adac558f815
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.minu.h x32, x32, x32
+    cv.minu.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-minu-h-pass.d
new file mode 100644
index 00000000000..dd00cb5d9e9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-minu-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2800007b          	cv.minu.h	zero,zero,zero
+   4:	281080fb          	cv.minu.h	ra,ra,ra
+   8:	2821017b          	cv.minu.h	sp,sp,sp
+   c:	2884047b          	cv.minu.h	s0,s0,s0
+  10:	294a0a7b          	cv.minu.h	s4,s4,s4
+  14:	29ff8ffb          	cv.minu.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-minu-h-pass.s
new file mode 100644
index 00000000000..5dc4665db5b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.minu.h x0, x0, x0
+    cv.minu.h x1, x1, x1
+    cv.minu.h x2, x2, x2
+    cv.minu.h x8, x8, x8
+    cv.minu.h x20, x20, x20
+    cv.minu.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-minu-sc-b-fail.d
new file mode 100644
index 00000000000..865ba166c10
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-minu-sc-b-fail.s
+#error_output: cv-simd-minu-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-minu-sc-b-fail.l
new file mode 100644
index 00000000000..de8c2c89c0e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.minu.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.minu.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-minu-sc-b-fail.s
new file mode 100644
index 00000000000..4de7d026b80
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.minu.sc.b x32, x32, x32
+    cv.minu.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-minu-sc-b-pass.d
new file mode 100644
index 00000000000..c3f33bc2649
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-minu-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2800507b          	cv.minu.sc.b	zero,zero,zero
+   4:	2810d0fb          	cv.minu.sc.b	ra,ra,ra
+   8:	2821517b          	cv.minu.sc.b	sp,sp,sp
+   c:	2884547b          	cv.minu.sc.b	s0,s0,s0
+  10:	294a5a7b          	cv.minu.sc.b	s4,s4,s4
+  14:	29ffdffb          	cv.minu.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-minu-sc-b-pass.s
new file mode 100644
index 00000000000..ba273c21fff
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.minu.sc.b x0, x0, x0
+    cv.minu.sc.b x1, x1, x1
+    cv.minu.sc.b x2, x2, x2
+    cv.minu.sc.b x8, x8, x8
+    cv.minu.sc.b x20, x20, x20
+    cv.minu.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-minu-sc-h-fail.d
new file mode 100644
index 00000000000..eb2298dc4cb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-minu-sc-h-fail.s
+#error_output: cv-simd-minu-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-minu-sc-h-fail.l
new file mode 100644
index 00000000000..9d66f906a9f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.minu.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.minu.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-minu-sc-h-fail.s
new file mode 100644
index 00000000000..243526d32cc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.minu.sc.h x32, x32, x32
+    cv.minu.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-minu-sc-h-pass.d
new file mode 100644
index 00000000000..517459662aa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-minu-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2800407b          	cv.minu.sc.h	zero,zero,zero
+   4:	2810c0fb          	cv.minu.sc.h	ra,ra,ra
+   8:	2821417b          	cv.minu.sc.h	sp,sp,sp
+   c:	2884447b          	cv.minu.sc.h	s0,s0,s0
+  10:	294a4a7b          	cv.minu.sc.h	s4,s4,s4
+  14:	29ffcffb          	cv.minu.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-minu-sc-h-pass.s
new file mode 100644
index 00000000000..7a211d5f755
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.minu.sc.h x0, x0, x0
+    cv.minu.sc.h x1, x1, x1
+    cv.minu.sc.h x2, x2, x2
+    cv.minu.sc.h x8, x8, x8
+    cv.minu.sc.h x20, x20, x20
+    cv.minu.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-minu-sci-b-fail.d
new file mode 100644
index 00000000000..644315337e3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-minu-sci-b-fail.s
+#error_output: cv-simd-minu-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-minu-sci-b-fail.l
new file mode 100644
index 00000000000..b4fd02693a2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.minu.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.minu.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-minu-sci-b-fail.s
new file mode 100644
index 00000000000..a19173479d1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.minu.sci.b x32, x32, 20
+    cv.minu.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.minu.sci.b x6, x7, -1
+    cv.minu.sci.b x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-minu-sci-b-pass.d
new file mode 100644
index 00000000000..37bb919f7e0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-sci-b-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-minu-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	28a0707b          	cv.minu.sci.b	zero,zero,20
+   4:	28a0f0fb          	cv.minu.sci.b	ra,ra,20
+   8:	28a1717b          	cv.minu.sci.b	sp,sp,20
+   c:	28a4747b          	cv.minu.sci.b	s0,s0,20
+  10:	28aa7a7b          	cv.minu.sci.b	s4,s4,20
+  14:	28affffb          	cv.minu.sci.b	t6,t6,20
+  18:	2803f37b          	cv.minu.sci.b	t1,t2,0
+  1c:	2bf3f37b          	cv.minu.sci.b	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-minu-sci-b-pass.s
new file mode 100644
index 00000000000..3491555ee86
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-sci-b-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.minu.sci.b x0, x0, 20
+    cv.minu.sci.b x1, x1, 20
+    cv.minu.sci.b x2, x2, 20
+    cv.minu.sci.b x8, x8, 20
+    cv.minu.sci.b x20, x20, 20
+    cv.minu.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.minu.sci.b x6, x7, 0
+    cv.minu.sci.b x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-minu-sci-h-fail.d
new file mode 100644
index 00000000000..d3d2c9e63eb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-minu-sci-h-fail.s
+#error_output: cv-simd-minu-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-minu-sci-h-fail.l
new file mode 100644
index 00000000000..0b91dab3888
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.minu.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.minu.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-minu-sci-h-fail.s
new file mode 100644
index 00000000000..1cf624ac1bc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.minu.sci.h x32, x32, 20
+    cv.minu.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.minu.sci.h x6, x7, -1
+    cv.minu.sci.h x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-minu-sci-h-pass.d
new file mode 100644
index 00000000000..3676b051820
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-sci-h-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-minu-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	28a0607b          	cv.minu.sci.h	zero,zero,20
+   4:	28a0e0fb          	cv.minu.sci.h	ra,ra,20
+   8:	28a1617b          	cv.minu.sci.h	sp,sp,20
+   c:	28a4647b          	cv.minu.sci.h	s0,s0,20
+  10:	28aa6a7b          	cv.minu.sci.h	s4,s4,20
+  14:	28afeffb          	cv.minu.sci.h	t6,t6,20
+  18:	2803e37b          	cv.minu.sci.h	t1,t2,0
+  1c:	2bf3e37b          	cv.minu.sci.h	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-minu-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-minu-sci-h-pass.s
new file mode 100644
index 00000000000..39e6fd8458e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-minu-sci-h-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.minu.sci.h x0, x0, 20
+    cv.minu.sci.h x1, x1, 20
+    cv.minu.sci.h x2, x2, 20
+    cv.minu.sci.h x8, x8, 20
+    cv.minu.sci.h x20, x20, 20
+    cv.minu.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.minu.sci.h x6, x7, 0
+    cv.minu.sci.h x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-or-b-fail.d
new file mode 100644
index 00000000000..80bd5bfdd85
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-or-b-fail.s
+#error_output: cv-simd-or-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-or-b-fail.l
new file mode 100644
index 00000000000..b74c77f5aec
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.or.b x32,x32,x32'
+.*: Error: illegal operands `cv.or.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-or-b-fail.s
new file mode 100644
index 00000000000..aa00646a951
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.or.b x32, x32, x32
+    cv.or.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-or-b-pass.d
new file mode 100644
index 00000000000..f43c9a3feeb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-or-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	5800107b          	cv.or.b	zero,zero,zero
+   4:	581090fb          	cv.or.b	ra,ra,ra
+   8:	5821117b          	cv.or.b	sp,sp,sp
+   c:	5884147b          	cv.or.b	s0,s0,s0
+  10:	594a1a7b          	cv.or.b	s4,s4,s4
+  14:	59ff9ffb          	cv.or.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-or-b-pass.s
new file mode 100644
index 00000000000..8ef5e6ee58f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.or.b x0, x0, x0
+    cv.or.b x1, x1, x1
+    cv.or.b x2, x2, x2
+    cv.or.b x8, x8, x8
+    cv.or.b x20, x20, x20
+    cv.or.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-or-h-fail.d
new file mode 100644
index 00000000000..99835ee84bf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-or-h-fail.s
+#error_output: cv-simd-or-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-or-h-fail.l
new file mode 100644
index 00000000000..d0c6c34792e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.or.h x32,x32,x32'
+.*: Error: illegal operands `cv.or.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-or-h-fail.s
new file mode 100644
index 00000000000..aa4d3e6949e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.or.h x32, x32, x32
+    cv.or.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-or-h-pass.d
new file mode 100644
index 00000000000..1bf40c71728
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-or-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	5800007b          	cv.or.h	zero,zero,zero
+   4:	581080fb          	cv.or.h	ra,ra,ra
+   8:	5821017b          	cv.or.h	sp,sp,sp
+   c:	5884047b          	cv.or.h	s0,s0,s0
+  10:	594a0a7b          	cv.or.h	s4,s4,s4
+  14:	59ff8ffb          	cv.or.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-or-h-pass.s
new file mode 100644
index 00000000000..51eda75e4d1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.or.h x0, x0, x0
+    cv.or.h x1, x1, x1
+    cv.or.h x2, x2, x2
+    cv.or.h x8, x8, x8
+    cv.or.h x20, x20, x20
+    cv.or.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-or-sc-b-fail.d
new file mode 100644
index 00000000000..34675446982
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-or-sc-b-fail.s
+#error_output: cv-simd-or-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-or-sc-b-fail.l
new file mode 100644
index 00000000000..91efc3051a4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.or.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.or.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-or-sc-b-fail.s
new file mode 100644
index 00000000000..9376cb95a6d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.or.sc.b x32, x32, x32
+    cv.or.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-or-sc-b-pass.d
new file mode 100644
index 00000000000..784acbb5da4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-or-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	5800507b          	cv.or.sc.b	zero,zero,zero
+   4:	5810d0fb          	cv.or.sc.b	ra,ra,ra
+   8:	5821517b          	cv.or.sc.b	sp,sp,sp
+   c:	5884547b          	cv.or.sc.b	s0,s0,s0
+  10:	594a5a7b          	cv.or.sc.b	s4,s4,s4
+  14:	59ffdffb          	cv.or.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-or-sc-b-pass.s
new file mode 100644
index 00000000000..34cb4d3e4b6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.or.sc.b x0, x0, x0
+    cv.or.sc.b x1, x1, x1
+    cv.or.sc.b x2, x2, x2
+    cv.or.sc.b x8, x8, x8
+    cv.or.sc.b x20, x20, x20
+    cv.or.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-or-sc-h-fail.d
new file mode 100644
index 00000000000..000d3704839
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-or-sc-h-fail.s
+#error_output: cv-simd-or-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-or-sc-h-fail.l
new file mode 100644
index 00000000000..18e64bd956a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.or.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.or.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-or-sc-h-fail.s
new file mode 100644
index 00000000000..8560a8cca0b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.or.sc.h x32, x32, x32
+    cv.or.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-or-sc-h-pass.d
new file mode 100644
index 00000000000..5f4f09431a8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-or-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	5800407b          	cv.or.sc.h	zero,zero,zero
+   4:	5810c0fb          	cv.or.sc.h	ra,ra,ra
+   8:	5821417b          	cv.or.sc.h	sp,sp,sp
+   c:	5884447b          	cv.or.sc.h	s0,s0,s0
+  10:	594a4a7b          	cv.or.sc.h	s4,s4,s4
+  14:	59ffcffb          	cv.or.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-or-sc-h-pass.s
new file mode 100644
index 00000000000..35f86fe31d3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.or.sc.h x0, x0, x0
+    cv.or.sc.h x1, x1, x1
+    cv.or.sc.h x2, x2, x2
+    cv.or.sc.h x8, x8, x8
+    cv.or.sc.h x20, x20, x20
+    cv.or.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-or-sci-b-fail.d
new file mode 100644
index 00000000000..76eed3c76df
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-or-sci-b-fail.s
+#error_output: cv-simd-or-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-or-sci-b-fail.l
new file mode 100644
index 00000000000..475ea370e42
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.or.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.or.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-or-sci-b-fail.s
new file mode 100644
index 00000000000..24abb0e5b51
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.or.sci.b x32, x32, 20
+    cv.or.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.or.sci.b x6, x7, -33
+    cv.or.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-or-sci-b-pass.d
new file mode 100644
index 00000000000..a417f85956a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-or-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	58a0707b          	cv.or.sci.b	zero,zero,20
+   4:	58a0f0fb          	cv.or.sci.b	ra,ra,20
+   8:	58a1717b          	cv.or.sci.b	sp,sp,20
+   c:	58a4747b          	cv.or.sci.b	s0,s0,20
+  10:	58aa7a7b          	cv.or.sci.b	s4,s4,20
+  14:	58affffb          	cv.or.sci.b	t6,t6,20
+  18:	5903f37b          	cv.or.sci.b	t1,t2,-32
+  1c:	5803f37b          	cv.or.sci.b	t1,t2,0
+  20:	5af3f37b          	cv.or.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-or-sci-b-pass.s
new file mode 100644
index 00000000000..c7b98418cd1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-sci-b-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.or.sci.b x0, x0, 20
+    cv.or.sci.b x1, x1, 20
+    cv.or.sci.b x2, x2, 20
+    cv.or.sci.b x8, x8, 20
+    cv.or.sci.b x20, x20, 20
+    cv.or.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.or.sci.b x6, x7, -32
+    cv.or.sci.b x6, x7, 0
+    cv.or.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-or-sci-h-fail.d
new file mode 100644
index 00000000000..f6b8d5920ad
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-or-sci-h-fail.s
+#error_output: cv-simd-or-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-or-sci-h-fail.l
new file mode 100644
index 00000000000..691d6d4354b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.or.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.or.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-or-sci-h-fail.s
new file mode 100644
index 00000000000..b7130e81f6e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.or.sci.h x32, x32, 20
+    cv.or.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.or.sci.h x6, x7, -33
+    cv.or.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-or-sci-h-pass.d
new file mode 100644
index 00000000000..5ec05f4c33c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-or-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	58a0607b          	cv.or.sci.h	zero,zero,20
+   4:	58a0e0fb          	cv.or.sci.h	ra,ra,20
+   8:	58a1617b          	cv.or.sci.h	sp,sp,20
+   c:	58a4647b          	cv.or.sci.h	s0,s0,20
+  10:	58aa6a7b          	cv.or.sci.h	s4,s4,20
+  14:	58afeffb          	cv.or.sci.h	t6,t6,20
+  18:	5903e37b          	cv.or.sci.h	t1,t2,-32
+  1c:	5803e37b          	cv.or.sci.h	t1,t2,0
+  20:	5af3e37b          	cv.or.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-or-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-or-sci-h-pass.s
new file mode 100644
index 00000000000..b1658bc21fd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-or-sci-h-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.or.sci.h x0, x0, 20
+    cv.or.sci.h x1, x1, 20
+    cv.or.sci.h x2, x2, 20
+    cv.or.sci.h x8, x8, 20
+    cv.or.sci.h x20, x20, 20
+    cv.or.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.or.sci.h x6, x7, -32
+    cv.or.sci.h x6, x7, 0
+    cv.or.sci.h x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-pack-fail.d b/gas/testsuite/gas/riscv/cv-simd-pack-fail.d
new file mode 100644
index 00000000000..a2d609657c1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-pack-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-pack-fail.s
+#error_output: cv-simd-pack-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-pack-fail.l b/gas/testsuite/gas/riscv/cv-simd-pack-fail.l
new file mode 100644
index 00000000000..9668f1f40c0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-pack-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.pack x32,x32,x32'
+.*: Error: illegal operands `cv.pack x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-pack-fail.s b/gas/testsuite/gas/riscv/cv-simd-pack-fail.s
new file mode 100644
index 00000000000..b2bcd883301
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-pack-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.pack x32, x32, x32
+    cv.pack x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-pack-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-pack-h-fail.d
new file mode 100644
index 00000000000..07a3e2f9a21
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-pack-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-pack-h-fail.s
+#error_output: cv-simd-pack-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-pack-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-pack-h-fail.l
new file mode 100644
index 00000000000..db35aa977f5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-pack-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.pack.h x32,x32,x32'
+.*: Error: illegal operands `cv.pack.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-pack-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-pack-h-fail.s
new file mode 100644
index 00000000000..a7632834a30
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-pack-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.pack.h x32, x32, x32
+    cv.pack.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-pack-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-pack-h-pass.d
new file mode 100644
index 00000000000..89e420c8940
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-pack-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-pack-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	f200007b          	cv.pack.h	zero,zero,zero
+   4:	f21080fb          	cv.pack.h	ra,ra,ra
+   8:	f221017b          	cv.pack.h	sp,sp,sp
+   c:	f284047b          	cv.pack.h	s0,s0,s0
+  10:	f34a0a7b          	cv.pack.h	s4,s4,s4
+  14:	f3ff8ffb          	cv.pack.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-pack-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-pack-h-pass.s
new file mode 100644
index 00000000000..4bf49c2bc8c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-pack-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.pack.h x0, x0, x0
+    cv.pack.h x1, x1, x1
+    cv.pack.h x2, x2, x2
+    cv.pack.h x8, x8, x8
+    cv.pack.h x20, x20, x20
+    cv.pack.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-pack-pass.d b/gas/testsuite/gas/riscv/cv-simd-pack-pass.d
new file mode 100644
index 00000000000..e6031015c71
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-pack-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-pack-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	f000007b          	cv.pack	zero,zero,zero
+   4:	f01080fb          	cv.pack	ra,ra,ra
+   8:	f021017b          	cv.pack	sp,sp,sp
+   c:	f084047b          	cv.pack	s0,s0,s0
+  10:	f14a0a7b          	cv.pack	s4,s4,s4
+  14:	f1ff8ffb          	cv.pack	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-pack-pass.s b/gas/testsuite/gas/riscv/cv-simd-pack-pass.s
new file mode 100644
index 00000000000..5dddf9c08d0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-pack-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.pack x0, x0, x0
+    cv.pack x1, x1, x1
+    cv.pack x2, x2, x2
+    cv.pack x8, x8, x8
+    cv.pack x20, x20, x20
+    cv.pack x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-packhi-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-packhi-b-fail.d
new file mode 100644
index 00000000000..745dac08bc5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-packhi-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-packhi-b-fail.s
+#error_output: cv-simd-packhi-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-packhi-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-packhi-b-fail.l
new file mode 100644
index 00000000000..60cc30ac241
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-packhi-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.packhi.b x32,x32,x32'
+.*: Error: illegal operands `cv.packhi.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-packhi-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-packhi-b-fail.s
new file mode 100644
index 00000000000..35b95425c06
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-packhi-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.packhi.b x32, x32, x32
+    cv.packhi.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-packhi-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-packhi-b-pass.d
new file mode 100644
index 00000000000..72a07bba6b5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-packhi-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-packhi-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	fa00107b          	cv.packhi.b	zero,zero,zero
+   4:	fa1090fb          	cv.packhi.b	ra,ra,ra
+   8:	fa21117b          	cv.packhi.b	sp,sp,sp
+   c:	fa84147b          	cv.packhi.b	s0,s0,s0
+  10:	fb4a1a7b          	cv.packhi.b	s4,s4,s4
+  14:	fbff9ffb          	cv.packhi.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-packhi-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-packhi-b-pass.s
new file mode 100644
index 00000000000..e974e1daf23
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-packhi-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.packhi.b x0, x0, x0
+    cv.packhi.b x1, x1, x1
+    cv.packhi.b x2, x2, x2
+    cv.packhi.b x8, x8, x8
+    cv.packhi.b x20, x20, x20
+    cv.packhi.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-packlo-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-packlo-b-fail.d
new file mode 100644
index 00000000000..3fc6ee8c396
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-packlo-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-packlo-b-fail.s
+#error_output: cv-simd-packlo-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-packlo-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-packlo-b-fail.l
new file mode 100644
index 00000000000..1141174e9e7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-packlo-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.packlo.b x32,x32,x32'
+.*: Error: illegal operands `cv.packlo.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-packlo-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-packlo-b-fail.s
new file mode 100644
index 00000000000..4f783ef8fa8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-packlo-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.packlo.b x32, x32, x32
+    cv.packlo.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-packlo-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-packlo-b-pass.d
new file mode 100644
index 00000000000..bc63970192d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-packlo-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-packlo-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	f800107b          	cv.packlo.b	zero,zero,zero
+   4:	f81090fb          	cv.packlo.b	ra,ra,ra
+   8:	f821117b          	cv.packlo.b	sp,sp,sp
+   c:	f884147b          	cv.packlo.b	s0,s0,s0
+  10:	f94a1a7b          	cv.packlo.b	s4,s4,s4
+  14:	f9ff9ffb          	cv.packlo.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-packlo-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-packlo-b-pass.s
new file mode 100644
index 00000000000..827a1311583
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-packlo-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.packlo.b x0, x0, x0
+    cv.packlo.b x1, x1, x1
+    cv.packlo.b x2, x2, x2
+    cv.packlo.b x8, x8, x8
+    cv.packlo.b x20, x20, x20
+    cv.packlo.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-sdotsp-b-fail.d
new file mode 100644
index 00000000000..80d14327e23
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotsp-b-fail.s
+#error_output: cv-simd-sdotsp-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-sdotsp-b-fail.l
new file mode 100644
index 00000000000..0171aeac5ed
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sdotsp.b x32,x32,x32'
+.*: Error: illegal operands `cv.sdotsp.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-sdotsp-b-fail.s
new file mode 100644
index 00000000000..6d9a04ee6e2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.sdotsp.b x32, x32, x32
+    cv.sdotsp.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-sdotsp-b-pass.d
new file mode 100644
index 00000000000..bc4609ed8cb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotsp-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	a800107b          	cv.sdotsp.b	zero,zero,zero
+   4:	a81090fb          	cv.sdotsp.b	ra,ra,ra
+   8:	a821117b          	cv.sdotsp.b	sp,sp,sp
+   c:	a884147b          	cv.sdotsp.b	s0,s0,s0
+  10:	a94a1a7b          	cv.sdotsp.b	s4,s4,s4
+  14:	a9ff9ffb          	cv.sdotsp.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-sdotsp-b-pass.s
new file mode 100644
index 00000000000..3988512f609
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.sdotsp.b x0, x0, x0
+    cv.sdotsp.b x1, x1, x1
+    cv.sdotsp.b x2, x2, x2
+    cv.sdotsp.b x8, x8, x8
+    cv.sdotsp.b x20, x20, x20
+    cv.sdotsp.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-sdotsp-h-fail.d
new file mode 100644
index 00000000000..821d988cd60
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotsp-h-fail.s
+#error_output: cv-simd-sdotsp-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-sdotsp-h-fail.l
new file mode 100644
index 00000000000..ae9b66816ae
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sdotsp.h x32,x32,x32'
+.*: Error: illegal operands `cv.sdotsp.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-sdotsp-h-fail.s
new file mode 100644
index 00000000000..304f1e4589c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.sdotsp.h x32, x32, x32
+    cv.sdotsp.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-sdotsp-h-pass.d
new file mode 100644
index 00000000000..19d7265febd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotsp-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	a800007b          	cv.sdotsp.h	zero,zero,zero
+   4:	a81080fb          	cv.sdotsp.h	ra,ra,ra
+   8:	a821017b          	cv.sdotsp.h	sp,sp,sp
+   c:	a884047b          	cv.sdotsp.h	s0,s0,s0
+  10:	a94a0a7b          	cv.sdotsp.h	s4,s4,s4
+  14:	a9ff8ffb          	cv.sdotsp.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-sdotsp-h-pass.s
new file mode 100644
index 00000000000..e2bfb3aa555
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.sdotsp.h x0, x0, x0
+    cv.sdotsp.h x1, x1, x1
+    cv.sdotsp.h x2, x2, x2
+    cv.sdotsp.h x8, x8, x8
+    cv.sdotsp.h x20, x20, x20
+    cv.sdotsp.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-b-fail.d
new file mode 100644
index 00000000000..c47123c226e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotsp-sc-b-fail.s
+#error_output: cv-simd-sdotsp-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-b-fail.l
new file mode 100644
index 00000000000..020979b381c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sdotsp.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.sdotsp.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-b-fail.s
new file mode 100644
index 00000000000..33e2ab91152
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.sdotsp.sc.b x32, x32, x32
+    cv.sdotsp.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-b-pass.d
new file mode 100644
index 00000000000..8dd43031fdd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotsp-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	a800507b          	cv.sdotsp.sc.b	zero,zero,zero
+   4:	a810d0fb          	cv.sdotsp.sc.b	ra,ra,ra
+   8:	a821517b          	cv.sdotsp.sc.b	sp,sp,sp
+   c:	a884547b          	cv.sdotsp.sc.b	s0,s0,s0
+  10:	a94a5a7b          	cv.sdotsp.sc.b	s4,s4,s4
+  14:	a9ffdffb          	cv.sdotsp.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-b-pass.s
new file mode 100644
index 00000000000..8e2c737e56f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.sdotsp.sc.b x0, x0, x0
+    cv.sdotsp.sc.b x1, x1, x1
+    cv.sdotsp.sc.b x2, x2, x2
+    cv.sdotsp.sc.b x8, x8, x8
+    cv.sdotsp.sc.b x20, x20, x20
+    cv.sdotsp.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-h-fail.d
new file mode 100644
index 00000000000..2118706c8d4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotsp-sc-h-fail.s
+#error_output: cv-simd-sdotsp-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-h-fail.l
new file mode 100644
index 00000000000..8a24210b195
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sdotsp.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.sdotsp.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-h-fail.s
new file mode 100644
index 00000000000..98ddf44256f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.sdotsp.sc.h x32, x32, x32
+    cv.sdotsp.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-h-pass.d
new file mode 100644
index 00000000000..2df11341849
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotsp-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	a800407b          	cv.sdotsp.sc.h	zero,zero,zero
+   4:	a810c0fb          	cv.sdotsp.sc.h	ra,ra,ra
+   8:	a821417b          	cv.sdotsp.sc.h	sp,sp,sp
+   c:	a884447b          	cv.sdotsp.sc.h	s0,s0,s0
+  10:	a94a4a7b          	cv.sdotsp.sc.h	s4,s4,s4
+  14:	a9ffcffb          	cv.sdotsp.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-h-pass.s
new file mode 100644
index 00000000000..a50b1ecd958
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.sdotsp.sc.h x0, x0, x0
+    cv.sdotsp.sc.h x1, x1, x1
+    cv.sdotsp.sc.h x2, x2, x2
+    cv.sdotsp.sc.h x8, x8, x8
+    cv.sdotsp.sc.h x20, x20, x20
+    cv.sdotsp.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-b-fail.d
new file mode 100644
index 00000000000..94bcf063687
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotsp-sci-b-fail.s
+#error_output: cv-simd-sdotsp-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-b-fail.l
new file mode 100644
index 00000000000..39f53beb9c3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sdotsp.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.sdotsp.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-b-fail.s
new file mode 100644
index 00000000000..31909d81531
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.sdotsp.sci.b x32, x32, 20
+    cv.sdotsp.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.sdotsp.sci.b x6, x7, -33
+    cv.sdotsp.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-b-pass.d
new file mode 100644
index 00000000000..0e51830b652
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotsp-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	a8a0707b          	cv.sdotsp.sci.b	zero,zero,20
+   4:	a8a0f0fb          	cv.sdotsp.sci.b	ra,ra,20
+   8:	a8a1717b          	cv.sdotsp.sci.b	sp,sp,20
+   c:	a8a4747b          	cv.sdotsp.sci.b	s0,s0,20
+  10:	a8aa7a7b          	cv.sdotsp.sci.b	s4,s4,20
+  14:	a8affffb          	cv.sdotsp.sci.b	t6,t6,20
+  18:	a903f37b          	cv.sdotsp.sci.b	t1,t2,-32
+  1c:	a803f37b          	cv.sdotsp.sci.b	t1,t2,0
+  20:	aaf3f37b          	cv.sdotsp.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-b-pass.s
new file mode 100644
index 00000000000..ae47ef6ca34
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-b-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.sdotsp.sci.b x0, x0, 20
+    cv.sdotsp.sci.b x1, x1, 20
+    cv.sdotsp.sci.b x2, x2, 20
+    cv.sdotsp.sci.b x8, x8, 20
+    cv.sdotsp.sci.b x20, x20, 20
+    cv.sdotsp.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.sdotsp.sci.b x6, x7, -32
+    cv.sdotsp.sci.b x6, x7, 0
+    cv.sdotsp.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-h-fail.d
new file mode 100644
index 00000000000..67509879f4c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotsp-sci-h-fail.s
+#error_output: cv-simd-sdotsp-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-h-fail.l
new file mode 100644
index 00000000000..28dda486916
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sdotsp.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.sdotsp.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-h-fail.s
new file mode 100644
index 00000000000..643aee4a38c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.sdotsp.sci.h x32, x32, 20
+    cv.sdotsp.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.sdotsp.sci.h x6, x7, -33
+    cv.sdotsp.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-h-pass.d
new file mode 100644
index 00000000000..6c7cbf53c2d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotsp-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	a8a0607b          	cv.sdotsp.sci.h	zero,zero,20
+   4:	a8a0e0fb          	cv.sdotsp.sci.h	ra,ra,20
+   8:	a8a1617b          	cv.sdotsp.sci.h	sp,sp,20
+   c:	a8a4647b          	cv.sdotsp.sci.h	s0,s0,20
+  10:	a8aa6a7b          	cv.sdotsp.sci.h	s4,s4,20
+  14:	a8afeffb          	cv.sdotsp.sci.h	t6,t6,20
+  18:	a903e37b          	cv.sdotsp.sci.h	t1,t2,-32
+  1c:	a803e37b          	cv.sdotsp.sci.h	t1,t2,0
+  20:	aaf3e37b          	cv.sdotsp.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-h-pass.s
new file mode 100644
index 00000000000..72299328f80
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotsp-sci-h-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.sdotsp.sci.h x0, x0, 20
+    cv.sdotsp.sci.h x1, x1, 20
+    cv.sdotsp.sci.h x2, x2, 20
+    cv.sdotsp.sci.h x8, x8, 20
+    cv.sdotsp.sci.h x20, x20, 20
+    cv.sdotsp.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.sdotsp.sci.h x6, x7, -32
+    cv.sdotsp.sci.h x6, x7, 0
+    cv.sdotsp.sci.h x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-sdotup-b-fail.d
new file mode 100644
index 00000000000..2a54817d10f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotup-b-fail.s
+#error_output: cv-simd-sdotup-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-sdotup-b-fail.l
new file mode 100644
index 00000000000..0230952e061
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sdotup.b x32,x32,x32'
+.*: Error: illegal operands `cv.sdotup.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-sdotup-b-fail.s
new file mode 100644
index 00000000000..7aca3c0f6d8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.sdotup.b x32, x32, x32
+    cv.sdotup.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-sdotup-b-pass.d
new file mode 100644
index 00000000000..a14a4946c93
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotup-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	9800107b          	cv.sdotup.b	zero,zero,zero
+   4:	981090fb          	cv.sdotup.b	ra,ra,ra
+   8:	9821117b          	cv.sdotup.b	sp,sp,sp
+   c:	9884147b          	cv.sdotup.b	s0,s0,s0
+  10:	994a1a7b          	cv.sdotup.b	s4,s4,s4
+  14:	99ff9ffb          	cv.sdotup.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-sdotup-b-pass.s
new file mode 100644
index 00000000000..b91d0e02d22
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.sdotup.b x0, x0, x0
+    cv.sdotup.b x1, x1, x1
+    cv.sdotup.b x2, x2, x2
+    cv.sdotup.b x8, x8, x8
+    cv.sdotup.b x20, x20, x20
+    cv.sdotup.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-sdotup-h-fail.d
new file mode 100644
index 00000000000..b40273bff97
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotup-h-fail.s
+#error_output: cv-simd-sdotup-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-sdotup-h-fail.l
new file mode 100644
index 00000000000..cb56228f18c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sdotup.h x32,x32,x32'
+.*: Error: illegal operands `cv.sdotup.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-sdotup-h-fail.s
new file mode 100644
index 00000000000..02ba76549c1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.sdotup.h x32, x32, x32
+    cv.sdotup.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-sdotup-h-pass.d
new file mode 100644
index 00000000000..31b1afe8888
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotup-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	9800007b          	cv.sdotup.h	zero,zero,zero
+   4:	981080fb          	cv.sdotup.h	ra,ra,ra
+   8:	9821017b          	cv.sdotup.h	sp,sp,sp
+   c:	9884047b          	cv.sdotup.h	s0,s0,s0
+  10:	994a0a7b          	cv.sdotup.h	s4,s4,s4
+  14:	99ff8ffb          	cv.sdotup.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-sdotup-h-pass.s
new file mode 100644
index 00000000000..5bcbb33bac2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.sdotup.h x0, x0, x0
+    cv.sdotup.h x1, x1, x1
+    cv.sdotup.h x2, x2, x2
+    cv.sdotup.h x8, x8, x8
+    cv.sdotup.h x20, x20, x20
+    cv.sdotup.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-b-fail.d
new file mode 100644
index 00000000000..631daae5343
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotup-sc-b-fail.s
+#error_output: cv-simd-sdotup-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-b-fail.l
new file mode 100644
index 00000000000..79ebb6da0ac
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sdotup.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.sdotup.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-b-fail.s
new file mode 100644
index 00000000000..8c007fc84b6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.sdotup.sc.b x32, x32, x32
+    cv.sdotup.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-b-pass.d
new file mode 100644
index 00000000000..ac08c73d9a0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotup-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	9800507b          	cv.sdotup.sc.b	zero,zero,zero
+   4:	9810d0fb          	cv.sdotup.sc.b	ra,ra,ra
+   8:	9821517b          	cv.sdotup.sc.b	sp,sp,sp
+   c:	9884547b          	cv.sdotup.sc.b	s0,s0,s0
+  10:	994a5a7b          	cv.sdotup.sc.b	s4,s4,s4
+  14:	99ffdffb          	cv.sdotup.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-b-pass.s
new file mode 100644
index 00000000000..506bc5089c6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.sdotup.sc.b x0, x0, x0
+    cv.sdotup.sc.b x1, x1, x1
+    cv.sdotup.sc.b x2, x2, x2
+    cv.sdotup.sc.b x8, x8, x8
+    cv.sdotup.sc.b x20, x20, x20
+    cv.sdotup.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-h-fail.d
new file mode 100644
index 00000000000..a9582cb71b8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotup-sc-h-fail.s
+#error_output: cv-simd-sdotup-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-h-fail.l
new file mode 100644
index 00000000000..c770ee8f30d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sdotup.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.sdotup.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-h-fail.s
new file mode 100644
index 00000000000..5e026134914
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.sdotup.sc.h x32, x32, x32
+    cv.sdotup.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-h-pass.d
new file mode 100644
index 00000000000..6514df356a5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotup-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	9800407b          	cv.sdotup.sc.h	zero,zero,zero
+   4:	9810c0fb          	cv.sdotup.sc.h	ra,ra,ra
+   8:	9821417b          	cv.sdotup.sc.h	sp,sp,sp
+   c:	9884447b          	cv.sdotup.sc.h	s0,s0,s0
+  10:	994a4a7b          	cv.sdotup.sc.h	s4,s4,s4
+  14:	99ffcffb          	cv.sdotup.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-h-pass.s
new file mode 100644
index 00000000000..5d5148c9450
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.sdotup.sc.h x0, x0, x0
+    cv.sdotup.sc.h x1, x1, x1
+    cv.sdotup.sc.h x2, x2, x2
+    cv.sdotup.sc.h x8, x8, x8
+    cv.sdotup.sc.h x20, x20, x20
+    cv.sdotup.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-b-fail.d
new file mode 100644
index 00000000000..b546567f5aa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotup-sci-b-fail.s
+#error_output: cv-simd-sdotup-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-b-fail.l
new file mode 100644
index 00000000000..961bb876c3b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sdotup.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.sdotup.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-b-fail.s
new file mode 100644
index 00000000000..10b8cf83ad7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.sdotup.sci.b x32, x32, 20
+    cv.sdotup.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.sdotup.sci.b x6, x7, -1
+    cv.sdotup.sci.b x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-b-pass.d
new file mode 100644
index 00000000000..e5e1d87ef90
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-b-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotup-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	98a0707b          	cv.sdotup.sci.b	zero,zero,20
+   4:	98a0f0fb          	cv.sdotup.sci.b	ra,ra,20
+   8:	98a1717b          	cv.sdotup.sci.b	sp,sp,20
+   c:	98a4747b          	cv.sdotup.sci.b	s0,s0,20
+  10:	98aa7a7b          	cv.sdotup.sci.b	s4,s4,20
+  14:	98affffb          	cv.sdotup.sci.b	t6,t6,20
+  18:	9803f37b          	cv.sdotup.sci.b	t1,t2,0
+  1c:	9bf3f37b          	cv.sdotup.sci.b	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-b-pass.s
new file mode 100644
index 00000000000..71c6845d331
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-b-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.sdotup.sci.b x0, x0, 20
+    cv.sdotup.sci.b x1, x1, 20
+    cv.sdotup.sci.b x2, x2, 20
+    cv.sdotup.sci.b x8, x8, 20
+    cv.sdotup.sci.b x20, x20, 20
+    cv.sdotup.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.sdotup.sci.b x6, x7, 0
+    cv.sdotup.sci.b x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-h-fail.d
new file mode 100644
index 00000000000..e215f69ae48
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotup-sci-h-fail.s
+#error_output: cv-simd-sdotup-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-h-fail.l
new file mode 100644
index 00000000000..323e89fe522
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sdotup.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.sdotup.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-h-fail.s
new file mode 100644
index 00000000000..967ab987688
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.sdotup.sci.h x32, x32, 20
+    cv.sdotup.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.sdotup.sci.h x6, x7, -1
+    cv.sdotup.sci.h x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-h-pass.d
new file mode 100644
index 00000000000..6f82a62dc66
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-h-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotup-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	98a0607b          	cv.sdotup.sci.h	zero,zero,20
+   4:	98a0e0fb          	cv.sdotup.sci.h	ra,ra,20
+   8:	98a1617b          	cv.sdotup.sci.h	sp,sp,20
+   c:	98a4647b          	cv.sdotup.sci.h	s0,s0,20
+  10:	98aa6a7b          	cv.sdotup.sci.h	s4,s4,20
+  14:	98afeffb          	cv.sdotup.sci.h	t6,t6,20
+  18:	9803e37b          	cv.sdotup.sci.h	t1,t2,0
+  1c:	9bf3e37b          	cv.sdotup.sci.h	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-h-pass.s
new file mode 100644
index 00000000000..c80cc696f78
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotup-sci-h-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.sdotup.sci.h x0, x0, 20
+    cv.sdotup.sci.h x1, x1, 20
+    cv.sdotup.sci.h x2, x2, 20
+    cv.sdotup.sci.h x8, x8, 20
+    cv.sdotup.sci.h x20, x20, 20
+    cv.sdotup.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.sdotup.sci.h x6, x7, 0
+    cv.sdotup.sci.h x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-sdotusp-b-fail.d
new file mode 100644
index 00000000000..071fb82c15a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotusp-b-fail.s
+#error_output: cv-simd-sdotusp-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-sdotusp-b-fail.l
new file mode 100644
index 00000000000..7488a3d54a6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sdotusp.b x32,x32,x32'
+.*: Error: illegal operands `cv.sdotusp.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-sdotusp-b-fail.s
new file mode 100644
index 00000000000..2202c634a26
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.sdotusp.b x32, x32, x32
+    cv.sdotusp.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-sdotusp-b-pass.d
new file mode 100644
index 00000000000..4ae36a515a8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotusp-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	a000107b          	cv.sdotusp.b	zero,zero,zero
+   4:	a01090fb          	cv.sdotusp.b	ra,ra,ra
+   8:	a021117b          	cv.sdotusp.b	sp,sp,sp
+   c:	a084147b          	cv.sdotusp.b	s0,s0,s0
+  10:	a14a1a7b          	cv.sdotusp.b	s4,s4,s4
+  14:	a1ff9ffb          	cv.sdotusp.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-sdotusp-b-pass.s
new file mode 100644
index 00000000000..6b461f1130c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.sdotusp.b x0, x0, x0
+    cv.sdotusp.b x1, x1, x1
+    cv.sdotusp.b x2, x2, x2
+    cv.sdotusp.b x8, x8, x8
+    cv.sdotusp.b x20, x20, x20
+    cv.sdotusp.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-sdotusp-h-fail.d
new file mode 100644
index 00000000000..d2951d6a703
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotusp-h-fail.s
+#error_output: cv-simd-sdotusp-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-sdotusp-h-fail.l
new file mode 100644
index 00000000000..82883936dea
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sdotusp.h x32,x32,x32'
+.*: Error: illegal operands `cv.sdotusp.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-sdotusp-h-fail.s
new file mode 100644
index 00000000000..4740b6e0adf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.sdotusp.h x32, x32, x32
+    cv.sdotusp.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-sdotusp-h-pass.d
new file mode 100644
index 00000000000..47a5bbf8c87
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotusp-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	a000007b          	cv.sdotusp.h	zero,zero,zero
+   4:	a01080fb          	cv.sdotusp.h	ra,ra,ra
+   8:	a021017b          	cv.sdotusp.h	sp,sp,sp
+   c:	a084047b          	cv.sdotusp.h	s0,s0,s0
+  10:	a14a0a7b          	cv.sdotusp.h	s4,s4,s4
+  14:	a1ff8ffb          	cv.sdotusp.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-sdotusp-h-pass.s
new file mode 100644
index 00000000000..f637546bce5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.sdotusp.h x0, x0, x0
+    cv.sdotusp.h x1, x1, x1
+    cv.sdotusp.h x2, x2, x2
+    cv.sdotusp.h x8, x8, x8
+    cv.sdotusp.h x20, x20, x20
+    cv.sdotusp.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-b-fail.d
new file mode 100644
index 00000000000..dc4a9da6b59
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotusp-sc-b-fail.s
+#error_output: cv-simd-sdotusp-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-b-fail.l
new file mode 100644
index 00000000000..0224aea1c52
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sdotusp.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.sdotusp.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-b-fail.s
new file mode 100644
index 00000000000..6a876909951
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.sdotusp.sc.b x32, x32, x32
+    cv.sdotusp.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-b-pass.d
new file mode 100644
index 00000000000..9a88454cbc4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotusp-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	a000507b          	cv.sdotusp.sc.b	zero,zero,zero
+   4:	a010d0fb          	cv.sdotusp.sc.b	ra,ra,ra
+   8:	a021517b          	cv.sdotusp.sc.b	sp,sp,sp
+   c:	a084547b          	cv.sdotusp.sc.b	s0,s0,s0
+  10:	a14a5a7b          	cv.sdotusp.sc.b	s4,s4,s4
+  14:	a1ffdffb          	cv.sdotusp.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-b-pass.s
new file mode 100644
index 00000000000..6f8f2081cc7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.sdotusp.sc.b x0, x0, x0
+    cv.sdotusp.sc.b x1, x1, x1
+    cv.sdotusp.sc.b x2, x2, x2
+    cv.sdotusp.sc.b x8, x8, x8
+    cv.sdotusp.sc.b x20, x20, x20
+    cv.sdotusp.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-h-fail.d
new file mode 100644
index 00000000000..1f88d60190d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotusp-sc-h-fail.s
+#error_output: cv-simd-sdotusp-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-h-fail.l
new file mode 100644
index 00000000000..9f55f7dc75d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sdotusp.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.sdotusp.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-h-fail.s
new file mode 100644
index 00000000000..a9a7a932113
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.sdotusp.sc.h x32, x32, x32
+    cv.sdotusp.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-h-pass.d
new file mode 100644
index 00000000000..d95de772535
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotusp-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	a000407b          	cv.sdotusp.sc.h	zero,zero,zero
+   4:	a010c0fb          	cv.sdotusp.sc.h	ra,ra,ra
+   8:	a021417b          	cv.sdotusp.sc.h	sp,sp,sp
+   c:	a084447b          	cv.sdotusp.sc.h	s0,s0,s0
+  10:	a14a4a7b          	cv.sdotusp.sc.h	s4,s4,s4
+  14:	a1ffcffb          	cv.sdotusp.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-h-pass.s
new file mode 100644
index 00000000000..52a0fefedd3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.sdotusp.sc.h x0, x0, x0
+    cv.sdotusp.sc.h x1, x1, x1
+    cv.sdotusp.sc.h x2, x2, x2
+    cv.sdotusp.sc.h x8, x8, x8
+    cv.sdotusp.sc.h x20, x20, x20
+    cv.sdotusp.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-b-fail.d
new file mode 100644
index 00000000000..6fcc866dbff
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotusp-sci-b-fail.s
+#error_output: cv-simd-sdotusp-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-b-fail.l
new file mode 100644
index 00000000000..efd927e7658
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sdotusp.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.sdotusp.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-b-fail.s
new file mode 100644
index 00000000000..35ab2fbe03d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.sdotusp.sci.b x32, x32, 20
+    cv.sdotusp.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.sdotusp.sci.b x6, x7, -33
+    cv.sdotusp.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-b-pass.d
new file mode 100644
index 00000000000..3c8d95ec868
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotusp-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	a0a0707b          	cv.sdotusp.sci.b	zero,zero,20
+   4:	a0a0f0fb          	cv.sdotusp.sci.b	ra,ra,20
+   8:	a0a1717b          	cv.sdotusp.sci.b	sp,sp,20
+   c:	a0a4747b          	cv.sdotusp.sci.b	s0,s0,20
+  10:	a0aa7a7b          	cv.sdotusp.sci.b	s4,s4,20
+  14:	a0affffb          	cv.sdotusp.sci.b	t6,t6,20
+  18:	a103f37b          	cv.sdotusp.sci.b	t1,t2,-32
+  1c:	a003f37b          	cv.sdotusp.sci.b	t1,t2,0
+  20:	a2f3f37b          	cv.sdotusp.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-b-pass.s
new file mode 100644
index 00000000000..b66e52e93ec
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-b-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.sdotusp.sci.b x0, x0, 20
+    cv.sdotusp.sci.b x1, x1, 20
+    cv.sdotusp.sci.b x2, x2, 20
+    cv.sdotusp.sci.b x8, x8, 20
+    cv.sdotusp.sci.b x20, x20, 20
+    cv.sdotusp.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.sdotusp.sci.b x6, x7, -32
+    cv.sdotusp.sci.b x6, x7, 0
+    cv.sdotusp.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-h-fail.d
new file mode 100644
index 00000000000..36d3ab6950b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotusp-sci-h-fail.s
+#error_output: cv-simd-sdotusp-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-h-fail.l
new file mode 100644
index 00000000000..abc1063c15d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sdotusp.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.sdotusp.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-h-fail.s
new file mode 100644
index 00000000000..0ac401ef3f5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.sdotusp.sci.h x32, x32, 20
+    cv.sdotusp.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.sdotusp.sci.h x6, x7, -33
+    cv.sdotusp.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-h-pass.d
new file mode 100644
index 00000000000..7b656986ff9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sdotusp-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	a0a0607b          	cv.sdotusp.sci.h	zero,zero,20
+   4:	a0a0e0fb          	cv.sdotusp.sci.h	ra,ra,20
+   8:	a0a1617b          	cv.sdotusp.sci.h	sp,sp,20
+   c:	a0a4647b          	cv.sdotusp.sci.h	s0,s0,20
+  10:	a0aa6a7b          	cv.sdotusp.sci.h	s4,s4,20
+  14:	a0afeffb          	cv.sdotusp.sci.h	t6,t6,20
+  18:	a103e37b          	cv.sdotusp.sci.h	t1,t2,-32
+  1c:	a003e37b          	cv.sdotusp.sci.h	t1,t2,0
+  20:	a2f3e37b          	cv.sdotusp.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-h-pass.s
new file mode 100644
index 00000000000..107a05f7897
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sdotusp-sci-h-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.sdotusp.sci.h x0, x0, 20
+    cv.sdotusp.sci.h x1, x1, 20
+    cv.sdotusp.sci.h x2, x2, 20
+    cv.sdotusp.sci.h x8, x8, 20
+    cv.sdotusp.sci.h x20, x20, 20
+    cv.sdotusp.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.sdotusp.sci.h x6, x7, -32
+    cv.sdotusp.sci.h x6, x7, 0
+    cv.sdotusp.sci.h x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-shuffle-b-fail.d
new file mode 100644
index 00000000000..0889cbf4826
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-shuffle-b-fail.s
+#error_output: cv-simd-shuffle-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-shuffle-b-fail.l
new file mode 100644
index 00000000000..6ccb07a2a96
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.shuffle.b x32,x32,x32'
+.*: Error: illegal operands `cv.shuffle.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-shuffle-b-fail.s
new file mode 100644
index 00000000000..502cb20bc19
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.shuffle.b x32, x32, x32
+    cv.shuffle.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-shuffle-b-pass.d
new file mode 100644
index 00000000000..f751a03bef4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-shuffle-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	c000107b          	cv.shuffle.b	zero,zero,zero
+   4:	c01090fb          	cv.shuffle.b	ra,ra,ra
+   8:	c021117b          	cv.shuffle.b	sp,sp,sp
+   c:	c084147b          	cv.shuffle.b	s0,s0,s0
+  10:	c14a1a7b          	cv.shuffle.b	s4,s4,s4
+  14:	c1ff9ffb          	cv.shuffle.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-shuffle-b-pass.s
new file mode 100644
index 00000000000..2b94bdfbbf7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.shuffle.b x0, x0, x0
+    cv.shuffle.b x1, x1, x1
+    cv.shuffle.b x2, x2, x2
+    cv.shuffle.b x8, x8, x8
+    cv.shuffle.b x20, x20, x20
+    cv.shuffle.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-shuffle-h-fail.d
new file mode 100644
index 00000000000..3c1d6268a7d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-shuffle-h-fail.s
+#error_output: cv-simd-shuffle-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-shuffle-h-fail.l
new file mode 100644
index 00000000000..28004f29675
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.shuffle.h x32,x32,x32'
+.*: Error: illegal operands `cv.shuffle.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-shuffle-h-fail.s
new file mode 100644
index 00000000000..7526f6767c2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.shuffle.h x32, x32, x32
+    cv.shuffle.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-shuffle-h-pass.d
new file mode 100644
index 00000000000..5ae168db9a4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-shuffle-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	c000007b          	cv.shuffle.h	zero,zero,zero
+   4:	c01080fb          	cv.shuffle.h	ra,ra,ra
+   8:	c021017b          	cv.shuffle.h	sp,sp,sp
+   c:	c084047b          	cv.shuffle.h	s0,s0,s0
+  10:	c14a0a7b          	cv.shuffle.h	s4,s4,s4
+  14:	c1ff8ffb          	cv.shuffle.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-shuffle-h-pass.s
new file mode 100644
index 00000000000..898d1c918b9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.shuffle.h x0, x0, x0
+    cv.shuffle.h x1, x1, x1
+    cv.shuffle.h x2, x2, x2
+    cv.shuffle.h x8, x8, x8
+    cv.shuffle.h x20, x20, x20
+    cv.shuffle.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-shuffle-sci-h-fail.d
new file mode 100644
index 00000000000..9657e9a994c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-shuffle-sci-h-fail.s
+#error_output: cv-simd-shuffle-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-shuffle-sci-h-fail.l
new file mode 100644
index 00000000000..4cb3b46692a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.shuffle.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.shuffle.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-shuffle-sci-h-fail.s
new file mode 100644
index 00000000000..b28731b53ac
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.shuffle.sci.h x32, x32, 20
+    cv.shuffle.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.shuffle.sci.h x6, x7, -1
+    cv.shuffle.sci.h x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-shuffle-sci-h-pass.d
new file mode 100644
index 00000000000..6620e0c6bb4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle-sci-h-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-shuffle-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	c0a0607b          	cv.shuffle.sci.h	zero,zero,20
+   4:	c0a0e0fb          	cv.shuffle.sci.h	ra,ra,20
+   8:	c0a1617b          	cv.shuffle.sci.h	sp,sp,20
+   c:	c0a4647b          	cv.shuffle.sci.h	s0,s0,20
+  10:	c0aa6a7b          	cv.shuffle.sci.h	s4,s4,20
+  14:	c0afeffb          	cv.shuffle.sci.h	t6,t6,20
+  18:	c003e37b          	cv.shuffle.sci.h	t1,t2,0
+  1c:	c3f3e37b          	cv.shuffle.sci.h	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-shuffle-sci-h-pass.s
new file mode 100644
index 00000000000..c71e8061584
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle-sci-h-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.shuffle.sci.h x0, x0, 20
+    cv.shuffle.sci.h x1, x1, 20
+    cv.shuffle.sci.h x2, x2, 20
+    cv.shuffle.sci.h x8, x8, 20
+    cv.shuffle.sci.h x20, x20, 20
+    cv.shuffle.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.shuffle.sci.h x6, x7, 0
+    cv.shuffle.sci.h x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle2-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-shuffle2-b-fail.d
new file mode 100644
index 00000000000..f714cf9ab2b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle2-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-shuffle2-b-fail.s
+#error_output: cv-simd-shuffle2-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle2-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-shuffle2-b-fail.l
new file mode 100644
index 00000000000..94e47f7f8c7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle2-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.shuffle2.b x32,x32,x32'
+.*: Error: illegal operands `cv.shuffle2.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle2-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-shuffle2-b-fail.s
new file mode 100644
index 00000000000..5adf9f32e66
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle2-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.shuffle2.b x32, x32, x32
+    cv.shuffle2.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle2-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-shuffle2-b-pass.d
new file mode 100644
index 00000000000..7116c7913a4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle2-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-shuffle2-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	e000107b          	cv.shuffle2.b	zero,zero,zero
+   4:	e01090fb          	cv.shuffle2.b	ra,ra,ra
+   8:	e021117b          	cv.shuffle2.b	sp,sp,sp
+   c:	e084147b          	cv.shuffle2.b	s0,s0,s0
+  10:	e14a1a7b          	cv.shuffle2.b	s4,s4,s4
+  14:	e1ff9ffb          	cv.shuffle2.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle2-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-shuffle2-b-pass.s
new file mode 100644
index 00000000000..3db4896c27f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle2-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.shuffle2.b x0, x0, x0
+    cv.shuffle2.b x1, x1, x1
+    cv.shuffle2.b x2, x2, x2
+    cv.shuffle2.b x8, x8, x8
+    cv.shuffle2.b x20, x20, x20
+    cv.shuffle2.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle2-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-shuffle2-h-fail.d
new file mode 100644
index 00000000000..e1fba2e4d3d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle2-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-shuffle2-h-fail.s
+#error_output: cv-simd-shuffle2-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle2-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-shuffle2-h-fail.l
new file mode 100644
index 00000000000..31b69598bbf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle2-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.shuffle2.h x32,x32,x32'
+.*: Error: illegal operands `cv.shuffle2.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle2-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-shuffle2-h-fail.s
new file mode 100644
index 00000000000..f233fc0ad16
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle2-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.shuffle2.h x32, x32, x32
+    cv.shuffle2.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle2-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-shuffle2-h-pass.d
new file mode 100644
index 00000000000..d4af2fd10b4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle2-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-shuffle2-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	e000007b          	cv.shuffle2.h	zero,zero,zero
+   4:	e01080fb          	cv.shuffle2.h	ra,ra,ra
+   8:	e021017b          	cv.shuffle2.h	sp,sp,sp
+   c:	e084047b          	cv.shuffle2.h	s0,s0,s0
+  10:	e14a0a7b          	cv.shuffle2.h	s4,s4,s4
+  14:	e1ff8ffb          	cv.shuffle2.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-shuffle2-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-shuffle2-h-pass.s
new file mode 100644
index 00000000000..794fb83ebc6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shuffle2-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.shuffle2.h x0, x0, x0
+    cv.shuffle2.h x1, x1, x1
+    cv.shuffle2.h x2, x2, x2
+    cv.shuffle2.h x8, x8, x8
+    cv.shuffle2.h x20, x20, x20
+    cv.shuffle2.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-shufflei0-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-shufflei0-sci-b-fail.d
new file mode 100644
index 00000000000..40cc0724237
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shufflei0-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-shufflei0-sci-b-fail.s
+#error_output: cv-simd-shufflei0-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-shufflei0-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-shufflei0-sci-b-fail.l
new file mode 100644
index 00000000000..64a0bbaee56
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shufflei0-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.shufflei0.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.shufflei0.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-shufflei0-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-shufflei0-sci-b-fail.s
new file mode 100644
index 00000000000..78aa8ea7e7e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shufflei0-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.shufflei0.sci.b x32, x32, 20
+    cv.shufflei0.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.shufflei0.sci.b x6, x7, -1
+    cv.shufflei0.sci.b x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-shufflei0-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-shufflei0-sci-b-pass.d
new file mode 100644
index 00000000000..9bf3b044749
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shufflei0-sci-b-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-shufflei0-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	c0a0707b          	cv.shufflei0.sci.b	zero,zero,20
+   4:	c0a0f0fb          	cv.shufflei0.sci.b	ra,ra,20
+   8:	c0a1717b          	cv.shufflei0.sci.b	sp,sp,20
+   c:	c0a4747b          	cv.shufflei0.sci.b	s0,s0,20
+  10:	c0aa7a7b          	cv.shufflei0.sci.b	s4,s4,20
+  14:	c0affffb          	cv.shufflei0.sci.b	t6,t6,20
+  18:	c003f37b          	cv.shufflei0.sci.b	t1,t2,0
+  1c:	c3f3f37b          	cv.shufflei0.sci.b	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-shufflei0-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-shufflei0-sci-b-pass.s
new file mode 100644
index 00000000000..d40c845d766
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shufflei0-sci-b-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.shufflei0.sci.b x0, x0, 20
+    cv.shufflei0.sci.b x1, x1, 20
+    cv.shufflei0.sci.b x2, x2, 20
+    cv.shufflei0.sci.b x8, x8, 20
+    cv.shufflei0.sci.b x20, x20, 20
+    cv.shufflei0.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.shufflei0.sci.b x6, x7, 0
+    cv.shufflei0.sci.b x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-shufflei1-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-shufflei1-sci-b-fail.d
new file mode 100644
index 00000000000..4dba182f72c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shufflei1-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-shufflei1-sci-b-fail.s
+#error_output: cv-simd-shufflei1-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-shufflei1-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-shufflei1-sci-b-fail.l
new file mode 100644
index 00000000000..a77e4235c78
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shufflei1-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.shufflei1.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.shufflei1.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-shufflei1-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-shufflei1-sci-b-fail.s
new file mode 100644
index 00000000000..558484f4318
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shufflei1-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.shufflei1.sci.b x32, x32, 20
+    cv.shufflei1.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.shufflei1.sci.b x6, x7, -1
+    cv.shufflei1.sci.b x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-shufflei1-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-shufflei1-sci-b-pass.d
new file mode 100644
index 00000000000..bbc75744400
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shufflei1-sci-b-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-shufflei1-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	c8a0707b          	cv.shufflei1.sci.b	zero,zero,20
+   4:	c8a0f0fb          	cv.shufflei1.sci.b	ra,ra,20
+   8:	c8a1717b          	cv.shufflei1.sci.b	sp,sp,20
+   c:	c8a4747b          	cv.shufflei1.sci.b	s0,s0,20
+  10:	c8aa7a7b          	cv.shufflei1.sci.b	s4,s4,20
+  14:	c8affffb          	cv.shufflei1.sci.b	t6,t6,20
+  18:	c803f37b          	cv.shufflei1.sci.b	t1,t2,0
+  1c:	cbf3f37b          	cv.shufflei1.sci.b	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-shufflei1-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-shufflei1-sci-b-pass.s
new file mode 100644
index 00000000000..379693b67c6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shufflei1-sci-b-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.shufflei1.sci.b x0, x0, 20
+    cv.shufflei1.sci.b x1, x1, 20
+    cv.shufflei1.sci.b x2, x2, 20
+    cv.shufflei1.sci.b x8, x8, 20
+    cv.shufflei1.sci.b x20, x20, 20
+    cv.shufflei1.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.shufflei1.sci.b x6, x7, 0
+    cv.shufflei1.sci.b x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-shufflei2-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-shufflei2-sci-b-fail.d
new file mode 100644
index 00000000000..1113d60d073
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shufflei2-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-shufflei2-sci-b-fail.s
+#error_output: cv-simd-shufflei2-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-shufflei2-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-shufflei2-sci-b-fail.l
new file mode 100644
index 00000000000..c136de86700
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shufflei2-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.shufflei2.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.shufflei2.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-shufflei2-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-shufflei2-sci-b-fail.s
new file mode 100644
index 00000000000..565b0c599d5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shufflei2-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.shufflei2.sci.b x32, x32, 20
+    cv.shufflei2.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.shufflei2.sci.b x6, x7, -1
+    cv.shufflei2.sci.b x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-shufflei2-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-shufflei2-sci-b-pass.d
new file mode 100644
index 00000000000..0ec56cfa0ca
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shufflei2-sci-b-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-shufflei2-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	d0a0707b          	cv.shufflei2.sci.b	zero,zero,20
+   4:	d0a0f0fb          	cv.shufflei2.sci.b	ra,ra,20
+   8:	d0a1717b          	cv.shufflei2.sci.b	sp,sp,20
+   c:	d0a4747b          	cv.shufflei2.sci.b	s0,s0,20
+  10:	d0aa7a7b          	cv.shufflei2.sci.b	s4,s4,20
+  14:	d0affffb          	cv.shufflei2.sci.b	t6,t6,20
+  18:	d003f37b          	cv.shufflei2.sci.b	t1,t2,0
+  1c:	d3f3f37b          	cv.shufflei2.sci.b	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-shufflei2-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-shufflei2-sci-b-pass.s
new file mode 100644
index 00000000000..c0baa2609d8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shufflei2-sci-b-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.shufflei2.sci.b x0, x0, 20
+    cv.shufflei2.sci.b x1, x1, 20
+    cv.shufflei2.sci.b x2, x2, 20
+    cv.shufflei2.sci.b x8, x8, 20
+    cv.shufflei2.sci.b x20, x20, 20
+    cv.shufflei2.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.shufflei2.sci.b x6, x7, 0
+    cv.shufflei2.sci.b x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-shufflei3-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-shufflei3-sci-b-fail.d
new file mode 100644
index 00000000000..eb783f4d831
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shufflei3-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-shufflei3-sci-b-fail.s
+#error_output: cv-simd-shufflei3-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-shufflei3-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-shufflei3-sci-b-fail.l
new file mode 100644
index 00000000000..41cadc70ed6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shufflei3-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.shufflei3.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.shufflei3.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-shufflei3-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-shufflei3-sci-b-fail.s
new file mode 100644
index 00000000000..43bfefb1cf8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shufflei3-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.shufflei3.sci.b x32, x32, 20
+    cv.shufflei3.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.shufflei3.sci.b x6, x7, -1
+    cv.shufflei3.sci.b x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-shufflei3-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-shufflei3-sci-b-pass.d
new file mode 100644
index 00000000000..ef9d3018f34
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shufflei3-sci-b-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-shufflei3-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	d8a0707b          	cv.shufflei3.sci.b	zero,zero,20
+   4:	d8a0f0fb          	cv.shufflei3.sci.b	ra,ra,20
+   8:	d8a1717b          	cv.shufflei3.sci.b	sp,sp,20
+   c:	d8a4747b          	cv.shufflei3.sci.b	s0,s0,20
+  10:	d8aa7a7b          	cv.shufflei3.sci.b	s4,s4,20
+  14:	d8affffb          	cv.shufflei3.sci.b	t6,t6,20
+  18:	d803f37b          	cv.shufflei3.sci.b	t1,t2,0
+  1c:	dbf3f37b          	cv.shufflei3.sci.b	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-shufflei3-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-shufflei3-sci-b-pass.s
new file mode 100644
index 00000000000..b320d1a2c52
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-shufflei3-sci-b-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.shufflei3.sci.b x0, x0, 20
+    cv.shufflei3.sci.b x1, x1, 20
+    cv.shufflei3.sci.b x2, x2, 20
+    cv.shufflei3.sci.b x8, x8, 20
+    cv.shufflei3.sci.b x20, x20, 20
+    cv.shufflei3.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.shufflei3.sci.b x6, x7, 0
+    cv.shufflei3.sci.b x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-sll-b-fail.d
new file mode 100644
index 00000000000..77dec2bbf74
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sll-b-fail.s
+#error_output: cv-simd-sll-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-sll-b-fail.l
new file mode 100644
index 00000000000..4bf8b2b1f97
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sll.b x32,x32,x32'
+.*: Error: illegal operands `cv.sll.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-sll-b-fail.s
new file mode 100644
index 00000000000..3af9d4fb436
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.sll.b x32, x32, x32
+    cv.sll.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-sll-b-pass.d
new file mode 100644
index 00000000000..0896652ce8d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sll-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	5000107b          	cv.sll.b	zero,zero,zero
+   4:	501090fb          	cv.sll.b	ra,ra,ra
+   8:	5021117b          	cv.sll.b	sp,sp,sp
+   c:	5084147b          	cv.sll.b	s0,s0,s0
+  10:	514a1a7b          	cv.sll.b	s4,s4,s4
+  14:	51ff9ffb          	cv.sll.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-sll-b-pass.s
new file mode 100644
index 00000000000..2f39d96332a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.sll.b x0, x0, x0
+    cv.sll.b x1, x1, x1
+    cv.sll.b x2, x2, x2
+    cv.sll.b x8, x8, x8
+    cv.sll.b x20, x20, x20
+    cv.sll.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-sll-h-fail.d
new file mode 100644
index 00000000000..79f1bfdf4e6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sll-h-fail.s
+#error_output: cv-simd-sll-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-sll-h-fail.l
new file mode 100644
index 00000000000..3ea79744e4f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sll.h x32,x32,x32'
+.*: Error: illegal operands `cv.sll.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-sll-h-fail.s
new file mode 100644
index 00000000000..b3994452649
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.sll.h x32, x32, x32
+    cv.sll.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-sll-h-pass.d
new file mode 100644
index 00000000000..c9f21b61afe
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sll-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	5000007b          	cv.sll.h	zero,zero,zero
+   4:	501080fb          	cv.sll.h	ra,ra,ra
+   8:	5021017b          	cv.sll.h	sp,sp,sp
+   c:	5084047b          	cv.sll.h	s0,s0,s0
+  10:	514a0a7b          	cv.sll.h	s4,s4,s4
+  14:	51ff8ffb          	cv.sll.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-sll-h-pass.s
new file mode 100644
index 00000000000..d352da86ef5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.sll.h x0, x0, x0
+    cv.sll.h x1, x1, x1
+    cv.sll.h x2, x2, x2
+    cv.sll.h x8, x8, x8
+    cv.sll.h x20, x20, x20
+    cv.sll.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-sll-sc-b-fail.d
new file mode 100644
index 00000000000..f03efb96d60
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sll-sc-b-fail.s
+#error_output: cv-simd-sll-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-sll-sc-b-fail.l
new file mode 100644
index 00000000000..ce3d6df659a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sll.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.sll.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-sll-sc-b-fail.s
new file mode 100644
index 00000000000..d67c1f8a708
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.sll.sc.b x32, x32, x32
+    cv.sll.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-sll-sc-b-pass.d
new file mode 100644
index 00000000000..0ac1111df99
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sll-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	5000507b          	cv.sll.sc.b	zero,zero,zero
+   4:	5010d0fb          	cv.sll.sc.b	ra,ra,ra
+   8:	5021517b          	cv.sll.sc.b	sp,sp,sp
+   c:	5084547b          	cv.sll.sc.b	s0,s0,s0
+  10:	514a5a7b          	cv.sll.sc.b	s4,s4,s4
+  14:	51ffdffb          	cv.sll.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-sll-sc-b-pass.s
new file mode 100644
index 00000000000..0555a81bb22
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.sll.sc.b x0, x0, x0
+    cv.sll.sc.b x1, x1, x1
+    cv.sll.sc.b x2, x2, x2
+    cv.sll.sc.b x8, x8, x8
+    cv.sll.sc.b x20, x20, x20
+    cv.sll.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-sll-sc-h-fail.d
new file mode 100644
index 00000000000..73447182489
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sll-sc-h-fail.s
+#error_output: cv-simd-sll-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-sll-sc-h-fail.l
new file mode 100644
index 00000000000..320fa74ec56
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sll.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.sll.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-sll-sc-h-fail.s
new file mode 100644
index 00000000000..3b85647483f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.sll.sc.h x32, x32, x32
+    cv.sll.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-sll-sc-h-pass.d
new file mode 100644
index 00000000000..37d4d74cdeb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sll-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	5000407b          	cv.sll.sc.h	zero,zero,zero
+   4:	5010c0fb          	cv.sll.sc.h	ra,ra,ra
+   8:	5021417b          	cv.sll.sc.h	sp,sp,sp
+   c:	5084447b          	cv.sll.sc.h	s0,s0,s0
+  10:	514a4a7b          	cv.sll.sc.h	s4,s4,s4
+  14:	51ffcffb          	cv.sll.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-sll-sc-h-pass.s
new file mode 100644
index 00000000000..79f5894ccf4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.sll.sc.h x0, x0, x0
+    cv.sll.sc.h x1, x1, x1
+    cv.sll.sc.h x2, x2, x2
+    cv.sll.sc.h x8, x8, x8
+    cv.sll.sc.h x20, x20, x20
+    cv.sll.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-sll-sci-b-fail.d
new file mode 100644
index 00000000000..fe54c3062b0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sll-sci-b-fail.s
+#error_output: cv-simd-sll-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-sll-sci-b-fail.l
new file mode 100644
index 00000000000..b262ddf0b81
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sll.sci.b x32,x32,4'
+.*: Error: illegal operands `cv.sll.sci.b x33,x33,4'
+.*: Error: immediate value must be 3-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 3-bit unsigned, 8 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-sll-sci-b-fail.s
new file mode 100644
index 00000000000..5072be7045c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.sll.sci.b x32, x32, 4
+    cv.sll.sci.b x33, x33, 4
+    #Boundary Immediate Values Test
+    cv.sll.sci.b x6, x7, -1
+    cv.sll.sci.b x6, x7, 8
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-sll-sci-b-pass.d
new file mode 100644
index 00000000000..5a7a250d26f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-sci-b-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sll-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	5020707b          	cv.sll.sci.b	zero,zero,4
+   4:	5020f0fb          	cv.sll.sci.b	ra,ra,4
+   8:	5021717b          	cv.sll.sci.b	sp,sp,4
+   c:	5024747b          	cv.sll.sci.b	s0,s0,4
+  10:	502a7a7b          	cv.sll.sci.b	s4,s4,4
+  14:	502ffffb          	cv.sll.sci.b	t6,t6,4
+  18:	5003f37b          	cv.sll.sci.b	t1,t2,0
+  1c:	5233f37b          	cv.sll.sci.b	t1,t2,7
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-sll-sci-b-pass.s
new file mode 100644
index 00000000000..2a44a0f9ab5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-sci-b-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.sll.sci.b x0, x0, 4
+    cv.sll.sci.b x1, x1, 4
+    cv.sll.sci.b x2, x2, 4
+    cv.sll.sci.b x8, x8, 4
+    cv.sll.sci.b x20, x20, 4
+    cv.sll.sci.b x31, x31, 4
+    #Immediate Values Test
+    cv.sll.sci.b x6, x7, 0
+    cv.sll.sci.b x6, x7, 7
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-sll-sci-h-fail.d
new file mode 100644
index 00000000000..0bc189f2c89
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sll-sci-h-fail.s
+#error_output: cv-simd-sll-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-sll-sci-h-fail.l
new file mode 100644
index 00000000000..98eab6ec8d3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sll.sci.h x32,x32,12'
+.*: Error: illegal operands `cv.sll.sci.h x33,x33,12'
+.*: Error: immediate value must be 4-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 4-bit unsigned, 16 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-sll-sci-h-fail.s
new file mode 100644
index 00000000000..a0e2efb5c20
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.sll.sci.h x32, x32, 12
+    cv.sll.sci.h x33, x33, 12
+    #Boundary Immediate Values Test
+    cv.sll.sci.h x6, x7, -1
+    cv.sll.sci.h x6, x7, 16
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-sll-sci-h-pass.d
new file mode 100644
index 00000000000..ca477571cca
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-sci-h-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sll-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	5060607b          	cv.sll.sci.h	zero,zero,12
+   4:	5060e0fb          	cv.sll.sci.h	ra,ra,12
+   8:	5061617b          	cv.sll.sci.h	sp,sp,12
+   c:	5064647b          	cv.sll.sci.h	s0,s0,12
+  10:	506a6a7b          	cv.sll.sci.h	s4,s4,12
+  14:	506feffb          	cv.sll.sci.h	t6,t6,12
+  18:	5003e37b          	cv.sll.sci.h	t1,t2,0
+  1c:	5273e37b          	cv.sll.sci.h	t1,t2,15
diff --git a/gas/testsuite/gas/riscv/cv-simd-sll-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-sll-sci-h-pass.s
new file mode 100644
index 00000000000..975ec3e41ac
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sll-sci-h-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.sll.sci.h x0, x0, 12
+    cv.sll.sci.h x1, x1, 12
+    cv.sll.sci.h x2, x2, 12
+    cv.sll.sci.h x8, x8, 12
+    cv.sll.sci.h x20, x20, 12
+    cv.sll.sci.h x31, x31, 12
+    #Immediate Values Test
+    cv.sll.sci.h x6, x7, 0
+    cv.sll.sci.h x6, x7, 15
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-sra-b-fail.d
new file mode 100644
index 00000000000..43ea15bf717
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sra-b-fail.s
+#error_output: cv-simd-sra-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-sra-b-fail.l
new file mode 100644
index 00000000000..e6d5a094539
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sra.b x32,x32,x32'
+.*: Error: illegal operands `cv.sra.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-sra-b-fail.s
new file mode 100644
index 00000000000..13420a236d4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.sra.b x32, x32, x32
+    cv.sra.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-sra-b-pass.d
new file mode 100644
index 00000000000..76522b8e892
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sra-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4800107b          	cv.sra.b	zero,zero,zero
+   4:	481090fb          	cv.sra.b	ra,ra,ra
+   8:	4821117b          	cv.sra.b	sp,sp,sp
+   c:	4884147b          	cv.sra.b	s0,s0,s0
+  10:	494a1a7b          	cv.sra.b	s4,s4,s4
+  14:	49ff9ffb          	cv.sra.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-sra-b-pass.s
new file mode 100644
index 00000000000..854a6411b32
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.sra.b x0, x0, x0
+    cv.sra.b x1, x1, x1
+    cv.sra.b x2, x2, x2
+    cv.sra.b x8, x8, x8
+    cv.sra.b x20, x20, x20
+    cv.sra.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-sra-h-fail.d
new file mode 100644
index 00000000000..ddda6efdcdd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sra-h-fail.s
+#error_output: cv-simd-sra-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-sra-h-fail.l
new file mode 100644
index 00000000000..ddf7b46acb0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sra.h x32,x32,x32'
+.*: Error: illegal operands `cv.sra.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-sra-h-fail.s
new file mode 100644
index 00000000000..d08278de466
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.sra.h x32, x32, x32
+    cv.sra.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-sra-h-pass.d
new file mode 100644
index 00000000000..b7eab0a980c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sra-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4800007b          	cv.sra.h	zero,zero,zero
+   4:	481080fb          	cv.sra.h	ra,ra,ra
+   8:	4821017b          	cv.sra.h	sp,sp,sp
+   c:	4884047b          	cv.sra.h	s0,s0,s0
+  10:	494a0a7b          	cv.sra.h	s4,s4,s4
+  14:	49ff8ffb          	cv.sra.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-sra-h-pass.s
new file mode 100644
index 00000000000..f71c72977b4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.sra.h x0, x0, x0
+    cv.sra.h x1, x1, x1
+    cv.sra.h x2, x2, x2
+    cv.sra.h x8, x8, x8
+    cv.sra.h x20, x20, x20
+    cv.sra.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-sra-sc-b-fail.d
new file mode 100644
index 00000000000..1a26f3fac35
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sra-sc-b-fail.s
+#error_output: cv-simd-sra-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-sra-sc-b-fail.l
new file mode 100644
index 00000000000..72df02d3a2d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sra.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.sra.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-sra-sc-b-fail.s
new file mode 100644
index 00000000000..dac3ee65159
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.sra.sc.b x32, x32, x32
+    cv.sra.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-sra-sc-b-pass.d
new file mode 100644
index 00000000000..23bd8eea69f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sra-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4800507b          	cv.sra.sc.b	zero,zero,zero
+   4:	4810d0fb          	cv.sra.sc.b	ra,ra,ra
+   8:	4821517b          	cv.sra.sc.b	sp,sp,sp
+   c:	4884547b          	cv.sra.sc.b	s0,s0,s0
+  10:	494a5a7b          	cv.sra.sc.b	s4,s4,s4
+  14:	49ffdffb          	cv.sra.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-sra-sc-b-pass.s
new file mode 100644
index 00000000000..c2e68edf304
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.sra.sc.b x0, x0, x0
+    cv.sra.sc.b x1, x1, x1
+    cv.sra.sc.b x2, x2, x2
+    cv.sra.sc.b x8, x8, x8
+    cv.sra.sc.b x20, x20, x20
+    cv.sra.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-sra-sc-h-fail.d
new file mode 100644
index 00000000000..7583498c1f4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sra-sc-h-fail.s
+#error_output: cv-simd-sra-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-sra-sc-h-fail.l
new file mode 100644
index 00000000000..68eef579272
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sra.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.sra.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-sra-sc-h-fail.s
new file mode 100644
index 00000000000..5a9221ba04d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.sra.sc.h x32, x32, x32
+    cv.sra.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-sra-sc-h-pass.d
new file mode 100644
index 00000000000..5617de5e462
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sra-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4800407b          	cv.sra.sc.h	zero,zero,zero
+   4:	4810c0fb          	cv.sra.sc.h	ra,ra,ra
+   8:	4821417b          	cv.sra.sc.h	sp,sp,sp
+   c:	4884447b          	cv.sra.sc.h	s0,s0,s0
+  10:	494a4a7b          	cv.sra.sc.h	s4,s4,s4
+  14:	49ffcffb          	cv.sra.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-sra-sc-h-pass.s
new file mode 100644
index 00000000000..2a370fd307a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.sra.sc.h x0, x0, x0
+    cv.sra.sc.h x1, x1, x1
+    cv.sra.sc.h x2, x2, x2
+    cv.sra.sc.h x8, x8, x8
+    cv.sra.sc.h x20, x20, x20
+    cv.sra.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-sra-sci-b-fail.d
new file mode 100644
index 00000000000..23a5e75ca59
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sra-sci-b-fail.s
+#error_output: cv-simd-sra-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-sra-sci-b-fail.l
new file mode 100644
index 00000000000..f49e9e1867d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sra.sci.b x32,x32,4'
+.*: Error: illegal operands `cv.sra.sci.b x33,x33,4'
+.*: Error: immediate value must be 3-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 3-bit unsigned, 8 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-sra-sci-b-fail.s
new file mode 100644
index 00000000000..4285e3778e3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.sra.sci.b x32, x32, 4
+    cv.sra.sci.b x33, x33, 4
+    #Boundary Immediate Values Test
+    cv.sra.sci.b x6, x7, -1
+    cv.sra.sci.b x6, x7, 8
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-sra-sci-b-pass.d
new file mode 100644
index 00000000000..e5ddc8f530d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-sci-b-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sra-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4820707b          	cv.sra.sci.b	zero,zero,4
+   4:	4820f0fb          	cv.sra.sci.b	ra,ra,4
+   8:	4821717b          	cv.sra.sci.b	sp,sp,4
+   c:	4824747b          	cv.sra.sci.b	s0,s0,4
+  10:	482a7a7b          	cv.sra.sci.b	s4,s4,4
+  14:	482ffffb          	cv.sra.sci.b	t6,t6,4
+  18:	4803f37b          	cv.sra.sci.b	t1,t2,0
+  1c:	4a33f37b          	cv.sra.sci.b	t1,t2,7
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-sra-sci-b-pass.s
new file mode 100644
index 00000000000..cd34936b289
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-sci-b-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.sra.sci.b x0, x0, 4
+    cv.sra.sci.b x1, x1, 4
+    cv.sra.sci.b x2, x2, 4
+    cv.sra.sci.b x8, x8, 4
+    cv.sra.sci.b x20, x20, 4
+    cv.sra.sci.b x31, x31, 4
+    #Immediate Values Test
+    cv.sra.sci.b x6, x7, 0
+    cv.sra.sci.b x6, x7, 7
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-sra-sci-h-fail.d
new file mode 100644
index 00000000000..de26bbf183c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sra-sci-h-fail.s
+#error_output: cv-simd-sra-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-sra-sci-h-fail.l
new file mode 100644
index 00000000000..cab4c6f3369
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sra.sci.h x32,x32,12'
+.*: Error: illegal operands `cv.sra.sci.h x33,x33,12'
+.*: Error: immediate value must be 4-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 4-bit unsigned, 16 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-sra-sci-h-fail.s
new file mode 100644
index 00000000000..66957489d2f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.sra.sci.h x32, x32, 12
+    cv.sra.sci.h x33, x33, 12
+    #Boundary Immediate Values Test
+    cv.sra.sci.h x6, x7, -1
+    cv.sra.sci.h x6, x7, 16
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-sra-sci-h-pass.d
new file mode 100644
index 00000000000..f182758d768
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-sci-h-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sra-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4860607b          	cv.sra.sci.h	zero,zero,12
+   4:	4860e0fb          	cv.sra.sci.h	ra,ra,12
+   8:	4861617b          	cv.sra.sci.h	sp,sp,12
+   c:	4864647b          	cv.sra.sci.h	s0,s0,12
+  10:	486a6a7b          	cv.sra.sci.h	s4,s4,12
+  14:	486feffb          	cv.sra.sci.h	t6,t6,12
+  18:	4803e37b          	cv.sra.sci.h	t1,t2,0
+  1c:	4a73e37b          	cv.sra.sci.h	t1,t2,15
diff --git a/gas/testsuite/gas/riscv/cv-simd-sra-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-sra-sci-h-pass.s
new file mode 100644
index 00000000000..c59396b2760
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sra-sci-h-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.sra.sci.h x0, x0, 12
+    cv.sra.sci.h x1, x1, 12
+    cv.sra.sci.h x2, x2, 12
+    cv.sra.sci.h x8, x8, 12
+    cv.sra.sci.h x20, x20, 12
+    cv.sra.sci.h x31, x31, 12
+    #Immediate Values Test
+    cv.sra.sci.h x6, x7, 0
+    cv.sra.sci.h x6, x7, 15
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-srl-b-fail.d
new file mode 100644
index 00000000000..a28f67f7d30
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-srl-b-fail.s
+#error_output: cv-simd-srl-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-srl-b-fail.l
new file mode 100644
index 00000000000..2e8ea987dac
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.srl.b x32,x32,x32'
+.*: Error: illegal operands `cv.srl.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-srl-b-fail.s
new file mode 100644
index 00000000000..ea84d2ad24c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.srl.b x32, x32, x32
+    cv.srl.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-srl-b-pass.d
new file mode 100644
index 00000000000..e40562f3f66
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-srl-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4000107b          	cv.srl.b	zero,zero,zero
+   4:	401090fb          	cv.srl.b	ra,ra,ra
+   8:	4021117b          	cv.srl.b	sp,sp,sp
+   c:	4084147b          	cv.srl.b	s0,s0,s0
+  10:	414a1a7b          	cv.srl.b	s4,s4,s4
+  14:	41ff9ffb          	cv.srl.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-srl-b-pass.s
new file mode 100644
index 00000000000..a0dcde82d0d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.srl.b x0, x0, x0
+    cv.srl.b x1, x1, x1
+    cv.srl.b x2, x2, x2
+    cv.srl.b x8, x8, x8
+    cv.srl.b x20, x20, x20
+    cv.srl.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-srl-h-fail.d
new file mode 100644
index 00000000000..932568b5f3e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-srl-h-fail.s
+#error_output: cv-simd-srl-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-srl-h-fail.l
new file mode 100644
index 00000000000..427b72b5219
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.srl.h x32,x32,x32'
+.*: Error: illegal operands `cv.srl.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-srl-h-fail.s
new file mode 100644
index 00000000000..8ed38d0e5ef
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.srl.h x32, x32, x32
+    cv.srl.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-srl-h-pass.d
new file mode 100644
index 00000000000..24dde446e7c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-srl-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4000007b          	cv.srl.h	zero,zero,zero
+   4:	401080fb          	cv.srl.h	ra,ra,ra
+   8:	4021017b          	cv.srl.h	sp,sp,sp
+   c:	4084047b          	cv.srl.h	s0,s0,s0
+  10:	414a0a7b          	cv.srl.h	s4,s4,s4
+  14:	41ff8ffb          	cv.srl.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-srl-h-pass.s
new file mode 100644
index 00000000000..b699443d211
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.srl.h x0, x0, x0
+    cv.srl.h x1, x1, x1
+    cv.srl.h x2, x2, x2
+    cv.srl.h x8, x8, x8
+    cv.srl.h x20, x20, x20
+    cv.srl.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-srl-sc-b-fail.d
new file mode 100644
index 00000000000..84a93573f39
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-srl-sc-b-fail.s
+#error_output: cv-simd-srl-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-srl-sc-b-fail.l
new file mode 100644
index 00000000000..48f43ede7bc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.srl.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.srl.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-srl-sc-b-fail.s
new file mode 100644
index 00000000000..99cc20de497
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.srl.sc.b x32, x32, x32
+    cv.srl.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-srl-sc-b-pass.d
new file mode 100644
index 00000000000..a8e07f3ab86
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-srl-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4000507b          	cv.srl.sc.b	zero,zero,zero
+   4:	4010d0fb          	cv.srl.sc.b	ra,ra,ra
+   8:	4021517b          	cv.srl.sc.b	sp,sp,sp
+   c:	4084547b          	cv.srl.sc.b	s0,s0,s0
+  10:	414a5a7b          	cv.srl.sc.b	s4,s4,s4
+  14:	41ffdffb          	cv.srl.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-srl-sc-b-pass.s
new file mode 100644
index 00000000000..3e82412e323
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.srl.sc.b x0, x0, x0
+    cv.srl.sc.b x1, x1, x1
+    cv.srl.sc.b x2, x2, x2
+    cv.srl.sc.b x8, x8, x8
+    cv.srl.sc.b x20, x20, x20
+    cv.srl.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-srl-sc-h-fail.d
new file mode 100644
index 00000000000..d7477a206e4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-srl-sc-h-fail.s
+#error_output: cv-simd-srl-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-srl-sc-h-fail.l
new file mode 100644
index 00000000000..721754b3854
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.srl.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.srl.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-srl-sc-h-fail.s
new file mode 100644
index 00000000000..2e82f4f2bb7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.srl.sc.h x32, x32, x32
+    cv.srl.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-srl-sc-h-pass.d
new file mode 100644
index 00000000000..4b986e2a873
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-srl-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4000407b          	cv.srl.sc.h	zero,zero,zero
+   4:	4010c0fb          	cv.srl.sc.h	ra,ra,ra
+   8:	4021417b          	cv.srl.sc.h	sp,sp,sp
+   c:	4084447b          	cv.srl.sc.h	s0,s0,s0
+  10:	414a4a7b          	cv.srl.sc.h	s4,s4,s4
+  14:	41ffcffb          	cv.srl.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-srl-sc-h-pass.s
new file mode 100644
index 00000000000..0369498379c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.srl.sc.h x0, x0, x0
+    cv.srl.sc.h x1, x1, x1
+    cv.srl.sc.h x2, x2, x2
+    cv.srl.sc.h x8, x8, x8
+    cv.srl.sc.h x20, x20, x20
+    cv.srl.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-srl-sci-b-fail.d
new file mode 100644
index 00000000000..f1189136da3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-srl-sci-b-fail.s
+#error_output: cv-simd-srl-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-srl-sci-b-fail.l
new file mode 100644
index 00000000000..f7401636a8d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.srl.sci.b x32,x32,4'
+.*: Error: illegal operands `cv.srl.sci.b x33,x33,4'
+.*: Error: immediate value must be 3-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 3-bit unsigned, 8 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-srl-sci-b-fail.s
new file mode 100644
index 00000000000..1d938e776c8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.srl.sci.b x32, x32, 4
+    cv.srl.sci.b x33, x33, 4
+    #Boundary Immediate Values Test
+    cv.srl.sci.b x6, x7, -1
+    cv.srl.sci.b x6, x7, 8
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-srl-sci-b-pass.d
new file mode 100644
index 00000000000..c6bffc59aa7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-sci-b-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-srl-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4020707b          	cv.srl.sci.b	zero,zero,4
+   4:	4020f0fb          	cv.srl.sci.b	ra,ra,4
+   8:	4021717b          	cv.srl.sci.b	sp,sp,4
+   c:	4024747b          	cv.srl.sci.b	s0,s0,4
+  10:	402a7a7b          	cv.srl.sci.b	s4,s4,4
+  14:	402ffffb          	cv.srl.sci.b	t6,t6,4
+  18:	4003f37b          	cv.srl.sci.b	t1,t2,0
+  1c:	4233f37b          	cv.srl.sci.b	t1,t2,7
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-srl-sci-b-pass.s
new file mode 100644
index 00000000000..9012a9e151c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-sci-b-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.srl.sci.b x0, x0, 4
+    cv.srl.sci.b x1, x1, 4
+    cv.srl.sci.b x2, x2, 4
+    cv.srl.sci.b x8, x8, 4
+    cv.srl.sci.b x20, x20, 4
+    cv.srl.sci.b x31, x31, 4
+    #Immediate Values Test
+    cv.srl.sci.b x6, x7, 0
+    cv.srl.sci.b x6, x7, 7
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-srl-sci-h-fail.d
new file mode 100644
index 00000000000..fbbeae20041
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-srl-sci-h-fail.s
+#error_output: cv-simd-srl-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-srl-sci-h-fail.l
new file mode 100644
index 00000000000..4ad84725786
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.srl.sci.h x32,x32,12'
+.*: Error: illegal operands `cv.srl.sci.h x33,x33,12'
+.*: Error: immediate value must be 4-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 4-bit unsigned, 16 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-srl-sci-h-fail.s
new file mode 100644
index 00000000000..debd2880a84
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.srl.sci.h x32, x32, 12
+    cv.srl.sci.h x33, x33, 12
+    #Boundary Immediate Values Test
+    cv.srl.sci.h x6, x7, -1
+    cv.srl.sci.h x6, x7, 16
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-srl-sci-h-pass.d
new file mode 100644
index 00000000000..1a85023870a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-sci-h-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-srl-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4060607b          	cv.srl.sci.h	zero,zero,12
+   4:	4060e0fb          	cv.srl.sci.h	ra,ra,12
+   8:	4061617b          	cv.srl.sci.h	sp,sp,12
+   c:	4064647b          	cv.srl.sci.h	s0,s0,12
+  10:	406a6a7b          	cv.srl.sci.h	s4,s4,12
+  14:	406feffb          	cv.srl.sci.h	t6,t6,12
+  18:	4003e37b          	cv.srl.sci.h	t1,t2,0
+  1c:	4273e37b          	cv.srl.sci.h	t1,t2,15
diff --git a/gas/testsuite/gas/riscv/cv-simd-srl-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-srl-sci-h-pass.s
new file mode 100644
index 00000000000..8376745954e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-srl-sci-h-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.srl.sci.h x0, x0, 12
+    cv.srl.sci.h x1, x1, 12
+    cv.srl.sci.h x2, x2, 12
+    cv.srl.sci.h x8, x8, 12
+    cv.srl.sci.h x20, x20, 12
+    cv.srl.sci.h x31, x31, 12
+    #Immediate Values Test
+    cv.srl.sci.h x6, x7, 0
+    cv.srl.sci.h x6, x7, 15
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-sub-b-fail.d
new file mode 100644
index 00000000000..8b07b42ae3a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sub-b-fail.s
+#error_output: cv-simd-sub-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-sub-b-fail.l
new file mode 100644
index 00000000000..02dc7c9c35c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sub.b x32,x32,x32'
+.*: Error: illegal operands `cv.sub.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-sub-b-fail.s
new file mode 100644
index 00000000000..b6bf861f0e1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.sub.b x32, x32, x32
+    cv.sub.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-sub-b-pass.d
new file mode 100644
index 00000000000..705955d82c6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sub-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0800107b          	cv.sub.b	zero,zero,zero
+   4:	081090fb          	cv.sub.b	ra,ra,ra
+   8:	0821117b          	cv.sub.b	sp,sp,sp
+   c:	0884147b          	cv.sub.b	s0,s0,s0
+  10:	094a1a7b          	cv.sub.b	s4,s4,s4
+  14:	09ff9ffb          	cv.sub.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-sub-b-pass.s
new file mode 100644
index 00000000000..7730ac51f78
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.sub.b x0, x0, x0
+    cv.sub.b x1, x1, x1
+    cv.sub.b x2, x2, x2
+    cv.sub.b x8, x8, x8
+    cv.sub.b x20, x20, x20
+    cv.sub.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-div2-fail.d b/gas/testsuite/gas/riscv/cv-simd-sub-div2-fail.d
new file mode 100644
index 00000000000..ce6f41cea9b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-div2-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sub-div2-fail.s
+#error_output: cv-simd-sub-div2-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-div2-fail.l b/gas/testsuite/gas/riscv/cv-simd-sub-div2-fail.l
new file mode 100644
index 00000000000..7776bd5850f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-div2-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sub.div2 x32,x32,x32'
+.*: Error: illegal operands `cv.sub.div2 x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-div2-fail.s b/gas/testsuite/gas/riscv/cv-simd-sub-div2-fail.s
new file mode 100644
index 00000000000..dc956b8d4b8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-div2-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.sub.div2 x32, x32, x32
+    cv.sub.div2 x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-div2-pass.d b/gas/testsuite/gas/riscv/cv-simd-sub-div2-pass.d
new file mode 100644
index 00000000000..fb7c2dc1a57
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-div2-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sub-div2-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	7400207b          	cv.sub.div2	zero,zero,zero
+   4:	7410a0fb          	cv.sub.div2	ra,ra,ra
+   8:	7421217b          	cv.sub.div2	sp,sp,sp
+   c:	7484247b          	cv.sub.div2	s0,s0,s0
+  10:	754a2a7b          	cv.sub.div2	s4,s4,s4
+  14:	75ffaffb          	cv.sub.div2	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-div2-pass.s b/gas/testsuite/gas/riscv/cv-simd-sub-div2-pass.s
new file mode 100644
index 00000000000..823f1b7c1f2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-div2-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.sub.div2 x0, x0, x0
+    cv.sub.div2 x1, x1, x1
+    cv.sub.div2 x2, x2, x2
+    cv.sub.div2 x8, x8, x8
+    cv.sub.div2 x20, x20, x20
+    cv.sub.div2 x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-div4-fail.d b/gas/testsuite/gas/riscv/cv-simd-sub-div4-fail.d
new file mode 100644
index 00000000000..a1cd49b8bdf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-div4-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sub-div4-fail.s
+#error_output: cv-simd-sub-div4-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-div4-fail.l b/gas/testsuite/gas/riscv/cv-simd-sub-div4-fail.l
new file mode 100644
index 00000000000..886d6783979
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-div4-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sub.div4 x32,x32,x32'
+.*: Error: illegal operands `cv.sub.div4 x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-div4-fail.s b/gas/testsuite/gas/riscv/cv-simd-sub-div4-fail.s
new file mode 100644
index 00000000000..1f9f4bfb8ab
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-div4-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.sub.div4 x32, x32, x32
+    cv.sub.div4 x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-div4-pass.d b/gas/testsuite/gas/riscv/cv-simd-sub-div4-pass.d
new file mode 100644
index 00000000000..8b182daac1d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-div4-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sub-div4-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	7400407b          	cv.sub.div4	zero,zero,zero
+   4:	7410c0fb          	cv.sub.div4	ra,ra,ra
+   8:	7421417b          	cv.sub.div4	sp,sp,sp
+   c:	7484447b          	cv.sub.div4	s0,s0,s0
+  10:	754a4a7b          	cv.sub.div4	s4,s4,s4
+  14:	75ffcffb          	cv.sub.div4	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-div4-pass.s b/gas/testsuite/gas/riscv/cv-simd-sub-div4-pass.s
new file mode 100644
index 00000000000..de6061db498
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-div4-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.sub.div4 x0, x0, x0
+    cv.sub.div4 x1, x1, x1
+    cv.sub.div4 x2, x2, x2
+    cv.sub.div4 x8, x8, x8
+    cv.sub.div4 x20, x20, x20
+    cv.sub.div4 x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-div8-fail.d b/gas/testsuite/gas/riscv/cv-simd-sub-div8-fail.d
new file mode 100644
index 00000000000..a7e4b1a1679
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-div8-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sub-div8-fail.s
+#error_output: cv-simd-sub-div8-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-div8-fail.l b/gas/testsuite/gas/riscv/cv-simd-sub-div8-fail.l
new file mode 100644
index 00000000000..c6141b1dc69
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-div8-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sub.div8 x32,x32,x32'
+.*: Error: illegal operands `cv.sub.div8 x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-div8-fail.s b/gas/testsuite/gas/riscv/cv-simd-sub-div8-fail.s
new file mode 100644
index 00000000000..a9c637837bf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-div8-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.sub.div8 x32, x32, x32
+    cv.sub.div8 x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-div8-pass.d b/gas/testsuite/gas/riscv/cv-simd-sub-div8-pass.d
new file mode 100644
index 00000000000..f0ce2ce92f0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-div8-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sub-div8-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	7400607b          	cv.sub.div8	zero,zero,zero
+   4:	7410e0fb          	cv.sub.div8	ra,ra,ra
+   8:	7421617b          	cv.sub.div8	sp,sp,sp
+   c:	7484647b          	cv.sub.div8	s0,s0,s0
+  10:	754a6a7b          	cv.sub.div8	s4,s4,s4
+  14:	75ffeffb          	cv.sub.div8	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-div8-pass.s b/gas/testsuite/gas/riscv/cv-simd-sub-div8-pass.s
new file mode 100644
index 00000000000..c52f5275878
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-div8-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.sub.div8 x0, x0, x0
+    cv.sub.div8 x1, x1, x1
+    cv.sub.div8 x2, x2, x2
+    cv.sub.div8 x8, x8, x8
+    cv.sub.div8 x20, x20, x20
+    cv.sub.div8 x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-sub-h-fail.d
new file mode 100644
index 00000000000..2fd004df55e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sub-h-fail.s
+#error_output: cv-simd-sub-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-sub-h-fail.l
new file mode 100644
index 00000000000..36728c3b84b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sub.h x32,x32,x32'
+.*: Error: illegal operands `cv.sub.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-sub-h-fail.s
new file mode 100644
index 00000000000..4c8feb42344
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.sub.h x32, x32, x32
+    cv.sub.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-sub-h-pass.d
new file mode 100644
index 00000000000..697f6eef4c4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sub-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0800007b          	cv.sub.h	zero,zero,zero
+   4:	081080fb          	cv.sub.h	ra,ra,ra
+   8:	0821017b          	cv.sub.h	sp,sp,sp
+   c:	0884047b          	cv.sub.h	s0,s0,s0
+  10:	094a0a7b          	cv.sub.h	s4,s4,s4
+  14:	09ff8ffb          	cv.sub.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-sub-h-pass.s
new file mode 100644
index 00000000000..e95b834959c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.sub.h x0, x0, x0
+    cv.sub.h x1, x1, x1
+    cv.sub.h x2, x2, x2
+    cv.sub.h x8, x8, x8
+    cv.sub.h x20, x20, x20
+    cv.sub.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-sub-sc-b-fail.d
new file mode 100644
index 00000000000..d993b5c20f7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sub-sc-b-fail.s
+#error_output: cv-simd-sub-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-sub-sc-b-fail.l
new file mode 100644
index 00000000000..785f3c7c3be
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sub.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.sub.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-sub-sc-b-fail.s
new file mode 100644
index 00000000000..59231416a63
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.sub.sc.b x32, x32, x32
+    cv.sub.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-sub-sc-b-pass.d
new file mode 100644
index 00000000000..3092dca0b2b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sub-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0800507b          	cv.sub.sc.b	zero,zero,zero
+   4:	0810d0fb          	cv.sub.sc.b	ra,ra,ra
+   8:	0821517b          	cv.sub.sc.b	sp,sp,sp
+   c:	0884547b          	cv.sub.sc.b	s0,s0,s0
+  10:	094a5a7b          	cv.sub.sc.b	s4,s4,s4
+  14:	09ffdffb          	cv.sub.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-sub-sc-b-pass.s
new file mode 100644
index 00000000000..0ab843c7170
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.sub.sc.b x0, x0, x0
+    cv.sub.sc.b x1, x1, x1
+    cv.sub.sc.b x2, x2, x2
+    cv.sub.sc.b x8, x8, x8
+    cv.sub.sc.b x20, x20, x20
+    cv.sub.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-sub-sc-h-fail.d
new file mode 100644
index 00000000000..027adeb6915
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sub-sc-h-fail.s
+#error_output: cv-simd-sub-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-sub-sc-h-fail.l
new file mode 100644
index 00000000000..5d5c6b67ac2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sub.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.sub.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-sub-sc-h-fail.s
new file mode 100644
index 00000000000..533d9e9855d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.sub.sc.h x32, x32, x32
+    cv.sub.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-sub-sc-h-pass.d
new file mode 100644
index 00000000000..29c0fbf7d8a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sub-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0800407b          	cv.sub.sc.h	zero,zero,zero
+   4:	0810c0fb          	cv.sub.sc.h	ra,ra,ra
+   8:	0821417b          	cv.sub.sc.h	sp,sp,sp
+   c:	0884447b          	cv.sub.sc.h	s0,s0,s0
+  10:	094a4a7b          	cv.sub.sc.h	s4,s4,s4
+  14:	09ffcffb          	cv.sub.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-sub-sc-h-pass.s
new file mode 100644
index 00000000000..7df69795f14
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.sub.sc.h x0, x0, x0
+    cv.sub.sc.h x1, x1, x1
+    cv.sub.sc.h x2, x2, x2
+    cv.sub.sc.h x8, x8, x8
+    cv.sub.sc.h x20, x20, x20
+    cv.sub.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-sub-sci-b-fail.d
new file mode 100644
index 00000000000..9b1f5367c54
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sub-sci-b-fail.s
+#error_output: cv-simd-sub-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-sub-sci-b-fail.l
new file mode 100644
index 00000000000..d45c4089d7c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sub.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.sub.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-sub-sci-b-fail.s
new file mode 100644
index 00000000000..f13856f20e3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.sub.sci.b x32, x32, 20
+    cv.sub.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.sub.sci.b x6, x7, -33
+    cv.sub.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-sub-sci-b-pass.d
new file mode 100644
index 00000000000..7de24649a44
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sub-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	08a0707b          	cv.sub.sci.b	zero,zero,20
+   4:	08a0f0fb          	cv.sub.sci.b	ra,ra,20
+   8:	08a1717b          	cv.sub.sci.b	sp,sp,20
+   c:	08a4747b          	cv.sub.sci.b	s0,s0,20
+  10:	08aa7a7b          	cv.sub.sci.b	s4,s4,20
+  14:	08affffb          	cv.sub.sci.b	t6,t6,20
+  18:	0903f37b          	cv.sub.sci.b	t1,t2,-32
+  1c:	0803f37b          	cv.sub.sci.b	t1,t2,0
+  20:	0af3f37b          	cv.sub.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-sub-sci-b-pass.s
new file mode 100644
index 00000000000..850e1431f97
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-sci-b-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.sub.sci.b x0, x0, 20
+    cv.sub.sci.b x1, x1, 20
+    cv.sub.sci.b x2, x2, 20
+    cv.sub.sci.b x8, x8, 20
+    cv.sub.sci.b x20, x20, 20
+    cv.sub.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.sub.sci.b x6, x7, -32
+    cv.sub.sci.b x6, x7, 0
+    cv.sub.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-sub-sci-h-fail.d
new file mode 100644
index 00000000000..f9703b9271f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sub-sci-h-fail.s
+#error_output: cv-simd-sub-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-sub-sci-h-fail.l
new file mode 100644
index 00000000000..ff9425a4435
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.sub.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.sub.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-sub-sci-h-fail.s
new file mode 100644
index 00000000000..ebb0aa2c2aa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.sub.sci.h x32, x32, 20
+    cv.sub.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.sub.sci.h x6, x7, -33
+    cv.sub.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-sub-sci-h-pass.d
new file mode 100644
index 00000000000..36ed84a7392
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-sub-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	08a0607b          	cv.sub.sci.h	zero,zero,20
+   4:	08a0e0fb          	cv.sub.sci.h	ra,ra,20
+   8:	08a1617b          	cv.sub.sci.h	sp,sp,20
+   c:	08a4647b          	cv.sub.sci.h	s0,s0,20
+  10:	08aa6a7b          	cv.sub.sci.h	s4,s4,20
+  14:	08afeffb          	cv.sub.sci.h	t6,t6,20
+  18:	0903e37b          	cv.sub.sci.h	t1,t2,-32
+  1c:	0803e37b          	cv.sub.sci.h	t1,t2,0
+  20:	0af3e37b          	cv.sub.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-sub-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-sub-sci-h-pass.s
new file mode 100644
index 00000000000..1ce641cb351
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-sub-sci-h-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.sub.sci.h x0, x0, 20
+    cv.sub.sci.h x1, x1, 20
+    cv.sub.sci.h x2, x2, 20
+    cv.sub.sci.h x8, x8, 20
+    cv.sub.sci.h x20, x20, 20
+    cv.sub.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.sub.sci.h x6, x7, -32
+    cv.sub.sci.h x6, x7, 0
+    cv.sub.sci.h x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-subrotmj-div2-fail.d b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div2-fail.d
new file mode 100644
index 00000000000..101d8a33c99
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div2-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-subrotmj-div2-fail.s
+#error_output: cv-simd-subrotmj-div2-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-subrotmj-div2-fail.l b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div2-fail.l
new file mode 100644
index 00000000000..324fe88cfc7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div2-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.subrotmj.div2 x32,x32,x32'
+.*: Error: illegal operands `cv.subrotmj.div2 x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-subrotmj-div2-fail.s b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div2-fail.s
new file mode 100644
index 00000000000..e46657cd5fc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div2-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.subrotmj.div2 x32, x32, x32
+    cv.subrotmj.div2 x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-subrotmj-div2-pass.d b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div2-pass.d
new file mode 100644
index 00000000000..2c65227723f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div2-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-subrotmj-div2-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	6400207b          	cv.subrotmj.div2	zero,zero,zero
+   4:	6410a0fb          	cv.subrotmj.div2	ra,ra,ra
+   8:	6421217b          	cv.subrotmj.div2	sp,sp,sp
+   c:	6484247b          	cv.subrotmj.div2	s0,s0,s0
+  10:	654a2a7b          	cv.subrotmj.div2	s4,s4,s4
+  14:	65ffaffb          	cv.subrotmj.div2	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-subrotmj-div2-pass.s b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div2-pass.s
new file mode 100644
index 00000000000..eed20c971c0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div2-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.subrotmj.div2 x0, x0, x0
+    cv.subrotmj.div2 x1, x1, x1
+    cv.subrotmj.div2 x2, x2, x2
+    cv.subrotmj.div2 x8, x8, x8
+    cv.subrotmj.div2 x20, x20, x20
+    cv.subrotmj.div2 x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-subrotmj-div4-fail.d b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div4-fail.d
new file mode 100644
index 00000000000..6eb69c0754f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div4-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-subrotmj-div4-fail.s
+#error_output: cv-simd-subrotmj-div4-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-subrotmj-div4-fail.l b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div4-fail.l
new file mode 100644
index 00000000000..73b9e0eea13
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div4-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.subrotmj.div4 x32,x32,x32'
+.*: Error: illegal operands `cv.subrotmj.div4 x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-subrotmj-div4-fail.s b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div4-fail.s
new file mode 100644
index 00000000000..2a684c982b2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div4-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.subrotmj.div4 x32, x32, x32
+    cv.subrotmj.div4 x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-subrotmj-div4-pass.d b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div4-pass.d
new file mode 100644
index 00000000000..65084e82258
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div4-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-subrotmj-div4-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	6400407b          	cv.subrotmj.div4	zero,zero,zero
+   4:	6410c0fb          	cv.subrotmj.div4	ra,ra,ra
+   8:	6421417b          	cv.subrotmj.div4	sp,sp,sp
+   c:	6484447b          	cv.subrotmj.div4	s0,s0,s0
+  10:	654a4a7b          	cv.subrotmj.div4	s4,s4,s4
+  14:	65ffcffb          	cv.subrotmj.div4	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-subrotmj-div4-pass.s b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div4-pass.s
new file mode 100644
index 00000000000..3f3e8784d59
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div4-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.subrotmj.div4 x0, x0, x0
+    cv.subrotmj.div4 x1, x1, x1
+    cv.subrotmj.div4 x2, x2, x2
+    cv.subrotmj.div4 x8, x8, x8
+    cv.subrotmj.div4 x20, x20, x20
+    cv.subrotmj.div4 x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-subrotmj-div8-fail.d b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div8-fail.d
new file mode 100644
index 00000000000..3102640f806
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div8-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-subrotmj-div8-fail.s
+#error_output: cv-simd-subrotmj-div8-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-subrotmj-div8-fail.l b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div8-fail.l
new file mode 100644
index 00000000000..558de39886d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div8-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.subrotmj.div8 x32,x32,x32'
+.*: Error: illegal operands `cv.subrotmj.div8 x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-subrotmj-div8-fail.s b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div8-fail.s
new file mode 100644
index 00000000000..cf0226d41d3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div8-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.subrotmj.div8 x32, x32, x32
+    cv.subrotmj.div8 x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-subrotmj-div8-pass.d b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div8-pass.d
new file mode 100644
index 00000000000..29560b68dac
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div8-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-subrotmj-div8-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	6400607b          	cv.subrotmj.div8	zero,zero,zero
+   4:	6410e0fb          	cv.subrotmj.div8	ra,ra,ra
+   8:	6421617b          	cv.subrotmj.div8	sp,sp,sp
+   c:	6484647b          	cv.subrotmj.div8	s0,s0,s0
+  10:	654a6a7b          	cv.subrotmj.div8	s4,s4,s4
+  14:	65ffeffb          	cv.subrotmj.div8	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-subrotmj-div8-pass.s b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div8-pass.s
new file mode 100644
index 00000000000..7e088796438
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-subrotmj-div8-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.subrotmj.div8 x0, x0, x0
+    cv.subrotmj.div8 x1, x1, x1
+    cv.subrotmj.div8 x2, x2, x2
+    cv.subrotmj.div8 x8, x8, x8
+    cv.subrotmj.div8 x20, x20, x20
+    cv.subrotmj.div8 x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-subrotmj-fail.d b/gas/testsuite/gas/riscv/cv-simd-subrotmj-fail.d
new file mode 100644
index 00000000000..21ace4da2d8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-subrotmj-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-subrotmj-fail.s
+#error_output: cv-simd-subrotmj-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-subrotmj-fail.l b/gas/testsuite/gas/riscv/cv-simd-subrotmj-fail.l
new file mode 100644
index 00000000000..1e7f31b1221
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-subrotmj-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.subrotmj x32,x32,x32'
+.*: Error: illegal operands `cv.subrotmj x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-subrotmj-fail.s b/gas/testsuite/gas/riscv/cv-simd-subrotmj-fail.s
new file mode 100644
index 00000000000..3fddab9d73d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-subrotmj-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.subrotmj x32, x32, x32
+    cv.subrotmj x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-subrotmj-pass.d b/gas/testsuite/gas/riscv/cv-simd-subrotmj-pass.d
new file mode 100644
index 00000000000..c6843343b7e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-subrotmj-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-subrotmj-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	6400007b          	cv.subrotmj	zero,zero,zero
+   4:	641080fb          	cv.subrotmj	ra,ra,ra
+   8:	6421017b          	cv.subrotmj	sp,sp,sp
+   c:	6484047b          	cv.subrotmj	s0,s0,s0
+  10:	654a0a7b          	cv.subrotmj	s4,s4,s4
+  14:	65ff8ffb          	cv.subrotmj	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-subrotmj-pass.s b/gas/testsuite/gas/riscv/cv-simd-subrotmj-pass.s
new file mode 100644
index 00000000000..c2ada3395bf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-subrotmj-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.subrotmj x0, x0, x0
+    cv.subrotmj x1, x1, x1
+    cv.subrotmj x2, x2, x2
+    cv.subrotmj x8, x8, x8
+    cv.subrotmj x20, x20, x20
+    cv.subrotmj x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-xor-b-fail.d
new file mode 100644
index 00000000000..13adc9f2136
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-xor-b-fail.s
+#error_output: cv-simd-xor-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-xor-b-fail.l
new file mode 100644
index 00000000000..85aba380181
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.xor.b x32,x32,x32'
+.*: Error: illegal operands `cv.xor.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-xor-b-fail.s
new file mode 100644
index 00000000000..f81d3eda47b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.xor.b x32, x32, x32
+    cv.xor.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-xor-b-pass.d
new file mode 100644
index 00000000000..c5aed6ec9d6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-xor-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	6000107b          	cv.xor.b	zero,zero,zero
+   4:	601090fb          	cv.xor.b	ra,ra,ra
+   8:	6021117b          	cv.xor.b	sp,sp,sp
+   c:	6084147b          	cv.xor.b	s0,s0,s0
+  10:	614a1a7b          	cv.xor.b	s4,s4,s4
+  14:	61ff9ffb          	cv.xor.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-xor-b-pass.s
new file mode 100644
index 00000000000..aefc8f7f2b4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.xor.b x0, x0, x0
+    cv.xor.b x1, x1, x1
+    cv.xor.b x2, x2, x2
+    cv.xor.b x8, x8, x8
+    cv.xor.b x20, x20, x20
+    cv.xor.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-xor-h-fail.d
new file mode 100644
index 00000000000..2d5d8f2da79
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-xor-h-fail.s
+#error_output: cv-simd-xor-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-xor-h-fail.l
new file mode 100644
index 00000000000..e17ec8a240d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.xor.h x32,x32,x32'
+.*: Error: illegal operands `cv.xor.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-xor-h-fail.s
new file mode 100644
index 00000000000..84e9c95215b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.xor.h x32, x32, x32
+    cv.xor.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-xor-h-pass.d
new file mode 100644
index 00000000000..377c5f4257e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-xor-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	6000007b          	cv.xor.h	zero,zero,zero
+   4:	601080fb          	cv.xor.h	ra,ra,ra
+   8:	6021017b          	cv.xor.h	sp,sp,sp
+   c:	6084047b          	cv.xor.h	s0,s0,s0
+  10:	614a0a7b          	cv.xor.h	s4,s4,s4
+  14:	61ff8ffb          	cv.xor.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-xor-h-pass.s
new file mode 100644
index 00000000000..01fe1c40655
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.xor.h x0, x0, x0
+    cv.xor.h x1, x1, x1
+    cv.xor.h x2, x2, x2
+    cv.xor.h x8, x8, x8
+    cv.xor.h x20, x20, x20
+    cv.xor.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-xor-sc-b-fail.d
new file mode 100644
index 00000000000..5467367f223
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-xor-sc-b-fail.s
+#error_output: cv-simd-xor-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-xor-sc-b-fail.l
new file mode 100644
index 00000000000..91a28985589
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.xor.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.xor.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-xor-sc-b-fail.s
new file mode 100644
index 00000000000..7de717fea8e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.xor.sc.b x32, x32, x32
+    cv.xor.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-xor-sc-b-pass.d
new file mode 100644
index 00000000000..12e6917f2b1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-xor-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	6000507b          	cv.xor.sc.b	zero,zero,zero
+   4:	6010d0fb          	cv.xor.sc.b	ra,ra,ra
+   8:	6021517b          	cv.xor.sc.b	sp,sp,sp
+   c:	6084547b          	cv.xor.sc.b	s0,s0,s0
+  10:	614a5a7b          	cv.xor.sc.b	s4,s4,s4
+  14:	61ffdffb          	cv.xor.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-xor-sc-b-pass.s
new file mode 100644
index 00000000000..0c7238d6043
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.xor.sc.b x0, x0, x0
+    cv.xor.sc.b x1, x1, x1
+    cv.xor.sc.b x2, x2, x2
+    cv.xor.sc.b x8, x8, x8
+    cv.xor.sc.b x20, x20, x20
+    cv.xor.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-xor-sc-h-fail.d
new file mode 100644
index 00000000000..7712206da4f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-xor-sc-h-fail.s
+#error_output: cv-simd-xor-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-xor-sc-h-fail.l
new file mode 100644
index 00000000000..b2417b49029
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.xor.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.xor.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-xor-sc-h-fail.s
new file mode 100644
index 00000000000..0063297c4cf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.xor.sc.h x32, x32, x32
+    cv.xor.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-xor-sc-h-pass.d
new file mode 100644
index 00000000000..5dc5fd83e2c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-xor-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	6000407b          	cv.xor.sc.h	zero,zero,zero
+   4:	6010c0fb          	cv.xor.sc.h	ra,ra,ra
+   8:	6021417b          	cv.xor.sc.h	sp,sp,sp
+   c:	6084447b          	cv.xor.sc.h	s0,s0,s0
+  10:	614a4a7b          	cv.xor.sc.h	s4,s4,s4
+  14:	61ffcffb          	cv.xor.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-xor-sc-h-pass.s
new file mode 100644
index 00000000000..b579d11f7c7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.xor.sc.h x0, x0, x0
+    cv.xor.sc.h x1, x1, x1
+    cv.xor.sc.h x2, x2, x2
+    cv.xor.sc.h x8, x8, x8
+    cv.xor.sc.h x20, x20, x20
+    cv.xor.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-xor-sci-b-fail.d
new file mode 100644
index 00000000000..52dcc30c7ef
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-xor-sci-b-fail.s
+#error_output: cv-simd-xor-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-xor-sci-b-fail.l
new file mode 100644
index 00000000000..64e90bac715
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.xor.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.xor.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-xor-sci-b-fail.s
new file mode 100644
index 00000000000..0a33168810f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.xor.sci.b x32, x32, 20
+    cv.xor.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.xor.sci.b x6, x7, -33
+    cv.xor.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-xor-sci-b-pass.d
new file mode 100644
index 00000000000..e1eab657bfb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-xor-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	60a0707b          	cv.xor.sci.b	zero,zero,20
+   4:	60a0f0fb          	cv.xor.sci.b	ra,ra,20
+   8:	60a1717b          	cv.xor.sci.b	sp,sp,20
+   c:	60a4747b          	cv.xor.sci.b	s0,s0,20
+  10:	60aa7a7b          	cv.xor.sci.b	s4,s4,20
+  14:	60affffb          	cv.xor.sci.b	t6,t6,20
+  18:	6103f37b          	cv.xor.sci.b	t1,t2,-32
+  1c:	6003f37b          	cv.xor.sci.b	t1,t2,0
+  20:	62f3f37b          	cv.xor.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-xor-sci-b-pass.s
new file mode 100644
index 00000000000..3636df6374a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-sci-b-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.xor.sci.b x0, x0, 20
+    cv.xor.sci.b x1, x1, 20
+    cv.xor.sci.b x2, x2, 20
+    cv.xor.sci.b x8, x8, 20
+    cv.xor.sci.b x20, x20, 20
+    cv.xor.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.xor.sci.b x6, x7, -32
+    cv.xor.sci.b x6, x7, 0
+    cv.xor.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-xor-sci-h-fail.d
new file mode 100644
index 00000000000..1572fc54ec3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-xor-sci-h-fail.s
+#error_output: cv-simd-xor-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-xor-sci-h-fail.l
new file mode 100644
index 00000000000..a4124657858
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.xor.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.xor.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-xor-sci-h-fail.s
new file mode 100644
index 00000000000..0448863d511
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.xor.sci.h x32, x32, 20
+    cv.xor.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.xor.sci.h x6, x7, -33
+    cv.xor.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-xor-sci-h-pass.d
new file mode 100644
index 00000000000..e84c597abc0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-xor-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	60a0607b          	cv.xor.sci.h	zero,zero,20
+   4:	60a0e0fb          	cv.xor.sci.h	ra,ra,20
+   8:	60a1617b          	cv.xor.sci.h	sp,sp,20
+   c:	60a4647b          	cv.xor.sci.h	s0,s0,20
+  10:	60aa6a7b          	cv.xor.sci.h	s4,s4,20
+  14:	60afeffb          	cv.xor.sci.h	t6,t6,20
+  18:	6103e37b          	cv.xor.sci.h	t1,t2,-32
+  1c:	6003e37b          	cv.xor.sci.h	t1,t2,0
+  20:	62f3e37b          	cv.xor.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-xor-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-xor-sci-h-pass.s
new file mode 100644
index 00000000000..e0c94ee6223
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-xor-sci-h-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.xor.sci.h x0, x0, 20
+    cv.xor.sci.h x1, x1, 20
+    cv.xor.sci.h x2, x2, 20
+    cv.xor.sci.h x8, x8, 20
+    cv.xor.sci.h x20, x20, 20
+    cv.xor.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.xor.sci.h x6, x7, -32
+    cv.xor.sci.h x6, x7, 0
+    cv.xor.sci.h x6, x7, 31
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index e77b49a6298..3fec649495f 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2424,6 +2424,449 @@
 #define MASK_CV_SUBRN 0xc000707f
 #define MATCH_CV_SUBURN 0xc000305b
 #define MASK_CV_SUBURN 0xc000707f
+/* Vendor-specific (CORE-V) Xcvsimd instructions. */
+#define MATCH_CV_ADD_H             0x7b
+#define MATCH_CV_ADD_B             0x107b
+#define MATCH_CV_ADD_SC_H          0x407b
+#define MATCH_CV_ADD_SC_B          0x507b
+#define MATCH_CV_ADD_SCI_H         0x607b
+#define MATCH_CV_ADD_SCI_B         0x707b
+#define MATCH_CV_SUB_H             0x800007b
+#define MATCH_CV_SUB_B             0x800107b
+#define MATCH_CV_SUB_SC_H          0x800407b
+#define MATCH_CV_SUB_SC_B          0x800507b
+#define MATCH_CV_SUB_SCI_H         0x800607b
+#define MATCH_CV_SUB_SCI_B         0x800707b
+#define MATCH_CV_AVG_H             0x1000007b
+#define MATCH_CV_AVG_B             0x1000107b
+#define MATCH_CV_AVG_SC_H          0x1000407b
+#define MATCH_CV_AVG_SC_B          0x1000507b
+#define MATCH_CV_AVG_SCI_H         0x1000607b
+#define MATCH_CV_AVG_SCI_B         0x1000707b
+#define MATCH_CV_AVGU_H            0x1800007b
+#define MATCH_CV_AVGU_B            0x1800107b
+#define MATCH_CV_AVGU_SC_H         0x1800407b
+#define MATCH_CV_AVGU_SC_B         0x1800507b
+#define MATCH_CV_AVGU_SCI_H        0x1800607b
+#define MATCH_CV_AVGU_SCI_B        0x1800707b
+#define MATCH_CV_MIN_H             0x2000007b
+#define MATCH_CV_MIN_B             0x2000107b
+#define MATCH_CV_MIN_SC_H          0x2000407b
+#define MATCH_CV_MIN_SC_B          0x2000507b
+#define MATCH_CV_MIN_SCI_H         0x2000607b
+#define MATCH_CV_MIN_SCI_B         0x2000707b
+#define MATCH_CV_MINU_H            0x2800007b
+#define MATCH_CV_MINU_B            0x2800107b
+#define MATCH_CV_MINU_SC_H         0x2800407b
+#define MATCH_CV_MINU_SC_B         0x2800507b
+#define MATCH_CV_MINU_SCI_H        0x2800607b
+#define MATCH_CV_MINU_SCI_B        0x2800707b
+#define MATCH_CV_MAX_H             0x3000007b
+#define MATCH_CV_MAX_B             0x3000107b
+#define MATCH_CV_MAX_SC_H          0x3000407b
+#define MATCH_CV_MAX_SC_B          0x3000507b
+#define MATCH_CV_MAX_SCI_H         0x3000607b
+#define MATCH_CV_MAX_SCI_B         0x3000707b
+#define MATCH_CV_MAXU_H            0x3800007b
+#define MATCH_CV_MAXU_B            0x3800107b
+#define MATCH_CV_MAXU_SC_H         0x3800407b
+#define MATCH_CV_MAXU_SC_B         0x3800507b
+#define MATCH_CV_MAXU_SCI_H        0x3800607b
+#define MATCH_CV_MAXU_SCI_B        0x3800707b
+#define MATCH_CV_SRL_H             0x4000007b
+#define MATCH_CV_SRL_B             0x4000107b
+#define MATCH_CV_SRL_SC_H          0x4000407b
+#define MATCH_CV_SRL_SC_B          0x4000507b
+#define MATCH_CV_SRL_SCI_H         0x4000607b
+#define MATCH_CV_SRL_SCI_B         0x4000707b
+#define MATCH_CV_SRA_H             0x4800007b
+#define MATCH_CV_SRA_B             0x4800107b
+#define MATCH_CV_SRA_SC_H          0x4800407b
+#define MATCH_CV_SRA_SC_B          0x4800507b
+#define MATCH_CV_SRA_SCI_H         0x4800607b
+#define MATCH_CV_SRA_SCI_B         0x4800707b
+#define MATCH_CV_SLL_H             0x5000007b
+#define MATCH_CV_SLL_B             0x5000107b
+#define MATCH_CV_SLL_SC_H          0x5000407b
+#define MATCH_CV_SLL_SC_B          0x5000507b
+#define MATCH_CV_SLL_SCI_H         0x5000607b
+#define MATCH_CV_SLL_SCI_B         0x5000707b
+#define MATCH_CV_OR_H              0x5800007b
+#define MATCH_CV_OR_B              0x5800107b
+#define MATCH_CV_OR_SC_H           0x5800407b
+#define MATCH_CV_OR_SC_B           0x5800507b
+#define MATCH_CV_OR_SCI_H          0x5800607b
+#define MATCH_CV_OR_SCI_B          0x5800707b
+#define MATCH_CV_XOR_H             0x6000007b
+#define MATCH_CV_XOR_B             0x6000107b
+#define MATCH_CV_XOR_SC_H          0x6000407b
+#define MATCH_CV_XOR_SC_B          0x6000507b
+#define MATCH_CV_XOR_SCI_H         0x6000607b
+#define MATCH_CV_XOR_SCI_B         0x6000707b
+#define MATCH_CV_AND_H             0x6800007b
+#define MATCH_CV_AND_B             0x6800107b
+#define MATCH_CV_AND_SC_H          0x6800407b
+#define MATCH_CV_AND_SC_B          0x6800507b
+#define MATCH_CV_AND_SCI_H         0x6800607b
+#define MATCH_CV_AND_SCI_B         0x6800707b
+#define MATCH_CV_ABS_H             0x7000007b
+#define MATCH_CV_ABS_B             0x7000107b
+#define MATCH_CV_DOTUP_H           0x8000007b
+#define MATCH_CV_DOTUP_B           0x8000107b
+#define MATCH_CV_DOTUP_SC_H        0x8000407b
+#define MATCH_CV_DOTUP_SC_B        0x8000507b
+#define MATCH_CV_DOTUP_SCI_H       0x8000607b
+#define MATCH_CV_DOTUP_SCI_B       0x8000707b
+#define MATCH_CV_DOTUSP_H          0x8800007b
+#define MATCH_CV_DOTUSP_B          0x8800107b
+#define MATCH_CV_DOTUSP_SC_H       0x8800407b
+#define MATCH_CV_DOTUSP_SC_B       0x8800507b
+#define MATCH_CV_DOTUSP_SCI_H      0x8800607b
+#define MATCH_CV_DOTUSP_SCI_B      0x8800707b
+#define MATCH_CV_DOTSP_H           0x9000007b
+#define MATCH_CV_DOTSP_B           0x9000107b
+#define MATCH_CV_DOTSP_SC_H        0x9000407b
+#define MATCH_CV_DOTSP_SC_B        0x9000507b
+#define MATCH_CV_DOTSP_SCI_H       0x9000607b
+#define MATCH_CV_DOTSP_SCI_B       0x9000707b
+#define MATCH_CV_SDOTUP_H          0x9800007b
+#define MATCH_CV_SDOTUP_B          0x9800107b
+#define MATCH_CV_SDOTUP_SC_H       0x9800407b
+#define MATCH_CV_SDOTUP_SC_B       0x9800507b
+#define MATCH_CV_SDOTUP_SCI_H      0x9800607b
+#define MATCH_CV_SDOTUP_SCI_B      0x9800707b
+#define MATCH_CV_SDOTUSP_H         0xa000007b
+#define MATCH_CV_SDOTUSP_B         0xa000107b
+#define MATCH_CV_SDOTUSP_SC_H      0xa000407b
+#define MATCH_CV_SDOTUSP_SC_B      0xa000507b
+#define MATCH_CV_SDOTUSP_SCI_H     0xa000607b
+#define MATCH_CV_SDOTUSP_SCI_B     0xa000707b
+#define MATCH_CV_SDOTSP_H          0xa800007b
+#define MATCH_CV_SDOTSP_B          0xa800107b
+#define MATCH_CV_SDOTSP_SC_H       0xa800407b
+#define MATCH_CV_SDOTSP_SC_B       0xa800507b
+#define MATCH_CV_SDOTSP_SCI_H      0xa800607b
+#define MATCH_CV_SDOTSP_SCI_B      0xa800707b
+#define MATCH_CV_EXTRACT_H         0xb800007b
+#define MATCH_CV_EXTRACT_B         0xb800107b
+#define MATCH_CV_EXTRACTU_H        0xb800207b
+#define MATCH_CV_EXTRACTU_B        0xb800307b
+#define MATCH_CV_INSERT_H          0xb800407b
+#define MATCH_CV_INSERT_B          0xb800507b
+#define MATCH_CV_SHUFFLE_H         0xc000007b
+#define MATCH_CV_SHUFFLE_B         0xc000107b
+#define MATCH_CV_SHUFFLE_SCI_H     0xc000607b
+#define MATCH_CV_SHUFFLEI0_SCI_B   0xc000707b
+#define MATCH_CV_SHUFFLEI1_SCI_B   0xc800707b
+#define MATCH_CV_SHUFFLEI2_SCI_B   0xd000707b
+#define MATCH_CV_SHUFFLEI3_SCI_B   0xd800707b
+#define MATCH_CV_SHUFFLE2_H        0xe000007b
+#define MATCH_CV_SHUFFLE2_B        0xe000107b
+#define MATCH_CV_PACK              0xf000007b
+#define MATCH_CV_PACK_H            0xf200007b
+#define MATCH_CV_PACKHI_B          0xfa00107b
+#define MATCH_CV_PACKLO_B          0xf800107b
+#define MATCH_CV_CMPEQ_H           0x400007b
+#define MATCH_CV_CMPEQ_B           0x400107b
+#define MATCH_CV_CMPEQ_SC_H        0x400407b
+#define MATCH_CV_CMPEQ_SC_B        0x400507b
+#define MATCH_CV_CMPEQ_SCI_H       0x400607b
+#define MATCH_CV_CMPEQ_SCI_B       0x400707b
+#define MATCH_CV_CMPNE_H           0xc00007b
+#define MATCH_CV_CMPNE_B           0xc00107b
+#define MATCH_CV_CMPNE_SC_H        0xc00407b
+#define MATCH_CV_CMPNE_SC_B        0xc00507b
+#define MATCH_CV_CMPNE_SCI_H       0xc00607b
+#define MATCH_CV_CMPNE_SCI_B       0xc00707b
+#define MATCH_CV_CMPGT_H           0x1400007b
+#define MATCH_CV_CMPGT_B           0x1400107b
+#define MATCH_CV_CMPGT_SC_H        0x1400407b
+#define MATCH_CV_CMPGT_SC_B        0x1400507b
+#define MATCH_CV_CMPGT_SCI_H       0x1400607b
+#define MATCH_CV_CMPGT_SCI_B       0x1400707b
+#define MATCH_CV_CMPGE_H           0x1c00007b
+#define MATCH_CV_CMPGE_B           0x1c00107b
+#define MATCH_CV_CMPGE_SC_H        0x1c00407b
+#define MATCH_CV_CMPGE_SC_B        0x1c00507b
+#define MATCH_CV_CMPGE_SCI_H       0x1c00607b
+#define MATCH_CV_CMPGE_SCI_B       0x1c00707b
+#define MATCH_CV_CMPLT_H           0x2400007b
+#define MATCH_CV_CMPLT_B           0x2400107b
+#define MATCH_CV_CMPLT_SC_H        0x2400407b
+#define MATCH_CV_CMPLT_SC_B        0x2400507b
+#define MATCH_CV_CMPLT_SCI_H       0x2400607b
+#define MATCH_CV_CMPLT_SCI_B       0x2400707b
+#define MATCH_CV_CMPLE_H           0x2c00007b
+#define MATCH_CV_CMPLE_B           0x2c00107b
+#define MATCH_CV_CMPLE_SC_H        0x2c00407b
+#define MATCH_CV_CMPLE_SC_B        0x2c00507b
+#define MATCH_CV_CMPLE_SCI_H       0x2c00607b
+#define MATCH_CV_CMPLE_SCI_B       0x2c00707b
+#define MATCH_CV_CMPGTU_H          0x3400007b
+#define MATCH_CV_CMPGTU_B          0x3400107b
+#define MATCH_CV_CMPGTU_SC_H       0x3400407b
+#define MATCH_CV_CMPGTU_SC_B       0x3400507b
+#define MATCH_CV_CMPGTU_SCI_H      0x3400607b
+#define MATCH_CV_CMPGTU_SCI_B      0x3400707b
+#define MATCH_CV_CMPGEU_H          0x3c00007b
+#define MATCH_CV_CMPGEU_B          0x3c00107b
+#define MATCH_CV_CMPGEU_SC_H       0x3c00407b
+#define MATCH_CV_CMPGEU_SC_B       0x3c00507b
+#define MATCH_CV_CMPGEU_SCI_H      0x3c00607b
+#define MATCH_CV_CMPGEU_SCI_B      0x3c00707b
+#define MATCH_CV_CMPLTU_H          0x4400007b
+#define MATCH_CV_CMPLTU_B          0x4400107b
+#define MATCH_CV_CMPLTU_SC_H       0x4400407b
+#define MATCH_CV_CMPLTU_SC_B       0x4400507b
+#define MATCH_CV_CMPLTU_SCI_H      0x4400607b
+#define MATCH_CV_CMPLTU_SCI_B      0x4400707b
+#define MATCH_CV_CMPLEU_H          0x4c00007b
+#define MATCH_CV_CMPLEU_B          0x4c00107b
+#define MATCH_CV_CMPLEU_SC_H       0x4c00407b
+#define MATCH_CV_CMPLEU_SC_B       0x4c00507b
+#define MATCH_CV_CMPLEU_SCI_H      0x4c00607b
+#define MATCH_CV_CMPLEU_SCI_B      0x4c00707b
+#define MATCH_CV_CPLXMUL_R         0x5400007b
+#define MATCH_CV_CPLXMUL_I         0x5600007b
+#define MATCH_CV_CPLXMUL_R_DIV2    0x5400207b
+#define MATCH_CV_CPLXMUL_I_DIV2    0x5600207b
+#define MATCH_CV_CPLXMUL_R_DIV4    0x5400407b
+#define MATCH_CV_CPLXMUL_I_DIV4    0x5600407b
+#define MATCH_CV_CPLXMUL_R_DIV8    0x5400607b
+#define MATCH_CV_CPLXMUL_I_DIV8    0x5600607b
+#define MATCH_CV_CPLXCONJ          0x5c00007b
+#define MATCH_CV_SUBROTMJ          0x6400007b
+#define MATCH_CV_SUBROTMJ_DIV2     0x6400207b
+#define MATCH_CV_SUBROTMJ_DIV4     0x6400407b
+#define MATCH_CV_SUBROTMJ_DIV8     0x6400607b
+#define MATCH_CV_ADD_DIV2          0x6c00207b
+#define MATCH_CV_ADD_DIV4          0x6c00407b
+#define MATCH_CV_ADD_DIV8          0x6c00607b
+#define MATCH_CV_SUB_DIV2          0x7400207b
+#define MATCH_CV_SUB_DIV4          0x7400407b
+#define MATCH_CV_SUB_DIV8          0x7400607b
+#define MASK_CV_ADD_H              0xfe00707f
+#define MASK_CV_ADD_B              0xfe00707f
+#define MASK_CV_ADD_SC_H           0xfe00707f
+#define MASK_CV_ADD_SC_B           0xfe00707f
+#define MASK_CV_ADD_SCI_H          0xfc00707f
+#define MASK_CV_ADD_SCI_B          0xfc00707f
+#define MASK_CV_SUB_H              0xfe00707f
+#define MASK_CV_SUB_B              0xfe00707f
+#define MASK_CV_SUB_SC_H           0xfe00707f
+#define MASK_CV_SUB_SC_B           0xfe00707f
+#define MASK_CV_SUB_SCI_H          0xfc00707f
+#define MASK_CV_SUB_SCI_B          0xfc00707f
+#define MASK_CV_AVG_H              0xfe00707f
+#define MASK_CV_AVG_B              0xfe00707f
+#define MASK_CV_AVG_SC_H           0xfe00707f
+#define MASK_CV_AVG_SC_B           0xfe00707f
+#define MASK_CV_AVG_SCI_H          0xfc00707f
+#define MASK_CV_AVG_SCI_B          0xfc00707f
+#define MASK_CV_AVGU_H             0xfe00707f
+#define MASK_CV_AVGU_B             0xfe00707f
+#define MASK_CV_AVGU_SC_H          0xfe00707f
+#define MASK_CV_AVGU_SC_B          0xfe00707f
+#define MASK_CV_AVGU_SCI_H         0xfc00707f
+#define MASK_CV_AVGU_SCI_B         0xfc00707f
+#define MASK_CV_MIN_H              0xfe00707f
+#define MASK_CV_MIN_B              0xfe00707f
+#define MASK_CV_MIN_SC_H           0xfe00707f
+#define MASK_CV_MIN_SC_B           0xfe00707f
+#define MASK_CV_MIN_SCI_H          0xfc00707f
+#define MASK_CV_MIN_SCI_B          0xfc00707f
+#define MASK_CV_MINU_H             0xfe00707f
+#define MASK_CV_MINU_B             0xfe00707f
+#define MASK_CV_MINU_SC_H          0xfe00707f
+#define MASK_CV_MINU_SC_B          0xfe00707f
+#define MASK_CV_MINU_SCI_H         0xfc00707f
+#define MASK_CV_MINU_SCI_B         0xfc00707f
+#define MASK_CV_MAX_H              0xfe00707f
+#define MASK_CV_MAX_B              0xfe00707f
+#define MASK_CV_MAX_SC_H           0xfe00707f
+#define MASK_CV_MAX_SC_B           0xfe00707f
+#define MASK_CV_MAX_SCI_H          0xfc00707f
+#define MASK_CV_MAX_SCI_B          0xfc00707f
+#define MASK_CV_MAXU_H             0xfe00707f
+#define MASK_CV_MAXU_B             0xfe00707f
+#define MASK_CV_MAXU_SC_H          0xfe00707f
+#define MASK_CV_MAXU_SC_B          0xfe00707f
+#define MASK_CV_MAXU_SCI_H         0xfc00707f
+#define MASK_CV_MAXU_SCI_B         0xfc00707f
+#define MASK_CV_SRL_H              0xfe00707f
+#define MASK_CV_SRL_B              0xfe00707f
+#define MASK_CV_SRL_SC_H           0xfe00707f
+#define MASK_CV_SRL_SC_B           0xfe00707f
+#define MASK_CV_SRL_SCI_H          0xfc00707f
+#define MASK_CV_SRL_SCI_B          0xfc00707f
+#define MASK_CV_SRA_H              0xfe00707f
+#define MASK_CV_SRA_B              0xfe00707f
+#define MASK_CV_SRA_SC_H           0xfe00707f
+#define MASK_CV_SRA_SC_B           0xfe00707f
+#define MASK_CV_SRA_SCI_H          0xfc00707f
+#define MASK_CV_SRA_SCI_B          0xfc00707f
+#define MASK_CV_SLL_H              0xfe00707f
+#define MASK_CV_SLL_B              0xfe00707f
+#define MASK_CV_SLL_SC_H           0xfe00707f
+#define MASK_CV_SLL_SC_B           0xfe00707f
+#define MASK_CV_SLL_SCI_H          0xfc00707f
+#define MASK_CV_SLL_SCI_B          0xfc00707f
+#define MASK_CV_OR_H               0xfe00707f
+#define MASK_CV_OR_B               0xfe00707f
+#define MASK_CV_OR_SC_H            0xfe00707f
+#define MASK_CV_OR_SC_B            0xfe00707f
+#define MASK_CV_OR_SCI_H           0xfc00707f
+#define MASK_CV_OR_SCI_B           0xfc00707f
+#define MASK_CV_XOR_H              0xfe00707f
+#define MASK_CV_XOR_B              0xfe00707f
+#define MASK_CV_XOR_SC_H           0xfe00707f
+#define MASK_CV_XOR_SC_B           0xfe00707f
+#define MASK_CV_XOR_SCI_H          0xfc00707f
+#define MASK_CV_XOR_SCI_B          0xfc00707f
+#define MASK_CV_AND_H              0xfe00707f
+#define MASK_CV_AND_B              0xfe00707f
+#define MASK_CV_AND_SC_H           0xfe00707f
+#define MASK_CV_AND_SC_B           0xfe00707f
+#define MASK_CV_AND_SCI_H          0xfc00707f
+#define MASK_CV_AND_SCI_B          0xfc00707f
+#define MASK_CV_ABS_H              0xfff0707f
+#define MASK_CV_ABS_B              0xfff0707f
+#define MASK_CV_DOTUP_H            0xfe00707f
+#define MASK_CV_DOTUP_B            0xfe00707f
+#define MASK_CV_DOTUP_SC_H         0xfe00707f
+#define MASK_CV_DOTUP_SC_B         0xfe00707f
+#define MASK_CV_DOTUP_SCI_H        0xfc00707f
+#define MASK_CV_DOTUP_SCI_B        0xfc00707f
+#define MASK_CV_DOTUSP_H           0xfe00707f
+#define MASK_CV_DOTUSP_B           0xfe00707f
+#define MASK_CV_DOTUSP_SC_H        0xfe00707f
+#define MASK_CV_DOTUSP_SC_B        0xfe00707f
+#define MASK_CV_DOTUSP_SCI_H       0xfc00707f
+#define MASK_CV_DOTUSP_SCI_B       0xfc00707f
+#define MASK_CV_DOTSP_H            0xfe00707f
+#define MASK_CV_DOTSP_B            0xfe00707f
+#define MASK_CV_DOTSP_SC_H         0xfe00707f
+#define MASK_CV_DOTSP_SC_B         0xfe00707f
+#define MASK_CV_DOTSP_SCI_H        0xfc00707f
+#define MASK_CV_DOTSP_SCI_B        0xfc00707f
+#define MASK_CV_SDOTUP_H           0xfe00707f
+#define MASK_CV_SDOTUP_B           0xfe00707f
+#define MASK_CV_SDOTUP_SC_H        0xfe00707f
+#define MASK_CV_SDOTUP_SC_B        0xfe00707f
+#define MASK_CV_SDOTUP_SCI_H       0xfc00707f
+#define MASK_CV_SDOTUP_SCI_B       0xfc00707f
+#define MASK_CV_SDOTUSP_H          0xfe00707f
+#define MASK_CV_SDOTUSP_B          0xfe00707f
+#define MASK_CV_SDOTUSP_SC_H       0xfe00707f
+#define MASK_CV_SDOTUSP_SC_B       0xfe00707f
+#define MASK_CV_SDOTUSP_SCI_H      0xfc00707f
+#define MASK_CV_SDOTUSP_SCI_B      0xfc00707f
+#define MASK_CV_SDOTSP_H           0xfe00707f
+#define MASK_CV_SDOTSP_B           0xfe00707f
+#define MASK_CV_SDOTSP_SC_H        0xfe00707f
+#define MASK_CV_SDOTSP_SC_B        0xfe00707f
+#define MASK_CV_SDOTSP_SCI_H       0xfc00707f
+#define MASK_CV_SDOTSP_SCI_B       0xfc00707f
+#define MASK_CV_EXTRACT_H          0xfc00707f
+#define MASK_CV_EXTRACT_B          0xfc00707f
+#define MASK_CV_EXTRACTU_H         0xfc00707f
+#define MASK_CV_EXTRACTU_B         0xfc00707f
+#define MASK_CV_INSERT_H           0xfc00707f
+#define MASK_CV_INSERT_B           0xfc00707f
+#define MASK_CV_SHUFFLE_H          0xfe00707f
+#define MASK_CV_SHUFFLE_B          0xfe00707f
+#define MASK_CV_SHUFFLE_SCI_H      0xfc00707f
+#define MASK_CV_SHUFFLEI0_SCI_B    0xfc00707f
+#define MASK_CV_SHUFFLEI1_SCI_B    0xfc00707f
+#define MASK_CV_SHUFFLEI2_SCI_B    0xfc00707f
+#define MASK_CV_SHUFFLEI3_SCI_B    0xfc00707f
+#define MASK_CV_SHUFFLE2_H         0xfe00707f
+#define MASK_CV_SHUFFLE2_B         0xfe00707f
+#define MASK_CV_PACK               0xfe00707f
+#define MASK_CV_PACK_H             0xfe00707f
+#define MASK_CV_PACKHI_B           0xfe00707f
+#define MASK_CV_PACKLO_B           0xfe00707f
+#define MASK_CV_CMPEQ_H            0xfe00707f
+#define MASK_CV_CMPEQ_B            0xfe00707f
+#define MASK_CV_CMPEQ_SC_H         0xfe00707f
+#define MASK_CV_CMPEQ_SC_B         0xfe00707f
+#define MASK_CV_CMPEQ_SCI_H        0xfc00707f
+#define MASK_CV_CMPEQ_SCI_B        0xfc00707f
+#define MASK_CV_CMPNE_H            0xfe00707f
+#define MASK_CV_CMPNE_B            0xfe00707f
+#define MASK_CV_CMPNE_SC_H         0xfe00707f
+#define MASK_CV_CMPNE_SC_B         0xfe00707f
+#define MASK_CV_CMPNE_SCI_H        0xfc00707f
+#define MASK_CV_CMPNE_SCI_B        0xfc00707f
+#define MASK_CV_CMPGT_H            0xfe00707f
+#define MASK_CV_CMPGT_B            0xfe00707f
+#define MASK_CV_CMPGT_SC_H         0xfe00707f
+#define MASK_CV_CMPGT_SC_B         0xfe00707f
+#define MASK_CV_CMPGT_SCI_H        0xfc00707f
+#define MASK_CV_CMPGT_SCI_B        0xfc00707f
+#define MASK_CV_CMPGE_H            0xfe00707f
+#define MASK_CV_CMPGE_B            0xfe00707f
+#define MASK_CV_CMPGE_SC_H         0xfe00707f
+#define MASK_CV_CMPGE_SC_B         0xfe00707f
+#define MASK_CV_CMPGE_SCI_H        0xfc00707f
+#define MASK_CV_CMPGE_SCI_B        0xfc00707f
+#define MASK_CV_CMPLT_H            0xfe00707f
+#define MASK_CV_CMPLT_B            0xfe00707f
+#define MASK_CV_CMPLT_SC_H         0xfe00707f
+#define MASK_CV_CMPLT_SC_B         0xfe00707f
+#define MASK_CV_CMPLT_SCI_H        0xfc00707f
+#define MASK_CV_CMPLT_SCI_B        0xfc00707f
+#define MASK_CV_CMPLE_H            0xfe00707f
+#define MASK_CV_CMPLE_B            0xfe00707f
+#define MASK_CV_CMPLE_SC_H         0xfe00707f
+#define MASK_CV_CMPLE_SC_B         0xfe00707f
+#define MASK_CV_CMPLE_SCI_H        0xfc00707f
+#define MASK_CV_CMPLE_SCI_B        0xfc00707f
+#define MASK_CV_CMPGTU_H           0xfe00707f
+#define MASK_CV_CMPGTU_B           0xfe00707f
+#define MASK_CV_CMPGTU_SC_H        0xfe00707f
+#define MASK_CV_CMPGTU_SC_B        0xfe00707f
+#define MASK_CV_CMPGTU_SCI_H       0xfc00707f
+#define MASK_CV_CMPGTU_SCI_B       0xfc00707f
+#define MASK_CV_CMPGEU_H           0xfe00707f
+#define MASK_CV_CMPGEU_B           0xfe00707f
+#define MASK_CV_CMPGEU_SC_H        0xfe00707f
+#define MASK_CV_CMPGEU_SC_B        0xfe00707f
+#define MASK_CV_CMPGEU_SCI_H       0xfc00707f
+#define MASK_CV_CMPGEU_SC_B        0xfe00707f
+#define MASK_CV_CMPGEU_SCI_H       0xfc00707f
+#define MASK_CV_CMPGEU_SCI_B       0xfc00707f
+#define MASK_CV_CMPLTU_H           0xfe00707f
+#define MASK_CV_CMPLTU_B           0xfe00707f
+#define MASK_CV_CMPLTU_SC_H        0xfe00707f
+#define MASK_CV_CMPLTU_SC_B        0xfe00707f
+#define MASK_CV_CMPLTU_SCI_H       0xfc00707f
+#define MASK_CV_CMPLTU_SCI_B       0xfc00707f
+#define MASK_CV_CMPLEU_H           0xfe00707f
+#define MASK_CV_CMPLEU_B           0xfe00707f
+#define MASK_CV_CMPLEU_SC_H        0xfe00707f
+#define MASK_CV_CMPLEU_SC_B        0xfe00707f
+#define MASK_CV_CMPLEU_SCI_H       0xfc00707f
+#define MASK_CV_CMPLEU_SCI_B       0xfc00707f
+#define MASK_CV_CPLXMUL_R          0xfe00707f
+#define MASK_CV_CPLXMUL_I          0xfe00707f
+#define MASK_CV_CPLXMUL_R_DIV2     0xfe00707f
+#define MASK_CV_CPLXMUL_I_DIV2     0xfe00707f
+#define MASK_CV_CPLXMUL_R_DIV4     0xfe00707f
+#define MASK_CV_CPLXMUL_I_DIV4     0xfe00707f
+#define MASK_CV_CPLXMUL_R_DIV8     0xfe00707f
+#define MASK_CV_CPLXMUL_I_DIV8     0xfe00707f
+#define MASK_CV_CPLXCONJ           0xfff0707f
+#define MASK_CV_SUBROTMJ           0xfe00707f
+#define MASK_CV_SUBROTMJ_DIV2      0xfe00707f
+#define MASK_CV_SUBROTMJ_DIV4      0xfe00707f
+#define MASK_CV_SUBROTMJ_DIV8      0xfe00707f
+#define MASK_CV_ADD_DIV2           0xfe00707f
+#define MASK_CV_ADD_DIV4           0xfe00707f
+#define MASK_CV_ADD_DIV8           0xfe00707f
+#define MASK_CV_SUB_DIV2           0xfe00707f
+#define MASK_CV_SUB_DIV4           0xfe00707f
+#define MASK_CV_SUB_DIV8           0xfe00707f
 /* Vendor-specific (T-Head) XTheadBa instructions.  */
 #define MATCH_TH_ADDSL 0x0000100b
 #define MASK_TH_ADDSL 0xf800707f
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index adea7dbc794..9a5880f4e3e 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -55,6 +55,7 @@ static inline unsigned int riscv_insn_length (insn_t insn)
 #define RV_X(x, s, n)  (((x) >> (s)) & ((1 << (n)) - 1))
 #define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
 #define RV_X_SIGNED(x, s, n) (RV_X(x, s, n) | ((-(RV_X(x, (s + n - 1), 1))) << (n)))
+#define RV_IMM_SIGN_N(x, s, n) (-(((x) >> ((s) + (n) - 1)) & 1))
 
 #define EXTRACT_ITYPE_IMM(x) \
   (RV_X(x, 20, 12) | (RV_IMM_SIGN(x) << 12))
@@ -117,6 +118,12 @@ static inline unsigned int riscv_insn_length (insn_t insn)
   (RV_X(x, 20, 5))
 #define EXTRACT_CV_IS3_UIMM5(x) \
   (RV_X(x, 25, 5))
+#define EXTRACT_CV_BI_IMM5(x) \
+  (RV_X(x, 20, 5) | (RV_IMM_SIGN_N(x, 20, 5) << 5))
+#define EXTRACT_CV_SIMD_IMM6(x) \
+  ((RV_X(x, 25, 1)) | (RV_X(x, 20, 5) << 1) | (RV_IMM_SIGN_N(x, 20, 5) << 5))
+#define EXTRACT_CV_SIMD_UIMM6(x) \
+  ((RV_X(x, 25, 1)) | (RV_X(x, 20, 5) << 1))
 
 #define ENCODE_ITYPE_IMM(x) \
   (RV_X(x, 0, 12) << 20)
@@ -173,6 +180,12 @@ static inline unsigned int riscv_insn_length (insn_t insn)
   (RV_X(x, 0, 5) << 20)
 #define ENCODE_CV_IS3_UIMM5(x) \
   (RV_X(x, 0, 5) << 25)
+#define ENCODE_CV_UIMM5(x) \
+  (RV_X(x, 0, 5) << 20)
+#define ENCODE_CV_SIMD_IMM6(x) \
+  ((RV_X(x, 0, 1) << 25) | (RV_X(x, 1, 5) << 20))
+#define ENCODE_CV_SIMD_UIMM6(x) \
+  ((RV_X(x, 0, 1) << 25) | (RV_X(x, 1, 5) << 20))
 
 #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
 #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
@@ -471,6 +484,7 @@ enum riscv_insn_class
   INSN_CLASS_H,
   INSN_CLASS_XCVMAC,
   INSN_CLASS_XCVALU,
+  INSN_CLASS_XCVSIMD,
   INSN_CLASS_XTHEADBA,
   INSN_CLASS_XTHEADBB,
   INSN_CLASS_XTHEADBS,
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 3019b9a5130..e40bce212f3 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -429,6 +429,28 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 	    print (info->stream, dis_style_immediate, "0");
 	  break;
 
+	/* CORE-V Specific.  */
+	case 'b':
+	  if (oparg[1] == '4')
+	    {
+	      print (info->stream, dis_style_immediate, "%d", ((int) EXTRACT_CV_BI_IMM5 (l)));
+	      ++oparg;
+	      break;
+	    }
+	   else if (oparg[1] == '5')
+	    {
+	      print (info->stream, dis_style_immediate, "%d", ((int) EXTRACT_CV_SIMD_IMM6 (l)));
+	      ++oparg;
+	      break;
+	    }
+	   else if (oparg[1] == '8')
+	    {
+	      print (info->stream, dis_style_immediate, "%d", ((int) EXTRACT_CV_SIMD_UIMM6 (l)));
+	      if (oparg[2] == '1' || oparg[2] == '2' || oparg[2] == '3' || oparg[2] == '4') ++oparg;
+	      ++oparg;
+	      break;
+	    }
+	/* Fall through.  */
 	case 's':
 	  if ((l & MASK_JALR) == MATCH_JALR)
 	    maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0);
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index fdd05ac75dc..d7f88c86567 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2112,6 +2112,228 @@ const struct riscv_opcode riscv_opcodes[] =
 {"cv.subrnr",  0, INSN_CLASS_XCVALU, "d,s,t",     MATCH_CV_SUBRNR,  MASK_CV_SUBRNR, match_opcode, 0},
 {"cv.suburnr", 0, INSN_CLASS_XCVALU, "d,s,t",     MATCH_CV_SUBURNR, MASK_CV_SUBURNR, match_opcode, 0},
 
+/* Vendor-specific (CORE-V) Xcvsimd Instructions */
+{"cv.add.h",              0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_ADD_H, MASK_CV_ADD_H, match_opcode, 0},
+{"cv.add.b",              0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_ADD_B, MASK_CV_ADD_B, match_opcode, 0},
+{"cv.add.sc.h",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_ADD_SC_H, MASK_CV_ADD_SC_H, match_opcode, 0},
+{"cv.add.sc.b",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_ADD_SC_B, MASK_CV_ADD_SC_B, match_opcode, 0},
+{"cv.add.sci.h",          0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_ADD_SCI_H, MASK_CV_ADD_SCI_H, match_opcode, 0},
+{"cv.add.sci.b",          0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_ADD_SCI_B, MASK_CV_ADD_SCI_B, match_opcode, 0},
+{"cv.sub.h",              0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SUB_H, MASK_CV_SUB_H, match_opcode, 0},
+{"cv.sub.b",              0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SUB_B, MASK_CV_SUB_B, match_opcode, 0},
+{"cv.sub.sc.h",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SUB_SC_H, MASK_CV_SUB_SC_H, match_opcode, 0},
+{"cv.sub.sc.b",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SUB_SC_B, MASK_CV_SUB_SC_B, match_opcode, 0},
+{"cv.sub.sci.h",          0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_SUB_SCI_H, MASK_CV_SUB_SCI_H, match_opcode, 0},
+{"cv.sub.sci.b",          0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_SUB_SCI_B, MASK_CV_SUB_SCI_B, match_opcode, 0},
+{"cv.avg.h",              0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_AVG_H, MASK_CV_AVG_H, match_opcode, 0},
+{"cv.avg.b",              0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_AVG_B, MASK_CV_AVG_B, match_opcode, 0},
+{"cv.avg.sc.h",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_AVG_SC_H, MASK_CV_AVG_SC_H, match_opcode, 0},
+{"cv.avg.sc.b",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_AVG_SC_B, MASK_CV_AVG_SC_B, match_opcode, 0},
+{"cv.avg.sci.h",          0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_AVG_SCI_H, MASK_CV_AVG_SCI_H, match_opcode, 0},
+{"cv.avg.sci.b",          0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_AVG_SCI_B, MASK_CV_AVG_SCI_B, match_opcode, 0},
+{"cv.avgu.h",             0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_AVGU_H, MASK_CV_AVGU_H, match_opcode, 0},
+{"cv.avgu.b",             0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_AVGU_B, MASK_CV_AVGU_B, match_opcode, 0},
+{"cv.avgu.sc.h",          0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_AVGU_SC_H, MASK_CV_AVGU_SC_H, match_opcode, 0},
+{"cv.avgu.sc.b",          0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_AVGU_SC_B, MASK_CV_AVGU_SC_B, match_opcode, 0},
+{"cv.avgu.sci.h",         0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_AVGU_SCI_H, MASK_CV_AVGU_SCI_H, match_opcode, 0},
+{"cv.avgu.sci.b",         0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_AVGU_SCI_B, MASK_CV_AVGU_SCI_B, match_opcode, 0},
+{"cv.min.h",              0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_MIN_H, MASK_CV_MIN_H, match_opcode, 0},
+{"cv.min.b",              0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_MIN_B, MASK_CV_MIN_B, match_opcode, 0},
+{"cv.min.sc.h",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_MIN_SC_H, MASK_CV_MIN_SC_H, match_opcode, 0},
+{"cv.min.sc.b",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_MIN_SC_B, MASK_CV_MIN_SC_B, match_opcode, 0},
+{"cv.min.sci.h",          0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_MIN_SCI_H, MASK_CV_MIN_SCI_H, match_opcode, 0},
+{"cv.min.sci.b",          0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_MIN_SCI_B, MASK_CV_MIN_SCI_B, match_opcode, 0},
+{"cv.minu.h",             0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_MINU_H, MASK_CV_MINU_H, match_opcode, 0},
+{"cv.minu.b",             0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_MINU_B, MASK_CV_MINU_B, match_opcode, 0},
+{"cv.minu.sc.h",          0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_MINU_SC_H, MASK_CV_MINU_SC_H, match_opcode, 0},
+{"cv.minu.sc.b",          0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_MINU_SC_B, MASK_CV_MINU_SC_B, match_opcode, 0},
+{"cv.minu.sci.h",         0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_MINU_SCI_H, MASK_CV_MINU_SCI_H, match_opcode, 0},
+{"cv.minu.sci.b",         0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_MINU_SCI_B, MASK_CV_MINU_SCI_B, match_opcode, 0},
+{"cv.max.h",              0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_MAX_H, MASK_CV_MAX_H, match_opcode, 0},
+{"cv.max.b",              0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_MAX_B, MASK_CV_MAX_B, match_opcode, 0},
+{"cv.max.sc.h",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_MAX_SC_H, MASK_CV_MAX_SC_H, match_opcode, 0},
+{"cv.max.sc.b",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_MAX_SC_B, MASK_CV_MAX_SC_B, match_opcode, 0},
+{"cv.max.sci.h",          0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_MAX_SCI_H, MASK_CV_MAX_SCI_H, match_opcode, 0},
+{"cv.max.sci.b",          0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_MAX_SCI_B, MASK_CV_MAX_SCI_B, match_opcode, 0},
+{"cv.maxu.h",             0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_MAXU_H, MASK_CV_MAXU_H, match_opcode, 0},
+{"cv.maxu.b",             0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_MAXU_B, MASK_CV_MAXU_B, match_opcode, 0},
+{"cv.maxu.sc.h",          0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_MAXU_SC_H, MASK_CV_MAXU_SC_H, match_opcode, 0},
+{"cv.maxu.sc.b",          0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_MAXU_SC_B, MASK_CV_MAXU_SC_B, match_opcode, 0},
+{"cv.maxu.sci.h",         0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_MAXU_SCI_H, MASK_CV_MAXU_SCI_H, match_opcode, 0},
+{"cv.maxu.sci.b",         0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_MAXU_SCI_B, MASK_CV_MAXU_SCI_B, match_opcode, 0},
+{"cv.srl.h",              0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SRL_H, MASK_CV_SRL_H, match_opcode, 0},
+{"cv.srl.b",              0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SRL_B, MASK_CV_SRL_B, match_opcode, 0},
+{"cv.srl.sc.h",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SRL_SC_H, MASK_CV_SRL_SC_H, match_opcode, 0},
+{"cv.srl.sc.b",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SRL_SC_B, MASK_CV_SRL_SC_B, match_opcode, 0},
+{"cv.srl.sci.h",          0, INSN_CLASS_XCVSIMD, "d,s,b84", MATCH_CV_SRL_SCI_H, MASK_CV_SRL_SCI_H, match_opcode, 0},
+{"cv.srl.sci.b",          0, INSN_CLASS_XCVSIMD, "d,s,b83", MATCH_CV_SRL_SCI_B, MASK_CV_SRL_SCI_B, match_opcode, 0},
+{"cv.sra.h",              0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SRA_H, MASK_CV_SRA_H, match_opcode, 0},
+{"cv.sra.b",              0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SRA_B, MASK_CV_SRA_B, match_opcode, 0},
+{"cv.sra.sc.h",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SRA_SC_H, MASK_CV_SRA_SC_H, match_opcode, 0},
+{"cv.sra.sc.b",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SRA_SC_B, MASK_CV_SRA_SC_B, match_opcode, 0},
+{"cv.sra.sci.h",          0, INSN_CLASS_XCVSIMD, "d,s,b84", MATCH_CV_SRA_SCI_H, MASK_CV_SRA_SCI_H, match_opcode, 0},
+{"cv.sra.sci.b",          0, INSN_CLASS_XCVSIMD, "d,s,b83", MATCH_CV_SRA_SCI_B, MASK_CV_SRA_SCI_B, match_opcode, 0},
+{"cv.sll.h",              0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SLL_H, MASK_CV_SLL_H, match_opcode, 0},
+{"cv.sll.b",              0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SLL_B, MASK_CV_SLL_B, match_opcode, 0},
+{"cv.sll.sc.h",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SLL_SC_H, MASK_CV_SLL_SC_H, match_opcode, 0},
+{"cv.sll.sc.b",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SLL_SC_B, MASK_CV_SLL_SC_B, match_opcode, 0},
+{"cv.sll.sci.h",          0, INSN_CLASS_XCVSIMD, "d,s,b84", MATCH_CV_SLL_SCI_H, MASK_CV_SLL_SCI_H, match_opcode, 0},
+{"cv.sll.sci.b",          0, INSN_CLASS_XCVSIMD, "d,s,b83", MATCH_CV_SLL_SCI_B, MASK_CV_SLL_SCI_B, match_opcode, 0},
+{"cv.or.h",               0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_OR_H, MASK_CV_OR_H, match_opcode, 0},
+{"cv.or.b",               0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_OR_B, MASK_CV_OR_B, match_opcode, 0},
+{"cv.or.sc.h",            0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_OR_SC_H, MASK_CV_OR_SC_H, match_opcode, 0},
+{"cv.or.sc.b",            0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_OR_SC_B, MASK_CV_OR_SC_B, match_opcode, 0},
+{"cv.or.sci.h",           0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_OR_SCI_H, MASK_CV_OR_SCI_H, match_opcode, 0},
+{"cv.or.sci.b",           0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_OR_SCI_B, MASK_CV_OR_SCI_B, match_opcode, 0},
+{"cv.xor.h",              0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_XOR_H, MASK_CV_XOR_H, match_opcode, 0},
+{"cv.xor.b",              0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_XOR_B, MASK_CV_XOR_B, match_opcode, 0},
+{"cv.xor.sc.h",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_XOR_SC_H, MASK_CV_XOR_SC_H, match_opcode, 0},
+{"cv.xor.sc.b",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_XOR_SC_B, MASK_CV_XOR_SC_B, match_opcode, 0},
+{"cv.xor.sci.h",          0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_XOR_SCI_H, MASK_CV_XOR_SCI_H, match_opcode, 0},
+{"cv.xor.sci.b",          0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_XOR_SCI_B, MASK_CV_XOR_SCI_B, match_opcode, 0},
+{"cv.and.h",              0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_AND_H, MASK_CV_AND_H, match_opcode, 0},
+{"cv.and.b",              0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_AND_B, MASK_CV_AND_B, match_opcode, 0},
+{"cv.and.sc.h",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_AND_SC_H, MASK_CV_AND_SC_H, match_opcode, 0},
+{"cv.and.sc.b",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_AND_SC_B, MASK_CV_AND_SC_B, match_opcode, 0},
+{"cv.and.sci.h",          0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_AND_SCI_H, MASK_CV_AND_SCI_H, match_opcode, 0},
+{"cv.and.sci.b",          0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_AND_SCI_B, MASK_CV_AND_SCI_B, match_opcode, 0},
+{"cv.abs.h",              0, INSN_CLASS_XCVSIMD, "d,s",   MATCH_CV_ABS_H, MASK_CV_ABS_H, match_opcode, 0},
+{"cv.abs.b",              0, INSN_CLASS_XCVSIMD, "d,s",   MATCH_CV_ABS_B, MASK_CV_ABS_B, match_opcode, 0},
+{"cv.dotup.h",            0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_DOTUP_H, MASK_CV_DOTUP_H, match_opcode, 0},
+{"cv.dotup.b",            0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_DOTUP_B, MASK_CV_DOTUP_B, match_opcode, 0},
+{"cv.dotup.sc.h",         0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_DOTUP_SC_H, MASK_CV_DOTUP_SC_H, match_opcode, 0},
+{"cv.dotup.sc.b",         0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_DOTUP_SC_B, MASK_CV_DOTUP_SC_B, match_opcode, 0},
+{"cv.dotup.sci.h",        0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_DOTUP_SCI_H, MASK_CV_DOTUP_SCI_H, match_opcode, 0},
+{"cv.dotup.sci.b",        0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_DOTUP_SCI_B, MASK_CV_DOTUP_SCI_B, match_opcode, 0},
+{"cv.dotusp.h",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_DOTUSP_H, MASK_CV_DOTUSP_H, match_opcode, 0},
+{"cv.dotusp.b",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_DOTUSP_B, MASK_CV_DOTUSP_B, match_opcode, 0},
+{"cv.dotusp.sc.h",        0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_DOTUSP_SC_H, MASK_CV_DOTUSP_SC_H, match_opcode, 0},
+{"cv.dotusp.sc.b",        0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_DOTUSP_SC_B, MASK_CV_DOTUSP_SC_B, match_opcode, 0},
+{"cv.dotusp.sci.h",       0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_DOTUSP_SCI_H, MASK_CV_DOTUSP_SCI_H, match_opcode, 0},
+{"cv.dotusp.sci.b",       0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_DOTUSP_SCI_B, MASK_CV_DOTUSP_SCI_B, match_opcode, 0},
+{"cv.dotsp.h",            0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_DOTSP_H, MASK_CV_DOTSP_H, match_opcode, 0},
+{"cv.dotsp.b",            0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_DOTSP_B, MASK_CV_DOTSP_B, match_opcode, 0},
+{"cv.dotsp.sc.h",         0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_DOTSP_SC_H, MASK_CV_DOTSP_SC_H, match_opcode, 0},
+{"cv.dotsp.sc.b",         0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_DOTSP_SC_B, MASK_CV_DOTSP_SC_B, match_opcode, 0},
+{"cv.dotsp.sci.h",        0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_DOTSP_SCI_H, MASK_CV_DOTSP_SCI_H, match_opcode, 0},
+{"cv.dotsp.sci.b",        0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_DOTSP_SCI_B, MASK_CV_DOTSP_SCI_B, match_opcode, 0},
+{"cv.sdotup.h",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SDOTUP_H, MASK_CV_SDOTUP_H, match_opcode, 0},
+{"cv.sdotup.b",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SDOTUP_B, MASK_CV_SDOTUP_B, match_opcode, 0},
+{"cv.sdotup.sc.h",        0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SDOTUP_SC_H, MASK_CV_SDOTUP_SC_H, match_opcode, 0},
+{"cv.sdotup.sc.b",        0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SDOTUP_SC_B, MASK_CV_SDOTUP_SC_B, match_opcode, 0},
+{"cv.sdotup.sci.h",       0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_SDOTUP_SCI_H, MASK_CV_SDOTUP_SCI_H, match_opcode, 0},
+{"cv.sdotup.sci.b",       0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_SDOTUP_SCI_B, MASK_CV_SDOTUP_SCI_B, match_opcode, 0},
+{"cv.sdotusp.h",          0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SDOTUSP_H, MASK_CV_SDOTUSP_H, match_opcode, 0},
+{"cv.sdotusp.b",          0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SDOTUSP_B, MASK_CV_SDOTUSP_B, match_opcode, 0},
+{"cv.sdotusp.sc.h",       0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SDOTUSP_SC_H, MASK_CV_SDOTUSP_SC_H, match_opcode, 0},
+{"cv.sdotusp.sc.b",       0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SDOTUSP_SC_B, MASK_CV_SDOTUSP_SC_B, match_opcode, 0},
+{"cv.sdotusp.sci.h",      0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_SDOTUSP_SCI_H, MASK_CV_SDOTUSP_SCI_H, match_opcode, 0},
+{"cv.sdotusp.sci.b",      0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_SDOTUSP_SCI_B, MASK_CV_SDOTUSP_SCI_B, match_opcode, 0},
+{"cv.sdotsp.h",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SDOTSP_H, MASK_CV_SDOTSP_H, match_opcode, 0},
+{"cv.sdotsp.b",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SDOTSP_B, MASK_CV_SDOTSP_B, match_opcode, 0},
+{"cv.sdotsp.sc.h",        0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SDOTSP_SC_H, MASK_CV_SDOTSP_SC_H, match_opcode, 0},
+{"cv.sdotsp.sc.b",        0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SDOTSP_SC_B, MASK_CV_SDOTSP_SC_B, match_opcode, 0},
+{"cv.sdotsp.sci.h",       0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_SDOTSP_SCI_H, MASK_CV_SDOTSP_SCI_H, match_opcode, 0},
+{"cv.sdotsp.sci.b",       0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_SDOTSP_SCI_B, MASK_CV_SDOTSP_SCI_B, match_opcode, 0},
+{"cv.extract.h",          0, INSN_CLASS_XCVSIMD, "d,s,b81", MATCH_CV_EXTRACT_H, MASK_CV_EXTRACT_H, match_opcode, 0},
+{"cv.extract.b",          0, INSN_CLASS_XCVSIMD, "d,s,b82", MATCH_CV_EXTRACT_B, MASK_CV_EXTRACT_B, match_opcode, 0},
+{"cv.extractu.h",         0, INSN_CLASS_XCVSIMD, "d,s,b81", MATCH_CV_EXTRACTU_H, MASK_CV_EXTRACTU_H, match_opcode, 0},
+{"cv.extractu.b",         0, INSN_CLASS_XCVSIMD, "d,s,b82", MATCH_CV_EXTRACTU_B, MASK_CV_EXTRACTU_B, match_opcode, 0},
+{"cv.insert.h",           0, INSN_CLASS_XCVSIMD, "d,s,b81", MATCH_CV_INSERT_H, MASK_CV_INSERT_H, match_opcode, 0},
+{"cv.insert.b",           0, INSN_CLASS_XCVSIMD, "d,s,b82", MATCH_CV_INSERT_B, MASK_CV_INSERT_B, match_opcode, 0},
+{"cv.shuffle.h",          0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SHUFFLE_H, MASK_CV_SHUFFLE_H, match_opcode, 0},
+{"cv.shuffle.b",          0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SHUFFLE_B, MASK_CV_SHUFFLE_B, match_opcode, 0},
+{"cv.shuffle.sci.h",      0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_SHUFFLE_SCI_H, MASK_CV_SHUFFLE_SCI_H, match_opcode, 0},
+{"cv.shufflei0.sci.b",    0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_SHUFFLEI0_SCI_B, MASK_CV_SHUFFLEI0_SCI_B, match_opcode, 0},
+{"cv.shufflei1.sci.b",    0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_SHUFFLEI1_SCI_B, MASK_CV_SHUFFLEI1_SCI_B, match_opcode, 0},
+{"cv.shufflei2.sci.b",    0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_SHUFFLEI2_SCI_B, MASK_CV_SHUFFLEI2_SCI_B, match_opcode, 0},
+{"cv.shufflei3.sci.b",    0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_SHUFFLEI3_SCI_B, MASK_CV_SHUFFLEI3_SCI_B, match_opcode, 0},
+{"cv.shuffle2.h",         0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SHUFFLE2_H, MASK_CV_SHUFFLE2_H, match_opcode, 0},
+{"cv.shuffle2.b",         0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SHUFFLE2_B, MASK_CV_SHUFFLE2_B, match_opcode, 0},
+{"cv.pack",               0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_PACK, MASK_CV_PACK, match_opcode, 0},
+{"cv.pack.h",             0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_PACK_H, MASK_CV_PACK_H, match_opcode, 0},
+{"cv.packhi.b",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_PACKHI_B, MASK_CV_PACKHI_B, match_opcode, 0},
+{"cv.packlo.b",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_PACKLO_B, MASK_CV_PACKLO_B, match_opcode, 0},
+{"cv.cmpeq.h",            0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPEQ_H, MASK_CV_CMPEQ_H, match_opcode, 0},
+{"cv.cmpeq.b",            0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPEQ_B, MASK_CV_CMPEQ_B, match_opcode, 0},
+{"cv.cmpeq.sc.h",         0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPEQ_SC_H, MASK_CV_CMPEQ_SC_H, match_opcode, 0},
+{"cv.cmpeq.sc.b",         0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPEQ_SC_B, MASK_CV_CMPEQ_SC_B, match_opcode, 0},
+{"cv.cmpeq.sci.h",        0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_CMPEQ_SCI_H, MASK_CV_CMPEQ_SCI_H, match_opcode, 0},
+{"cv.cmpeq.sci.b",        0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_CMPEQ_SCI_B, MASK_CV_CMPEQ_SCI_B, match_opcode, 0},
+{"cv.cmpne.h",            0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPNE_H, MASK_CV_CMPNE_H, match_opcode, 0},
+{"cv.cmpne.b",            0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPNE_B, MASK_CV_CMPNE_B, match_opcode, 0},
+{"cv.cmpne.sc.h",         0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPNE_SC_H, MASK_CV_CMPNE_SC_H, match_opcode, 0},
+{"cv.cmpne.sc.b",         0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPNE_SC_B, MASK_CV_CMPNE_SC_B, match_opcode, 0},
+{"cv.cmpne.sci.h",        0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_CMPNE_SCI_H, MASK_CV_CMPNE_SCI_H, match_opcode, 0},
+{"cv.cmpne.sci.b",        0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_CMPNE_SCI_B, MASK_CV_CMPNE_SCI_B, match_opcode, 0},
+{"cv.cmpgt.h",            0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPGT_H, MASK_CV_CMPGT_H, match_opcode, 0},
+{"cv.cmpgt.b",            0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPGT_B, MASK_CV_CMPGT_B, match_opcode, 0},
+{"cv.cmpgt.sc.h",         0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPGT_SC_H, MASK_CV_CMPGT_SC_H, match_opcode, 0},
+{"cv.cmpgt.sc.b",         0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPGT_SC_B, MASK_CV_CMPGT_SC_B, match_opcode, 0},
+{"cv.cmpgt.sci.h",        0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_CMPGT_SCI_H, MASK_CV_CMPGT_SCI_H, match_opcode, 0},
+{"cv.cmpgt.sci.b",        0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_CMPGT_SCI_B, MASK_CV_CMPGT_SCI_B, match_opcode, 0},
+{"cv.cmpge.h",            0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPGE_H, MASK_CV_CMPGE_H, match_opcode, 0},
+{"cv.cmpge.b",            0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPGE_B, MASK_CV_CMPGE_B, match_opcode, 0},
+{"cv.cmpge.sc.h",         0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPGE_SC_H, MASK_CV_CMPGE_SC_H, match_opcode, 0},
+{"cv.cmpge.sc.b",         0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPGE_SC_B, MASK_CV_CMPGE_SC_B, match_opcode, 0},
+{"cv.cmpge.sci.h",        0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_CMPGE_SCI_H, MASK_CV_CMPGE_SCI_H, match_opcode, 0},
+{"cv.cmpge.sci.b",        0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_CMPGE_SCI_B, MASK_CV_CMPGE_SCI_B, match_opcode, 0},
+{"cv.cmplt.h",            0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPLT_H, MASK_CV_CMPLT_H, match_opcode, 0},
+{"cv.cmplt.b",            0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPLT_B, MASK_CV_CMPLT_B, match_opcode, 0},
+{"cv.cmplt.sc.h",         0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPLT_SC_H, MASK_CV_CMPLT_SC_H, match_opcode, 0},
+{"cv.cmplt.sc.b",         0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPLT_SC_B, MASK_CV_CMPLT_SC_B, match_opcode, 0},
+{"cv.cmplt.sci.h",        0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_CMPLT_SCI_H, MASK_CV_CMPLT_SCI_H, match_opcode, 0},
+{"cv.cmplt.sci.b",        0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_CMPLT_SCI_B, MASK_CV_CMPLT_SCI_B, match_opcode, 0},
+{"cv.cmple.h",            0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPLE_H, MASK_CV_CMPLE_H, match_opcode, 0},
+{"cv.cmple.b",            0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPLE_B, MASK_CV_CMPLE_B, match_opcode, 0},
+{"cv.cmple.sc.h",         0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPLE_SC_H, MASK_CV_CMPLE_SC_H, match_opcode, 0},
+{"cv.cmple.sc.b",         0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPLE_SC_B, MASK_CV_CMPLE_SC_B, match_opcode, 0},
+{"cv.cmple.sci.h",        0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_CMPLE_SCI_H, MASK_CV_CMPLE_SCI_H, match_opcode, 0},
+{"cv.cmple.sci.b",        0, INSN_CLASS_XCVSIMD, "d,s,b5", MATCH_CV_CMPLE_SCI_B, MASK_CV_CMPLE_SCI_B, match_opcode, 0},
+{"cv.cmpgtu.h",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPGTU_H, MASK_CV_CMPGTU_H, match_opcode, 0},
+{"cv.cmpgtu.b",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPGTU_B, MASK_CV_CMPGTU_B, match_opcode, 0},
+{"cv.cmpgtu.sc.h",        0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPGTU_SC_H, MASK_CV_CMPGTU_SC_H, match_opcode, 0},
+{"cv.cmpgtu.sc.b",        0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPGTU_SC_B, MASK_CV_CMPGTU_SC_B, match_opcode, 0},
+{"cv.cmpgtu.sci.h",       0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_CMPGTU_SCI_H, MASK_CV_CMPGTU_SCI_H, match_opcode, 0},
+{"cv.cmpgtu.sci.b",       0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_CMPGTU_SCI_B, MASK_CV_CMPGTU_SCI_B, match_opcode, 0},
+{"cv.cmpgeu.h",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPGEU_H, MASK_CV_CMPGEU_H, match_opcode, 0},
+{"cv.cmpgeu.b",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPGEU_B, MASK_CV_CMPGEU_B, match_opcode, 0},
+{"cv.cmpgeu.sc.h",        0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPGEU_SC_H, MASK_CV_CMPGEU_SC_H, match_opcode, 0},
+{"cv.cmpgeu.sc.b",        0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPGEU_SC_B, MASK_CV_CMPGEU_SC_B, match_opcode, 0},
+{"cv.cmpgeu.sci.h",       0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_CMPGEU_SCI_H, MASK_CV_CMPGEU_SCI_H, match_opcode, 0},
+{"cv.cmpgeu.sci.b",       0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_CMPGEU_SCI_B, MASK_CV_CMPGEU_SCI_B, match_opcode, 0},
+{"cv.cmpltu.h",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPLTU_H, MASK_CV_CMPLTU_H, match_opcode, 0},
+{"cv.cmpltu.b",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPLTU_B, MASK_CV_CMPLTU_B, match_opcode, 0},
+{"cv.cmpltu.sc.h",        0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPLTU_SC_H, MASK_CV_CMPLTU_SC_H, match_opcode, 0},
+{"cv.cmpltu.sc.b",        0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPLTU_SC_B, MASK_CV_CMPLTU_SC_B, match_opcode, 0},
+{"cv.cmpltu.sci.h",       0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_CMPLTU_SCI_H, MASK_CV_CMPLTU_SCI_H, match_opcode, 0},
+{"cv.cmpltu.sci.b",       0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_CMPLTU_SCI_B, MASK_CV_CMPLTU_SCI_B, match_opcode, 0},
+{"cv.cmpleu.h",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPLEU_H, MASK_CV_CMPLEU_H, match_opcode, 0},
+{"cv.cmpleu.b",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPLEU_B, MASK_CV_CMPLEU_B, match_opcode, 0},
+{"cv.cmpleu.sc.h",        0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPLEU_SC_H, MASK_CV_CMPLEU_SC_H, match_opcode, 0},
+{"cv.cmpleu.sc.b",        0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CMPLEU_SC_B, MASK_CV_CMPLEU_SC_B, match_opcode, 0},
+{"cv.cmpleu.sci.h",       0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_CMPLEU_SCI_H, MASK_CV_CMPLEU_SCI_H, match_opcode, 0},
+{"cv.cmpleu.sci.b",       0, INSN_CLASS_XCVSIMD, "d,s,b8", MATCH_CV_CMPLEU_SCI_B, MASK_CV_CMPLEU_SCI_B, match_opcode, 0},
+{"cv.cplxmul.r",          0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CPLXMUL_R, MASK_CV_CPLXMUL_R, match_opcode, 0},
+{"cv.cplxmul.i",          0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CPLXMUL_I, MASK_CV_CPLXMUL_I, match_opcode, 0},
+{"cv.cplxmul.r.div2",     0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CPLXMUL_R_DIV2, MASK_CV_CPLXMUL_R_DIV2, match_opcode, 0},
+{"cv.cplxmul.i.div2",     0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CPLXMUL_I_DIV2, MASK_CV_CPLXMUL_I_DIV2, match_opcode, 0},
+{"cv.cplxmul.r.div4",     0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CPLXMUL_R_DIV4, MASK_CV_CPLXMUL_R_DIV4, match_opcode, 0},
+{"cv.cplxmul.i.div4",     0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CPLXMUL_I_DIV4, MASK_CV_CPLXMUL_I_DIV4, match_opcode, 0},
+{"cv.cplxmul.r.div8",     0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CPLXMUL_R_DIV8, MASK_CV_CPLXMUL_R_DIV8, match_opcode, 0},
+{"cv.cplxmul.i.div8",     0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_CPLXMUL_I_DIV8, MASK_CV_CPLXMUL_I_DIV8, match_opcode, 0},
+{"cv.cplxconj",           0, INSN_CLASS_XCVSIMD, "d,s",   MATCH_CV_CPLXCONJ, MASK_CV_CPLXCONJ, match_opcode, 0},
+{"cv.subrotmj",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SUBROTMJ, MASK_CV_SUBROTMJ, match_opcode, 0},
+{"cv.subrotmj.div2",      0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SUBROTMJ_DIV2, MASK_CV_SUBROTMJ_DIV2, match_opcode, 0},
+{"cv.subrotmj.div4",      0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SUBROTMJ_DIV4, MASK_CV_SUBROTMJ_DIV4, match_opcode, 0},
+{"cv.subrotmj.div8",      0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SUBROTMJ_DIV8, MASK_CV_SUBROTMJ_DIV8, match_opcode, 0},
+{"cv.add.div2",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_ADD_DIV2, MASK_CV_ADD_DIV2, match_opcode, 0},
+{"cv.add.div4",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_ADD_DIV4, MASK_CV_ADD_DIV4, match_opcode, 0},
+{"cv.add.div8",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_ADD_DIV8, MASK_CV_ADD_DIV8, match_opcode, 0},
+{"cv.sub.div2",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SUB_DIV2, MASK_CV_SUB_DIV2, match_opcode, 0},
+{"cv.sub.div4",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SUB_DIV4, MASK_CV_SUB_DIV4, match_opcode, 0},
+{"cv.sub.div8",           0, INSN_CLASS_XCVSIMD, "d,s,t", MATCH_CV_SUB_DIV8, MASK_CV_SUB_DIV8, match_opcode, 0},
+
 /* Vendor-specific (T-Head) XTheadBa instructions.  */
 {"th.addsl",    0, INSN_CLASS_XTHEADBA,    "d,s,t,Xtu2@25",   MATCH_TH_ADDSL,    MASK_TH_ADDSL,    match_opcode, 0},
 
-- 
2.34.1