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* [PATCH 0/1] RISC-V: Support CORE-V XCVSIMD extension
@ 2024-02-08 22:15 mary.bennett682
  2024-02-08 22:15 ` [PATCH 1/1] RISC-V: Add support for XCVsimd extension in CV32E40Pv2 mary.bennett682
  0 siblings, 1 reply; 2+ messages in thread
From: mary.bennett682 @ 2024-02-08 22:15 UTC (permalink / raw)
  To: binutils; +Cc: mary.bennett682

Thank you for reviewing this patch. I do not have merge permissions. If
all looks good, please merge on my behalf.

This patch series presents the comprehensive implementation of the SIMD
extension for CORE-V.

Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
ensure its correctness and compatibility with the existing codebase.
However, your input, reviews, and suggestions are invaluable in making this
extension even more robust.

The CORE-V instructions are described in the specification [1] and work can be
found in the OpenHW group's Github repository [2].

[1] docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html

[2] github.com/openhwgroup/corev-binutils-gdb

Contributors:
  Mary Bennett <mary.bennett@embecosm.com>
  Nandni Jamnadas <nandni.jamnadas@embecosm.com>
  Pietra Ferreira <pietra.ferreira@embecosm.com>
  Charlie Keaney
  Jessica Mills
  Craig Blackmore <craig.blackmore@embecosm.com>
  Simon Cook <simon.cook@embecosm.com>
  Jeremy Bennett <jeremy.bennett@embecosm.com>
  Helene Chelin <helene.chelin@embecosm.com>

RISC-V: Add support for XCVsimd extension in CV32E40Pv2

 bfd/elfxx-riscv.c                             |   5 +
 gas/config/tc-riscv.c                         |  96 +++-
 gas/doc/c-riscv.texi                          |   5 +
 gas/testsuite/gas/riscv/cv-simd-abs-b-fail.d  |   3 +
 gas/testsuite/gas/riscv/cv-simd-abs-b-fail.l  |   3 +
 gas/testsuite/gas/riscv/cv-simd-abs-b-fail.s  |   4 +
 gas/testsuite/gas/riscv/cv-simd-abs-b-pass.d  |  16 +
 gas/testsuite/gas/riscv/cv-simd-abs-b-pass.s  |   8 +
 gas/testsuite/gas/riscv/cv-simd-abs-h-fail.d  |   3 +
 gas/testsuite/gas/riscv/cv-simd-abs-h-fail.l  |   3 +
 gas/testsuite/gas/riscv/cv-simd-abs-h-fail.s  |   4 +
 gas/testsuite/gas/riscv/cv-simd-abs-h-pass.d  |  16 +
 gas/testsuite/gas/riscv/cv-simd-abs-h-pass.s  |   8 +
 gas/testsuite/gas/riscv/cv-simd-add-b-fail.d  |   3 +
 gas/testsuite/gas/riscv/cv-simd-add-b-fail.l  |   3 +
 gas/testsuite/gas/riscv/cv-simd-add-b-fail.s  |   4 +
 gas/testsuite/gas/riscv/cv-simd-add-b-pass.d  |  16 +
 gas/testsuite/gas/riscv/cv-simd-add-b-pass.s  |   8 +
 .../gas/riscv/cv-simd-add-div2-fail.d         |   3 +
 .../gas/riscv/cv-simd-add-div2-fail.l         |   3 +
 .../gas/riscv/cv-simd-add-div2-fail.s         |   4 +
 .../gas/riscv/cv-simd-add-div2-pass.d         |  16 +
 .../gas/riscv/cv-simd-add-div2-pass.s         |   8 +
 .../gas/riscv/cv-simd-add-div4-fail.d         |   3 +
 .../gas/riscv/cv-simd-add-div4-fail.l         |   3 +
 .../gas/riscv/cv-simd-add-div4-fail.s         |   4 +
 .../gas/riscv/cv-simd-add-div4-pass.d         |  16 +
 .../gas/riscv/cv-simd-add-div4-pass.s         |   8 +
 .../gas/riscv/cv-simd-add-div8-fail.d         |   3 +
 .../gas/riscv/cv-simd-add-div8-fail.l         |   3 +
 .../gas/riscv/cv-simd-add-div8-fail.s         |   4 +
 .../gas/riscv/cv-simd-add-div8-pass.d         |  16 +
 .../gas/riscv/cv-simd-add-div8-pass.s         |   8 +
 gas/testsuite/gas/riscv/cv-simd-add-h-fail.d  |   3 +
 gas/testsuite/gas/riscv/cv-simd-add-h-fail.l  |   3 +
 gas/testsuite/gas/riscv/cv-simd-add-h-fail.s  |   4 +
 gas/testsuite/gas/riscv/cv-simd-add-h-pass.d  |  15 +
 gas/testsuite/gas/riscv/cv-simd-add-h-pass.s  |   8 +
 .../gas/riscv/cv-simd-add-sc-b-fail.d         |   3 +
 .../gas/riscv/cv-simd-add-sc-b-fail.l         |   3 +
 .../gas/riscv/cv-simd-add-sc-b-fail.s         |   4 +
 .../gas/riscv/cv-simd-add-sc-b-pass.d         |  16 +
 .../gas/riscv/cv-simd-add-sc-b-pass.s         |   8 +
 .../gas/riscv/cv-simd-add-sc-h-fail.d         |   3 +
 .../gas/riscv/cv-simd-add-sc-h-fail.l         |   3 +
 .../gas/riscv/cv-simd-add-sc-h-fail.s         |   4 +
 .../gas/riscv/cv-simd-add-sc-h-pass.d         |  16 +
 .../gas/riscv/cv-simd-add-sc-h-pass.s         |   8 +
 .../gas/riscv/cv-simd-add-sci-b-fail.d        |   3 +
 .../gas/riscv/cv-simd-add-sci-b-fail.l        |   5 +
 .../gas/riscv/cv-simd-add-sci-b-fail.s        |   7 +
 .../gas/riscv/cv-simd-add-sci-b-pass.d        |  19 +
 .../gas/riscv/cv-simd-add-sci-b-pass.s        |  12 +
 .../gas/riscv/cv-simd-add-sci-h-fail.d        |   3 +
 .../gas/riscv/cv-simd-add-sci-h-fail.l        |   5 +
 .../gas/riscv/cv-simd-add-sci-h-fail.s        |   7 +
 .../gas/riscv/cv-simd-add-sci-h-pass.d        |  19 +
 .../gas/riscv/cv-simd-add-sci-h-pass.s        |  12 +
 gas/testsuite/gas/riscv/cv-simd-and-b-fail.d  |   3 +
 gas/testsuite/gas/riscv/cv-simd-and-b-fail.l  |   3 +
 gas/testsuite/gas/riscv/cv-simd-and-b-fail.s  |   4 +
 gas/testsuite/gas/riscv/cv-simd-and-b-pass.d  |  16 +
 gas/testsuite/gas/riscv/cv-simd-and-b-pass.s  |   8 +
 gas/testsuite/gas/riscv/cv-simd-and-h-fail.d  |   3 +
 gas/testsuite/gas/riscv/cv-simd-and-h-fail.l  |   3 +
 gas/testsuite/gas/riscv/cv-simd-and-h-fail.s  |   4 +
 gas/testsuite/gas/riscv/cv-simd-and-h-pass.d  |  16 +
 gas/testsuite/gas/riscv/cv-simd-and-h-pass.s  |   8 +
 .../gas/riscv/cv-simd-and-sc-b-fail.d         |   3 +
 .../gas/riscv/cv-simd-and-sc-b-fail.l         |   3 +
 .../gas/riscv/cv-simd-and-sc-b-fail.s         |   4 +
 .../gas/riscv/cv-simd-and-sc-b-pass.d         |  16 +
 .../gas/riscv/cv-simd-and-sc-b-pass.s         |   8 +
 .../gas/riscv/cv-simd-and-sc-h-fail.d         |   3 +
 .../gas/riscv/cv-simd-and-sc-h-fail.l         |   3 +
 .../gas/riscv/cv-simd-and-sc-h-fail.s         |   4 +
 .../gas/riscv/cv-simd-and-sc-h-pass.d         |  16 +
 .../gas/riscv/cv-simd-and-sc-h-pass.s         |   8 +
 .../gas/riscv/cv-simd-and-sci-b-fail.d        |   3 +
 .../gas/riscv/cv-simd-and-sci-b-fail.l        |   5 +
 .../gas/riscv/cv-simd-and-sci-b-fail.s        |   7 +
 .../gas/riscv/cv-simd-and-sci-b-pass.d        |  19 +
 .../gas/riscv/cv-simd-and-sci-b-pass.s        |  12 +
 .../gas/riscv/cv-simd-and-sci-h-fail.d        |   3 +
 .../gas/riscv/cv-simd-and-sci-h-fail.l        |   5 +
 .../gas/riscv/cv-simd-and-sci-h-fail.s        |   7 +
 .../gas/riscv/cv-simd-and-sci-h-pass.d        |  19 +
 .../gas/riscv/cv-simd-and-sci-h-pass.s        |  12 +
 gas/testsuite/gas/riscv/cv-simd-avg-b-fail.d  |   3 +
 gas/testsuite/gas/riscv/cv-simd-avg-b-fail.l  |   3 +
 gas/testsuite/gas/riscv/cv-simd-avg-b-fail.s  |   4 +
 gas/testsuite/gas/riscv/cv-simd-avg-b-pass.d  |  16 +
 gas/testsuite/gas/riscv/cv-simd-avg-b-pass.s  |   8 +
 gas/testsuite/gas/riscv/cv-simd-avg-h-fail.d  |   3 +
 gas/testsuite/gas/riscv/cv-simd-avg-h-fail.l  |   3 +
 gas/testsuite/gas/riscv/cv-simd-avg-h-fail.s  |   4 +
 gas/testsuite/gas/riscv/cv-simd-avg-h-pass.d  |  16 +
 gas/testsuite/gas/riscv/cv-simd-avg-h-pass.s  |   8 +
 .../gas/riscv/cv-simd-avg-sc-b-fail.d         |   3 +
 .../gas/riscv/cv-simd-avg-sc-b-fail.l         |   3 +
 .../gas/riscv/cv-simd-avg-sc-b-fail.s         |   4 +
 .../gas/riscv/cv-simd-avg-sc-b-pass.d         |  16 +
 .../gas/riscv/cv-simd-avg-sc-b-pass.s         |   8 +
 .../gas/riscv/cv-simd-avg-sc-h-fail.d         |   3 +
 .../gas/riscv/cv-simd-avg-sc-h-fail.l         |   3 +
 .../gas/riscv/cv-simd-avg-sc-h-fail.s         |   4 +
 .../gas/riscv/cv-simd-avg-sc-h-pass.d         |  16 +
 .../gas/riscv/cv-simd-avg-sc-h-pass.s         |   8 +
 .../gas/riscv/cv-simd-avg-sci-b-fail.d        |   3 +
 .../gas/riscv/cv-simd-avg-sci-b-fail.l        |   5 +
 .../gas/riscv/cv-simd-avg-sci-b-fail.s        |   7 +
 .../gas/riscv/cv-simd-avg-sci-b-pass.d        |  19 +
 .../gas/riscv/cv-simd-avg-sci-b-pass.s        |  12 +
 .../gas/riscv/cv-simd-avg-sci-h-fail.d        |   3 +
 .../gas/riscv/cv-simd-avg-sci-h-fail.l        |   5 +
 .../gas/riscv/cv-simd-avg-sci-h-fail.s        |   7 +
 .../gas/riscv/cv-simd-avg-sci-h-pass.d        |  19 +
 .../gas/riscv/cv-simd-avg-sci-h-pass.s        |  12 +
 gas/testsuite/gas/riscv/cv-simd-avgu-b-fail.d |   3 +
 gas/testsuite/gas/riscv/cv-simd-avgu-b-fail.l |   3 +
 gas/testsuite/gas/riscv/cv-simd-avgu-b-fail.s |   4 +
 gas/testsuite/gas/riscv/cv-simd-avgu-b-pass.d |  16 +
 gas/testsuite/gas/riscv/cv-simd-avgu-b-pass.s |   8 +
 gas/testsuite/gas/riscv/cv-simd-avgu-h-fail.d |   3 +
 gas/testsuite/gas/riscv/cv-simd-avgu-h-fail.l |   3 +
 gas/testsuite/gas/riscv/cv-simd-avgu-h-fail.s |   4 +
 gas/testsuite/gas/riscv/cv-simd-avgu-h-pass.d |  16 +
 gas/testsuite/gas/riscv/cv-simd-avgu-h-pass.s |   8 +
 .../gas/riscv/cv-simd-avgu-sc-b-fail.d        |   3 +
 .../gas/riscv/cv-simd-avgu-sc-b-fail.l        |   3 +
 .../gas/riscv/cv-simd-avgu-sc-b-fail.s        |   4 +
 .../gas/riscv/cv-simd-avgu-sc-b-pass.d        |  16 +
 .../gas/riscv/cv-simd-avgu-sc-b-pass.s        |   8 +
 .../gas/riscv/cv-simd-avgu-sc-h-fail.d        |   3 +
 .../gas/riscv/cv-simd-avgu-sc-h-fail.l        |   3 +
 .../gas/riscv/cv-simd-avgu-sc-h-fail.s        |   4 +
 .../gas/riscv/cv-simd-avgu-sc-h-pass.d        |  16 +
 .../gas/riscv/cv-simd-avgu-sc-h-pass.s        |   8 +
 .../gas/riscv/cv-simd-avgu-sci-b-fail.d       |   3 +
 .../gas/riscv/cv-simd-avgu-sci-b-fail.l       |   5 +
 .../gas/riscv/cv-simd-avgu-sci-b-fail.s       |   7 +
 .../gas/riscv/cv-simd-avgu-sci-b-pass.d       |  18 +
 .../gas/riscv/cv-simd-avgu-sci-b-pass.s       |  11 +
 .../gas/riscv/cv-simd-avgu-sci-h-fail.d       |   3 +
 .../gas/riscv/cv-simd-avgu-sci-h-fail.l       |   5 +
 .../gas/riscv/cv-simd-avgu-sci-h-fail.s       |   7 +
 .../gas/riscv/cv-simd-avgu-sci-h-pass.d       |  18 +
 .../gas/riscv/cv-simd-avgu-sci-h-pass.s       |  11 +
 .../gas/riscv/cv-simd-cmpeq-b-fail.d          |   3 +
 .../gas/riscv/cv-simd-cmpeq-b-fail.l          |   3 +
 .../gas/riscv/cv-simd-cmpeq-b-fail.s          |   4 +
 .../gas/riscv/cv-simd-cmpeq-b-pass.d          |  16 +
 .../gas/riscv/cv-simd-cmpeq-b-pass.s          |   8 +
 .../gas/riscv/cv-simd-cmpeq-h-fail.d          |   3 +
 .../gas/riscv/cv-simd-cmpeq-h-fail.l          |   3 +
 .../gas/riscv/cv-simd-cmpeq-h-fail.s          |   4 +
 .../gas/riscv/cv-simd-cmpeq-h-pass.d          |  16 +
 .../gas/riscv/cv-simd-cmpeq-h-pass.s          |   8 +
 .../gas/riscv/cv-simd-cmpeq-sc-b-fail.d       |   3 +
 .../gas/riscv/cv-simd-cmpeq-sc-b-fail.l       |   3 +
 .../gas/riscv/cv-simd-cmpeq-sc-b-fail.s       |   4 +
 .../gas/riscv/cv-simd-cmpeq-sc-b-pass.d       |  16 +
 .../gas/riscv/cv-simd-cmpeq-sc-b-pass.s       |   8 +
 .../gas/riscv/cv-simd-cmpeq-sc-h-fail.d       |   3 +
 .../gas/riscv/cv-simd-cmpeq-sc-h-fail.l       |   3 +
 .../gas/riscv/cv-simd-cmpeq-sc-h-fail.s       |   4 +
 .../gas/riscv/cv-simd-cmpeq-sc-h-pass.d       |  16 +
 .../gas/riscv/cv-simd-cmpeq-sc-h-pass.s       |   8 +
 .../gas/riscv/cv-simd-cmpeq-sci-b-fail.d      |   3 +
 .../gas/riscv/cv-simd-cmpeq-sci-b-fail.l      |   5 +
 .../gas/riscv/cv-simd-cmpeq-sci-b-fail.s      |   7 +
 .../gas/riscv/cv-simd-cmpeq-sci-b-pass.d      |  19 +
 .../gas/riscv/cv-simd-cmpeq-sci-b-pass.s      |  12 +
 .../gas/riscv/cv-simd-cmpeq-sci-h-fail.d      |   3 +
 .../gas/riscv/cv-simd-cmpeq-sci-h-fail.l      |   5 +
 .../gas/riscv/cv-simd-cmpeq-sci-h-fail.s      |   7 +
 .../gas/riscv/cv-simd-cmpeq-sci-h-pass.d      |  19 +
 .../gas/riscv/cv-simd-cmpeq-sci-h-pass.s      |  12 +
 .../gas/riscv/cv-simd-cmpge-b-fail.d          |   3 +
 .../gas/riscv/cv-simd-cmpge-b-fail.l          |   3 +
 .../gas/riscv/cv-simd-cmpge-b-fail.s          |   4 +
 .../gas/riscv/cv-simd-cmpge-b-pass.d          |  16 +
 .../gas/riscv/cv-simd-cmpge-b-pass.s          |   8 +
 .../gas/riscv/cv-simd-cmpge-h-fail.d          |   3 +
 .../gas/riscv/cv-simd-cmpge-h-fail.l          |   3 +
 .../gas/riscv/cv-simd-cmpge-h-fail.s          |   4 +
 .../gas/riscv/cv-simd-cmpge-h-pass.d          |  16 +
 .../gas/riscv/cv-simd-cmpge-h-pass.s          |   8 +
 .../gas/riscv/cv-simd-cmpge-sc-b-fail.d       |   3 +
 .../gas/riscv/cv-simd-cmpge-sc-b-fail.l       |   3 +
 .../gas/riscv/cv-simd-cmpge-sc-b-fail.s       |   4 +
 .../gas/riscv/cv-simd-cmpge-sc-b-pass.d       |  16 +
 .../gas/riscv/cv-simd-cmpge-sc-b-pass.s       |   8 +
 .../gas/riscv/cv-simd-cmpge-sc-h-fail.d       |   3 +
 .../gas/riscv/cv-simd-cmpge-sc-h-fail.l       |   3 +
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 .../gas/riscv/cv-simd-cmpge-sc-h-pass.d       |  16 +
 .../gas/riscv/cv-simd-cmpge-sc-h-pass.s       |   8 +
 .../gas/riscv/cv-simd-cmpge-sci-b-fail.d      |   3 +
 .../gas/riscv/cv-simd-cmpge-sci-b-fail.l      |   5 +
 .../gas/riscv/cv-simd-cmpge-sci-b-fail.s      |   7 +
 .../gas/riscv/cv-simd-cmpge-sci-b-pass.d      |  19 +
 .../gas/riscv/cv-simd-cmpge-sci-b-pass.s      |  12 +
 .../gas/riscv/cv-simd-cmpge-sci-h-fail.d      |   3 +
 .../gas/riscv/cv-simd-cmpge-sci-h-fail.l      |   5 +
 .../gas/riscv/cv-simd-cmpge-sci-h-fail.s      |   7 +
 .../gas/riscv/cv-simd-cmpge-sci-h-pass.d      |  19 +
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 .../gas/riscv/cv-simd-cmpgeu-b-fail.d         |   3 +
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 .../gas/riscv/cv-simd-cmpgeu-h-fail.d         |   3 +
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 .../gas/riscv/cv-simd-cmpgeu-h-pass.d         |  16 +
 .../gas/riscv/cv-simd-cmpgeu-h-pass.s         |   8 +
 .../gas/riscv/cv-simd-cmpgeu-sc-b-fail.d      |   3 +
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 .../gas/riscv/cv-simd-cmpgt-b-fail.d          |   3 +
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 .../gas/riscv/cv-simd-cmpgt-h-fail.d          |   3 +
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 .../gas/riscv/cv-simd-cmpgt-sc-h-fail.d       |   3 +
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 .../gas/riscv/cv-simd-cmpgt-sc-h-fail.s       |   4 +
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 .../gas/riscv/cv-simd-xor-sci-h-pass.s        |  12 +
 include/opcode/riscv-opc.h                    | 443 ++++++++++++++++++
 include/opcode/riscv.h                        |  14 +
 opcodes/riscv-dis.c                           |  22 +
 opcodes/riscv-opc.c                           | 222 +++++++++
 1112 files changed, 9963 insertions(+), 1 deletion(-)
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 create mode 100644 gas/testsuite/gas/riscv/cv-simd-srl-sci-b-fail.l
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-srl-sci-b-fail.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-srl-sci-b-pass.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-srl-sci-b-pass.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-srl-sci-h-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-srl-sci-h-fail.l
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-srl-sci-h-fail.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-srl-sci-h-pass.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-srl-sci-h-pass.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-b-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-b-fail.l
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-b-fail.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-b-pass.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-b-pass.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-div2-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-div2-fail.l
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 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-div2-pass.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-div2-pass.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-div4-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-div4-fail.l
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-div4-fail.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-div4-pass.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-div4-pass.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-div8-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-div8-fail.l
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-div8-fail.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-div8-pass.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-div8-pass.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-h-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-h-fail.l
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 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-h-pass.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-h-pass.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-sc-b-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-sc-b-fail.l
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-sc-b-fail.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-sc-b-pass.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-sc-b-pass.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-sc-h-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-sc-h-fail.l
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-sc-h-fail.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-sc-h-pass.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-sc-h-pass.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-sci-b-fail.d
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 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-sci-h-fail.d
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 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-sci-h-pass.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-sci-h-pass.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-subrotmj-div2-fail.d
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 create mode 100644 gas/testsuite/gas/riscv/cv-simd-subrotmj-div8-fail.d
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 create mode 100644 gas/testsuite/gas/riscv/cv-simd-subrotmj-pass.d
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 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-b-fail.d
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 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-b-pass.d
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 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-h-fail.d
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 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-h-pass.d
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 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sc-b-fail.d
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 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sc-b-pass.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sc-b-pass.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sc-h-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sc-h-fail.l
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sc-h-fail.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sc-h-pass.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sc-h-pass.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sci-b-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sci-b-fail.l
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sci-b-fail.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sci-b-pass.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sci-b-pass.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sci-h-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sci-h-fail.l
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sci-h-fail.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sci-h-pass.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sci-h-pass.s

-- 
2.34.1


^ permalink raw reply	[flat|nested] 2+ messages in thread

* [PATCH 1/1] RISC-V: Add support for XCVsimd extension in CV32E40Pv2
  2024-02-08 22:15 [PATCH 0/1] RISC-V: Support CORE-V XCVSIMD extension mary.bennett682
@ 2024-02-08 22:15 ` mary.bennett682
  0 siblings, 0 replies; 2+ messages in thread
From: mary.bennett682 @ 2024-02-08 22:15 UTC (permalink / raw)
  To: binutils; +Cc: mary.bennett682

Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html

Contributors:
  Mary Bennett <mary.bennett@embecosm.com>
  Nandni Jamnadas <nandni.jamnadas@embecosm.com>
  Pietra Ferreira <pietra.ferreira@embecosm.com>
  Charlie Keaney
  Jessica Mills
  Craig Blackmore <craig.blackmore@embecosm.com>
  Simon Cook <simon.cook@embecosm.com>
  Jeremy Bennett <jeremy.bennett@embecosm.com>
  Helene Chelin <helene.chelin@embecosm.com>

bfd/ChangeLog:

        * elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvsimd`
          instruction class.
        (riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

        * doc/c-riscv.texi: Note XCVsimd as an additional ISA extension
          for CORE-V.
	* config/tc-riscv.c: Add new operands b4, b5 and b8.
 	* testsuite/gas/riscv/cv-simd-abs-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-abs-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-abs-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-abs-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-abs-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-abs-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-abs-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-abs-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-abs-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-abs-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-add-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-add-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-add-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-add-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-add-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-add-div2-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-add-div2-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-add-div2-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-add-div2-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-add-div2-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-add-div4-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-add-div4-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-add-div4-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-add-div4-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-add-div4-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-add-div8-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-add-div8-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-add-div8-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-add-div8-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-add-div8-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-add-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-add-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-add-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-add-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-add-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-add-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-add-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-add-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-add-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-add-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-add-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-add-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-add-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-add-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-add-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-add-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-add-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-add-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-add-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-add-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-add-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-add-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-add-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-add-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-add-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-and-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-and-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-and-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-and-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-and-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-and-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-and-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-and-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-and-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-and-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-and-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-and-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-and-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-and-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-and-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-and-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-and-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-and-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-and-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-and-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-and-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-and-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-and-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-and-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-and-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-and-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-and-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-and-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-and-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-and-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-avg-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-avg-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-avg-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-avg-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-avg-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-avg-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-avg-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-avg-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-avg-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-avg-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-avg-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-avg-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-avg-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-avg-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-avg-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-avg-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-avg-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-avg-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-avg-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-avg-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-avg-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-avg-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-avg-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-avg-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-avg-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-avg-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-avg-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-avg-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-avg-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-avg-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-avgu-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpeq-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpge-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgt-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmple-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpleu-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmplt-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpltu-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cmpne-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cplxconj-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cplxconj-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cplxconj-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cplxconj-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cplxconj-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-i-div2-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-i-div2-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-i-div2-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-i-div2-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-i-div2-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-i-div4-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-i-div4-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-i-div4-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-i-div4-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-i-div4-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-i-div8-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-i-div8-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-i-div8-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-i-div8-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-i-div8-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-i-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-i-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-i-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-i-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-i-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-r-div2-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-r-div2-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-r-div2-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-r-div2-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-r-div2-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-r-div4-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-r-div4-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-r-div4-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-r-div4-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-r-div4-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-r-div8-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-r-div8-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-r-div8-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-r-div8-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-r-div8-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-r-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-r-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-r-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-r-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-cplxmul-r-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotsp-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotup-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-dotusp-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-extract-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-extract-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-extract-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-extract-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-extract-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-extract-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-extract-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-extract-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-extract-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-extract-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-extractu-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-extractu-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-extractu-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-extractu-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-extractu-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-extractu-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-extractu-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-extractu-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-extractu-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-extractu-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-insert-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-insert-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-insert-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-insert-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-insert-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-insert-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-insert-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-insert-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-insert-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-insert-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-march-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-march-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-march-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-march-xcvsimd.d
 	* testsuite/gas/riscv/cv-simd-march-xcvsimd.s
 	* testsuite/gas/riscv/cv-simd-max-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-max-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-max-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-max-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-max-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-max-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-max-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-max-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-max-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-max-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-max-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-max-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-max-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-max-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-max-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-max-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-max-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-max-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-max-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-max-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-max-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-max-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-max-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-max-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-max-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-max-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-max-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-max-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-max-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-max-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-maxu-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-min-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-min-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-min-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-min-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-min-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-min-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-min-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-min-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-min-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-min-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-min-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-min-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-min-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-min-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-min-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-min-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-min-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-min-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-min-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-min-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-min-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-min-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-min-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-min-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-min-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-min-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-min-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-min-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-min-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-min-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-minu-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-minu-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-minu-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-minu-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-minu-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-minu-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-minu-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-minu-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-minu-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-minu-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-minu-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-minu-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-minu-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-minu-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-minu-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-minu-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-minu-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-minu-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-minu-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-minu-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-minu-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-minu-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-minu-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-minu-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-minu-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-minu-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-minu-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-minu-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-minu-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-minu-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-or-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-or-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-or-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-or-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-or-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-or-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-or-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-or-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-or-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-or-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-or-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-or-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-or-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-or-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-or-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-or-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-or-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-or-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-or-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-or-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-or-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-or-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-or-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-or-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-or-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-or-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-or-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-or-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-or-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-or-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-pack-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-pack-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-pack-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-pack-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-pack-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-pack-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-pack-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-pack-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-pack-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-pack-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-packhi-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-packhi-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-packhi-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-packhi-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-packhi-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-packlo-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-packlo-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-packlo-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-packlo-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-packlo-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotsp-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotup-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sdotusp-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle2-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle2-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle2-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle2-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle2-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle2-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle2-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle2-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle2-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-shuffle2-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-shufflei0-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-shufflei0-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-shufflei0-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-shufflei0-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-shufflei0-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-shufflei1-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-shufflei1-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-shufflei1-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-shufflei1-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-shufflei1-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-shufflei2-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-shufflei2-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-shufflei2-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-shufflei2-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-shufflei2-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-shufflei3-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-shufflei3-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-shufflei3-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-shufflei3-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-shufflei3-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sll-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sll-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sll-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sll-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sll-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sll-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sll-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sll-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sll-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sll-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sll-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sll-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sll-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sll-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sll-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sll-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sll-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sll-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sll-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sll-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sll-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sll-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sll-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sll-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sll-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sll-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sll-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sll-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sll-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sll-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sra-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sra-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sra-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sra-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sra-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sra-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sra-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sra-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sra-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sra-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sra-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sra-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sra-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sra-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sra-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sra-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sra-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sra-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sra-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sra-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sra-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sra-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sra-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sra-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sra-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sra-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sra-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sra-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sra-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sra-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-srl-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-srl-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-srl-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-srl-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-srl-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-srl-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-srl-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-srl-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-srl-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-srl-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-srl-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-srl-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-srl-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-srl-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-srl-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-srl-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-srl-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-srl-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-srl-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-srl-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-srl-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-srl-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-srl-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-srl-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-srl-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-srl-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-srl-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-srl-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-srl-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-srl-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sub-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sub-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sub-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sub-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sub-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sub-div2-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sub-div2-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sub-div2-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sub-div2-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sub-div2-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sub-div4-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sub-div4-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sub-div4-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sub-div4-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sub-div4-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sub-div8-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sub-div8-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sub-div8-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sub-div8-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sub-div8-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sub-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sub-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sub-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sub-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sub-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sub-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sub-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sub-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sub-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sub-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sub-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sub-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sub-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sub-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sub-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sub-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sub-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sub-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sub-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sub-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-sub-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-sub-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-sub-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-sub-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-sub-sci-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-subrotmj-div2-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-subrotmj-div2-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-subrotmj-div2-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-subrotmj-div2-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-subrotmj-div2-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-subrotmj-div4-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-subrotmj-div4-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-subrotmj-div4-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-subrotmj-div4-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-subrotmj-div4-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-subrotmj-div8-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-subrotmj-div8-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-subrotmj-div8-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-subrotmj-div8-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-subrotmj-div8-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-subrotmj-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-subrotmj-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-subrotmj-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-subrotmj-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-subrotmj-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-xor-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-xor-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-xor-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-xor-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-xor-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-xor-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-xor-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-xor-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-xor-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-xor-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-xor-sc-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-xor-sc-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-xor-sc-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-xor-sc-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-xor-sc-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-xor-sc-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-xor-sc-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-xor-sc-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-xor-sc-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-xor-sc-h-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-xor-sci-b-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-xor-sci-b-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-xor-sci-b-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-xor-sci-b-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-xor-sci-b-pass.s: New test.
 	* testsuite/gas/riscv/cv-simd-xor-sci-h-fail.d: New test.
 	* testsuite/gas/riscv/cv-simd-xor-sci-h-fail.l: New test.
 	* testsuite/gas/riscv/cv-simd-xor-sci-h-fail.s: New test.
 	* testsuite/gas/riscv/cv-simd-xor-sci-h-pass.d: New test.
 	* testsuite/gas/riscv/cv-simd-xor-sci-h-pass.s: New test.

include/ChangeLog:

        * opcode/riscv-opc.h: Add corresponding MATCH and MASK
          instruction opcode macros.
        * opcode/riscv.h (riscv_insn_class): Add INSN_CLASS_XCVSIMD.

opcodes/ChangeLog:

	* riscv-dis.c (print_insn_args): Add new operands.
        * riscv-opc.c (riscv_opcode): Add simd instructions.
---
 bfd/elfxx-riscv.c                             |   5 +
 gas/config/tc-riscv.c                         |  96 +++-
 gas/doc/c-riscv.texi                          |   5 +
 gas/testsuite/gas/riscv/cv-simd-abs-b-fail.d  |   3 +
 gas/testsuite/gas/riscv/cv-simd-abs-b-fail.l  |   3 +
 gas/testsuite/gas/riscv/cv-simd-abs-b-fail.s  |   4 +
 gas/testsuite/gas/riscv/cv-simd-abs-b-pass.d  |  16 +
 gas/testsuite/gas/riscv/cv-simd-abs-b-pass.s  |   8 +
 gas/testsuite/gas/riscv/cv-simd-abs-h-fail.d  |   3 +
 gas/testsuite/gas/riscv/cv-simd-abs-h-fail.l  |   3 +
 gas/testsuite/gas/riscv/cv-simd-abs-h-fail.s  |   4 +
 gas/testsuite/gas/riscv/cv-simd-abs-h-pass.d  |  16 +
 gas/testsuite/gas/riscv/cv-simd-abs-h-pass.s  |   8 +
 gas/testsuite/gas/riscv/cv-simd-add-b-fail.d  |   3 +
 gas/testsuite/gas/riscv/cv-simd-add-b-fail.l  |   3 +
 gas/testsuite/gas/riscv/cv-simd-add-b-fail.s  |   4 +
 gas/testsuite/gas/riscv/cv-simd-add-b-pass.d  |  16 +
 gas/testsuite/gas/riscv/cv-simd-add-b-pass.s  |   8 +
 .../gas/riscv/cv-simd-add-div2-fail.d         |   3 +
 .../gas/riscv/cv-simd-add-div2-fail.l         |   3 +
 .../gas/riscv/cv-simd-add-div2-fail.s         |   4 +
 .../gas/riscv/cv-simd-add-div2-pass.d         |  16 +
 .../gas/riscv/cv-simd-add-div2-pass.s         |   8 +
 .../gas/riscv/cv-simd-add-div4-fail.d         |   3 +
 .../gas/riscv/cv-simd-add-div4-fail.l         |   3 +
 .../gas/riscv/cv-simd-add-div4-fail.s         |   4 +
 .../gas/riscv/cv-simd-add-div4-pass.d         |  16 +
 .../gas/riscv/cv-simd-add-div4-pass.s         |   8 +
 .../gas/riscv/cv-simd-add-div8-fail.d         |   3 +
 .../gas/riscv/cv-simd-add-div8-fail.l         |   3 +
 .../gas/riscv/cv-simd-add-div8-fail.s         |   4 +
 .../gas/riscv/cv-simd-add-div8-pass.d         |  16 +
 .../gas/riscv/cv-simd-add-div8-pass.s         |   8 +
 gas/testsuite/gas/riscv/cv-simd-add-h-fail.d  |   3 +
 gas/testsuite/gas/riscv/cv-simd-add-h-fail.l  |   3 +
 gas/testsuite/gas/riscv/cv-simd-add-h-fail.s  |   4 +
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 include/opcode/riscv-opc.h                    | 443 ++++++++++++++++++
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 opcodes/riscv-dis.c                           |  22 +
 opcodes/riscv-opc.c                           | 222 +++++++++
 1112 files changed, 9963 insertions(+), 1 deletion(-)
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-abs-b-fail.d
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 create mode 100644 gas/testsuite/gas/riscv/cv-simd-abs-h-fail.d
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 create mode 100644 gas/testsuite/gas/riscv/cv-simd-add-b-fail.d
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 create mode 100644 gas/testsuite/gas/riscv/cv-simd-add-b-pass.d
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 create mode 100644 gas/testsuite/gas/riscv/cv-simd-add-div2-fail.d
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 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-sci-h-fail.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-sci-h-pass.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-sub-sci-h-pass.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-subrotmj-div2-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-subrotmj-div2-fail.l
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-subrotmj-div2-fail.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-subrotmj-div2-pass.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-subrotmj-div2-pass.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-subrotmj-div4-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-subrotmj-div4-fail.l
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-subrotmj-div4-fail.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-subrotmj-div4-pass.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-subrotmj-div4-pass.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-subrotmj-div8-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-subrotmj-div8-fail.l
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-subrotmj-div8-fail.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-subrotmj-div8-pass.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-subrotmj-div8-pass.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-subrotmj-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-subrotmj-fail.l
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-subrotmj-fail.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-subrotmj-pass.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-subrotmj-pass.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-b-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-b-fail.l
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-b-fail.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-b-pass.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-b-pass.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-h-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-h-fail.l
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-h-fail.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-h-pass.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-h-pass.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sc-b-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sc-b-fail.l
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sc-b-fail.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sc-b-pass.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sc-b-pass.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sc-h-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sc-h-fail.l
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sc-h-fail.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sc-h-pass.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sc-h-pass.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sci-b-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sci-b-fail.l
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sci-b-fail.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sci-b-pass.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sci-b-pass.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sci-h-fail.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sci-h-fail.l
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sci-h-fail.s
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sci-h-pass.d
 create mode 100644 gas/testsuite/gas/riscv/cv-simd-xor-sci-h-pass.s

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 9a121b47121..d0ecab02fed 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1369,6 +1369,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
 {
   {"xcvmac",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xcvalu",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
+  {"xcvsimd",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadba",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadbb",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadbs",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
@@ -2576,6 +2577,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "xcvmac");
     case INSN_CLASS_XCVALU:
       return riscv_subset_supports (rps, "xcvalu");
+    case INSN_CLASS_XCVSIMD:
+      return riscv_subset_supports (rps, "xcvsimd");
     case INSN_CLASS_XTHEADBA:
       return riscv_subset_supports (rps, "xtheadba");
     case INSN_CLASS_XTHEADBB:
@@ -2828,6 +2831,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return "xcvmac";
     case INSN_CLASS_XCVALU:
       return "xcvalu";
+    case INSN_CLASS_XCVSIMD:
+      return "xcvsimd";
     case INSN_CLASS_XTHEADBA:
       return "xtheadba";
     case INSN_CLASS_XTHEADBB:
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index a4161420128..ce55f46cdc5 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1373,6 +1373,24 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
 	case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
 	case 'A': break; /* Macro operand, must be symbol.  */
 	case 'B': break; /* Macro operand, must be symbol or constant.  */
+	case 'b': /* CORE-V Specific.  */
+	  if (oparg[1] == '4')
+	    {
+	      used_bits |= ENCODE_CV_UIMM5(-1U);
+	      ++oparg; break;
+	    }
+	  else if (oparg[1] == '5')
+	    {
+	      used_bits |= ENCODE_CV_SIMD_IMM6(-1U);
+	      ++oparg; break;
+	    }
+	  else if (oparg[1] == '8')
+	    {
+	      used_bits |= ENCODE_CV_SIMD_UIMM6(-1U);
+	      if (oparg[2] == '1' || oparg[2] == '2' || oparg[2] == '3' || oparg[2] == '4') ++oparg;
+	      ++oparg; break;
+	    }
+	  break;
 	case 'c': break; /* Macro operand, must be symbol or constant.  */
 	case 'I': break; /* Macro operand, must be constant.  */
 	case 'D': /* RD, floating point.  */
@@ -3361,7 +3379,83 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 	      *imm_reloc = BFD_RELOC_32;
 	      asarg = expr_parse_end;
 	      continue;
-
+	      /* CORE-V Specific.	 */
+	    case 'b':
+	      if (oparg[1] == '4')
+		{
+		  my_getExpression (imm_expr, asarg);
+		  check_absolute_expr (ip, imm_expr, FALSE);
+		  asarg = expr_parse_end;
+		  if (imm_expr->X_add_number<-16 || imm_expr->X_add_number>15)
+		  as_bad(_("immediate value must be 5-bit signed, %ld is out of range"),
+		  imm_expr->X_add_number);
+		  ip->insn_opcode |= ENCODE_CV_UIMM5 (imm_expr->X_add_number);
+		  ++oparg;
+		}
+	      else if (oparg[1] == '5')
+		// b5: imm6 bits signed immediate bits
+		{
+		  my_getExpression (imm_expr, asarg);
+		  check_absolute_expr (ip, imm_expr, FALSE);
+		  asarg = expr_parse_end;
+		  if (imm_expr->X_add_number<-32 || imm_expr->X_add_number>31)
+		  as_bad(_("immediate value must be 6-bit signed, %ld is out of range"),
+		  imm_expr->X_add_number);
+		  ip->insn_opcode |= ENCODE_CV_SIMD_IMM6 (imm_expr->X_add_number);
+		  ++oparg;
+		}
+	      else if (oparg[1] == '8')
+		// b8: uimm6 bits unsigned immediate bits
+		// b81: Imm6[0]
+		// b83: Imm6[2:0]
+		// b84: Imm6[3:0]
+		{
+		  my_getExpression (imm_expr, asarg);
+		  check_absolute_expr (ip, imm_expr, FALSE);
+		  asarg = expr_parse_end;
+		  if (oparg[2] == '1')
+		  {
+		    if (imm_expr->X_add_number<0 || imm_expr->X_add_number>1)
+		    as_bad(_("immediate value must be 1-bit unsigned, %ld is out of range"),
+		    imm_expr->X_add_number);
+		    ++oparg;
+		  }
+		  else if (oparg[2] == '2')
+		  {
+		    if (imm_expr->X_add_number<0 || imm_expr->X_add_number>3)
+		    as_bad(_("immediate value must be 2-bit unsigned, %ld is out of range"),
+		    imm_expr->X_add_number);
+		    ++oparg;
+		  }
+		  else if (oparg[2] == '3')
+		  {
+		    if (imm_expr->X_add_number<0 || imm_expr->X_add_number>7)
+		    as_bad(_("immediate value must be 3-bit unsigned, %ld is out of range"),
+		    imm_expr->X_add_number);
+		    ++oparg;
+		  }
+		  else if (oparg[2] == '4')
+		  {
+		    if (imm_expr->X_add_number<0 || imm_expr->X_add_number>15)
+		    as_bad(_("immediate value must be 4-bit unsigned, %ld is out of range"),
+		    imm_expr->X_add_number);
+		    ++oparg;
+		  }
+		  else
+		  {
+		    if (imm_expr->X_add_number<0 || imm_expr->X_add_number>63)
+		    as_bad(_("immediate value must be 6-bit unsigned, %ld is out of range"),
+		    imm_expr->X_add_number);
+		  }
+		  ip->insn_opcode |= ENCODE_CV_SIMD_UIMM6 (imm_expr->X_add_number);
+		  ++oparg;
+		}
+	      else
+		{
+		  my_getExpression (imm_expr, asarg);
+		  asarg = expr_parse_end;
+		}
+	      continue;
 	    case 'B':
 	      my_getExpression (imm_expr, asarg);
 	      normalize_constant_expr (imm_expr);
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 7484a71798a..f8c6bcd5f3d 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -750,6 +750,11 @@ The Xcvalu extension provides instructions for general ALU operations.
 
 It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
 
+@item Xcvsimd
+The Xcvsimd extension provides instructions for SIMD operations.
+
+It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
+
 @item XTheadBa
 The XTheadBa extension provides instructions for address calculations.
 
diff --git a/gas/testsuite/gas/riscv/cv-simd-abs-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-abs-b-fail.d
new file mode 100644
index 00000000000..d42b44dd49f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-abs-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-abs-b-fail.s
+#error_output: cv-simd-abs-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-abs-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-abs-b-fail.l
new file mode 100644
index 00000000000..93156ef3807
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-abs-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.abs.b x32,x32'
+.*: Error: illegal operands `cv.abs.b x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-abs-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-abs-b-fail.s
new file mode 100644
index 00000000000..77ae67f0daf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-abs-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.abs.b x32, x32
+    cv.abs.b x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-abs-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-abs-b-pass.d
new file mode 100644
index 00000000000..b50e9508bb4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-abs-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-abs-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	7000107b          	cv.abs.b	zero,zero
+   4:	700090fb          	cv.abs.b	ra,ra
+   8:	7001117b          	cv.abs.b	sp,sp
+   c:	7004147b          	cv.abs.b	s0,s0
+  10:	700a1a7b          	cv.abs.b	s4,s4
+  14:	700f9ffb          	cv.abs.b	t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-abs-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-abs-b-pass.s
new file mode 100644
index 00000000000..9e228305641
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-abs-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.abs.b x0, x0
+    cv.abs.b x1, x1
+    cv.abs.b x2, x2
+    cv.abs.b x8, x8
+    cv.abs.b x20, x20
+    cv.abs.b x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-abs-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-abs-h-fail.d
new file mode 100644
index 00000000000..b3938c89647
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-abs-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-abs-h-fail.s
+#error_output: cv-simd-abs-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-abs-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-abs-h-fail.l
new file mode 100644
index 00000000000..74867e1b611
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-abs-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.abs.h x32,x32'
+.*: Error: illegal operands `cv.abs.h x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-abs-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-abs-h-fail.s
new file mode 100644
index 00000000000..2e711546ce6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-abs-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.abs.h x32, x32
+    cv.abs.h x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-abs-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-abs-h-pass.d
new file mode 100644
index 00000000000..b8d09bb427f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-abs-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-abs-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	7000007b          	cv.abs.h	zero,zero
+   4:	700080fb          	cv.abs.h	ra,ra
+   8:	7001017b          	cv.abs.h	sp,sp
+   c:	7004047b          	cv.abs.h	s0,s0
+  10:	700a0a7b          	cv.abs.h	s4,s4
+  14:	700f8ffb          	cv.abs.h	t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-abs-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-abs-h-pass.s
new file mode 100644
index 00000000000..1d455699073
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-abs-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.abs.h x0, x0
+    cv.abs.h x1, x1
+    cv.abs.h x2, x2
+    cv.abs.h x8, x8
+    cv.abs.h x20, x20
+    cv.abs.h x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-add-b-fail.d
new file mode 100644
index 00000000000..1105a46a384
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-b-fail.s
+#error_output: cv-simd-add-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-add-b-fail.l
new file mode 100644
index 00000000000..e43a2c5536b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.add.b x32,x32,x32'
+.*: Error: illegal operands `cv.add.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-add-b-fail.s
new file mode 100644
index 00000000000..02b5c5d148f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.add.b x32, x32, x32
+    cv.add.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-add-b-pass.d
new file mode 100644
index 00000000000..371e0fb6af6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0000107b          	cv.add.b	zero,zero,zero
+   4:	001090fb          	cv.add.b	ra,ra,ra
+   8:	0021117b          	cv.add.b	sp,sp,sp
+   c:	0084147b          	cv.add.b	s0,s0,s0
+  10:	014a1a7b          	cv.add.b	s4,s4,s4
+  14:	01ff9ffb          	cv.add.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-add-b-pass.s
new file mode 100644
index 00000000000..77da5630aa8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.add.b x0, x0, x0
+    cv.add.b x1, x1, x1
+    cv.add.b x2, x2, x2
+    cv.add.b x8, x8, x8
+    cv.add.b x20, x20, x20
+    cv.add.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-div2-fail.d b/gas/testsuite/gas/riscv/cv-simd-add-div2-fail.d
new file mode 100644
index 00000000000..0430f5445d0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-div2-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-div2-fail.s
+#error_output: cv-simd-add-div2-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-div2-fail.l b/gas/testsuite/gas/riscv/cv-simd-add-div2-fail.l
new file mode 100644
index 00000000000..aaf581ef21d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-div2-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.add.div2 x32,x32,x32'
+.*: Error: illegal operands `cv.add.div2 x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-div2-fail.s b/gas/testsuite/gas/riscv/cv-simd-add-div2-fail.s
new file mode 100644
index 00000000000..ef37cafa2ae
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-div2-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.add.div2 x32, x32, x32
+    cv.add.div2 x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-div2-pass.d b/gas/testsuite/gas/riscv/cv-simd-add-div2-pass.d
new file mode 100644
index 00000000000..ec7c9478a2e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-div2-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-div2-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	6c00207b          	cv.add.div2	zero,zero,zero
+   4:	6c10a0fb          	cv.add.div2	ra,ra,ra
+   8:	6c21217b          	cv.add.div2	sp,sp,sp
+   c:	6c84247b          	cv.add.div2	s0,s0,s0
+  10:	6d4a2a7b          	cv.add.div2	s4,s4,s4
+  14:	6dffaffb          	cv.add.div2	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-div2-pass.s b/gas/testsuite/gas/riscv/cv-simd-add-div2-pass.s
new file mode 100644
index 00000000000..02bb555d39d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-div2-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.add.div2 x0, x0, x0
+    cv.add.div2 x1, x1, x1
+    cv.add.div2 x2, x2, x2
+    cv.add.div2 x8, x8, x8
+    cv.add.div2 x20, x20, x20
+    cv.add.div2 x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-div4-fail.d b/gas/testsuite/gas/riscv/cv-simd-add-div4-fail.d
new file mode 100644
index 00000000000..950e50f68f0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-div4-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-div4-fail.s
+#error_output: cv-simd-add-div4-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-div4-fail.l b/gas/testsuite/gas/riscv/cv-simd-add-div4-fail.l
new file mode 100644
index 00000000000..4f91c5031c8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-div4-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.add.div4 x32,x32,x32'
+.*: Error: illegal operands `cv.add.div4 x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-div4-fail.s b/gas/testsuite/gas/riscv/cv-simd-add-div4-fail.s
new file mode 100644
index 00000000000..94be2df60a5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-div4-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.add.div4 x32, x32, x32
+    cv.add.div4 x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-div4-pass.d b/gas/testsuite/gas/riscv/cv-simd-add-div4-pass.d
new file mode 100644
index 00000000000..b2ab67c3e46
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-div4-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-div4-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	6c00407b          	cv.add.div4	zero,zero,zero
+   4:	6c10c0fb          	cv.add.div4	ra,ra,ra
+   8:	6c21417b          	cv.add.div4	sp,sp,sp
+   c:	6c84447b          	cv.add.div4	s0,s0,s0
+  10:	6d4a4a7b          	cv.add.div4	s4,s4,s4
+  14:	6dffcffb          	cv.add.div4	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-div4-pass.s b/gas/testsuite/gas/riscv/cv-simd-add-div4-pass.s
new file mode 100644
index 00000000000..9f3afd2cbc0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-div4-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.add.div4 x0, x0, x0
+    cv.add.div4 x1, x1, x1
+    cv.add.div4 x2, x2, x2
+    cv.add.div4 x8, x8, x8
+    cv.add.div4 x20, x20, x20
+    cv.add.div4 x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-div8-fail.d b/gas/testsuite/gas/riscv/cv-simd-add-div8-fail.d
new file mode 100644
index 00000000000..dc238baf678
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-div8-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-div8-fail.s
+#error_output: cv-simd-add-div8-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-div8-fail.l b/gas/testsuite/gas/riscv/cv-simd-add-div8-fail.l
new file mode 100644
index 00000000000..b5628ada078
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-div8-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.add.div8 x32,x32,x32'
+.*: Error: illegal operands `cv.add.div8 x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-div8-fail.s b/gas/testsuite/gas/riscv/cv-simd-add-div8-fail.s
new file mode 100644
index 00000000000..d4c2c4afbfe
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-div8-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.add.div8 x32, x32, x32
+    cv.add.div8 x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-div8-pass.d b/gas/testsuite/gas/riscv/cv-simd-add-div8-pass.d
new file mode 100644
index 00000000000..df2687734a6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-div8-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-div8-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	6c00607b          	cv.add.div8	zero,zero,zero
+   4:	6c10e0fb          	cv.add.div8	ra,ra,ra
+   8:	6c21617b          	cv.add.div8	sp,sp,sp
+   c:	6c84647b          	cv.add.div8	s0,s0,s0
+  10:	6d4a6a7b          	cv.add.div8	s4,s4,s4
+  14:	6dffeffb          	cv.add.div8	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-div8-pass.s b/gas/testsuite/gas/riscv/cv-simd-add-div8-pass.s
new file mode 100644
index 00000000000..a0e33130eec
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-div8-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.add.div8 x0, x0, x0
+    cv.add.div8 x1, x1, x1
+    cv.add.div8 x2, x2, x2
+    cv.add.div8 x8, x8, x8
+    cv.add.div8 x20, x20, x20
+    cv.add.div8 x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-add-h-fail.d
new file mode 100644
index 00000000000..2955fadd135
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-h-fail.s
+#error_output: cv-simd-add-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-add-h-fail.l
new file mode 100644
index 00000000000..a82b28674ac
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.add.h x32,x32,x32'
+.*: Error: illegal operands `cv.add.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-add-h-fail.s
new file mode 100644
index 00000000000..2c9ffa090ca
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.add.h x32, x32, x32
+    cv.add.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-add-h-pass.d
new file mode 100644
index 00000000000..1a8515046a6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-h-pass.d
@@ -0,0 +1,15 @@
+#as: -march=rv32i_xcvsimd
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0000007b          	cv.add.h	zero,zero,zero
+   4:	001080fb          	cv.add.h	ra,ra,ra
+   8:	0021017b          	cv.add.h	sp,sp,sp
+   c:	0084047b          	cv.add.h	s0,s0,s0
+  10:	014a0a7b          	cv.add.h	s4,s4,s4
+  14:	01ff8ffb          	cv.add.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-add-h-pass.s
new file mode 100644
index 00000000000..46e91513932
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.add.h x0, x0, x0
+    cv.add.h x1, x1, x1
+    cv.add.h x2, x2, x2
+    cv.add.h x8, x8, x8
+    cv.add.h x20, x20, x20
+    cv.add.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-add-sc-b-fail.d
new file mode 100644
index 00000000000..5203f945385
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-sc-b-fail.s
+#error_output: cv-simd-add-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-add-sc-b-fail.l
new file mode 100644
index 00000000000..20b1f4fa1dd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.add.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.add.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-add-sc-b-fail.s
new file mode 100644
index 00000000000..9121fd4fefb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.add.sc.b x32, x32, x32
+    cv.add.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-add-sc-b-pass.d
new file mode 100644
index 00000000000..70c4d4d7a5f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0000507b          	cv.add.sc.b	zero,zero,zero
+   4:	0010d0fb          	cv.add.sc.b	ra,ra,ra
+   8:	0021517b          	cv.add.sc.b	sp,sp,sp
+   c:	0084547b          	cv.add.sc.b	s0,s0,s0
+  10:	014a5a7b          	cv.add.sc.b	s4,s4,s4
+  14:	01ffdffb          	cv.add.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-add-sc-b-pass.s
new file mode 100644
index 00000000000..e041df004cc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.add.sc.b x0, x0, x0
+    cv.add.sc.b x1, x1, x1
+    cv.add.sc.b x2, x2, x2
+    cv.add.sc.b x8, x8, x8
+    cv.add.sc.b x20, x20, x20
+    cv.add.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-add-sc-h-fail.d
new file mode 100644
index 00000000000..da90549036e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-sc-h-fail.s
+#error_output: cv-simd-add-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-add-sc-h-fail.l
new file mode 100644
index 00000000000..eaba711f44a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.add.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.add.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-add-sc-h-fail.s
new file mode 100644
index 00000000000..032270dc4e6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.add.sc.h x32, x32, x32
+    cv.add.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-add-sc-h-pass.d
new file mode 100644
index 00000000000..6292cead61a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0000407b          	cv.add.sc.h	zero,zero,zero
+   4:	0010c0fb          	cv.add.sc.h	ra,ra,ra
+   8:	0021417b          	cv.add.sc.h	sp,sp,sp
+   c:	0084447b          	cv.add.sc.h	s0,s0,s0
+  10:	014a4a7b          	cv.add.sc.h	s4,s4,s4
+  14:	01ffcffb          	cv.add.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-add-sc-h-pass.s
new file mode 100644
index 00000000000..27626c6af1a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.add.sc.h x0, x0, x0
+    cv.add.sc.h x1, x1, x1
+    cv.add.sc.h x2, x2, x2
+    cv.add.sc.h x8, x8, x8
+    cv.add.sc.h x20, x20, x20
+    cv.add.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-add-sci-b-fail.d
new file mode 100644
index 00000000000..4a887bf0b03
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-sci-b-fail.s
+#error_output: cv-simd-add-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-add-sci-b-fail.l
new file mode 100644
index 00000000000..c3f90cce759
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.add.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.add.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-add-sci-b-fail.s
new file mode 100644
index 00000000000..d3e2e2aae57
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.add.sci.b x32, x32, 20
+    cv.add.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.add.sci.b x6, x7, -33
+    cv.add.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-add-sci-b-pass.d
new file mode 100644
index 00000000000..a619e5c2a7e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	00a0707b          	cv.add.sci.b	zero,zero,20
+   4:	00a0f0fb          	cv.add.sci.b	ra,ra,20
+   8:	00a1717b          	cv.add.sci.b	sp,sp,20
+   c:	00a4747b          	cv.add.sci.b	s0,s0,20
+  10:	00aa7a7b          	cv.add.sci.b	s4,s4,20
+  14:	00affffb          	cv.add.sci.b	t6,t6,20
+  18:	0103f37b          	cv.add.sci.b	t1,t2,-32
+  1c:	0003f37b          	cv.add.sci.b	t1,t2,0
+  20:	02f3f37b          	cv.add.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-add-sci-b-pass.s
new file mode 100644
index 00000000000..3502bc197be
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sci-b-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.add.sci.b x0, x0, 20
+    cv.add.sci.b x1, x1, 20
+    cv.add.sci.b x2, x2, 20
+    cv.add.sci.b x8, x8, 20
+    cv.add.sci.b x20, x20, 20
+    cv.add.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.add.sci.b x6, x7, -32
+    cv.add.sci.b x6, x7, 0
+    cv.add.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-add-sci-h-fail.d
new file mode 100644
index 00000000000..0903b08b12a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-sci-h-fail.s
+#error_output: cv-simd-add-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-add-sci-h-fail.l
new file mode 100644
index 00000000000..2f0656f83a3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.add.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.add.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-add-sci-h-fail.s
new file mode 100644
index 00000000000..538864a7f48
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.add.sci.h x32, x32, 20
+    cv.add.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.add.sci.h x6, x7, -33
+    cv.add.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-add-sci-h-pass.d
new file mode 100644
index 00000000000..8feb432283e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-add-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	00a0607b          	cv.add.sci.h	zero,zero,20
+   4:	00a0e0fb          	cv.add.sci.h	ra,ra,20
+   8:	00a1617b          	cv.add.sci.h	sp,sp,20
+   c:	00a4647b          	cv.add.sci.h	s0,s0,20
+  10:	00aa6a7b          	cv.add.sci.h	s4,s4,20
+  14:	00afeffb          	cv.add.sci.h	t6,t6,20
+  18:	0103e37b          	cv.add.sci.h	t1,t2,-32
+  1c:	0003e37b          	cv.add.sci.h	t1,t2,0
+  20:	02f3e37b          	cv.add.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-add-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-add-sci-h-pass.s
new file mode 100644
index 00000000000..6ce7055482b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-add-sci-h-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.add.sci.h x0, x0, 20
+    cv.add.sci.h x1, x1, 20
+    cv.add.sci.h x2, x2, 20
+    cv.add.sci.h x8, x8, 20
+    cv.add.sci.h x20, x20, 20
+    cv.add.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.add.sci.h x6, x7, -32
+    cv.add.sci.h x6, x7, 0
+    cv.add.sci.h x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-and-b-fail.d
new file mode 100644
index 00000000000..90dcc73303d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-and-b-fail.s
+#error_output: cv-simd-and-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-and-b-fail.l
new file mode 100644
index 00000000000..18102aad53f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.and.b x32,x32,x32'
+.*: Error: illegal operands `cv.and.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-and-b-fail.s
new file mode 100644
index 00000000000..576d7feecf6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.and.b x32, x32, x32
+    cv.and.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-and-b-pass.d
new file mode 100644
index 00000000000..3c04c58671c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-and-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	6800107b          	cv.and.b	zero,zero,zero
+   4:	681090fb          	cv.and.b	ra,ra,ra
+   8:	6821117b          	cv.and.b	sp,sp,sp
+   c:	6884147b          	cv.and.b	s0,s0,s0
+  10:	694a1a7b          	cv.and.b	s4,s4,s4
+  14:	69ff9ffb          	cv.and.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-and-b-pass.s
new file mode 100644
index 00000000000..84bd68710fa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.and.b x0, x0, x0
+    cv.and.b x1, x1, x1
+    cv.and.b x2, x2, x2
+    cv.and.b x8, x8, x8
+    cv.and.b x20, x20, x20
+    cv.and.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-and-h-fail.d
new file mode 100644
index 00000000000..8afc79a69b7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-and-h-fail.s
+#error_output: cv-simd-and-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-and-h-fail.l
new file mode 100644
index 00000000000..a12d6a349db
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.and.h x32,x32,x32'
+.*: Error: illegal operands `cv.and.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-and-h-fail.s
new file mode 100644
index 00000000000..f60f7afbcaf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.and.h x32, x32, x32
+    cv.and.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-and-h-pass.d
new file mode 100644
index 00000000000..543d22a8acc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-and-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	6800007b          	cv.and.h	zero,zero,zero
+   4:	681080fb          	cv.and.h	ra,ra,ra
+   8:	6821017b          	cv.and.h	sp,sp,sp
+   c:	6884047b          	cv.and.h	s0,s0,s0
+  10:	694a0a7b          	cv.and.h	s4,s4,s4
+  14:	69ff8ffb          	cv.and.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-and-h-pass.s
new file mode 100644
index 00000000000..776fce71297
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.and.h x0, x0, x0
+    cv.and.h x1, x1, x1
+    cv.and.h x2, x2, x2
+    cv.and.h x8, x8, x8
+    cv.and.h x20, x20, x20
+    cv.and.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-and-sc-b-fail.d
new file mode 100644
index 00000000000..6144978cf6c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-and-sc-b-fail.s
+#error_output: cv-simd-and-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-and-sc-b-fail.l
new file mode 100644
index 00000000000..cf9dd0e2935
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.and.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.and.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-and-sc-b-fail.s
new file mode 100644
index 00000000000..77e76d667b6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.and.sc.b x32, x32, x32
+    cv.and.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-and-sc-b-pass.d
new file mode 100644
index 00000000000..303b08034ef
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-and-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	6800507b          	cv.and.sc.b	zero,zero,zero
+   4:	6810d0fb          	cv.and.sc.b	ra,ra,ra
+   8:	6821517b          	cv.and.sc.b	sp,sp,sp
+   c:	6884547b          	cv.and.sc.b	s0,s0,s0
+  10:	694a5a7b          	cv.and.sc.b	s4,s4,s4
+  14:	69ffdffb          	cv.and.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-and-sc-b-pass.s
new file mode 100644
index 00000000000..d6b116a7bca
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.and.sc.b x0, x0, x0
+    cv.and.sc.b x1, x1, x1
+    cv.and.sc.b x2, x2, x2
+    cv.and.sc.b x8, x8, x8
+    cv.and.sc.b x20, x20, x20
+    cv.and.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-and-sc-h-fail.d
new file mode 100644
index 00000000000..c8bb0149d9a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-and-sc-h-fail.s
+#error_output: cv-simd-and-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-and-sc-h-fail.l
new file mode 100644
index 00000000000..cc0e3329db6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.and.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.and.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-and-sc-h-fail.s
new file mode 100644
index 00000000000..cfdc62d6512
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.and.sc.h x32, x32, x32
+    cv.and.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-and-sc-h-pass.d
new file mode 100644
index 00000000000..66eee81b941
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-and-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	6800407b          	cv.and.sc.h	zero,zero,zero
+   4:	6810c0fb          	cv.and.sc.h	ra,ra,ra
+   8:	6821417b          	cv.and.sc.h	sp,sp,sp
+   c:	6884447b          	cv.and.sc.h	s0,s0,s0
+  10:	694a4a7b          	cv.and.sc.h	s4,s4,s4
+  14:	69ffcffb          	cv.and.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-and-sc-h-pass.s
new file mode 100644
index 00000000000..a3ae1596c13
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.and.sc.h x0, x0, x0
+    cv.and.sc.h x1, x1, x1
+    cv.and.sc.h x2, x2, x2
+    cv.and.sc.h x8, x8, x8
+    cv.and.sc.h x20, x20, x20
+    cv.and.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-and-sci-b-fail.d
new file mode 100644
index 00000000000..f208bb9600e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-and-sci-b-fail.s
+#error_output: cv-simd-and-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-and-sci-b-fail.l
new file mode 100644
index 00000000000..a259452d78d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.and.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.and.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-and-sci-b-fail.s
new file mode 100644
index 00000000000..842278fb71f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.and.sci.b x32, x32, 20
+    cv.and.sci.b x33, x33, 20
+    #Boundary Ibmediate Values Test
+    cv.and.sci.b x6, x7, -33
+    cv.and.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-and-sci-b-pass.d
new file mode 100644
index 00000000000..df234b3bfe1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-and-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	68a0707b          	cv.and.sci.b	zero,zero,20
+   4:	68a0f0fb          	cv.and.sci.b	ra,ra,20
+   8:	68a1717b          	cv.and.sci.b	sp,sp,20
+   c:	68a4747b          	cv.and.sci.b	s0,s0,20
+  10:	68aa7a7b          	cv.and.sci.b	s4,s4,20
+  14:	68affffb          	cv.and.sci.b	t6,t6,20
+  18:	6903f37b          	cv.and.sci.b	t1,t2,-32
+  1c:	6803f37b          	cv.and.sci.b	t1,t2,0
+  20:	6af3f37b          	cv.and.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-and-sci-b-pass.s
new file mode 100644
index 00000000000..33aa654af1f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sci-b-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.and.sci.b x0, x0, 20
+    cv.and.sci.b x1, x1, 20
+    cv.and.sci.b x2, x2, 20
+    cv.and.sci.b x8, x8, 20
+    cv.and.sci.b x20, x20, 20
+    cv.and.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.and.sci.b x6, x7, -32
+    cv.and.sci.b x6, x7, 0
+    cv.and.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-and-sci-h-fail.d
new file mode 100644
index 00000000000..3f17a36db14
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-and-sci-h-fail.s
+#error_output: cv-simd-and-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-and-sci-h-fail.l
new file mode 100644
index 00000000000..3564a7fce86
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.and.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.and.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-and-sci-h-fail.s
new file mode 100644
index 00000000000..b510be5346a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.and.sci.h x32, x32, 20
+    cv.and.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.and.sci.h x6, x7, -33
+    cv.and.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-and-sci-h-pass.d
new file mode 100644
index 00000000000..e9f68737c8e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-and-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	68a0607b          	cv.and.sci.h	zero,zero,20
+   4:	68a0e0fb          	cv.and.sci.h	ra,ra,20
+   8:	68a1617b          	cv.and.sci.h	sp,sp,20
+   c:	68a4647b          	cv.and.sci.h	s0,s0,20
+  10:	68aa6a7b          	cv.and.sci.h	s4,s4,20
+  14:	68afeffb          	cv.and.sci.h	t6,t6,20
+  18:	6903e37b          	cv.and.sci.h	t1,t2,-32
+  1c:	6803e37b          	cv.and.sci.h	t1,t2,0
+  20:	6af3e37b          	cv.and.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-and-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-and-sci-h-pass.s
new file mode 100644
index 00000000000..5c06d000996
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-and-sci-h-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.and.sci.h x0, x0, 20
+    cv.and.sci.h x1, x1, 20
+    cv.and.sci.h x2, x2, 20
+    cv.and.sci.h x8, x8, 20
+    cv.and.sci.h x20, x20, 20
+    cv.and.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.and.sci.h x6, x7, -32
+    cv.and.sci.h x6, x7, 0
+    cv.and.sci.h x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-avg-b-fail.d
new file mode 100644
index 00000000000..8e1fedc4f4b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avg-b-fail.s
+#error_output: cv-simd-avg-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-avg-b-fail.l
new file mode 100644
index 00000000000..7b693315d5e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.avg.b x32,x32,x32'
+.*: Error: illegal operands `cv.avg.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-avg-b-fail.s
new file mode 100644
index 00000000000..0488df691e2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.avg.b x32, x32, x32
+    cv.avg.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-avg-b-pass.d
new file mode 100644
index 00000000000..2f6b39e151a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avg-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1000107b          	cv.avg.b	zero,zero,zero
+   4:	101090fb          	cv.avg.b	ra,ra,ra
+   8:	1021117b          	cv.avg.b	sp,sp,sp
+   c:	1084147b          	cv.avg.b	s0,s0,s0
+  10:	114a1a7b          	cv.avg.b	s4,s4,s4
+  14:	11ff9ffb          	cv.avg.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-avg-b-pass.s
new file mode 100644
index 00000000000..bc299360a7d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.avg.b x0, x0, x0
+    cv.avg.b x1, x1, x1
+    cv.avg.b x2, x2, x2
+    cv.avg.b x8, x8, x8
+    cv.avg.b x20, x20, x20
+    cv.avg.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-avg-h-fail.d
new file mode 100644
index 00000000000..027118446fb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avg-h-fail.s
+#error_output: cv-simd-avg-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-avg-h-fail.l
new file mode 100644
index 00000000000..387e31e1f04
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.avg.h x32,x32,x32'
+.*: Error: illegal operands `cv.avg.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-avg-h-fail.s
new file mode 100644
index 00000000000..bd8f8bb5f40
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.avg.h x32, x32, x32
+    cv.avg.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-avg-h-pass.d
new file mode 100644
index 00000000000..044b292c450
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avg-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1000007b          	cv.avg.h	zero,zero,zero
+   4:	101080fb          	cv.avg.h	ra,ra,ra
+   8:	1021017b          	cv.avg.h	sp,sp,sp
+   c:	1084047b          	cv.avg.h	s0,s0,s0
+  10:	114a0a7b          	cv.avg.h	s4,s4,s4
+  14:	11ff8ffb          	cv.avg.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-avg-h-pass.s
new file mode 100644
index 00000000000..e2558e322d8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.avg.h x0, x0, x0
+    cv.avg.h x1, x1, x1
+    cv.avg.h x2, x2, x2
+    cv.avg.h x8, x8, x8
+    cv.avg.h x20, x20, x20
+    cv.avg.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-avg-sc-b-fail.d
new file mode 100644
index 00000000000..a452363f4d7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avg-sc-b-fail.s
+#error_output: cv-simd-avg-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-avg-sc-b-fail.l
new file mode 100644
index 00000000000..dd22457c92d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.avg.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.avg.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-avg-sc-b-fail.s
new file mode 100644
index 00000000000..b40ce82d61b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.avg.sc.b x32, x32, x32
+    cv.avg.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-avg-sc-b-pass.d
new file mode 100644
index 00000000000..24c9362fec0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avg-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1000507b          	cv.avg.sc.b	zero,zero,zero
+   4:	1010d0fb          	cv.avg.sc.b	ra,ra,ra
+   8:	1021517b          	cv.avg.sc.b	sp,sp,sp
+   c:	1084547b          	cv.avg.sc.b	s0,s0,s0
+  10:	114a5a7b          	cv.avg.sc.b	s4,s4,s4
+  14:	11ffdffb          	cv.avg.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-avg-sc-b-pass.s
new file mode 100644
index 00000000000..a78c7d56c1e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.avg.sc.b x0, x0, x0
+    cv.avg.sc.b x1, x1, x1
+    cv.avg.sc.b x2, x2, x2
+    cv.avg.sc.b x8, x8, x8
+    cv.avg.sc.b x20, x20, x20
+    cv.avg.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-avg-sc-h-fail.d
new file mode 100644
index 00000000000..5e48b003006
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avg-sc-h-fail.s
+#error_output: cv-simd-avg-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-avg-sc-h-fail.l
new file mode 100644
index 00000000000..3df6422a9d4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.avg.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.avg.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-avg-sc-h-fail.s
new file mode 100644
index 00000000000..fa3a4d2e700
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.avg.sc.h x32, x32, x32
+    cv.avg.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-avg-sc-h-pass.d
new file mode 100644
index 00000000000..f4cd1bcfe73
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avg-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1000407b          	cv.avg.sc.h	zero,zero,zero
+   4:	1010c0fb          	cv.avg.sc.h	ra,ra,ra
+   8:	1021417b          	cv.avg.sc.h	sp,sp,sp
+   c:	1084447b          	cv.avg.sc.h	s0,s0,s0
+  10:	114a4a7b          	cv.avg.sc.h	s4,s4,s4
+  14:	11ffcffb          	cv.avg.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-avg-sc-h-pass.s
new file mode 100644
index 00000000000..28bf8536fa3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.avg.sc.h x0, x0, x0
+    cv.avg.sc.h x1, x1, x1
+    cv.avg.sc.h x2, x2, x2
+    cv.avg.sc.h x8, x8, x8
+    cv.avg.sc.h x20, x20, x20
+    cv.avg.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-avg-sci-b-fail.d
new file mode 100644
index 00000000000..166015a1156
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avg-sci-b-fail.s
+#error_output: cv-simd-avg-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-avg-sci-b-fail.l
new file mode 100644
index 00000000000..1d66f52499b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.avg.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.avg.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-avg-sci-b-fail.s
new file mode 100644
index 00000000000..dd0eb100064
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.avg.sci.b x32, x32, 20
+    cv.avg.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.avg.sci.b x6, x7, -33
+    cv.avg.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-avg-sci-b-pass.d
new file mode 100644
index 00000000000..023b3201d14
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avg-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	10a0707b          	cv.avg.sci.b	zero,zero,20
+   4:	10a0f0fb          	cv.avg.sci.b	ra,ra,20
+   8:	10a1717b          	cv.avg.sci.b	sp,sp,20
+   c:	10a4747b          	cv.avg.sci.b	s0,s0,20
+  10:	10aa7a7b          	cv.avg.sci.b	s4,s4,20
+  14:	10affffb          	cv.avg.sci.b	t6,t6,20
+  18:	1103f37b          	cv.avg.sci.b	t1,t2,-32
+  1c:	1003f37b          	cv.avg.sci.b	t1,t2,0
+  20:	12f3f37b          	cv.avg.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-avg-sci-b-pass.s
new file mode 100644
index 00000000000..cef5caba22c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sci-b-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.avg.sci.b x0, x0, 20
+    cv.avg.sci.b x1, x1, 20
+    cv.avg.sci.b x2, x2, 20
+    cv.avg.sci.b x8, x8, 20
+    cv.avg.sci.b x20, x20, 20
+    cv.avg.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.avg.sci.b x6, x7, -32
+    cv.avg.sci.b x6, x7, 0
+    cv.avg.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-avg-sci-h-fail.d
new file mode 100644
index 00000000000..d995769504d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avg-sci-h-fail.s
+#error_output: cv-simd-avg-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-avg-sci-h-fail.l
new file mode 100644
index 00000000000..a5bc7a5cdb9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.avg.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.avg.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-avg-sci-h-fail.s
new file mode 100644
index 00000000000..41144e20d77
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.avg.sci.h x32, x32, 20
+    cv.avg.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.avg.sci.h x6, x7, -33
+    cv.avg.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-avg-sci-h-pass.d
new file mode 100644
index 00000000000..43e6089b2b9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avg-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	10a0607b          	cv.avg.sci.h	zero,zero,20
+   4:	10a0e0fb          	cv.avg.sci.h	ra,ra,20
+   8:	10a1617b          	cv.avg.sci.h	sp,sp,20
+   c:	10a4647b          	cv.avg.sci.h	s0,s0,20
+  10:	10aa6a7b          	cv.avg.sci.h	s4,s4,20
+  14:	10afeffb          	cv.avg.sci.h	t6,t6,20
+  18:	1103e37b          	cv.avg.sci.h	t1,t2,-32
+  1c:	1003e37b          	cv.avg.sci.h	t1,t2,0
+  20:	12f3e37b          	cv.avg.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-avg-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-avg-sci-h-pass.s
new file mode 100644
index 00000000000..a489cbbdaac
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avg-sci-h-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.avg.sci.h x0, x0, 20
+    cv.avg.sci.h x1, x1, 20
+    cv.avg.sci.h x2, x2, 20
+    cv.avg.sci.h x8, x8, 20
+    cv.avg.sci.h x20, x20, 20
+    cv.avg.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.avg.sci.h x6, x7, -32
+    cv.avg.sci.h x6, x7, 0
+    cv.avg.sci.h x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-avgu-b-fail.d
new file mode 100644
index 00000000000..af1ddbe83ca
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avgu-b-fail.s
+#error_output: cv-simd-avgu-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-avgu-b-fail.l
new file mode 100644
index 00000000000..945d5b11ad7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.avgu.b x32,x32,x32'
+.*: Error: illegal operands `cv.avgu.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-avgu-b-fail.s
new file mode 100644
index 00000000000..8401e7c18bc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.avgu.b x32, x32, x32
+    cv.avgu.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-avgu-b-pass.d
new file mode 100644
index 00000000000..f7e548a3ca2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avgu-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1800107b          	cv.avgu.b	zero,zero,zero
+   4:	181090fb          	cv.avgu.b	ra,ra,ra
+   8:	1821117b          	cv.avgu.b	sp,sp,sp
+   c:	1884147b          	cv.avgu.b	s0,s0,s0
+  10:	194a1a7b          	cv.avgu.b	s4,s4,s4
+  14:	19ff9ffb          	cv.avgu.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-avgu-b-pass.s
new file mode 100644
index 00000000000..afea2b753de
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.avgu.b x0, x0, x0
+    cv.avgu.b x1, x1, x1
+    cv.avgu.b x2, x2, x2
+    cv.avgu.b x8, x8, x8
+    cv.avgu.b x20, x20, x20
+    cv.avgu.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-avgu-h-fail.d
new file mode 100644
index 00000000000..caabe1b56af
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avgu-h-fail.s
+#error_output: cv-simd-avgu-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-avgu-h-fail.l
new file mode 100644
index 00000000000..7c8f1554713
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.avgu.h x32,x32,x32'
+.*: Error: illegal operands `cv.avgu.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-avgu-h-fail.s
new file mode 100644
index 00000000000..0d68904a760
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.avgu.h x32, x32, x32
+    cv.avgu.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-avgu-h-pass.d
new file mode 100644
index 00000000000..21d3e815119
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avgu-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1800007b          	cv.avgu.h	zero,zero,zero
+   4:	181080fb          	cv.avgu.h	ra,ra,ra
+   8:	1821017b          	cv.avgu.h	sp,sp,sp
+   c:	1884047b          	cv.avgu.h	s0,s0,s0
+  10:	194a0a7b          	cv.avgu.h	s4,s4,s4
+  14:	19ff8ffb          	cv.avgu.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-avgu-h-pass.s
new file mode 100644
index 00000000000..2bf5b99bcb4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.avgu.h x0, x0, x0
+    cv.avgu.h x1, x1, x1
+    cv.avgu.h x2, x2, x2
+    cv.avgu.h x8, x8, x8
+    cv.avgu.h x20, x20, x20
+    cv.avgu.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-b-fail.d
new file mode 100644
index 00000000000..9528a0ef082
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avgu-sc-b-fail.s
+#error_output: cv-simd-avgu-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-b-fail.l
new file mode 100644
index 00000000000..477e1703fd2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.avgu.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.avgu.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-b-fail.s
new file mode 100644
index 00000000000..6d6f0814829
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.avgu.sc.b x32, x32, x32
+    cv.avgu.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-b-pass.d
new file mode 100644
index 00000000000..4b7819c5705
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avgu-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1800507b          	cv.avgu.sc.b	zero,zero,zero
+   4:	1810d0fb          	cv.avgu.sc.b	ra,ra,ra
+   8:	1821517b          	cv.avgu.sc.b	sp,sp,sp
+   c:	1884547b          	cv.avgu.sc.b	s0,s0,s0
+  10:	194a5a7b          	cv.avgu.sc.b	s4,s4,s4
+  14:	19ffdffb          	cv.avgu.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-b-pass.s
new file mode 100644
index 00000000000..a22ee098d2b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.avgu.sc.b x0, x0, x0
+    cv.avgu.sc.b x1, x1, x1
+    cv.avgu.sc.b x2, x2, x2
+    cv.avgu.sc.b x8, x8, x8
+    cv.avgu.sc.b x20, x20, x20
+    cv.avgu.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-h-fail.d
new file mode 100644
index 00000000000..63ae30b9c62
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avgu-sc-h-fail.s
+#error_output: cv-simd-avgu-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-h-fail.l
new file mode 100644
index 00000000000..b4192d02b66
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.avgu.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.avgu.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-h-fail.s
new file mode 100644
index 00000000000..f42e01e2e2c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.avgu.sc.h x32, x32, x32
+    cv.avgu.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-h-pass.d
new file mode 100644
index 00000000000..c084dbd8aed
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avgu-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1800407b          	cv.avgu.sc.h	zero,zero,zero
+   4:	1810c0fb          	cv.avgu.sc.h	ra,ra,ra
+   8:	1821417b          	cv.avgu.sc.h	sp,sp,sp
+   c:	1884447b          	cv.avgu.sc.h	s0,s0,s0
+  10:	194a4a7b          	cv.avgu.sc.h	s4,s4,s4
+  14:	19ffcffb          	cv.avgu.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-h-pass.s
new file mode 100644
index 00000000000..ea6ad17c56e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.avgu.sc.h x0, x0, x0
+    cv.avgu.sc.h x1, x1, x1
+    cv.avgu.sc.h x2, x2, x2
+    cv.avgu.sc.h x8, x8, x8
+    cv.avgu.sc.h x20, x20, x20
+    cv.avgu.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-fail.d
new file mode 100644
index 00000000000..071985022d0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avgu-sci-b-fail.s
+#error_output: cv-simd-avgu-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-fail.l
new file mode 100644
index 00000000000..241f8ae1341
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.avgu.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.avgu.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-fail.s
new file mode 100644
index 00000000000..ddf40939b69
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.avgu.sci.b x32, x32, 20
+    cv.avgu.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.avgu.sci.b x6, x7, -1
+    cv.avgu.sci.b x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-pass.d
new file mode 100644
index 00000000000..0668fe1848d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avgu-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	18a0707b          	cv.avgu.sci.b	zero,zero,20
+   4:	18a0f0fb          	cv.avgu.sci.b	ra,ra,20
+   8:	18a1717b          	cv.avgu.sci.b	sp,sp,20
+   c:	18a4747b          	cv.avgu.sci.b	s0,s0,20
+  10:	18aa7a7b          	cv.avgu.sci.b	s4,s4,20
+  14:	18affffb          	cv.avgu.sci.b	t6,t6,20
+  18:	1803f37b          	cv.avgu.sci.b	t1,t2,0
+  1c:	1bf3f37b          	cv.avgu.sci.b	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-pass.s
new file mode 100644
index 00000000000..dc8073603cc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.avgu.sci.b x0, x0, 20
+    cv.avgu.sci.b x1, x1, 20
+    cv.avgu.sci.b x2, x2, 20
+    cv.avgu.sci.b x8, x8, 20
+    cv.avgu.sci.b x20, x20, 20
+    cv.avgu.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.avgu.sci.b x6, x7, 0
+    cv.avgu.sci.b x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-h-fail.d
new file mode 100644
index 00000000000..398239769ff
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avgu-sci-h-fail.s
+#error_output: cv-simd-avgu-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-h-fail.l
new file mode 100644
index 00000000000..ec018bdd1ef
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.avgu.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.avgu.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-h-fail.s
new file mode 100644
index 00000000000..cae50e2320d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.avgu.sci.h x32, x32, 20
+    cv.avgu.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.avgu.sci.h x6, x7, -1
+    cv.avgu.sci.h x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-h-pass.d
new file mode 100644
index 00000000000..1f9902d0dc4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-h-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-avgu-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	18a0607b          	cv.avgu.sci.h	zero,zero,20
+   4:	18a0e0fb          	cv.avgu.sci.h	ra,ra,20
+   8:	18a1617b          	cv.avgu.sci.h	sp,sp,20
+   c:	18a4647b          	cv.avgu.sci.h	s0,s0,20
+  10:	18aa6a7b          	cv.avgu.sci.h	s4,s4,20
+  14:	18afeffb          	cv.avgu.sci.h	t6,t6,20
+  18:	1803e37b          	cv.avgu.sci.h	t1,t2,0
+  1c:	1bf3e37b          	cv.avgu.sci.h	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-avgu-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-h-pass.s
new file mode 100644
index 00000000000..f638387199b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-avgu-sci-h-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.avgu.sci.h x0, x0, 20
+    cv.avgu.sci.h x1, x1, 20
+    cv.avgu.sci.h x2, x2, 20
+    cv.avgu.sci.h x8, x8, 20
+    cv.avgu.sci.h x20, x20, 20
+    cv.avgu.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.avgu.sci.h x6, x7, 0
+    cv.avgu.sci.h x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpeq-b-fail.d
new file mode 100644
index 00000000000..2a3318d5dfe
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpeq-b-fail.s
+#error_output: cv-simd-cmpeq-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpeq-b-fail.l
new file mode 100644
index 00000000000..4aac9f46da2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpeq.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpeq.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpeq-b-fail.s
new file mode 100644
index 00000000000..a0f528ad7c1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpeq.b x32, x32, x32
+    cv.cmpeq.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpeq-b-pass.d
new file mode 100644
index 00000000000..bd2b2f9b0a6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpeq-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0400107b          	cv.cmpeq.b	zero,zero,zero
+   4:	041090fb          	cv.cmpeq.b	ra,ra,ra
+   8:	0421117b          	cv.cmpeq.b	sp,sp,sp
+   c:	0484147b          	cv.cmpeq.b	s0,s0,s0
+  10:	054a1a7b          	cv.cmpeq.b	s4,s4,s4
+  14:	05ff9ffb          	cv.cmpeq.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpeq-b-pass.s
new file mode 100644
index 00000000000..a4875125eeb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpeq.b x0, x0, x0
+    cv.cmpeq.b x1, x1, x1
+    cv.cmpeq.b x2, x2, x2
+    cv.cmpeq.b x8, x8, x8
+    cv.cmpeq.b x20, x20, x20
+    cv.cmpeq.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpeq-h-fail.d
new file mode 100644
index 00000000000..b258f49d2ec
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpeq-h-fail.s
+#error_output: cv-simd-cmpeq-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpeq-h-fail.l
new file mode 100644
index 00000000000..a4a2d73299c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpeq.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpeq.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpeq-h-fail.s
new file mode 100644
index 00000000000..72008f735cd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpeq.h x32, x32, x32
+    cv.cmpeq.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpeq-h-pass.d
new file mode 100644
index 00000000000..f5e54008311
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpeq-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0400007b          	cv.cmpeq.h	zero,zero,zero
+   4:	041080fb          	cv.cmpeq.h	ra,ra,ra
+   8:	0421017b          	cv.cmpeq.h	sp,sp,sp
+   c:	0484047b          	cv.cmpeq.h	s0,s0,s0
+  10:	054a0a7b          	cv.cmpeq.h	s4,s4,s4
+  14:	05ff8ffb          	cv.cmpeq.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpeq-h-pass.s
new file mode 100644
index 00000000000..5bef92b2dbe
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpeq.h x0, x0, x0
+    cv.cmpeq.h x1, x1, x1
+    cv.cmpeq.h x2, x2, x2
+    cv.cmpeq.h x8, x8, x8
+    cv.cmpeq.h x20, x20, x20
+    cv.cmpeq.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-b-fail.d
new file mode 100644
index 00000000000..e2fe218cdd4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpeq-sc-b-fail.s
+#error_output: cv-simd-cmpeq-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-b-fail.l
new file mode 100644
index 00000000000..43c0f88c42b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpeq.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpeq.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-b-fail.s
new file mode 100644
index 00000000000..46edcf3b987
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpeq.sc.b x32, x32, x32
+    cv.cmpeq.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-b-pass.d
new file mode 100644
index 00000000000..81d4ee3964c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpeq-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0400507b          	cv.cmpeq.sc.b	zero,zero,zero
+   4:	0410d0fb          	cv.cmpeq.sc.b	ra,ra,ra
+   8:	0421517b          	cv.cmpeq.sc.b	sp,sp,sp
+   c:	0484547b          	cv.cmpeq.sc.b	s0,s0,s0
+  10:	054a5a7b          	cv.cmpeq.sc.b	s4,s4,s4
+  14:	05ffdffb          	cv.cmpeq.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-b-pass.s
new file mode 100644
index 00000000000..73808e038fa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpeq.sc.b x0, x0, x0
+    cv.cmpeq.sc.b x1, x1, x1
+    cv.cmpeq.sc.b x2, x2, x2
+    cv.cmpeq.sc.b x8, x8, x8
+    cv.cmpeq.sc.b x20, x20, x20
+    cv.cmpeq.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-h-fail.d
new file mode 100644
index 00000000000..cc28bad796d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpeq-sc-h-fail.s
+#error_output: cv-simd-cmpeq-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-h-fail.l
new file mode 100644
index 00000000000..13275a99112
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpeq.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpeq.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-h-fail.s
new file mode 100644
index 00000000000..24e211af754
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpeq.sc.h x32, x32, x32
+    cv.cmpeq.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-h-pass.d
new file mode 100644
index 00000000000..11a5774ebc9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpeq-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0400407b          	cv.cmpeq.sc.h	zero,zero,zero
+   4:	0410c0fb          	cv.cmpeq.sc.h	ra,ra,ra
+   8:	0421417b          	cv.cmpeq.sc.h	sp,sp,sp
+   c:	0484447b          	cv.cmpeq.sc.h	s0,s0,s0
+  10:	054a4a7b          	cv.cmpeq.sc.h	s4,s4,s4
+  14:	05ffcffb          	cv.cmpeq.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-h-pass.s
new file mode 100644
index 00000000000..fc8f7686695
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpeq.sc.h x0, x0, x0
+    cv.cmpeq.sc.h x1, x1, x1
+    cv.cmpeq.sc.h x2, x2, x2
+    cv.cmpeq.sc.h x8, x8, x8
+    cv.cmpeq.sc.h x20, x20, x20
+    cv.cmpeq.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-b-fail.d
new file mode 100644
index 00000000000..ee63eaa3a7c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpeq-sci-b-fail.s
+#error_output: cv-simd-cmpeq-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-b-fail.l
new file mode 100644
index 00000000000..0d488f66ce1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpeq.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.cmpeq.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-b-fail.s
new file mode 100644
index 00000000000..6cf4cb09612
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.cmpeq.sci.b x32, x32, 20
+    cv.cmpeq.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpeq.sci.b x6, x7, -33
+    cv.cmpeq.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-b-pass.d
new file mode 100644
index 00000000000..c0dead860d9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpeq-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	04a0707b          	cv.cmpeq.sci.b	zero,zero,20
+   4:	04a0f0fb          	cv.cmpeq.sci.b	ra,ra,20
+   8:	04a1717b          	cv.cmpeq.sci.b	sp,sp,20
+   c:	04a4747b          	cv.cmpeq.sci.b	s0,s0,20
+  10:	04aa7a7b          	cv.cmpeq.sci.b	s4,s4,20
+  14:	04affffb          	cv.cmpeq.sci.b	t6,t6,20
+  18:	0503f37b          	cv.cmpeq.sci.b	t1,t2,-32
+  1c:	0403f37b          	cv.cmpeq.sci.b	t1,t2,0
+  20:	06f3f37b          	cv.cmpeq.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-b-pass.s
new file mode 100644
index 00000000000..aa079a6780b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-b-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.cmpeq.sci.b x0, x0, 20
+    cv.cmpeq.sci.b x1, x1, 20
+    cv.cmpeq.sci.b x2, x2, 20
+    cv.cmpeq.sci.b x8, x8, 20
+    cv.cmpeq.sci.b x20, x20, 20
+    cv.cmpeq.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.cmpeq.sci.b x6, x7, -32
+    cv.cmpeq.sci.b x6, x7, 0
+    cv.cmpeq.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-h-fail.d
new file mode 100644
index 00000000000..878e99672f7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpeq-sci-h-fail.s
+#error_output: cv-simd-cmpeq-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-h-fail.l
new file mode 100644
index 00000000000..77a6cd56bf1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpeq.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.cmpeq.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-h-fail.s
new file mode 100644
index 00000000000..677b67ce279
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.cmpeq.sci.h x32, x32, 20
+    cv.cmpeq.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpeq.sci.h x6, x7, -33
+    cv.cmpeq.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-h-pass.d
new file mode 100644
index 00000000000..302d2f80cc3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpeq-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	04a0607b          	cv.cmpeq.sci.h	zero,zero,20
+   4:	04a0e0fb          	cv.cmpeq.sci.h	ra,ra,20
+   8:	04a1617b          	cv.cmpeq.sci.h	sp,sp,20
+   c:	04a4647b          	cv.cmpeq.sci.h	s0,s0,20
+  10:	04aa6a7b          	cv.cmpeq.sci.h	s4,s4,20
+  14:	04afeffb          	cv.cmpeq.sci.h	t6,t6,20
+  18:	0503e37b          	cv.cmpeq.sci.h	t1,t2,-32
+  1c:	0403e37b          	cv.cmpeq.sci.h	t1,t2,0
+  20:	06f3e37b          	cv.cmpeq.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-h-pass.s
new file mode 100644
index 00000000000..c5f00ca2070
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpeq-sci-h-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.cmpeq.sci.h x0, x0, 20
+    cv.cmpeq.sci.h x1, x1, 20
+    cv.cmpeq.sci.h x2, x2, 20
+    cv.cmpeq.sci.h x8, x8, 20
+    cv.cmpeq.sci.h x20, x20, 20
+    cv.cmpeq.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.cmpeq.sci.h x6, x7, -32
+    cv.cmpeq.sci.h x6, x7, 0
+    cv.cmpeq.sci.h x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpge-b-fail.d
new file mode 100644
index 00000000000..644f83b5692
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpge-b-fail.s
+#error_output: cv-simd-cmpge-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpge-b-fail.l
new file mode 100644
index 00000000000..a08e74fe104
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpge.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpge.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpge-b-fail.s
new file mode 100644
index 00000000000..a97fd9c1ac1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpge.b x32, x32, x32
+    cv.cmpge.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpge-b-pass.d
new file mode 100644
index 00000000000..029840c70d5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpge-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1c00107b          	cv.cmpge.b	zero,zero,zero
+   4:	1c1090fb          	cv.cmpge.b	ra,ra,ra
+   8:	1c21117b          	cv.cmpge.b	sp,sp,sp
+   c:	1c84147b          	cv.cmpge.b	s0,s0,s0
+  10:	1d4a1a7b          	cv.cmpge.b	s4,s4,s4
+  14:	1dff9ffb          	cv.cmpge.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpge-b-pass.s
new file mode 100644
index 00000000000..30f6576b832
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpge.b x0, x0, x0
+    cv.cmpge.b x1, x1, x1
+    cv.cmpge.b x2, x2, x2
+    cv.cmpge.b x8, x8, x8
+    cv.cmpge.b x20, x20, x20
+    cv.cmpge.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpge-h-fail.d
new file mode 100644
index 00000000000..7b7d123aa74
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpge-h-fail.s
+#error_output: cv-simd-cmpge-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpge-h-fail.l
new file mode 100644
index 00000000000..a9f0019ae95
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpge.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpge.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpge-h-fail.s
new file mode 100644
index 00000000000..04bd6e61f55
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpge.h x32, x32, x32
+    cv.cmpge.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpge-h-pass.d
new file mode 100644
index 00000000000..4ba0160c254
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpge-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1c00007b          	cv.cmpge.h	zero,zero,zero
+   4:	1c1080fb          	cv.cmpge.h	ra,ra,ra
+   8:	1c21017b          	cv.cmpge.h	sp,sp,sp
+   c:	1c84047b          	cv.cmpge.h	s0,s0,s0
+  10:	1d4a0a7b          	cv.cmpge.h	s4,s4,s4
+  14:	1dff8ffb          	cv.cmpge.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpge-h-pass.s
new file mode 100644
index 00000000000..83c9cbb7c5f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpge.h x0, x0, x0
+    cv.cmpge.h x1, x1, x1
+    cv.cmpge.h x2, x2, x2
+    cv.cmpge.h x8, x8, x8
+    cv.cmpge.h x20, x20, x20
+    cv.cmpge.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-b-fail.d
new file mode 100644
index 00000000000..996cd49af15
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpge-sc-b-fail.s
+#error_output: cv-simd-cmpge-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-b-fail.l
new file mode 100644
index 00000000000..2d73720e32c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpge.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpge.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-b-fail.s
new file mode 100644
index 00000000000..2282d53a132
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpge.sc.b x32, x32, x32
+    cv.cmpge.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-b-pass.d
new file mode 100644
index 00000000000..f00943ab68e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpge-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1c00507b          	cv.cmpge.sc.b	zero,zero,zero
+   4:	1c10d0fb          	cv.cmpge.sc.b	ra,ra,ra
+   8:	1c21517b          	cv.cmpge.sc.b	sp,sp,sp
+   c:	1c84547b          	cv.cmpge.sc.b	s0,s0,s0
+  10:	1d4a5a7b          	cv.cmpge.sc.b	s4,s4,s4
+  14:	1dffdffb          	cv.cmpge.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-b-pass.s
new file mode 100644
index 00000000000..d70ff7dbadb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpge.sc.b x0, x0, x0
+    cv.cmpge.sc.b x1, x1, x1
+    cv.cmpge.sc.b x2, x2, x2
+    cv.cmpge.sc.b x8, x8, x8
+    cv.cmpge.sc.b x20, x20, x20
+    cv.cmpge.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-h-fail.d
new file mode 100644
index 00000000000..e74c232991a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpge-sc-h-fail.s
+#error_output: cv-simd-cmpge-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-h-fail.l
new file mode 100644
index 00000000000..97c55e41c90
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpge.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpge.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-h-fail.s
new file mode 100644
index 00000000000..a753d789c82
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpge.sc.h x32, x32, x32
+    cv.cmpge.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-h-pass.d
new file mode 100644
index 00000000000..d44d2258a42
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpge-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1c00407b          	cv.cmpge.sc.h	zero,zero,zero
+   4:	1c10c0fb          	cv.cmpge.sc.h	ra,ra,ra
+   8:	1c21417b          	cv.cmpge.sc.h	sp,sp,sp
+   c:	1c84447b          	cv.cmpge.sc.h	s0,s0,s0
+  10:	1d4a4a7b          	cv.cmpge.sc.h	s4,s4,s4
+  14:	1dffcffb          	cv.cmpge.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-h-pass.s
new file mode 100644
index 00000000000..7013748e8ec
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpge.sc.h x0, x0, x0
+    cv.cmpge.sc.h x1, x1, x1
+    cv.cmpge.sc.h x2, x2, x2
+    cv.cmpge.sc.h x8, x8, x8
+    cv.cmpge.sc.h x20, x20, x20
+    cv.cmpge.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-b-fail.d
new file mode 100644
index 00000000000..80122bf062d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpge-sci-b-fail.s
+#error_output: cv-simd-cmpge-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-b-fail.l
new file mode 100644
index 00000000000..cfebdde1262
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpge.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.cmpge.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-b-fail.s
new file mode 100644
index 00000000000..3a1cda683e4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.cmpge.sci.b x32, x32, 20
+    cv.cmpge.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpge.sci.b x6, x7, -33
+    cv.cmpge.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-b-pass.d
new file mode 100644
index 00000000000..c7c0838d69e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpge-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1ca0707b          	cv.cmpge.sci.b	zero,zero,20
+   4:	1ca0f0fb          	cv.cmpge.sci.b	ra,ra,20
+   8:	1ca1717b          	cv.cmpge.sci.b	sp,sp,20
+   c:	1ca4747b          	cv.cmpge.sci.b	s0,s0,20
+  10:	1caa7a7b          	cv.cmpge.sci.b	s4,s4,20
+  14:	1caffffb          	cv.cmpge.sci.b	t6,t6,20
+  18:	1d03f37b          	cv.cmpge.sci.b	t1,t2,-32
+  1c:	1c03f37b          	cv.cmpge.sci.b	t1,t2,0
+  20:	1ef3f37b          	cv.cmpge.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-b-pass.s
new file mode 100644
index 00000000000..34a141f45fe
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-b-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.cmpge.sci.b x0, x0, 20
+    cv.cmpge.sci.b x1, x1, 20
+    cv.cmpge.sci.b x2, x2, 20
+    cv.cmpge.sci.b x8, x8, 20
+    cv.cmpge.sci.b x20, x20, 20
+    cv.cmpge.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.cmpge.sci.b x6, x7, -32
+    cv.cmpge.sci.b x6, x7, 0
+    cv.cmpge.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-h-fail.d
new file mode 100644
index 00000000000..b5a66ffd965
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpge-sci-h-fail.s
+#error_output: cv-simd-cmpge-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-h-fail.l
new file mode 100644
index 00000000000..b29956b0d6c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpge.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.cmpge.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-h-fail.s
new file mode 100644
index 00000000000..67c61e70c2b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.cmpge.sci.h x32, x32, 20
+    cv.cmpge.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpge.sci.h x6, x7, -33
+    cv.cmpge.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-h-pass.d
new file mode 100644
index 00000000000..4651c97bf4c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpge-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1ca0607b          	cv.cmpge.sci.h	zero,zero,20
+   4:	1ca0e0fb          	cv.cmpge.sci.h	ra,ra,20
+   8:	1ca1617b          	cv.cmpge.sci.h	sp,sp,20
+   c:	1ca4647b          	cv.cmpge.sci.h	s0,s0,20
+  10:	1caa6a7b          	cv.cmpge.sci.h	s4,s4,20
+  14:	1cafeffb          	cv.cmpge.sci.h	t6,t6,20
+  18:	1d03e37b          	cv.cmpge.sci.h	t1,t2,-32
+  1c:	1c03e37b          	cv.cmpge.sci.h	t1,t2,0
+  20:	1ef3e37b          	cv.cmpge.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-h-pass.s
new file mode 100644
index 00000000000..1ac8e796e6c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpge-sci-h-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.cmpge.sci.h x0, x0, 20
+    cv.cmpge.sci.h x1, x1, 20
+    cv.cmpge.sci.h x2, x2, 20
+    cv.cmpge.sci.h x8, x8, 20
+    cv.cmpge.sci.h x20, x20, 20
+    cv.cmpge.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.cmpge.sci.h x6, x7, -32
+    cv.cmpge.sci.h x6, x7, 0
+    cv.cmpge.sci.h x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-b-fail.d
new file mode 100644
index 00000000000..52fbe0058e4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgeu-b-fail.s
+#error_output: cv-simd-cmpgeu-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-b-fail.l
new file mode 100644
index 00000000000..a5765fd2abb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgeu.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpgeu.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-b-fail.s
new file mode 100644
index 00000000000..73f313280cf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpgeu.b x32, x32, x32
+    cv.cmpgeu.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-b-pass.d
new file mode 100644
index 00000000000..755a62d7636
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgeu-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3c00107b          	cv.cmpgeu.b	zero,zero,zero
+   4:	3c1090fb          	cv.cmpgeu.b	ra,ra,ra
+   8:	3c21117b          	cv.cmpgeu.b	sp,sp,sp
+   c:	3c84147b          	cv.cmpgeu.b	s0,s0,s0
+  10:	3d4a1a7b          	cv.cmpgeu.b	s4,s4,s4
+  14:	3dff9ffb          	cv.cmpgeu.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-b-pass.s
new file mode 100644
index 00000000000..9d134a5f9c9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpgeu.b x0, x0, x0
+    cv.cmpgeu.b x1, x1, x1
+    cv.cmpgeu.b x2, x2, x2
+    cv.cmpgeu.b x8, x8, x8
+    cv.cmpgeu.b x20, x20, x20
+    cv.cmpgeu.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-h-fail.d
new file mode 100644
index 00000000000..b026ee73432
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgeu-h-fail.s
+#error_output: cv-simd-cmpgeu-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-h-fail.l
new file mode 100644
index 00000000000..237d1505e05
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgeu.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpgeu.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-h-fail.s
new file mode 100644
index 00000000000..6c58cc8c466
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpgeu.h x32, x32, x32
+    cv.cmpgeu.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-h-pass.d
new file mode 100644
index 00000000000..ba0f05878ed
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgeu-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3c00007b          	cv.cmpgeu.h	zero,zero,zero
+   4:	3c1080fb          	cv.cmpgeu.h	ra,ra,ra
+   8:	3c21017b          	cv.cmpgeu.h	sp,sp,sp
+   c:	3c84047b          	cv.cmpgeu.h	s0,s0,s0
+  10:	3d4a0a7b          	cv.cmpgeu.h	s4,s4,s4
+  14:	3dff8ffb          	cv.cmpgeu.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-h-pass.s
new file mode 100644
index 00000000000..6981d4bf05e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpgeu.h x0, x0, x0
+    cv.cmpgeu.h x1, x1, x1
+    cv.cmpgeu.h x2, x2, x2
+    cv.cmpgeu.h x8, x8, x8
+    cv.cmpgeu.h x20, x20, x20
+    cv.cmpgeu.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-fail.d
new file mode 100644
index 00000000000..92885ecc5a7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgeu-sc-b-fail.s
+#error_output: cv-simd-cmpgeu-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-fail.l
new file mode 100644
index 00000000000..d80803402ba
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgeu.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpgeu.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-fail.s
new file mode 100644
index 00000000000..59641fd93ca
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpgeu.sc.b x32, x32, x32
+    cv.cmpgeu.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-pass.d
new file mode 100644
index 00000000000..11cf81d6cce
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgeu-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3c00507b          	cv.cmpgeu.sc.b	zero,zero,zero
+   4:	3c10d0fb          	cv.cmpgeu.sc.b	ra,ra,ra
+   8:	3c21517b          	cv.cmpgeu.sc.b	sp,sp,sp
+   c:	3c84547b          	cv.cmpgeu.sc.b	s0,s0,s0
+  10:	3d4a5a7b          	cv.cmpgeu.sc.b	s4,s4,s4
+  14:	3dffdffb          	cv.cmpgeu.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-pass.s
new file mode 100644
index 00000000000..bad8aad78b4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpgeu.sc.b x0, x0, x0
+    cv.cmpgeu.sc.b x1, x1, x1
+    cv.cmpgeu.sc.b x2, x2, x2
+    cv.cmpgeu.sc.b x8, x8, x8
+    cv.cmpgeu.sc.b x20, x20, x20
+    cv.cmpgeu.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-fail.d
new file mode 100644
index 00000000000..e8e302d2f86
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgeu-sc-h-fail.s
+#error_output: cv-simd-cmpgeu-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-fail.l
new file mode 100644
index 00000000000..711b5fd0a4f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgeu.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpgeu.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-fail.s
new file mode 100644
index 00000000000..f3e9c164cdc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpgeu.sc.h x32, x32, x32
+    cv.cmpgeu.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-pass.d
new file mode 100644
index 00000000000..145bff760d6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgeu-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3c00407b          	cv.cmpgeu.sc.h	zero,zero,zero
+   4:	3c10c0fb          	cv.cmpgeu.sc.h	ra,ra,ra
+   8:	3c21417b          	cv.cmpgeu.sc.h	sp,sp,sp
+   c:	3c84447b          	cv.cmpgeu.sc.h	s0,s0,s0
+  10:	3d4a4a7b          	cv.cmpgeu.sc.h	s4,s4,s4
+  14:	3dffcffb          	cv.cmpgeu.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-pass.s
new file mode 100644
index 00000000000..78dcb5d7faa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpgeu.sc.h x0, x0, x0
+    cv.cmpgeu.sc.h x1, x1, x1
+    cv.cmpgeu.sc.h x2, x2, x2
+    cv.cmpgeu.sc.h x8, x8, x8
+    cv.cmpgeu.sc.h x20, x20, x20
+    cv.cmpgeu.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-fail.d
new file mode 100644
index 00000000000..6f30fc63775
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgeu-sci-b-fail.s
+#error_output: cv-simd-cmpgeu-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-fail.l
new file mode 100644
index 00000000000..199cf8e2677
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgeu.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.cmpgeu.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-fail.s
new file mode 100644
index 00000000000..5ad2b6b2926
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.cmpgeu.sci.b x32, x32, 20
+    cv.cmpgeu.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpgeu.sci.b x6, x7, -1
+    cv.cmpgeu.sci.b x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-pass.d
new file mode 100644
index 00000000000..23bad539c54
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgeu-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3ca0707b          	cv.cmpgeu.sci.b	zero,zero,20
+   4:	3ca0f0fb          	cv.cmpgeu.sci.b	ra,ra,20
+   8:	3ca1717b          	cv.cmpgeu.sci.b	sp,sp,20
+   c:	3ca4747b          	cv.cmpgeu.sci.b	s0,s0,20
+  10:	3caa7a7b          	cv.cmpgeu.sci.b	s4,s4,20
+  14:	3caffffb          	cv.cmpgeu.sci.b	t6,t6,20
+  18:	3c03f37b          	cv.cmpgeu.sci.b	t1,t2,0
+  1c:	3ff3f37b          	cv.cmpgeu.sci.b	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-pass.s
new file mode 100644
index 00000000000..86db54973e1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-b-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.cmpgeu.sci.b x0, x0, 20
+    cv.cmpgeu.sci.b x1, x1, 20
+    cv.cmpgeu.sci.b x2, x2, 20
+    cv.cmpgeu.sci.b x8, x8, 20
+    cv.cmpgeu.sci.b x20, x20, 20
+    cv.cmpgeu.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.cmpgeu.sci.b x6, x7, 0
+    cv.cmpgeu.sci.b x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-fail.d
new file mode 100644
index 00000000000..850860ea855
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgeu-sci-h-fail.s
+#error_output: cv-simd-cmpgeu-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-fail.l
new file mode 100644
index 00000000000..81243bb67d0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgeu.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.cmpgeu.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-fail.s
new file mode 100644
index 00000000000..0efe6080655
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.cmpgeu.sci.h x32, x32, 20
+    cv.cmpgeu.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpgeu.sci.h x6, x7, -1
+    cv.cmpgeu.sci.h x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-pass.d
new file mode 100644
index 00000000000..8cfd2a47298
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgeu-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3ca0607b          	cv.cmpgeu.sci.h	zero,zero,20
+   4:	3ca0e0fb          	cv.cmpgeu.sci.h	ra,ra,20
+   8:	3ca1617b          	cv.cmpgeu.sci.h	sp,sp,20
+   c:	3ca4647b          	cv.cmpgeu.sci.h	s0,s0,20
+  10:	3caa6a7b          	cv.cmpgeu.sci.h	s4,s4,20
+  14:	3cafeffb          	cv.cmpgeu.sci.h	t6,t6,20
+  18:	3c03e37b          	cv.cmpgeu.sci.h	t1,t2,0
+  1c:	3ff3e37b          	cv.cmpgeu.sci.h	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-pass.s
new file mode 100644
index 00000000000..7272c7b4c68
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgeu-sci-h-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.cmpgeu.sci.h x0, x0, 20
+    cv.cmpgeu.sci.h x1, x1, 20
+    cv.cmpgeu.sci.h x2, x2, 20
+    cv.cmpgeu.sci.h x8, x8, 20
+    cv.cmpgeu.sci.h x20, x20, 20
+    cv.cmpgeu.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.cmpgeu.sci.h x6, x7, 0
+    cv.cmpgeu.sci.h x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgt-b-fail.d
new file mode 100644
index 00000000000..06713e63512
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgt-b-fail.s
+#error_output: cv-simd-cmpgt-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgt-b-fail.l
new file mode 100644
index 00000000000..4e68125dad4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgt.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpgt.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgt-b-fail.s
new file mode 100644
index 00000000000..378c6ece39b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpgt.b x32, x32, x32
+    cv.cmpgt.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgt-b-pass.d
new file mode 100644
index 00000000000..daf50430a15
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgt-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1400107b          	cv.cmpgt.b	zero,zero,zero
+   4:	141090fb          	cv.cmpgt.b	ra,ra,ra
+   8:	1421117b          	cv.cmpgt.b	sp,sp,sp
+   c:	1484147b          	cv.cmpgt.b	s0,s0,s0
+  10:	154a1a7b          	cv.cmpgt.b	s4,s4,s4
+  14:	15ff9ffb          	cv.cmpgt.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgt-b-pass.s
new file mode 100644
index 00000000000..eb895c512f6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpgt.b x0, x0, x0
+    cv.cmpgt.b x1, x1, x1
+    cv.cmpgt.b x2, x2, x2
+    cv.cmpgt.b x8, x8, x8
+    cv.cmpgt.b x20, x20, x20
+    cv.cmpgt.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgt-h-fail.d
new file mode 100644
index 00000000000..b1f8f066bb7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgt-h-fail.s
+#error_output: cv-simd-cmpgt-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgt-h-fail.l
new file mode 100644
index 00000000000..9237078e20a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgt.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpgt.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgt-h-fail.s
new file mode 100644
index 00000000000..d0c6cec4fed
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpgt.h x32, x32, x32
+    cv.cmpgt.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgt-h-pass.d
new file mode 100644
index 00000000000..74de9d8d350
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgt-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1400007b          	cv.cmpgt.h	zero,zero,zero
+   4:	141080fb          	cv.cmpgt.h	ra,ra,ra
+   8:	1421017b          	cv.cmpgt.h	sp,sp,sp
+   c:	1484047b          	cv.cmpgt.h	s0,s0,s0
+  10:	154a0a7b          	cv.cmpgt.h	s4,s4,s4
+  14:	15ff8ffb          	cv.cmpgt.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgt-h-pass.s
new file mode 100644
index 00000000000..721f9e7cc15
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpgt.h x0, x0, x0
+    cv.cmpgt.h x1, x1, x1
+    cv.cmpgt.h x2, x2, x2
+    cv.cmpgt.h x8, x8, x8
+    cv.cmpgt.h x20, x20, x20
+    cv.cmpgt.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-b-fail.d
new file mode 100644
index 00000000000..8bf0da8cbe0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgt-sc-b-fail.s
+#error_output: cv-simd-cmpgt-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-b-fail.l
new file mode 100644
index 00000000000..526c0b90ba9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgt.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpgt.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-b-fail.s
new file mode 100644
index 00000000000..d90150fdca5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpgt.sc.b x32, x32, x32
+    cv.cmpgt.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-b-pass.d
new file mode 100644
index 00000000000..a724df267d7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgt-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1400507b          	cv.cmpgt.sc.b	zero,zero,zero
+   4:	1410d0fb          	cv.cmpgt.sc.b	ra,ra,ra
+   8:	1421517b          	cv.cmpgt.sc.b	sp,sp,sp
+   c:	1484547b          	cv.cmpgt.sc.b	s0,s0,s0
+  10:	154a5a7b          	cv.cmpgt.sc.b	s4,s4,s4
+  14:	15ffdffb          	cv.cmpgt.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-b-pass.s
new file mode 100644
index 00000000000..bf0a2317a09
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpgt.sc.b x0, x0, x0
+    cv.cmpgt.sc.b x1, x1, x1
+    cv.cmpgt.sc.b x2, x2, x2
+    cv.cmpgt.sc.b x8, x8, x8
+    cv.cmpgt.sc.b x20, x20, x20
+    cv.cmpgt.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-h-fail.d
new file mode 100644
index 00000000000..03744bfd706
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgt-sc-h-fail.s
+#error_output: cv-simd-cmpgt-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-h-fail.l
new file mode 100644
index 00000000000..e13663d6149
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgt.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpgt.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-h-fail.s
new file mode 100644
index 00000000000..a69ec47ce84
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpgt.sc.h x32, x32, x32
+    cv.cmpgt.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-h-pass.d
new file mode 100644
index 00000000000..ea7792b1411
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgt-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	1400407b          	cv.cmpgt.sc.h	zero,zero,zero
+   4:	1410c0fb          	cv.cmpgt.sc.h	ra,ra,ra
+   8:	1421417b          	cv.cmpgt.sc.h	sp,sp,sp
+   c:	1484447b          	cv.cmpgt.sc.h	s0,s0,s0
+  10:	154a4a7b          	cv.cmpgt.sc.h	s4,s4,s4
+  14:	15ffcffb          	cv.cmpgt.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-h-pass.s
new file mode 100644
index 00000000000..4d9d07011d7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpgt.sc.h x0, x0, x0
+    cv.cmpgt.sc.h x1, x1, x1
+    cv.cmpgt.sc.h x2, x2, x2
+    cv.cmpgt.sc.h x8, x8, x8
+    cv.cmpgt.sc.h x20, x20, x20
+    cv.cmpgt.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-b-fail.d
new file mode 100644
index 00000000000..2919d4bb629
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgt-sci-b-fail.s
+#error_output: cv-simd-cmpgt-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-b-fail.l
new file mode 100644
index 00000000000..0afcded817f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgt.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.cmpgt.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-b-fail.s
new file mode 100644
index 00000000000..6afc6cfa887
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.cmpgt.sci.b x32, x32, 20
+    cv.cmpgt.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpgt.sci.b x6, x7, -33
+    cv.cmpgt.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-b-pass.d
new file mode 100644
index 00000000000..da3734fc1dc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgt-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	14a0707b          	cv.cmpgt.sci.b	zero,zero,20
+   4:	14a0f0fb          	cv.cmpgt.sci.b	ra,ra,20
+   8:	14a1717b          	cv.cmpgt.sci.b	sp,sp,20
+   c:	14a4747b          	cv.cmpgt.sci.b	s0,s0,20
+  10:	14aa7a7b          	cv.cmpgt.sci.b	s4,s4,20
+  14:	14affffb          	cv.cmpgt.sci.b	t6,t6,20
+  18:	1503f37b          	cv.cmpgt.sci.b	t1,t2,-32
+  1c:	1403f37b          	cv.cmpgt.sci.b	t1,t2,0
+  20:	16f3f37b          	cv.cmpgt.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-b-pass.s
new file mode 100644
index 00000000000..be38ddfe800
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-b-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.cmpgt.sci.b x0, x0, 20
+    cv.cmpgt.sci.b x1, x1, 20
+    cv.cmpgt.sci.b x2, x2, 20
+    cv.cmpgt.sci.b x8, x8, 20
+    cv.cmpgt.sci.b x20, x20, 20
+    cv.cmpgt.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.cmpgt.sci.b x6, x7, -32
+    cv.cmpgt.sci.b x6, x7, 0
+    cv.cmpgt.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-h-fail.d
new file mode 100644
index 00000000000..c90370a2788
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgt-sci-h-fail.s
+#error_output: cv-simd-cmpgt-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-h-fail.l
new file mode 100644
index 00000000000..cb3234ffa5d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgt.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.cmpgt.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-h-fail.s
new file mode 100644
index 00000000000..50e9975caf8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.cmpgt.sci.h x32, x32, 20
+    cv.cmpgt.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpgt.sci.h x6, x7, -33
+    cv.cmpgt.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-h-pass.d
new file mode 100644
index 00000000000..844dc76a020
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgt-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	14a0607b          	cv.cmpgt.sci.h	zero,zero,20
+   4:	14a0e0fb          	cv.cmpgt.sci.h	ra,ra,20
+   8:	14a1617b          	cv.cmpgt.sci.h	sp,sp,20
+   c:	14a4647b          	cv.cmpgt.sci.h	s0,s0,20
+  10:	14aa6a7b          	cv.cmpgt.sci.h	s4,s4,20
+  14:	14afeffb          	cv.cmpgt.sci.h	t6,t6,20
+  18:	1503e37b          	cv.cmpgt.sci.h	t1,t2,-32
+  1c:	1403e37b          	cv.cmpgt.sci.h	t1,t2,0
+  20:	16f3e37b          	cv.cmpgt.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-h-pass.s
new file mode 100644
index 00000000000..128e103f033
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgt-sci-h-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.cmpgt.sci.h x0, x0, 20
+    cv.cmpgt.sci.h x1, x1, 20
+    cv.cmpgt.sci.h x2, x2, 20
+    cv.cmpgt.sci.h x8, x8, 20
+    cv.cmpgt.sci.h x20, x20, 20
+    cv.cmpgt.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.cmpgt.sci.h x6, x7, -32
+    cv.cmpgt.sci.h x6, x7, 0
+    cv.cmpgt.sci.h x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-b-fail.d
new file mode 100644
index 00000000000..63ee1bdc4bd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgtu-b-fail.s
+#error_output: cv-simd-cmpgtu-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-b-fail.l
new file mode 100644
index 00000000000..dec5965c148
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgtu.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpgtu.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-b-fail.s
new file mode 100644
index 00000000000..42aa8c5611a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpgtu.b x32, x32, x32
+    cv.cmpgtu.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-b-pass.d
new file mode 100644
index 00000000000..5d3aa8d7ff5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgtu-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3400107b          	cv.cmpgtu.b	zero,zero,zero
+   4:	341090fb          	cv.cmpgtu.b	ra,ra,ra
+   8:	3421117b          	cv.cmpgtu.b	sp,sp,sp
+   c:	3484147b          	cv.cmpgtu.b	s0,s0,s0
+  10:	354a1a7b          	cv.cmpgtu.b	s4,s4,s4
+  14:	35ff9ffb          	cv.cmpgtu.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-b-pass.s
new file mode 100644
index 00000000000..d086aafd4f7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpgtu.b x0, x0, x0
+    cv.cmpgtu.b x1, x1, x1
+    cv.cmpgtu.b x2, x2, x2
+    cv.cmpgtu.b x8, x8, x8
+    cv.cmpgtu.b x20, x20, x20
+    cv.cmpgtu.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-h-fail.d
new file mode 100644
index 00000000000..fb528c57508
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgtu-h-fail.s
+#error_output: cv-simd-cmpgtu-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-h-fail.l
new file mode 100644
index 00000000000..09b6b0c67fb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgtu.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpgtu.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-h-fail.s
new file mode 100644
index 00000000000..3ddcd7aba97
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpgtu.h x32, x32, x32
+    cv.cmpgtu.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-h-pass.d
new file mode 100644
index 00000000000..a08da4ff5b2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgtu-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3400007b          	cv.cmpgtu.h	zero,zero,zero
+   4:	341080fb          	cv.cmpgtu.h	ra,ra,ra
+   8:	3421017b          	cv.cmpgtu.h	sp,sp,sp
+   c:	3484047b          	cv.cmpgtu.h	s0,s0,s0
+  10:	354a0a7b          	cv.cmpgtu.h	s4,s4,s4
+  14:	35ff8ffb          	cv.cmpgtu.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-h-pass.s
new file mode 100644
index 00000000000..5487c53a4c9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpgtu.h x0, x0, x0
+    cv.cmpgtu.h x1, x1, x1
+    cv.cmpgtu.h x2, x2, x2
+    cv.cmpgtu.h x8, x8, x8
+    cv.cmpgtu.h x20, x20, x20
+    cv.cmpgtu.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-fail.d
new file mode 100644
index 00000000000..cebe6125b5c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgtu-sc-b-fail.s
+#error_output: cv-simd-cmpgtu-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-fail.l
new file mode 100644
index 00000000000..8e61b4687f9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgtu.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpgtu.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-fail.s
new file mode 100644
index 00000000000..995f3d9f7ab
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpgtu.sc.b x32, x32, x32
+    cv.cmpgtu.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-pass.d
new file mode 100644
index 00000000000..cfbe16753df
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgtu-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3400507b          	cv.cmpgtu.sc.b	zero,zero,zero
+   4:	3410d0fb          	cv.cmpgtu.sc.b	ra,ra,ra
+   8:	3421517b          	cv.cmpgtu.sc.b	sp,sp,sp
+   c:	3484547b          	cv.cmpgtu.sc.b	s0,s0,s0
+  10:	354a5a7b          	cv.cmpgtu.sc.b	s4,s4,s4
+  14:	35ffdffb          	cv.cmpgtu.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-pass.s
new file mode 100644
index 00000000000..7433324f6fa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpgtu.sc.b x0, x0, x0
+    cv.cmpgtu.sc.b x1, x1, x1
+    cv.cmpgtu.sc.b x2, x2, x2
+    cv.cmpgtu.sc.b x8, x8, x8
+    cv.cmpgtu.sc.b x20, x20, x20
+    cv.cmpgtu.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-fail.d
new file mode 100644
index 00000000000..3dfb1d87383
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgtu-sc-h-fail.s
+#error_output: cv-simd-cmpgtu-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-fail.l
new file mode 100644
index 00000000000..db82748d2ab
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgtu.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpgtu.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-fail.s
new file mode 100644
index 00000000000..bc6a47abb5f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpgtu.sc.h x32, x32, x32
+    cv.cmpgtu.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-pass.d
new file mode 100644
index 00000000000..46f600935f6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgtu-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	3400407b          	cv.cmpgtu.sc.h	zero,zero,zero
+   4:	3410c0fb          	cv.cmpgtu.sc.h	ra,ra,ra
+   8:	3421417b          	cv.cmpgtu.sc.h	sp,sp,sp
+   c:	3484447b          	cv.cmpgtu.sc.h	s0,s0,s0
+  10:	354a4a7b          	cv.cmpgtu.sc.h	s4,s4,s4
+  14:	35ffcffb          	cv.cmpgtu.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-pass.s
new file mode 100644
index 00000000000..6f9e70effb3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpgtu.sc.h x0, x0, x0
+    cv.cmpgtu.sc.h x1, x1, x1
+    cv.cmpgtu.sc.h x2, x2, x2
+    cv.cmpgtu.sc.h x8, x8, x8
+    cv.cmpgtu.sc.h x20, x20, x20
+    cv.cmpgtu.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-fail.d
new file mode 100644
index 00000000000..511d8b71653
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgtu-sci-b-fail.s
+#error_output: cv-simd-cmpgtu-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-fail.l
new file mode 100644
index 00000000000..765eb803d77
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgtu.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.cmpgtu.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-fail.s
new file mode 100644
index 00000000000..aacb26b1159
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.cmpgtu.sci.b x32, x32, 20
+    cv.cmpgtu.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpgtu.sci.b x6, x7, -1
+    cv.cmpgtu.sci.b x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-pass.d
new file mode 100644
index 00000000000..8e230445944
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgtu-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	34a0707b          	cv.cmpgtu.sci.b	zero,zero,20
+   4:	34a0f0fb          	cv.cmpgtu.sci.b	ra,ra,20
+   8:	34a1717b          	cv.cmpgtu.sci.b	sp,sp,20
+   c:	34a4747b          	cv.cmpgtu.sci.b	s0,s0,20
+  10:	34aa7a7b          	cv.cmpgtu.sci.b	s4,s4,20
+  14:	34affffb          	cv.cmpgtu.sci.b	t6,t6,20
+  18:	3403f37b          	cv.cmpgtu.sci.b	t1,t2,0
+  1c:	37f3f37b          	cv.cmpgtu.sci.b	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-pass.s
new file mode 100644
index 00000000000..0d60dbd2792
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-b-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.cmpgtu.sci.b x0, x0, 20
+    cv.cmpgtu.sci.b x1, x1, 20
+    cv.cmpgtu.sci.b x2, x2, 20
+    cv.cmpgtu.sci.b x8, x8, 20
+    cv.cmpgtu.sci.b x20, x20, 20
+    cv.cmpgtu.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.cmpgtu.sci.b x6, x7, 0
+    cv.cmpgtu.sci.b x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-fail.d
new file mode 100644
index 00000000000..7813fc68442
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgtu-sci-h-fail.s
+#error_output: cv-simd-cmpgtu-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-fail.l
new file mode 100644
index 00000000000..424630562ee
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpgtu.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.cmpgtu.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-fail.s
new file mode 100644
index 00000000000..a3c6ae574c3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.cmpgtu.sci.h x32, x32, 20
+    cv.cmpgtu.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpgtu.sci.h x6, x7, -1
+    cv.cmpgtu.sci.h x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-pass.d
new file mode 100644
index 00000000000..9f7ea98e3fa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpgtu-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	34a0607b          	cv.cmpgtu.sci.h	zero,zero,20
+   4:	34a0e0fb          	cv.cmpgtu.sci.h	ra,ra,20
+   8:	34a1617b          	cv.cmpgtu.sci.h	sp,sp,20
+   c:	34a4647b          	cv.cmpgtu.sci.h	s0,s0,20
+  10:	34aa6a7b          	cv.cmpgtu.sci.h	s4,s4,20
+  14:	34afeffb          	cv.cmpgtu.sci.h	t6,t6,20
+  18:	3403e37b          	cv.cmpgtu.sci.h	t1,t2,0
+  1c:	37f3e37b          	cv.cmpgtu.sci.h	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-pass.s
new file mode 100644
index 00000000000..2a9d34ebfec
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpgtu-sci-h-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.cmpgtu.sci.h x0, x0, 20
+    cv.cmpgtu.sci.h x1, x1, 20
+    cv.cmpgtu.sci.h x2, x2, 20
+    cv.cmpgtu.sci.h x8, x8, 20
+    cv.cmpgtu.sci.h x20, x20, 20
+    cv.cmpgtu.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.cmpgtu.sci.h x6, x7, 0
+    cv.cmpgtu.sci.h x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmple-b-fail.d
new file mode 100644
index 00000000000..a6907dd5a95
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmple-b-fail.s
+#error_output: cv-simd-cmple-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmple-b-fail.l
new file mode 100644
index 00000000000..c1ce1e95e57
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmple.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmple.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmple-b-fail.s
new file mode 100644
index 00000000000..9c8aae64d55
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmple.b x32, x32, x32
+    cv.cmple.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmple-b-pass.d
new file mode 100644
index 00000000000..927374db6cf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmple-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2c00107b          	cv.cmple.b	zero,zero,zero
+   4:	2c1090fb          	cv.cmple.b	ra,ra,ra
+   8:	2c21117b          	cv.cmple.b	sp,sp,sp
+   c:	2c84147b          	cv.cmple.b	s0,s0,s0
+  10:	2d4a1a7b          	cv.cmple.b	s4,s4,s4
+  14:	2dff9ffb          	cv.cmple.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmple-b-pass.s
new file mode 100644
index 00000000000..5fab1cd9124
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmple.b x0, x0, x0
+    cv.cmple.b x1, x1, x1
+    cv.cmple.b x2, x2, x2
+    cv.cmple.b x8, x8, x8
+    cv.cmple.b x20, x20, x20
+    cv.cmple.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmple-h-fail.d
new file mode 100644
index 00000000000..bbc68c94565
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmple-h-fail.s
+#error_output: cv-simd-cmple-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmple-h-fail.l
new file mode 100644
index 00000000000..90dc4e90829
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmple.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmple.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmple-h-fail.s
new file mode 100644
index 00000000000..d80043ebde5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmple.h x32, x32, x32
+    cv.cmple.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmple-h-pass.d
new file mode 100644
index 00000000000..b98c0094d42
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmple-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2c00007b          	cv.cmple.h	zero,zero,zero
+   4:	2c1080fb          	cv.cmple.h	ra,ra,ra
+   8:	2c21017b          	cv.cmple.h	sp,sp,sp
+   c:	2c84047b          	cv.cmple.h	s0,s0,s0
+  10:	2d4a0a7b          	cv.cmple.h	s4,s4,s4
+  14:	2dff8ffb          	cv.cmple.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmple-h-pass.s
new file mode 100644
index 00000000000..afcf7435a36
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmple.h x0, x0, x0
+    cv.cmple.h x1, x1, x1
+    cv.cmple.h x2, x2, x2
+    cv.cmple.h x8, x8, x8
+    cv.cmple.h x20, x20, x20
+    cv.cmple.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-b-fail.d
new file mode 100644
index 00000000000..74c37e5f187
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmple-sc-b-fail.s
+#error_output: cv-simd-cmple-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-b-fail.l
new file mode 100644
index 00000000000..74b287452ea
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmple.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmple.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-b-fail.s
new file mode 100644
index 00000000000..6c2a2b3cf38
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmple.sc.b x32, x32, x32
+    cv.cmple.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-b-pass.d
new file mode 100644
index 00000000000..00120c97862
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmple-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2c00507b          	cv.cmple.sc.b	zero,zero,zero
+   4:	2c10d0fb          	cv.cmple.sc.b	ra,ra,ra
+   8:	2c21517b          	cv.cmple.sc.b	sp,sp,sp
+   c:	2c84547b          	cv.cmple.sc.b	s0,s0,s0
+  10:	2d4a5a7b          	cv.cmple.sc.b	s4,s4,s4
+  14:	2dffdffb          	cv.cmple.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-b-pass.s
new file mode 100644
index 00000000000..90d8115fb15
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmple.sc.b x0, x0, x0
+    cv.cmple.sc.b x1, x1, x1
+    cv.cmple.sc.b x2, x2, x2
+    cv.cmple.sc.b x8, x8, x8
+    cv.cmple.sc.b x20, x20, x20
+    cv.cmple.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-h-fail.d
new file mode 100644
index 00000000000..86ba75fde12
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmple-sc-h-fail.s
+#error_output: cv-simd-cmple-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-h-fail.l
new file mode 100644
index 00000000000..781dcb28e9a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmple.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmple.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-h-fail.s
new file mode 100644
index 00000000000..f88621036ca
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmple.sc.h x32, x32, x32
+    cv.cmple.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-h-pass.d
new file mode 100644
index 00000000000..750cf51f0fd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmple-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2c00407b          	cv.cmple.sc.h	zero,zero,zero
+   4:	2c10c0fb          	cv.cmple.sc.h	ra,ra,ra
+   8:	2c21417b          	cv.cmple.sc.h	sp,sp,sp
+   c:	2c84447b          	cv.cmple.sc.h	s0,s0,s0
+  10:	2d4a4a7b          	cv.cmple.sc.h	s4,s4,s4
+  14:	2dffcffb          	cv.cmple.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-h-pass.s
new file mode 100644
index 00000000000..94a4f5ea19d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmple.sc.h x0, x0, x0
+    cv.cmple.sc.h x1, x1, x1
+    cv.cmple.sc.h x2, x2, x2
+    cv.cmple.sc.h x8, x8, x8
+    cv.cmple.sc.h x20, x20, x20
+    cv.cmple.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-b-fail.d
new file mode 100644
index 00000000000..92aaddd59ff
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmple-sci-b-fail.s
+#error_output: cv-simd-cmple-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-b-fail.l
new file mode 100644
index 00000000000..6fbc895b3ea
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmple.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.cmple.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-b-fail.s
new file mode 100644
index 00000000000..76927d84bd6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.cmple.sci.b x32, x32, 20
+    cv.cmple.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmple.sci.b x6, x7, -33
+    cv.cmple.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-b-pass.d
new file mode 100644
index 00000000000..c9851df4ad5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmple-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2ca0707b          	cv.cmple.sci.b	zero,zero,20
+   4:	2ca0f0fb          	cv.cmple.sci.b	ra,ra,20
+   8:	2ca1717b          	cv.cmple.sci.b	sp,sp,20
+   c:	2ca4747b          	cv.cmple.sci.b	s0,s0,20
+  10:	2caa7a7b          	cv.cmple.sci.b	s4,s4,20
+  14:	2caffffb          	cv.cmple.sci.b	t6,t6,20
+  18:	2d03f37b          	cv.cmple.sci.b	t1,t2,-32
+  1c:	2c03f37b          	cv.cmple.sci.b	t1,t2,0
+  20:	2ef3f37b          	cv.cmple.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-b-pass.s
new file mode 100644
index 00000000000..472cda7f1de
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-b-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.cmple.sci.b x0, x0, 20
+    cv.cmple.sci.b x1, x1, 20
+    cv.cmple.sci.b x2, x2, 20
+    cv.cmple.sci.b x8, x8, 20
+    cv.cmple.sci.b x20, x20, 20
+    cv.cmple.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.cmple.sci.b x6, x7, -32
+    cv.cmple.sci.b x6, x7, 0
+    cv.cmple.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-h-fail.d
new file mode 100644
index 00000000000..30002602360
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmple-sci-h-fail.s
+#error_output: cv-simd-cmple-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-h-fail.l
new file mode 100644
index 00000000000..ccbf473dbd3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmple.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.cmple.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-h-fail.s
new file mode 100644
index 00000000000..fb4620a024f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.cmple.sci.h x32, x32, 20
+    cv.cmple.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmple.sci.h x6, x7, -33
+    cv.cmple.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-h-pass.d
new file mode 100644
index 00000000000..0a10894d659
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmple-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2ca0607b          	cv.cmple.sci.h	zero,zero,20
+   4:	2ca0e0fb          	cv.cmple.sci.h	ra,ra,20
+   8:	2ca1617b          	cv.cmple.sci.h	sp,sp,20
+   c:	2ca4647b          	cv.cmple.sci.h	s0,s0,20
+  10:	2caa6a7b          	cv.cmple.sci.h	s4,s4,20
+  14:	2cafeffb          	cv.cmple.sci.h	t6,t6,20
+  18:	2d03e37b          	cv.cmple.sci.h	t1,t2,-32
+  1c:	2c03e37b          	cv.cmple.sci.h	t1,t2,0
+  20:	2ef3e37b          	cv.cmple.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmple-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-h-pass.s
new file mode 100644
index 00000000000..fcfe70449b6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmple-sci-h-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.cmple.sci.h x0, x0, 20
+    cv.cmple.sci.h x1, x1, 20
+    cv.cmple.sci.h x2, x2, 20
+    cv.cmple.sci.h x8, x8, 20
+    cv.cmple.sci.h x20, x20, 20
+    cv.cmple.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.cmple.sci.h x6, x7, -32
+    cv.cmple.sci.h x6, x7, 0
+    cv.cmple.sci.h x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpleu-b-fail.d
new file mode 100644
index 00000000000..635991b6097
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpleu-b-fail.s
+#error_output: cv-simd-cmpleu-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpleu-b-fail.l
new file mode 100644
index 00000000000..906bb044ca7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpleu.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpleu.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpleu-b-fail.s
new file mode 100644
index 00000000000..4e44ba9c39c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpleu.b x32, x32, x32
+    cv.cmpleu.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpleu-b-pass.d
new file mode 100644
index 00000000000..8cb04f5a11a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpleu-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4c00107b          	cv.cmpleu.b	zero,zero,zero
+   4:	4c1090fb          	cv.cmpleu.b	ra,ra,ra
+   8:	4c21117b          	cv.cmpleu.b	sp,sp,sp
+   c:	4c84147b          	cv.cmpleu.b	s0,s0,s0
+  10:	4d4a1a7b          	cv.cmpleu.b	s4,s4,s4
+  14:	4dff9ffb          	cv.cmpleu.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpleu-b-pass.s
new file mode 100644
index 00000000000..f8026b29065
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpleu.b x0, x0, x0
+    cv.cmpleu.b x1, x1, x1
+    cv.cmpleu.b x2, x2, x2
+    cv.cmpleu.b x8, x8, x8
+    cv.cmpleu.b x20, x20, x20
+    cv.cmpleu.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpleu-h-fail.d
new file mode 100644
index 00000000000..f2a3d69363c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpleu-h-fail.s
+#error_output: cv-simd-cmpleu-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpleu-h-fail.l
new file mode 100644
index 00000000000..1bcab7179eb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpleu.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpleu.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpleu-h-fail.s
new file mode 100644
index 00000000000..93b039a8f10
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpleu.h x32, x32, x32
+    cv.cmpleu.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpleu-h-pass.d
new file mode 100644
index 00000000000..88510d9e822
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpleu-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4c00007b          	cv.cmpleu.h	zero,zero,zero
+   4:	4c1080fb          	cv.cmpleu.h	ra,ra,ra
+   8:	4c21017b          	cv.cmpleu.h	sp,sp,sp
+   c:	4c84047b          	cv.cmpleu.h	s0,s0,s0
+  10:	4d4a0a7b          	cv.cmpleu.h	s4,s4,s4
+  14:	4dff8ffb          	cv.cmpleu.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpleu-h-pass.s
new file mode 100644
index 00000000000..ce120275cdf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpleu.h x0, x0, x0
+    cv.cmpleu.h x1, x1, x1
+    cv.cmpleu.h x2, x2, x2
+    cv.cmpleu.h x8, x8, x8
+    cv.cmpleu.h x20, x20, x20
+    cv.cmpleu.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-b-fail.d
new file mode 100644
index 00000000000..3dbb3317678
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpleu-sc-b-fail.s
+#error_output: cv-simd-cmpleu-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-b-fail.l
new file mode 100644
index 00000000000..5fde1fae238
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpleu.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpleu.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-b-fail.s
new file mode 100644
index 00000000000..b0eb2333f24
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpleu.sc.b x32, x32, x32
+    cv.cmpleu.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-b-pass.d
new file mode 100644
index 00000000000..25200479d35
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpleu-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4c00507b          	cv.cmpleu.sc.b	zero,zero,zero
+   4:	4c10d0fb          	cv.cmpleu.sc.b	ra,ra,ra
+   8:	4c21517b          	cv.cmpleu.sc.b	sp,sp,sp
+   c:	4c84547b          	cv.cmpleu.sc.b	s0,s0,s0
+  10:	4d4a5a7b          	cv.cmpleu.sc.b	s4,s4,s4
+  14:	4dffdffb          	cv.cmpleu.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-b-pass.s
new file mode 100644
index 00000000000..3f2ecfd7e67
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpleu.sc.b x0, x0, x0
+    cv.cmpleu.sc.b x1, x1, x1
+    cv.cmpleu.sc.b x2, x2, x2
+    cv.cmpleu.sc.b x8, x8, x8
+    cv.cmpleu.sc.b x20, x20, x20
+    cv.cmpleu.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-h-fail.d
new file mode 100644
index 00000000000..9ddd9d42c7b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpleu-sc-h-fail.s
+#error_output: cv-simd-cmpleu-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-h-fail.l
new file mode 100644
index 00000000000..11438240a92
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpleu.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpleu.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-h-fail.s
new file mode 100644
index 00000000000..8265fb20add
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpleu.sc.h x32, x32, x32
+    cv.cmpleu.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-h-pass.d
new file mode 100644
index 00000000000..acbfa417945
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpleu-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4c00407b          	cv.cmpleu.sc.h	zero,zero,zero
+   4:	4c10c0fb          	cv.cmpleu.sc.h	ra,ra,ra
+   8:	4c21417b          	cv.cmpleu.sc.h	sp,sp,sp
+   c:	4c84447b          	cv.cmpleu.sc.h	s0,s0,s0
+  10:	4d4a4a7b          	cv.cmpleu.sc.h	s4,s4,s4
+  14:	4dffcffb          	cv.cmpleu.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-h-pass.s
new file mode 100644
index 00000000000..3860ae1122e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpleu.sc.h x0, x0, x0
+    cv.cmpleu.sc.h x1, x1, x1
+    cv.cmpleu.sc.h x2, x2, x2
+    cv.cmpleu.sc.h x8, x8, x8
+    cv.cmpleu.sc.h x20, x20, x20
+    cv.cmpleu.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-b-fail.d
new file mode 100644
index 00000000000..81a56d4c797
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpleu-sci-b-fail.s
+#error_output: cv-simd-cmpleu-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-b-fail.l
new file mode 100644
index 00000000000..589af59d74e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpleu.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.cmpleu.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-b-fail.s
new file mode 100644
index 00000000000..5efddc4e080
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.cmpleu.sci.b x32, x32, 20
+    cv.cmpleu.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpleu.sci.b x6, x7, -1
+    cv.cmpleu.sci.b x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-b-pass.d
new file mode 100644
index 00000000000..8a0ac6cbdfc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-b-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpleu-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4ca0707b          	cv.cmpleu.sci.b	zero,zero,20
+   4:	4ca0f0fb          	cv.cmpleu.sci.b	ra,ra,20
+   8:	4ca1717b          	cv.cmpleu.sci.b	sp,sp,20
+   c:	4ca4747b          	cv.cmpleu.sci.b	s0,s0,20
+  10:	4caa7a7b          	cv.cmpleu.sci.b	s4,s4,20
+  14:	4caffffb          	cv.cmpleu.sci.b	t6,t6,20
+  18:	4c03f37b          	cv.cmpleu.sci.b	t1,t2,0
+  1c:	4ff3f37b          	cv.cmpleu.sci.b	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-b-pass.s
new file mode 100644
index 00000000000..a5c4b273c62
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-b-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.cmpleu.sci.b x0, x0, 20
+    cv.cmpleu.sci.b x1, x1, 20
+    cv.cmpleu.sci.b x2, x2, 20
+    cv.cmpleu.sci.b x8, x8, 20
+    cv.cmpleu.sci.b x20, x20, 20
+    cv.cmpleu.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.cmpleu.sci.b x6, x7, 0
+    cv.cmpleu.sci.b x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-h-fail.d
new file mode 100644
index 00000000000..34a81b5cd8a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpleu-sci-h-fail.s
+#error_output: cv-simd-cmpleu-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-h-fail.l
new file mode 100644
index 00000000000..a7969bb4db2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpleu.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.cmpleu.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
\ No newline at end of file
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-h-fail.s
new file mode 100644
index 00000000000..a4dbd6fcb8f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.cmpleu.sci.h x32, x32, 20
+    cv.cmpleu.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpleu.sci.h x6, x7, -1
+    cv.cmpleu.sci.h x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-h-pass.d
new file mode 100644
index 00000000000..83ca67a305e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-h-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpleu-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4ca0607b          	cv.cmpleu.sci.h	zero,zero,20
+   4:	4ca0e0fb          	cv.cmpleu.sci.h	ra,ra,20
+   8:	4ca1617b          	cv.cmpleu.sci.h	sp,sp,20
+   c:	4ca4647b          	cv.cmpleu.sci.h	s0,s0,20
+  10:	4caa6a7b          	cv.cmpleu.sci.h	s4,s4,20
+  14:	4cafeffb          	cv.cmpleu.sci.h	t6,t6,20
+  18:	4c03e37b          	cv.cmpleu.sci.h	t1,t2,0
+  1c:	4ff3e37b          	cv.cmpleu.sci.h	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-h-pass.s
new file mode 100644
index 00000000000..a090b350010
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpleu-sci-h-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.cmpleu.sci.h x0, x0, 20
+    cv.cmpleu.sci.h x1, x1, 20
+    cv.cmpleu.sci.h x2, x2, 20
+    cv.cmpleu.sci.h x8, x8, 20
+    cv.cmpleu.sci.h x20, x20, 20
+    cv.cmpleu.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.cmpleu.sci.h x6, x7, 0
+    cv.cmpleu.sci.h x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmplt-b-fail.d
new file mode 100644
index 00000000000..242b75786d6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmplt-b-fail.s
+#error_output: cv-simd-cmplt-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmplt-b-fail.l
new file mode 100644
index 00000000000..0f98b08b92e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmplt.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmplt.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmplt-b-fail.s
new file mode 100644
index 00000000000..0c67c18560f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmplt.b x32, x32, x32
+    cv.cmplt.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmplt-b-pass.d
new file mode 100644
index 00000000000..90d4f22903e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmplt-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2400107b          	cv.cmplt.b	zero,zero,zero
+   4:	241090fb          	cv.cmplt.b	ra,ra,ra
+   8:	2421117b          	cv.cmplt.b	sp,sp,sp
+   c:	2484147b          	cv.cmplt.b	s0,s0,s0
+  10:	254a1a7b          	cv.cmplt.b	s4,s4,s4
+  14:	25ff9ffb          	cv.cmplt.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmplt-b-pass.s
new file mode 100644
index 00000000000..a511a83ff14
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmplt.b x0, x0, x0
+    cv.cmplt.b x1, x1, x1
+    cv.cmplt.b x2, x2, x2
+    cv.cmplt.b x8, x8, x8
+    cv.cmplt.b x20, x20, x20
+    cv.cmplt.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmplt-h-fail.d
new file mode 100644
index 00000000000..fddea37a26f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmplt-h-fail.s
+#error_output: cv-simd-cmplt-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmplt-h-fail.l
new file mode 100644
index 00000000000..b2c5298e1e3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmplt.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmplt.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmplt-h-fail.s
new file mode 100644
index 00000000000..3d47de30ab4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmplt.h x32, x32, x32
+    cv.cmplt.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmplt-h-pass.d
new file mode 100644
index 00000000000..42b980e670e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmplt-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2400007b          	cv.cmplt.h	zero,zero,zero
+   4:	241080fb          	cv.cmplt.h	ra,ra,ra
+   8:	2421017b          	cv.cmplt.h	sp,sp,sp
+   c:	2484047b          	cv.cmplt.h	s0,s0,s0
+  10:	254a0a7b          	cv.cmplt.h	s4,s4,s4
+  14:	25ff8ffb          	cv.cmplt.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmplt-h-pass.s
new file mode 100644
index 00000000000..85bcb8970a4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmplt.h x0, x0, x0
+    cv.cmplt.h x1, x1, x1
+    cv.cmplt.h x2, x2, x2
+    cv.cmplt.h x8, x8, x8
+    cv.cmplt.h x20, x20, x20
+    cv.cmplt.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-b-fail.d
new file mode 100644
index 00000000000..20491b47b11
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmplt-sc-b-fail.s
+#error_output: cv-simd-cmplt-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-b-fail.l
new file mode 100644
index 00000000000..bc8340f218b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmplt.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmplt.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-b-fail.s
new file mode 100644
index 00000000000..2fbc6c49ecc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmplt.sc.b x32, x32, x32
+    cv.cmplt.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-b-pass.d
new file mode 100644
index 00000000000..58dc2cc2458
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmplt-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2400507b          	cv.cmplt.sc.b	zero,zero,zero
+   4:	2410d0fb          	cv.cmplt.sc.b	ra,ra,ra
+   8:	2421517b          	cv.cmplt.sc.b	sp,sp,sp
+   c:	2484547b          	cv.cmplt.sc.b	s0,s0,s0
+  10:	254a5a7b          	cv.cmplt.sc.b	s4,s4,s4
+  14:	25ffdffb          	cv.cmplt.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-b-pass.s
new file mode 100644
index 00000000000..0909cd18619
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmplt.sc.b x0, x0, x0
+    cv.cmplt.sc.b x1, x1, x1
+    cv.cmplt.sc.b x2, x2, x2
+    cv.cmplt.sc.b x8, x8, x8
+    cv.cmplt.sc.b x20, x20, x20
+    cv.cmplt.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-h-fail.d
new file mode 100644
index 00000000000..9aa9ab6b6ee
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmplt-sc-h-fail.s
+#error_output: cv-simd-cmplt-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-h-fail.l
new file mode 100644
index 00000000000..9d7c9e05479
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmplt.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmplt.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-h-fail.s
new file mode 100644
index 00000000000..ffc1d9f5b98
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmplt.sc.h x32, x32, x32
+    cv.cmplt.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-h-pass.d
new file mode 100644
index 00000000000..c3a5de547e3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmplt-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	2400407b          	cv.cmplt.sc.h	zero,zero,zero
+   4:	2410c0fb          	cv.cmplt.sc.h	ra,ra,ra
+   8:	2421417b          	cv.cmplt.sc.h	sp,sp,sp
+   c:	2484447b          	cv.cmplt.sc.h	s0,s0,s0
+  10:	254a4a7b          	cv.cmplt.sc.h	s4,s4,s4
+  14:	25ffcffb          	cv.cmplt.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-h-pass.s
new file mode 100644
index 00000000000..4278bf94e05
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmplt.sc.h x0, x0, x0
+    cv.cmplt.sc.h x1, x1, x1
+    cv.cmplt.sc.h x2, x2, x2
+    cv.cmplt.sc.h x8, x8, x8
+    cv.cmplt.sc.h x20, x20, x20
+    cv.cmplt.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-b-fail.d
new file mode 100644
index 00000000000..f678f979ab3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmplt-sci-b-fail.s
+#error_output: cv-simd-cmplt-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-b-fail.l
new file mode 100644
index 00000000000..2d5cdad6b80
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmplt.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.cmplt.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-b-fail.s
new file mode 100644
index 00000000000..e1fb4dd0887
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.cmplt.sci.b x32, x32, 20
+    cv.cmplt.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmplt.sci.b x6, x7, -33
+    cv.cmplt.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-b-pass.d
new file mode 100644
index 00000000000..7ff96089553
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmplt-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	24a0707b          	cv.cmplt.sci.b	zero,zero,20
+   4:	24a0f0fb          	cv.cmplt.sci.b	ra,ra,20
+   8:	24a1717b          	cv.cmplt.sci.b	sp,sp,20
+   c:	24a4747b          	cv.cmplt.sci.b	s0,s0,20
+  10:	24aa7a7b          	cv.cmplt.sci.b	s4,s4,20
+  14:	24affffb          	cv.cmplt.sci.b	t6,t6,20
+  18:	2503f37b          	cv.cmplt.sci.b	t1,t2,-32
+  1c:	2403f37b          	cv.cmplt.sci.b	t1,t2,0
+  20:	26f3f37b          	cv.cmplt.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-b-pass.s
new file mode 100644
index 00000000000..83bcbda6b9a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-b-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.cmplt.sci.b x0, x0, 20
+    cv.cmplt.sci.b x1, x1, 20
+    cv.cmplt.sci.b x2, x2, 20
+    cv.cmplt.sci.b x8, x8, 20
+    cv.cmplt.sci.b x20, x20, 20
+    cv.cmplt.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.cmplt.sci.b x6, x7, -32
+    cv.cmplt.sci.b x6, x7, 0
+    cv.cmplt.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-h-fail.d
new file mode 100644
index 00000000000..094b86805e4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmplt-sci-h-fail.s
+#error_output: cv-simd-cmplt-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-h-fail.l
new file mode 100644
index 00000000000..6be7bcaf461
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmplt.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.cmplt.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-h-fail.s
new file mode 100644
index 00000000000..5ce5511612c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.cmplt.sci.h x32, x32, 20
+    cv.cmplt.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmplt.sci.h x6, x7, -33
+    cv.cmplt.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-h-pass.d
new file mode 100644
index 00000000000..74831942dc1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmplt-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	24a0607b          	cv.cmplt.sci.h	zero,zero,20
+   4:	24a0e0fb          	cv.cmplt.sci.h	ra,ra,20
+   8:	24a1617b          	cv.cmplt.sci.h	sp,sp,20
+   c:	24a4647b          	cv.cmplt.sci.h	s0,s0,20
+  10:	24aa6a7b          	cv.cmplt.sci.h	s4,s4,20
+  14:	24afeffb          	cv.cmplt.sci.h	t6,t6,20
+  18:	2503e37b          	cv.cmplt.sci.h	t1,t2,-32
+  1c:	2403e37b          	cv.cmplt.sci.h	t1,t2,0
+  20:	26f3e37b          	cv.cmplt.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-h-pass.s
new file mode 100644
index 00000000000..fd1d4e4a20a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmplt-sci-h-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.cmplt.sci.h x0, x0, 20
+    cv.cmplt.sci.h x1, x1, 20
+    cv.cmplt.sci.h x2, x2, 20
+    cv.cmplt.sci.h x8, x8, 20
+    cv.cmplt.sci.h x20, x20, 20
+    cv.cmplt.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.cmplt.sci.h x6, x7, -32
+    cv.cmplt.sci.h x6, x7, 0
+    cv.cmplt.sci.h x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpltu-b-fail.d
new file mode 100644
index 00000000000..0050c0dfcbc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpltu-b-fail.s
+#error_output: cv-simd-cmpltu-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpltu-b-fail.l
new file mode 100644
index 00000000000..199b24d2c5e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpltu.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpltu.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpltu-b-fail.s
new file mode 100644
index 00000000000..b2c0b184925
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpltu.b x32, x32, x32
+    cv.cmpltu.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpltu-b-pass.d
new file mode 100644
index 00000000000..ae5e5d804c4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpltu-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4400107b          	cv.cmpltu.b	zero,zero,zero
+   4:	441090fb          	cv.cmpltu.b	ra,ra,ra
+   8:	4421117b          	cv.cmpltu.b	sp,sp,sp
+   c:	4484147b          	cv.cmpltu.b	s0,s0,s0
+  10:	454a1a7b          	cv.cmpltu.b	s4,s4,s4
+  14:	45ff9ffb          	cv.cmpltu.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpltu-b-pass.s
new file mode 100644
index 00000000000..c8478657052
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpltu.b x0, x0, x0
+    cv.cmpltu.b x1, x1, x1
+    cv.cmpltu.b x2, x2, x2
+    cv.cmpltu.b x8, x8, x8
+    cv.cmpltu.b x20, x20, x20
+    cv.cmpltu.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpltu-h-fail.d
new file mode 100644
index 00000000000..b37c94721ee
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpltu-h-fail.s
+#error_output: cv-simd-cmpltu-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpltu-h-fail.l
new file mode 100644
index 00000000000..7ec17d16181
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpltu.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpltu.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpltu-h-fail.s
new file mode 100644
index 00000000000..4153184c5fb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpltu.h x32, x32, x32
+    cv.cmpltu.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpltu-h-pass.d
new file mode 100644
index 00000000000..4c15ec5cc45
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpltu-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4400007b          	cv.cmpltu.h	zero,zero,zero
+   4:	441080fb          	cv.cmpltu.h	ra,ra,ra
+   8:	4421017b          	cv.cmpltu.h	sp,sp,sp
+   c:	4484047b          	cv.cmpltu.h	s0,s0,s0
+  10:	454a0a7b          	cv.cmpltu.h	s4,s4,s4
+  14:	45ff8ffb          	cv.cmpltu.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpltu-h-pass.s
new file mode 100644
index 00000000000..de032838e09
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpltu.h x0, x0, x0
+    cv.cmpltu.h x1, x1, x1
+    cv.cmpltu.h x2, x2, x2
+    cv.cmpltu.h x8, x8, x8
+    cv.cmpltu.h x20, x20, x20
+    cv.cmpltu.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-b-fail.d
new file mode 100644
index 00000000000..50bab346eec
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpltu-sc-b-fail.s
+#error_output: cv-simd-cmpltu-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-b-fail.l
new file mode 100644
index 00000000000..0b4c9992e7f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpltu.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpltu.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-b-fail.s
new file mode 100644
index 00000000000..6541d12e631
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpltu.sc.b x32, x32, x32
+    cv.cmpltu.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-b-pass.d
new file mode 100644
index 00000000000..3aa01db8faa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpltu-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4400507b          	cv.cmpltu.sc.b	zero,zero,zero
+   4:	4410d0fb          	cv.cmpltu.sc.b	ra,ra,ra
+   8:	4421517b          	cv.cmpltu.sc.b	sp,sp,sp
+   c:	4484547b          	cv.cmpltu.sc.b	s0,s0,s0
+  10:	454a5a7b          	cv.cmpltu.sc.b	s4,s4,s4
+  14:	45ffdffb          	cv.cmpltu.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-b-pass.s
new file mode 100644
index 00000000000..9c2647130e6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpltu.sc.b x0, x0, x0
+    cv.cmpltu.sc.b x1, x1, x1
+    cv.cmpltu.sc.b x2, x2, x2
+    cv.cmpltu.sc.b x8, x8, x8
+    cv.cmpltu.sc.b x20, x20, x20
+    cv.cmpltu.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-h-fail.d
new file mode 100644
index 00000000000..8422ac02345
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpltu-sc-h-fail.s
+#error_output: cv-simd-cmpltu-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-h-fail.l
new file mode 100644
index 00000000000..aa73e2dd5e1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpltu.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpltu.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-h-fail.s
new file mode 100644
index 00000000000..af03693e229
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpltu.sc.h x32, x32, x32
+    cv.cmpltu.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-h-pass.d
new file mode 100644
index 00000000000..6437841a4fa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpltu-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	4400407b          	cv.cmpltu.sc.h	zero,zero,zero
+   4:	4410c0fb          	cv.cmpltu.sc.h	ra,ra,ra
+   8:	4421417b          	cv.cmpltu.sc.h	sp,sp,sp
+   c:	4484447b          	cv.cmpltu.sc.h	s0,s0,s0
+  10:	454a4a7b          	cv.cmpltu.sc.h	s4,s4,s4
+  14:	45ffcffb          	cv.cmpltu.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-h-pass.s
new file mode 100644
index 00000000000..9b658a00bcd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpltu.sc.h x0, x0, x0
+    cv.cmpltu.sc.h x1, x1, x1
+    cv.cmpltu.sc.h x2, x2, x2
+    cv.cmpltu.sc.h x8, x8, x8
+    cv.cmpltu.sc.h x20, x20, x20
+    cv.cmpltu.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-b-fail.d
new file mode 100644
index 00000000000..ed3751de479
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpltu-sci-b-fail.s
+#error_output: cv-simd-cmpltu-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-b-fail.l
new file mode 100644
index 00000000000..810a82147fa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpltu.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.cmpltu.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
\ No newline at end of file
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-b-fail.s
new file mode 100644
index 00000000000..54736a9389f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.cmpltu.sci.b x32, x32, 20
+    cv.cmpltu.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpltu.sci.b x6, x7, -1
+    cv.cmpltu.sci.b x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-b-pass.d
new file mode 100644
index 00000000000..2ff3f7dc5fa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-b-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpltu-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	44a0707b          	cv.cmpltu.sci.b	zero,zero,20
+   4:	44a0f0fb          	cv.cmpltu.sci.b	ra,ra,20
+   8:	44a1717b          	cv.cmpltu.sci.b	sp,sp,20
+   c:	44a4747b          	cv.cmpltu.sci.b	s0,s0,20
+  10:	44aa7a7b          	cv.cmpltu.sci.b	s4,s4,20
+  14:	44affffb          	cv.cmpltu.sci.b	t6,t6,20
+  18:	4403f37b          	cv.cmpltu.sci.b	t1,t2,0
+  1c:	47f3f37b          	cv.cmpltu.sci.b	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-b-pass.s
new file mode 100644
index 00000000000..b72b4ca49ff
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-b-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.cmpltu.sci.b x0, x0, 20
+    cv.cmpltu.sci.b x1, x1, 20
+    cv.cmpltu.sci.b x2, x2, 20
+    cv.cmpltu.sci.b x8, x8, 20
+    cv.cmpltu.sci.b x20, x20, 20
+    cv.cmpltu.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.cmpltu.sci.b x6, x7, 0
+    cv.cmpltu.sci.b x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-h-fail.d
new file mode 100644
index 00000000000..4b4a7bee880
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpltu-sci-h-fail.s
+#error_output: cv-simd-cmpltu-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-h-fail.l
new file mode 100644
index 00000000000..73a451bfccc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpltu.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.cmpltu.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
\ No newline at end of file
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-h-fail.s
new file mode 100644
index 00000000000..d32c317e769
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.cmpltu.sci.h x32, x32, 20
+    cv.cmpltu.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpltu.sci.h x6, x7, -1
+    cv.cmpltu.sci.h x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-h-pass.d
new file mode 100644
index 00000000000..5c59dce3e54
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-h-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpltu-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	44a0607b          	cv.cmpltu.sci.h	zero,zero,20
+   4:	44a0e0fb          	cv.cmpltu.sci.h	ra,ra,20
+   8:	44a1617b          	cv.cmpltu.sci.h	sp,sp,20
+   c:	44a4647b          	cv.cmpltu.sci.h	s0,s0,20
+  10:	44aa6a7b          	cv.cmpltu.sci.h	s4,s4,20
+  14:	44afeffb          	cv.cmpltu.sci.h	t6,t6,20
+  18:	4403e37b          	cv.cmpltu.sci.h	t1,t2,0
+  1c:	47f3e37b          	cv.cmpltu.sci.h	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-h-pass.s
new file mode 100644
index 00000000000..092aead3d03
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpltu-sci-h-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.cmpltu.sci.h x0, x0, 20
+    cv.cmpltu.sci.h x1, x1, 20
+    cv.cmpltu.sci.h x2, x2, 20
+    cv.cmpltu.sci.h x8, x8, 20
+    cv.cmpltu.sci.h x20, x20, 20
+    cv.cmpltu.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.cmpltu.sci.h x6, x7, 0
+    cv.cmpltu.sci.h x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpne-b-fail.d
new file mode 100644
index 00000000000..51af5dec963
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpne-b-fail.s
+#error_output: cv-simd-cmpne-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpne-b-fail.l
new file mode 100644
index 00000000000..17dd8aad0d5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpne.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpne.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpne-b-fail.s
new file mode 100644
index 00000000000..996216864f7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpne.b x32, x32, x32
+    cv.cmpne.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpne-b-pass.d
new file mode 100644
index 00000000000..8d034c7e505
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpne-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0c00107b          	cv.cmpne.b	zero,zero,zero
+   4:	0c1090fb          	cv.cmpne.b	ra,ra,ra
+   8:	0c21117b          	cv.cmpne.b	sp,sp,sp
+   c:	0c84147b          	cv.cmpne.b	s0,s0,s0
+  10:	0d4a1a7b          	cv.cmpne.b	s4,s4,s4
+  14:	0dff9ffb          	cv.cmpne.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpne-b-pass.s
new file mode 100644
index 00000000000..cec97fd1411
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpne.b x0, x0, x0
+    cv.cmpne.b x1, x1, x1
+    cv.cmpne.b x2, x2, x2
+    cv.cmpne.b x8, x8, x8
+    cv.cmpne.b x20, x20, x20
+    cv.cmpne.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpne-h-fail.d
new file mode 100644
index 00000000000..624ccd8aaaa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpne-h-fail.s
+#error_output: cv-simd-cmpne-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpne-h-fail.l
new file mode 100644
index 00000000000..0b53e8f593c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpne.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpne.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpne-h-fail.s
new file mode 100644
index 00000000000..530f083631f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpne.h x32, x32, x32
+    cv.cmpne.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpne-h-pass.d
new file mode 100644
index 00000000000..029e561a41e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpne-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0c00007b          	cv.cmpne.h	zero,zero,zero
+   4:	0c1080fb          	cv.cmpne.h	ra,ra,ra
+   8:	0c21017b          	cv.cmpne.h	sp,sp,sp
+   c:	0c84047b          	cv.cmpne.h	s0,s0,s0
+  10:	0d4a0a7b          	cv.cmpne.h	s4,s4,s4
+  14:	0dff8ffb          	cv.cmpne.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpne-h-pass.s
new file mode 100644
index 00000000000..4394e5dc22c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpne.h x0, x0, x0
+    cv.cmpne.h x1, x1, x1
+    cv.cmpne.h x2, x2, x2
+    cv.cmpne.h x8, x8, x8
+    cv.cmpne.h x20, x20, x20
+    cv.cmpne.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-b-fail.d
new file mode 100644
index 00000000000..aff55fbae53
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpne-sc-b-fail.s
+#error_output: cv-simd-cmpne-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-b-fail.l
new file mode 100644
index 00000000000..24afd896558
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpne.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.cmpne.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-b-fail.s
new file mode 100644
index 00000000000..3aaa6d53445
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpne.sc.b x32, x32, x32
+    cv.cmpne.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-b-pass.d
new file mode 100644
index 00000000000..503ca16c0e5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpne-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0c00507b          	cv.cmpne.sc.b	zero,zero,zero
+   4:	0c10d0fb          	cv.cmpne.sc.b	ra,ra,ra
+   8:	0c21517b          	cv.cmpne.sc.b	sp,sp,sp
+   c:	0c84547b          	cv.cmpne.sc.b	s0,s0,s0
+  10:	0d4a5a7b          	cv.cmpne.sc.b	s4,s4,s4
+  14:	0dffdffb          	cv.cmpne.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-b-pass.s
new file mode 100644
index 00000000000..d08bd7b5d59
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpne.sc.b x0, x0, x0
+    cv.cmpne.sc.b x1, x1, x1
+    cv.cmpne.sc.b x2, x2, x2
+    cv.cmpne.sc.b x8, x8, x8
+    cv.cmpne.sc.b x20, x20, x20
+    cv.cmpne.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-h-fail.d
new file mode 100644
index 00000000000..fc715061d72
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpne-sc-h-fail.s
+#error_output: cv-simd-cmpne-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-h-fail.l
new file mode 100644
index 00000000000..34854ac8eee
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpne.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.cmpne.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-h-fail.s
new file mode 100644
index 00000000000..f1c84c3c95f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cmpne.sc.h x32, x32, x32
+    cv.cmpne.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-h-pass.d
new file mode 100644
index 00000000000..5d36594c891
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpne-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0c00407b          	cv.cmpne.sc.h	zero,zero,zero
+   4:	0c10c0fb          	cv.cmpne.sc.h	ra,ra,ra
+   8:	0c21417b          	cv.cmpne.sc.h	sp,sp,sp
+   c:	0c84447b          	cv.cmpne.sc.h	s0,s0,s0
+  10:	0d4a4a7b          	cv.cmpne.sc.h	s4,s4,s4
+  14:	0dffcffb          	cv.cmpne.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-h-pass.s
new file mode 100644
index 00000000000..f699512ba07
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cmpne.sc.h x0, x0, x0
+    cv.cmpne.sc.h x1, x1, x1
+    cv.cmpne.sc.h x2, x2, x2
+    cv.cmpne.sc.h x8, x8, x8
+    cv.cmpne.sc.h x20, x20, x20
+    cv.cmpne.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-b-fail.d
new file mode 100644
index 00000000000..83e37b66793
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpne-sci-b-fail.s
+#error_output: cv-simd-cmpne-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-b-fail.l
new file mode 100644
index 00000000000..9ad1b198f54
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpne.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.cmpne.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-b-fail.s
new file mode 100644
index 00000000000..bd2e550e544
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.cmpne.sci.b x32, x32, 20
+    cv.cmpne.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpne.sci.b x6, x7, -33
+    cv.cmpne.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-b-pass.d
new file mode 100644
index 00000000000..0c20249d25e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpne-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0ca0707b          	cv.cmpne.sci.b	zero,zero,20
+   4:	0ca0f0fb          	cv.cmpne.sci.b	ra,ra,20
+   8:	0ca1717b          	cv.cmpne.sci.b	sp,sp,20
+   c:	0ca4747b          	cv.cmpne.sci.b	s0,s0,20
+  10:	0caa7a7b          	cv.cmpne.sci.b	s4,s4,20
+  14:	0caffffb          	cv.cmpne.sci.b	t6,t6,20
+  18:	0d03f37b          	cv.cmpne.sci.b	t1,t2,-32
+  1c:	0c03f37b          	cv.cmpne.sci.b	t1,t2,0
+  20:	0ef3f37b          	cv.cmpne.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-b-pass.s
new file mode 100644
index 00000000000..465a42d3c79
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-b-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.cmpne.sci.b x0, x0, 20
+    cv.cmpne.sci.b x1, x1, 20
+    cv.cmpne.sci.b x2, x2, 20
+    cv.cmpne.sci.b x8, x8, 20
+    cv.cmpne.sci.b x20, x20, 20
+    cv.cmpne.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.cmpne.sci.b x6, x7, -32
+    cv.cmpne.sci.b x6, x7, 0
+    cv.cmpne.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-h-fail.d
new file mode 100644
index 00000000000..0a2f50e59c4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpne-sci-h-fail.s
+#error_output: cv-simd-cmpne-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-h-fail.l
new file mode 100644
index 00000000000..eba861843c8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cmpne.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.cmpne.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-h-fail.s
new file mode 100644
index 00000000000..10b9d4d8aa8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.cmpne.sci.h x32, x32, 20
+    cv.cmpne.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.cmpne.sci.h x6, x7, -33
+    cv.cmpne.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-h-pass.d
new file mode 100644
index 00000000000..19a3e4cfe73
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cmpne-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	0ca0607b          	cv.cmpne.sci.h	zero,zero,20
+   4:	0ca0e0fb          	cv.cmpne.sci.h	ra,ra,20
+   8:	0ca1617b          	cv.cmpne.sci.h	sp,sp,20
+   c:	0ca4647b          	cv.cmpne.sci.h	s0,s0,20
+  10:	0caa6a7b          	cv.cmpne.sci.h	s4,s4,20
+  14:	0cafeffb          	cv.cmpne.sci.h	t6,t6,20
+  18:	0d03e37b          	cv.cmpne.sci.h	t1,t2,-32
+  1c:	0c03e37b          	cv.cmpne.sci.h	t1,t2,0
+  20:	0ef3e37b          	cv.cmpne.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-h-pass.s
new file mode 100644
index 00000000000..93cdf3af6cb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cmpne-sci-h-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.cmpne.sci.h x0, x0, 20
+    cv.cmpne.sci.h x1, x1, 20
+    cv.cmpne.sci.h x2, x2, 20
+    cv.cmpne.sci.h x8, x8, 20
+    cv.cmpne.sci.h x20, x20, 20
+    cv.cmpne.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.cmpne.sci.h x6, x7, -32
+    cv.cmpne.sci.h x6, x7, 0
+    cv.cmpne.sci.h x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxconj-fail.d b/gas/testsuite/gas/riscv/cv-simd-cplxconj-fail.d
new file mode 100644
index 00000000000..a0605a09309
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxconj-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxconj-fail.s
+#error_output: cv-simd-cplxconj-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxconj-fail.l b/gas/testsuite/gas/riscv/cv-simd-cplxconj-fail.l
new file mode 100644
index 00000000000..ed0844fae23
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxconj-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cplxconj x32,x32'
+.*: Error: illegal operands `cv.cplxconj x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxconj-fail.s b/gas/testsuite/gas/riscv/cv-simd-cplxconj-fail.s
new file mode 100644
index 00000000000..186e85f8ea0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxconj-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cplxconj x32, x32
+    cv.cplxconj x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxconj-pass.d b/gas/testsuite/gas/riscv/cv-simd-cplxconj-pass.d
new file mode 100644
index 00000000000..c380f769cf8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxconj-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxconj-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	5c00007b          	cv.cplxconj	zero,zero
+   4:	5c0080fb          	cv.cplxconj	ra,ra
+   8:	5c01017b          	cv.cplxconj	sp,sp
+   c:	5c04047b          	cv.cplxconj	s0,s0
+  10:	5c0a0a7b          	cv.cplxconj	s4,s4
+  14:	5c0f8ffb          	cv.cplxconj	t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxconj-pass.s b/gas/testsuite/gas/riscv/cv-simd-cplxconj-pass.s
new file mode 100644
index 00000000000..7c1fc017ef7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxconj-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cplxconj x0, x0
+    cv.cplxconj x1, x1
+    cv.cplxconj x2, x2
+    cv.cplxconj x8, x8
+    cv.cplxconj x20, x20
+    cv.cplxconj x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div2-fail.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div2-fail.d
new file mode 100644
index 00000000000..7fb7a62b8a0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div2-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-i-div2-fail.s
+#error_output: cv-simd-cplxmul-i-div2-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div2-fail.l b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div2-fail.l
new file mode 100644
index 00000000000..9af5157824d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div2-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cplxmul.i.div2 x32,x32,x32'
+.*: Error: illegal operands `cv.cplxmul.i.div2 x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div2-fail.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div2-fail.s
new file mode 100644
index 00000000000..cdd5b8f1379
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div2-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cplxmul.i.div2 x32, x32, x32
+    cv.cplxmul.i.div2 x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div2-pass.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div2-pass.d
new file mode 100644
index 00000000000..582b2c63c1e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div2-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-i-div2-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	5600207b          	cv.cplxmul.i.div2	zero,zero,zero
+   4:	5610a0fb          	cv.cplxmul.i.div2	ra,ra,ra
+   8:	5621217b          	cv.cplxmul.i.div2	sp,sp,sp
+   c:	5684247b          	cv.cplxmul.i.div2	s0,s0,s0
+  10:	574a2a7b          	cv.cplxmul.i.div2	s4,s4,s4
+  14:	57ffaffb          	cv.cplxmul.i.div2	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div2-pass.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div2-pass.s
new file mode 100644
index 00000000000..c90292dbdd9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div2-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cplxmul.i.div2 x0, x0, x0
+    cv.cplxmul.i.div2 x1, x1, x1
+    cv.cplxmul.i.div2 x2, x2, x2
+    cv.cplxmul.i.div2 x8, x8, x8
+    cv.cplxmul.i.div2 x20, x20, x20
+    cv.cplxmul.i.div2 x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div4-fail.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div4-fail.d
new file mode 100644
index 00000000000..e9b9062f17e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div4-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-i-div4-fail.s
+#error_output: cv-simd-cplxmul-i-div4-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div4-fail.l b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div4-fail.l
new file mode 100644
index 00000000000..c3efbe053eb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div4-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cplxmul.i.div4 x32,x32,x32'
+.*: Error: illegal operands `cv.cplxmul.i.div4 x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div4-fail.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div4-fail.s
new file mode 100644
index 00000000000..e5464864280
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div4-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cplxmul.i.div4 x32, x32, x32
+    cv.cplxmul.i.div4 x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div4-pass.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div4-pass.d
new file mode 100644
index 00000000000..1091785e951
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div4-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-i-div4-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	5600407b          	cv.cplxmul.i.div4	zero,zero,zero
+   4:	5610c0fb          	cv.cplxmul.i.div4	ra,ra,ra
+   8:	5621417b          	cv.cplxmul.i.div4	sp,sp,sp
+   c:	5684447b          	cv.cplxmul.i.div4	s0,s0,s0
+  10:	574a4a7b          	cv.cplxmul.i.div4	s4,s4,s4
+  14:	57ffcffb          	cv.cplxmul.i.div4	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div4-pass.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div4-pass.s
new file mode 100644
index 00000000000..95c840436b1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div4-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cplxmul.i.div4 x0, x0, x0
+    cv.cplxmul.i.div4 x1, x1, x1
+    cv.cplxmul.i.div4 x2, x2, x2
+    cv.cplxmul.i.div4 x8, x8, x8
+    cv.cplxmul.i.div4 x20, x20, x20
+    cv.cplxmul.i.div4 x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div8-fail.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div8-fail.d
new file mode 100644
index 00000000000..a5959794dfe
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div8-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-i-div8-fail.s
+#error_output: cv-simd-cplxmul-i-div8-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div8-fail.l b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div8-fail.l
new file mode 100644
index 00000000000..cc52645bf80
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div8-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cplxmul.i.div8 x32,x32,x32'
+.*: Error: illegal operands `cv.cplxmul.i.div8 x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div8-fail.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div8-fail.s
new file mode 100644
index 00000000000..04b7b4688d6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div8-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cplxmul.i.div8 x32, x32, x32
+    cv.cplxmul.i.div8 x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div8-pass.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div8-pass.d
new file mode 100644
index 00000000000..c81a1dc7c8e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div8-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-i-div8-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	5600607b          	cv.cplxmul.i.div8	zero,zero,zero
+   4:	5610e0fb          	cv.cplxmul.i.div8	ra,ra,ra
+   8:	5621617b          	cv.cplxmul.i.div8	sp,sp,sp
+   c:	5684647b          	cv.cplxmul.i.div8	s0,s0,s0
+  10:	574a6a7b          	cv.cplxmul.i.div8	s4,s4,s4
+  14:	57ffeffb          	cv.cplxmul.i.div8	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div8-pass.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div8-pass.s
new file mode 100644
index 00000000000..5a265cc97fe
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-div8-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cplxmul.i.div8 x0, x0, x0
+    cv.cplxmul.i.div8 x1, x1, x1
+    cv.cplxmul.i.div8 x2, x2, x2
+    cv.cplxmul.i.div8 x8, x8, x8
+    cv.cplxmul.i.div8 x20, x20, x20
+    cv.cplxmul.i.div8 x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-fail.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-fail.d
new file mode 100644
index 00000000000..5a1f3f4025b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-i-fail.s
+#error_output: cv-simd-cplxmul-i-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-fail.l b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-fail.l
new file mode 100644
index 00000000000..4d63c3d02b5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cplxmul.i x32,x32,x32'
+.*: Error: illegal operands `cv.cplxmul.i x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-fail.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-fail.s
new file mode 100644
index 00000000000..de8deac97b9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cplxmul.i x32, x32, x32
+    cv.cplxmul.i x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-pass.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-pass.d
new file mode 100644
index 00000000000..4c346bde03d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-i-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	5600007b          	cv.cplxmul.i	zero,zero,zero
+   4:	561080fb          	cv.cplxmul.i	ra,ra,ra
+   8:	5621017b          	cv.cplxmul.i	sp,sp,sp
+   c:	5684047b          	cv.cplxmul.i	s0,s0,s0
+  10:	574a0a7b          	cv.cplxmul.i	s4,s4,s4
+  14:	57ff8ffb          	cv.cplxmul.i	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-pass.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-pass.s
new file mode 100644
index 00000000000..f3a20c71259
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-i-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cplxmul.i x0, x0, x0
+    cv.cplxmul.i x1, x1, x1
+    cv.cplxmul.i x2, x2, x2
+    cv.cplxmul.i x8, x8, x8
+    cv.cplxmul.i x20, x20, x20
+    cv.cplxmul.i x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div2-fail.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div2-fail.d
new file mode 100644
index 00000000000..329cfbdf65e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div2-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-r-div2-fail.s
+#error_output: cv-simd-cplxmul-r-div2-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div2-fail.l b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div2-fail.l
new file mode 100644
index 00000000000..0f6c70cbaa1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div2-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cplxmul.r.div2 x32,x32,x32'
+.*: Error: illegal operands `cv.cplxmul.r.div2 x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div2-fail.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div2-fail.s
new file mode 100644
index 00000000000..f37d2ebba3d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div2-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cplxmul.r.div2 x32, x32, x32
+    cv.cplxmul.r.div2 x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div2-pass.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div2-pass.d
new file mode 100644
index 00000000000..c8e8e61b55e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div2-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-r-div2-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	5400207b          	cv.cplxmul.r.div2	zero,zero,zero
+   4:	5410a0fb          	cv.cplxmul.r.div2	ra,ra,ra
+   8:	5421217b          	cv.cplxmul.r.div2	sp,sp,sp
+   c:	5484247b          	cv.cplxmul.r.div2	s0,s0,s0
+  10:	554a2a7b          	cv.cplxmul.r.div2	s4,s4,s4
+  14:	55ffaffb          	cv.cplxmul.r.div2	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div2-pass.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div2-pass.s
new file mode 100644
index 00000000000..12af3c2e772
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div2-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cplxmul.r.div2 x0, x0, x0
+    cv.cplxmul.r.div2 x1, x1, x1
+    cv.cplxmul.r.div2 x2, x2, x2
+    cv.cplxmul.r.div2 x8, x8, x8
+    cv.cplxmul.r.div2 x20, x20, x20
+    cv.cplxmul.r.div2 x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div4-fail.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div4-fail.d
new file mode 100644
index 00000000000..e1dd762124d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div4-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-r-div4-fail.s
+#error_output: cv-simd-cplxmul-r-div4-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div4-fail.l b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div4-fail.l
new file mode 100644
index 00000000000..3fa875f7a3c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div4-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cplxmul.r.div4 x32,x32,x32'
+.*: Error: illegal operands `cv.cplxmul.r.div4 x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div4-fail.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div4-fail.s
new file mode 100644
index 00000000000..15bd239d8ce
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div4-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cplxmul.r.div4 x32, x32, x32
+    cv.cplxmul.r.div4 x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div4-pass.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div4-pass.d
new file mode 100644
index 00000000000..3f99541f5bd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div4-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-r-div4-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	5400407b          	cv.cplxmul.r.div4	zero,zero,zero
+   4:	5410c0fb          	cv.cplxmul.r.div4	ra,ra,ra
+   8:	5421417b          	cv.cplxmul.r.div4	sp,sp,sp
+   c:	5484447b          	cv.cplxmul.r.div4	s0,s0,s0
+  10:	554a4a7b          	cv.cplxmul.r.div4	s4,s4,s4
+  14:	55ffcffb          	cv.cplxmul.r.div4	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div4-pass.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div4-pass.s
new file mode 100644
index 00000000000..d14f98520ea
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div4-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cplxmul.r.div4 x0, x0, x0
+    cv.cplxmul.r.div4 x1, x1, x1
+    cv.cplxmul.r.div4 x2, x2, x2
+    cv.cplxmul.r.div4 x8, x8, x8
+    cv.cplxmul.r.div4 x20, x20, x20
+    cv.cplxmul.r.div4 x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div8-fail.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div8-fail.d
new file mode 100644
index 00000000000..02b11f31228
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div8-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-r-div8-fail.s
+#error_output: cv-simd-cplxmul-r-div8-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div8-fail.l b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div8-fail.l
new file mode 100644
index 00000000000..ba8c9752dad
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div8-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cplxmul.r.div8 x32,x32,x32'
+.*: Error: illegal operands `cv.cplxmul.r.div8 x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div8-fail.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div8-fail.s
new file mode 100644
index 00000000000..62e66c984e0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div8-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cplxmul.r.div8 x32, x32, x32
+    cv.cplxmul.r.div8 x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div8-pass.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div8-pass.d
new file mode 100644
index 00000000000..cdc13e64fcd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div8-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-r-div8-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	5400607b          	cv.cplxmul.r.div8	zero,zero,zero
+   4:	5410e0fb          	cv.cplxmul.r.div8	ra,ra,ra
+   8:	5421617b          	cv.cplxmul.r.div8	sp,sp,sp
+   c:	5484647b          	cv.cplxmul.r.div8	s0,s0,s0
+  10:	554a6a7b          	cv.cplxmul.r.div8	s4,s4,s4
+  14:	55ffeffb          	cv.cplxmul.r.div8	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div8-pass.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div8-pass.s
new file mode 100644
index 00000000000..cee5c7bbbe2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-div8-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cplxmul.r.div8 x0, x0, x0
+    cv.cplxmul.r.div8 x1, x1, x1
+    cv.cplxmul.r.div8 x2, x2, x2
+    cv.cplxmul.r.div8 x8, x8, x8
+    cv.cplxmul.r.div8 x20, x20, x20
+    cv.cplxmul.r.div8 x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-fail.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-fail.d
new file mode 100644
index 00000000000..ee4480a46e7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-r-fail.s
+#error_output: cv-simd-cplxmul-r-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-fail.l b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-fail.l
new file mode 100644
index 00000000000..f3f3a9cc542
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.cplxmul.r x32,x32,x32'
+.*: Error: illegal operands `cv.cplxmul.r x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-fail.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-fail.s
new file mode 100644
index 00000000000..b21557bb80a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.cplxmul.r x32, x32, x32
+    cv.cplxmul.r x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-pass.d b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-pass.d
new file mode 100644
index 00000000000..d8f8c7ab0d8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-cplxmul-r-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	5400007b          	cv.cplxmul.r	zero,zero,zero
+   4:	541080fb          	cv.cplxmul.r	ra,ra,ra
+   8:	5421017b          	cv.cplxmul.r	sp,sp,sp
+   c:	5484047b          	cv.cplxmul.r	s0,s0,s0
+  10:	554a0a7b          	cv.cplxmul.r	s4,s4,s4
+  14:	55ff8ffb          	cv.cplxmul.r	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-pass.s b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-pass.s
new file mode 100644
index 00000000000..e2c929a485e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-cplxmul-r-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.cplxmul.r x0, x0, x0
+    cv.cplxmul.r x1, x1, x1
+    cv.cplxmul.r x2, x2, x2
+    cv.cplxmul.r x8, x8, x8
+    cv.cplxmul.r x20, x20, x20
+    cv.cplxmul.r x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotsp-b-fail.d
new file mode 100644
index 00000000000..78a375e025f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotsp-b-fail.s
+#error_output: cv-simd-dotsp-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotsp-b-fail.l
new file mode 100644
index 00000000000..05e06134148
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotsp.b x32,x32,x32'
+.*: Error: illegal operands `cv.dotsp.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotsp-b-fail.s
new file mode 100644
index 00000000000..fea262538e2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.dotsp.b x32, x32, x32
+    cv.dotsp.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotsp-b-pass.d
new file mode 100644
index 00000000000..43fb568fe05
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotsp-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	9000107b          	cv.dotsp.b	zero,zero,zero
+   4:	901090fb          	cv.dotsp.b	ra,ra,ra
+   8:	9021117b          	cv.dotsp.b	sp,sp,sp
+   c:	9084147b          	cv.dotsp.b	s0,s0,s0
+  10:	914a1a7b          	cv.dotsp.b	s4,s4,s4
+  14:	91ff9ffb          	cv.dotsp.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotsp-b-pass.s
new file mode 100644
index 00000000000..c9c1070f479
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.dotsp.b x0, x0, x0
+    cv.dotsp.b x1, x1, x1
+    cv.dotsp.b x2, x2, x2
+    cv.dotsp.b x8, x8, x8
+    cv.dotsp.b x20, x20, x20
+    cv.dotsp.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotsp-h-fail.d
new file mode 100644
index 00000000000..cb8ba2656fb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotsp-h-fail.s
+#error_output: cv-simd-dotsp-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotsp-h-fail.l
new file mode 100644
index 00000000000..9a4969c3e92
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotsp.h x32,x32,x32'
+.*: Error: illegal operands `cv.dotsp.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotsp-h-fail.s
new file mode 100644
index 00000000000..09ccb4898c3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.dotsp.h x32, x32, x32
+    cv.dotsp.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotsp-h-pass.d
new file mode 100644
index 00000000000..b6ee73a3f15
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotsp-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	9000007b          	cv.dotsp.h	zero,zero,zero
+   4:	901080fb          	cv.dotsp.h	ra,ra,ra
+   8:	9021017b          	cv.dotsp.h	sp,sp,sp
+   c:	9084047b          	cv.dotsp.h	s0,s0,s0
+  10:	914a0a7b          	cv.dotsp.h	s4,s4,s4
+  14:	91ff8ffb          	cv.dotsp.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotsp-h-pass.s
new file mode 100644
index 00000000000..5d651502c62
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.dotsp.h x0, x0, x0
+    cv.dotsp.h x1, x1, x1
+    cv.dotsp.h x2, x2, x2
+    cv.dotsp.h x8, x8, x8
+    cv.dotsp.h x20, x20, x20
+    cv.dotsp.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-b-fail.d
new file mode 100644
index 00000000000..cd9ffacc679
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotsp-sc-b-fail.s
+#error_output: cv-simd-dotsp-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-b-fail.l
new file mode 100644
index 00000000000..f08b9016d62
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotsp.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.dotsp.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-b-fail.s
new file mode 100644
index 00000000000..594a6f54983
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.dotsp.sc.b x32, x32, x32
+    cv.dotsp.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-b-pass.d
new file mode 100644
index 00000000000..d318e9030eb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotsp-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	9000507b          	cv.dotsp.sc.b	zero,zero,zero
+   4:	9010d0fb          	cv.dotsp.sc.b	ra,ra,ra
+   8:	9021517b          	cv.dotsp.sc.b	sp,sp,sp
+   c:	9084547b          	cv.dotsp.sc.b	s0,s0,s0
+  10:	914a5a7b          	cv.dotsp.sc.b	s4,s4,s4
+  14:	91ffdffb          	cv.dotsp.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-b-pass.s
new file mode 100644
index 00000000000..2a498253989
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.dotsp.sc.b x0, x0, x0
+    cv.dotsp.sc.b x1, x1, x1
+    cv.dotsp.sc.b x2, x2, x2
+    cv.dotsp.sc.b x8, x8, x8
+    cv.dotsp.sc.b x20, x20, x20
+    cv.dotsp.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-h-fail.d
new file mode 100644
index 00000000000..6760134f668
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotsp-sc-h-fail.s
+#error_output: cv-simd-dotsp-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-h-fail.l
new file mode 100644
index 00000000000..16aa43d60bd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotsp.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.dotsp.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-h-fail.s
new file mode 100644
index 00000000000..6873a449870
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.dotsp.sc.h x32, x32, x32
+    cv.dotsp.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-h-pass.d
new file mode 100644
index 00000000000..418ccea6343
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotsp-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	9000407b          	cv.dotsp.sc.h	zero,zero,zero
+   4:	9010c0fb          	cv.dotsp.sc.h	ra,ra,ra
+   8:	9021417b          	cv.dotsp.sc.h	sp,sp,sp
+   c:	9084447b          	cv.dotsp.sc.h	s0,s0,s0
+  10:	914a4a7b          	cv.dotsp.sc.h	s4,s4,s4
+  14:	91ffcffb          	cv.dotsp.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-h-pass.s
new file mode 100644
index 00000000000..a70c8278b67
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.dotsp.sc.h x0, x0, x0
+    cv.dotsp.sc.h x1, x1, x1
+    cv.dotsp.sc.h x2, x2, x2
+    cv.dotsp.sc.h x8, x8, x8
+    cv.dotsp.sc.h x20, x20, x20
+    cv.dotsp.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-b-fail.d
new file mode 100644
index 00000000000..57ec9b6093b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotsp-sci-b-fail.s
+#error_output: cv-simd-dotsp-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-b-fail.l
new file mode 100644
index 00000000000..76fff08f39b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotsp.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.dotsp.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-b-fail.s
new file mode 100644
index 00000000000..4d6307e1a7d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.dotsp.sci.b x32, x32, 20
+    cv.dotsp.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.dotsp.sci.b x6, x7, -33
+    cv.dotsp.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-b-pass.d
new file mode 100644
index 00000000000..f89184af378
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotsp-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	90a0707b          	cv.dotsp.sci.b	zero,zero,20
+   4:	90a0f0fb          	cv.dotsp.sci.b	ra,ra,20
+   8:	90a1717b          	cv.dotsp.sci.b	sp,sp,20
+   c:	90a4747b          	cv.dotsp.sci.b	s0,s0,20
+  10:	90aa7a7b          	cv.dotsp.sci.b	s4,s4,20
+  14:	90affffb          	cv.dotsp.sci.b	t6,t6,20
+  18:	9103f37b          	cv.dotsp.sci.b	t1,t2,-32
+  1c:	9003f37b          	cv.dotsp.sci.b	t1,t2,0
+  20:	92f3f37b          	cv.dotsp.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-b-pass.s
new file mode 100644
index 00000000000..e98e027903c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-b-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.dotsp.sci.b x0, x0, 20
+    cv.dotsp.sci.b x1, x1, 20
+    cv.dotsp.sci.b x2, x2, 20
+    cv.dotsp.sci.b x8, x8, 20
+    cv.dotsp.sci.b x20, x20, 20
+    cv.dotsp.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.dotsp.sci.b x6, x7, -32
+    cv.dotsp.sci.b x6, x7, 0
+    cv.dotsp.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-h-fail.d
new file mode 100644
index 00000000000..3aba92e6349
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotsp-sci-h-fail.s
+#error_output: cv-simd-dotsp-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-h-fail.l
new file mode 100644
index 00000000000..9410a24e1c9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotsp.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.dotsp.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-h-fail.s
new file mode 100644
index 00000000000..bc7fb62d76d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.dotsp.sci.h x32, x32, 20
+    cv.dotsp.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.dotsp.sci.h x6, x7, -33
+    cv.dotsp.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-h-pass.d
new file mode 100644
index 00000000000..330dcdadab0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotsp-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	90a0607b          	cv.dotsp.sci.h	zero,zero,20
+   4:	90a0e0fb          	cv.dotsp.sci.h	ra,ra,20
+   8:	90a1617b          	cv.dotsp.sci.h	sp,sp,20
+   c:	90a4647b          	cv.dotsp.sci.h	s0,s0,20
+  10:	90aa6a7b          	cv.dotsp.sci.h	s4,s4,20
+  14:	90afeffb          	cv.dotsp.sci.h	t6,t6,20
+  18:	9103e37b          	cv.dotsp.sci.h	t1,t2,-32
+  1c:	9003e37b          	cv.dotsp.sci.h	t1,t2,0
+  20:	92f3e37b          	cv.dotsp.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-h-pass.s
new file mode 100644
index 00000000000..d0bcf39c3ff
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotsp-sci-h-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.dotsp.sci.h x0, x0, 20
+    cv.dotsp.sci.h x1, x1, 20
+    cv.dotsp.sci.h x2, x2, 20
+    cv.dotsp.sci.h x8, x8, 20
+    cv.dotsp.sci.h x20, x20, 20
+    cv.dotsp.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.dotsp.sci.h x6, x7, -32
+    cv.dotsp.sci.h x6, x7, 0
+    cv.dotsp.sci.h x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotup-b-fail.d
new file mode 100644
index 00000000000..a1acd2d00d0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotup-b-fail.s
+#error_output: cv-simd-dotup-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotup-b-fail.l
new file mode 100644
index 00000000000..7a3964aece1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotup.b x32,x32,x32'
+.*: Error: illegal operands `cv.dotup.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotup-b-fail.s
new file mode 100644
index 00000000000..858ee2aac83
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.dotup.b x32, x32, x32
+    cv.dotup.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotup-b-pass.d
new file mode 100644
index 00000000000..baee7940f2e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotup-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	8000107b          	cv.dotup.b	zero,zero,zero
+   4:	801090fb          	cv.dotup.b	ra,ra,ra
+   8:	8021117b          	cv.dotup.b	sp,sp,sp
+   c:	8084147b          	cv.dotup.b	s0,s0,s0
+  10:	814a1a7b          	cv.dotup.b	s4,s4,s4
+  14:	81ff9ffb          	cv.dotup.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotup-b-pass.s
new file mode 100644
index 00000000000..f689f8f1225
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.dotup.b x0, x0, x0
+    cv.dotup.b x1, x1, x1
+    cv.dotup.b x2, x2, x2
+    cv.dotup.b x8, x8, x8
+    cv.dotup.b x20, x20, x20
+    cv.dotup.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotup-h-fail.d
new file mode 100644
index 00000000000..744f55d56c3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotup-h-fail.s
+#error_output: cv-simd-dotup-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotup-h-fail.l
new file mode 100644
index 00000000000..3bc820e3e8b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotup.h x32,x32,x32'
+.*: Error: illegal operands `cv.dotup.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotup-h-fail.s
new file mode 100644
index 00000000000..8148e5f9a17
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.dotup.h x32, x32, x32
+    cv.dotup.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotup-h-pass.d
new file mode 100644
index 00000000000..44f9c9c7e3c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotup-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	8000007b          	cv.dotup.h	zero,zero,zero
+   4:	801080fb          	cv.dotup.h	ra,ra,ra
+   8:	8021017b          	cv.dotup.h	sp,sp,sp
+   c:	8084047b          	cv.dotup.h	s0,s0,s0
+  10:	814a0a7b          	cv.dotup.h	s4,s4,s4
+  14:	81ff8ffb          	cv.dotup.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotup-h-pass.s
new file mode 100644
index 00000000000..bf8ac6d64ad
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.dotup.h x0, x0, x0
+    cv.dotup.h x1, x1, x1
+    cv.dotup.h x2, x2, x2
+    cv.dotup.h x8, x8, x8
+    cv.dotup.h x20, x20, x20
+    cv.dotup.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-b-fail.d
new file mode 100644
index 00000000000..b43265562a7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotup-sc-b-fail.s
+#error_output: cv-simd-dotup-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-b-fail.l
new file mode 100644
index 00000000000..86044aeac47
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotup.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.dotup.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-b-fail.s
new file mode 100644
index 00000000000..c050e02c185
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.dotup.sc.b x32, x32, x32
+    cv.dotup.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-b-pass.d
new file mode 100644
index 00000000000..305d5ec70c4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotup-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	8000507b          	cv.dotup.sc.b	zero,zero,zero
+   4:	8010d0fb          	cv.dotup.sc.b	ra,ra,ra
+   8:	8021517b          	cv.dotup.sc.b	sp,sp,sp
+   c:	8084547b          	cv.dotup.sc.b	s0,s0,s0
+  10:	814a5a7b          	cv.dotup.sc.b	s4,s4,s4
+  14:	81ffdffb          	cv.dotup.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-b-pass.s
new file mode 100644
index 00000000000..332c0abd010
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.dotup.sc.b x0, x0, x0
+    cv.dotup.sc.b x1, x1, x1
+    cv.dotup.sc.b x2, x2, x2
+    cv.dotup.sc.b x8, x8, x8
+    cv.dotup.sc.b x20, x20, x20
+    cv.dotup.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-h-fail.d
new file mode 100644
index 00000000000..5f2978f4bbe
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotup-sc-h-fail.s
+#error_output: cv-simd-dotup-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-h-fail.l
new file mode 100644
index 00000000000..c2264dcdb7c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotup.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.dotup.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-h-fail.s
new file mode 100644
index 00000000000..f60879dcefc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.dotup.sc.h x32, x32, x32
+    cv.dotup.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-h-pass.d
new file mode 100644
index 00000000000..72ce17d933b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotup-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	8000407b          	cv.dotup.sc.h	zero,zero,zero
+   4:	8010c0fb          	cv.dotup.sc.h	ra,ra,ra
+   8:	8021417b          	cv.dotup.sc.h	sp,sp,sp
+   c:	8084447b          	cv.dotup.sc.h	s0,s0,s0
+  10:	814a4a7b          	cv.dotup.sc.h	s4,s4,s4
+  14:	81ffcffb          	cv.dotup.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-h-pass.s
new file mode 100644
index 00000000000..305442c7bcc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.dotup.sc.h x0, x0, x0
+    cv.dotup.sc.h x1, x1, x1
+    cv.dotup.sc.h x2, x2, x2
+    cv.dotup.sc.h x8, x8, x8
+    cv.dotup.sc.h x20, x20, x20
+    cv.dotup.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-b-fail.d
new file mode 100644
index 00000000000..1e1d17b7df2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotup-sci-b-fail.s
+#error_output: cv-simd-dotup-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-b-fail.l
new file mode 100644
index 00000000000..06ab6ad68c9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotup.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.dotup.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-b-fail.s
new file mode 100644
index 00000000000..94e34518ccf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.dotup.sci.b x32, x32, 20
+    cv.dotup.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.dotup.sci.b x6, x7, -1
+    cv.dotup.sci.b x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-b-pass.d
new file mode 100644
index 00000000000..e730b7157e8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-b-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotup-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	80a0707b          	cv.dotup.sci.b	zero,zero,20
+   4:	80a0f0fb          	cv.dotup.sci.b	ra,ra,20
+   8:	80a1717b          	cv.dotup.sci.b	sp,sp,20
+   c:	80a4747b          	cv.dotup.sci.b	s0,s0,20
+  10:	80aa7a7b          	cv.dotup.sci.b	s4,s4,20
+  14:	80affffb          	cv.dotup.sci.b	t6,t6,20
+  18:	8003f37b          	cv.dotup.sci.b	t1,t2,0
+  1c:	83f3f37b          	cv.dotup.sci.b	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-b-pass.s
new file mode 100644
index 00000000000..9dcb63433f1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-b-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.dotup.sci.b x0, x0, 20
+    cv.dotup.sci.b x1, x1, 20
+    cv.dotup.sci.b x2, x2, 20
+    cv.dotup.sci.b x8, x8, 20
+    cv.dotup.sci.b x20, x20, 20
+    cv.dotup.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.dotup.sci.b x6, x7, 0
+    cv.dotup.sci.b x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-h-fail.d
new file mode 100644
index 00000000000..b2d54310161
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotup-sci-h-fail.s
+#error_output: cv-simd-dotup-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-h-fail.l
new file mode 100644
index 00000000000..f62408540de
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotup.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.dotup.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 6-bit unsigned, 64 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-h-fail.s
new file mode 100644
index 00000000000..5e08fc7a4ad
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.dotup.sci.h x32, x32, 20
+    cv.dotup.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.dotup.sci.h x6, x7, -1
+    cv.dotup.sci.h x6, x7, 64
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-h-pass.d
new file mode 100644
index 00000000000..fed5c6b5b8c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-h-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotup-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	80a0607b          	cv.dotup.sci.h	zero,zero,20
+   4:	80a0e0fb          	cv.dotup.sci.h	ra,ra,20
+   8:	80a1617b          	cv.dotup.sci.h	sp,sp,20
+   c:	80a4647b          	cv.dotup.sci.h	s0,s0,20
+  10:	80aa6a7b          	cv.dotup.sci.h	s4,s4,20
+  14:	80afeffb          	cv.dotup.sci.h	t6,t6,20
+  18:	8003e37b          	cv.dotup.sci.h	t1,t2,0
+  1c:	83f3e37b          	cv.dotup.sci.h	t1,t2,63
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotup-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-h-pass.s
new file mode 100644
index 00000000000..3ea446ded09
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotup-sci-h-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.dotup.sci.h x0, x0, 20
+    cv.dotup.sci.h x1, x1, 20
+    cv.dotup.sci.h x2, x2, 20
+    cv.dotup.sci.h x8, x8, 20
+    cv.dotup.sci.h x20, x20, 20
+    cv.dotup.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.dotup.sci.h x6, x7, 0
+    cv.dotup.sci.h x6, x7, 63
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotusp-b-fail.d
new file mode 100644
index 00000000000..cefd5542193
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotusp-b-fail.s
+#error_output: cv-simd-dotusp-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotusp-b-fail.l
new file mode 100644
index 00000000000..da8dcc44589
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotusp.b x32,x32,x32'
+.*: Error: illegal operands `cv.dotusp.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotusp-b-fail.s
new file mode 100644
index 00000000000..f7a1dfa2415
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.dotusp.b x32, x32, x32
+    cv.dotusp.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotusp-b-pass.d
new file mode 100644
index 00000000000..adb512c1d6d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotusp-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	8800107b          	cv.dotusp.b	zero,zero,zero
+   4:	881090fb          	cv.dotusp.b	ra,ra,ra
+   8:	8821117b          	cv.dotusp.b	sp,sp,sp
+   c:	8884147b          	cv.dotusp.b	s0,s0,s0
+  10:	894a1a7b          	cv.dotusp.b	s4,s4,s4
+  14:	89ff9ffb          	cv.dotusp.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotusp-b-pass.s
new file mode 100644
index 00000000000..50d191e0053
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.dotusp.b x0, x0, x0
+    cv.dotusp.b x1, x1, x1
+    cv.dotusp.b x2, x2, x2
+    cv.dotusp.b x8, x8, x8
+    cv.dotusp.b x20, x20, x20
+    cv.dotusp.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotusp-h-fail.d
new file mode 100644
index 00000000000..fdede84e736
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotusp-h-fail.s
+#error_output: cv-simd-dotusp-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotusp-h-fail.l
new file mode 100644
index 00000000000..3b025c9b718
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotusp.h x32,x32,x32'
+.*: Error: illegal operands `cv.dotusp.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotusp-h-fail.s
new file mode 100644
index 00000000000..69fd8c4b4f4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.dotusp.h x32, x32, x32
+    cv.dotusp.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotusp-h-pass.d
new file mode 100644
index 00000000000..4727622b959
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotusp-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	8800007b          	cv.dotusp.h	zero,zero,zero
+   4:	881080fb          	cv.dotusp.h	ra,ra,ra
+   8:	8821017b          	cv.dotusp.h	sp,sp,sp
+   c:	8884047b          	cv.dotusp.h	s0,s0,s0
+  10:	894a0a7b          	cv.dotusp.h	s4,s4,s4
+  14:	89ff8ffb          	cv.dotusp.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotusp-h-pass.s
new file mode 100644
index 00000000000..77e58734be0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.dotusp.h x0, x0, x0
+    cv.dotusp.h x1, x1, x1
+    cv.dotusp.h x2, x2, x2
+    cv.dotusp.h x8, x8, x8
+    cv.dotusp.h x20, x20, x20
+    cv.dotusp.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-b-fail.d
new file mode 100644
index 00000000000..dc763469da8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotusp-sc-b-fail.s
+#error_output: cv-simd-dotusp-sc-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-b-fail.l
new file mode 100644
index 00000000000..c1c7d325c99
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-b-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotusp.sc.b x32,x32,x32'
+.*: Error: illegal operands `cv.dotusp.sc.b x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-b-fail.s
new file mode 100644
index 00000000000..7a2863a5679
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-b-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.dotusp.sc.b x32, x32, x32
+    cv.dotusp.sc.b x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-b-pass.d
new file mode 100644
index 00000000000..a8c2408e753
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-b-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotusp-sc-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	8800507b          	cv.dotusp.sc.b	zero,zero,zero
+   4:	8810d0fb          	cv.dotusp.sc.b	ra,ra,ra
+   8:	8821517b          	cv.dotusp.sc.b	sp,sp,sp
+   c:	8884547b          	cv.dotusp.sc.b	s0,s0,s0
+  10:	894a5a7b          	cv.dotusp.sc.b	s4,s4,s4
+  14:	89ffdffb          	cv.dotusp.sc.b	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-b-pass.s
new file mode 100644
index 00000000000..6318c733d95
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-b-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.dotusp.sc.b x0, x0, x0
+    cv.dotusp.sc.b x1, x1, x1
+    cv.dotusp.sc.b x2, x2, x2
+    cv.dotusp.sc.b x8, x8, x8
+    cv.dotusp.sc.b x20, x20, x20
+    cv.dotusp.sc.b x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-h-fail.d
new file mode 100644
index 00000000000..aa166ddc6e7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotusp-sc-h-fail.s
+#error_output: cv-simd-dotusp-sc-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-h-fail.l
new file mode 100644
index 00000000000..48e1819aa53
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-h-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotusp.sc.h x32,x32,x32'
+.*: Error: illegal operands `cv.dotusp.sc.h x33,x33,x33'
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-h-fail.s
new file mode 100644
index 00000000000..1ef27353cdf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-h-fail.s
@@ -0,0 +1,4 @@
+target:
+    #Boundary Register Tests
+    cv.dotusp.sc.h x32, x32, x32
+    cv.dotusp.sc.h x33, x33, x33
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-h-pass.d
new file mode 100644
index 00000000000..a3afc79157e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-h-pass.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotusp-sc-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	8800407b          	cv.dotusp.sc.h	zero,zero,zero
+   4:	8810c0fb          	cv.dotusp.sc.h	ra,ra,ra
+   8:	8821417b          	cv.dotusp.sc.h	sp,sp,sp
+   c:	8884447b          	cv.dotusp.sc.h	s0,s0,s0
+  10:	894a4a7b          	cv.dotusp.sc.h	s4,s4,s4
+  14:	89ffcffb          	cv.dotusp.sc.h	t6,t6,t6
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-h-pass.s
new file mode 100644
index 00000000000..04e69bc7c6d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sc-h-pass.s
@@ -0,0 +1,8 @@
+target:
+    #Register Tests
+    cv.dotusp.sc.h x0, x0, x0
+    cv.dotusp.sc.h x1, x1, x1
+    cv.dotusp.sc.h x2, x2, x2
+    cv.dotusp.sc.h x8, x8, x8
+    cv.dotusp.sc.h x20, x20, x20
+    cv.dotusp.sc.h x31, x31, x31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-b-fail.d
new file mode 100644
index 00000000000..0ea3d54f7c7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotusp-sci-b-fail.s
+#error_output: cv-simd-dotusp-sci-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-b-fail.l
new file mode 100644
index 00000000000..6e3e7bf28de
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotusp.sci.b x32,x32,20'
+.*: Error: illegal operands `cv.dotusp.sci.b x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-b-fail.s
new file mode 100644
index 00000000000..78198cf290d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.dotusp.sci.b x32, x32, 20
+    cv.dotusp.sci.b x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.dotusp.sci.b x6, x7, -33
+    cv.dotusp.sci.b x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-b-pass.d
new file mode 100644
index 00000000000..e9f956ad384
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-b-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotusp-sci-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	88a0707b          	cv.dotusp.sci.b	zero,zero,20
+   4:	88a0f0fb          	cv.dotusp.sci.b	ra,ra,20
+   8:	88a1717b          	cv.dotusp.sci.b	sp,sp,20
+   c:	88a4747b          	cv.dotusp.sci.b	s0,s0,20
+  10:	88aa7a7b          	cv.dotusp.sci.b	s4,s4,20
+  14:	88affffb          	cv.dotusp.sci.b	t6,t6,20
+  18:	8903f37b          	cv.dotusp.sci.b	t1,t2,-32
+  1c:	8803f37b          	cv.dotusp.sci.b	t1,t2,0
+  20:	8af3f37b          	cv.dotusp.sci.b	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-b-pass.s
new file mode 100644
index 00000000000..618abbb88cb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-b-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.dotusp.sci.b x0, x0, 20
+    cv.dotusp.sci.b x1, x1, 20
+    cv.dotusp.sci.b x2, x2, 20
+    cv.dotusp.sci.b x8, x8, 20
+    cv.dotusp.sci.b x20, x20, 20
+    cv.dotusp.sci.b x31, x31, 20
+    #Immediate Values Test
+    cv.dotusp.sci.b x6, x7, -32
+    cv.dotusp.sci.b x6, x7, 0
+    cv.dotusp.sci.b x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-h-fail.d
new file mode 100644
index 00000000000..89ed824b8a6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotusp-sci-h-fail.s
+#error_output: cv-simd-dotusp-sci-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-h-fail.l
new file mode 100644
index 00000000000..99f14c09c12
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.dotusp.sci.h x32,x32,20'
+.*: Error: illegal operands `cv.dotusp.sci.h x33,x33,20'
+.*: Error: immediate value must be 6-bit signed, -33 is out of range
+.*: Error: immediate value must be 6-bit signed, 32 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-h-fail.s
new file mode 100644
index 00000000000..b5ae531aa6f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.dotusp.sci.h x32, x32, 20
+    cv.dotusp.sci.h x33, x33, 20
+    #Boundary Immediate Values Test
+    cv.dotusp.sci.h x6, x7, -33
+    cv.dotusp.sci.h x6, x7, 32
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-h-pass.d b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-h-pass.d
new file mode 100644
index 00000000000..cb5e2aeca57
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-h-pass.d
@@ -0,0 +1,19 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-dotusp-sci-h-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	88a0607b          	cv.dotusp.sci.h	zero,zero,20
+   4:	88a0e0fb          	cv.dotusp.sci.h	ra,ra,20
+   8:	88a1617b          	cv.dotusp.sci.h	sp,sp,20
+   c:	88a4647b          	cv.dotusp.sci.h	s0,s0,20
+  10:	88aa6a7b          	cv.dotusp.sci.h	s4,s4,20
+  14:	88afeffb          	cv.dotusp.sci.h	t6,t6,20
+  18:	8903e37b          	cv.dotusp.sci.h	t1,t2,-32
+  1c:	8803e37b          	cv.dotusp.sci.h	t1,t2,0
+  20:	8af3e37b          	cv.dotusp.sci.h	t1,t2,31
diff --git a/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-h-pass.s b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-h-pass.s
new file mode 100644
index 00000000000..991095197f0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-dotusp-sci-h-pass.s
@@ -0,0 +1,12 @@
+target:
+    #Register Tests
+    cv.dotusp.sci.h x0, x0, 20
+    cv.dotusp.sci.h x1, x1, 20
+    cv.dotusp.sci.h x2, x2, 20
+    cv.dotusp.sci.h x8, x8, 20
+    cv.dotusp.sci.h x20, x20, 20
+    cv.dotusp.sci.h x31, x31, 20
+    #Immediate Values Test
+    cv.dotusp.sci.h x6, x7, -32
+    cv.dotusp.sci.h x6, x7, 0
+    cv.dotusp.sci.h x6, x7, 31
diff --git a/gas/testsuite/gas/riscv/cv-simd-extract-b-fail.d b/gas/testsuite/gas/riscv/cv-simd-extract-b-fail.d
new file mode 100644
index 00000000000..dc987eef71c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extract-b-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-extract-b-fail.s
+#error_output: cv-simd-extract-b-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-extract-b-fail.l b/gas/testsuite/gas/riscv/cv-simd-extract-b-fail.l
new file mode 100644
index 00000000000..8bd2af78338
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extract-b-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.extract.b x32,x32,2'
+.*: Error: illegal operands `cv.extract.b x33,x33,2'
+.*: Error: immediate value must be 2-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 2-bit unsigned, 4 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-extract-b-fail.s b/gas/testsuite/gas/riscv/cv-simd-extract-b-fail.s
new file mode 100644
index 00000000000..bb5fc63e2b3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extract-b-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.extract.b x32, x32, 2
+    cv.extract.b x33, x33, 2
+    #Boundary Immediate Values Test
+    cv.extract.b x6, x7, -1
+    cv.extract.b x6, x7, 4
diff --git a/gas/testsuite/gas/riscv/cv-simd-extract-b-pass.d b/gas/testsuite/gas/riscv/cv-simd-extract-b-pass.d
new file mode 100644
index 00000000000..4e66cffd156
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extract-b-pass.d
@@ -0,0 +1,18 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-extract-b-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+   0:	b810107b          	cv.extract.b	zero,zero,2
+   4:	b81090fb          	cv.extract.b	ra,ra,2
+   8:	b811117b          	cv.extract.b	sp,sp,2
+   c:	b814147b          	cv.extract.b	s0,s0,2
+  10:	b81a1a7b          	cv.extract.b	s4,s4,2
+  14:	b81f9ffb          	cv.extract.b	t6,t6,2
+  18:	b803937b          	cv.extract.b	t1,t2,0
+  1c:	ba13937b          	cv.extract.b	t1,t2,3
diff --git a/gas/testsuite/gas/riscv/cv-simd-extract-b-pass.s b/gas/testsuite/gas/riscv/cv-simd-extract-b-pass.s
new file mode 100644
index 00000000000..04e87dbb847
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extract-b-pass.s
@@ -0,0 +1,11 @@
+target:
+    #Register Tests
+    cv.extract.b x0, x0, 2
+    cv.extract.b x1, x1, 2
+    cv.extract.b x2, x2, 2
+    cv.extract.b x8, x8, 2
+    cv.extract.b x20, x20, 2
+    cv.extract.b x31, x31, 2
+    #Immediate Values Test
+    cv.extract.b x6, x7, 0
+    cv.extract.b x6, x7, 3
diff --git a/gas/testsuite/gas/riscv/cv-simd-extract-h-fail.d b/gas/testsuite/gas/riscv/cv-simd-extract-h-fail.d
new file mode 100644
index 00000000000..b6f94bfb620
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extract-h-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvsimd
+#source: cv-simd-extract-h-fail.s
+#error_output: cv-simd-extract-h-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-simd-extract-h-fail.l b/gas/testsuite/gas/riscv/cv-simd-extract-h-fail.l
new file mode 100644
index 00000000000..efea5128201
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extract-h-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.extract.h x32,x32,1'
+.*: Error: illegal operands `cv.extract.h x33,x33,1'
+.*: Error: immediate value must be 1-bit unsigned, -1 is out of range
+.*: Error: immediate value must be 1-bit unsigned, 2 is out of range
diff --git a/gas/testsuite/gas/riscv/cv-simd-extract-h-fail.s b/gas/testsuite/gas/riscv/cv-simd-extract-h-fail.s
new file mode 100644
index 00000000000..bed9dc60b29
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-simd-extract-h-fail.s
@@ -0,0 +1,7 @@
+target:
+    #Boundary Register Tests
+    cv.extract.h x32, x32, 1
+    cv.extract.h x33, x33, 1
+    #Boundary Immediate Values Test
+    cv.extract.h x6, x7, -1
+    cv.extract.h x6, x7, 2