* [PATCH 0/6] [RFD] arm: Remove support for the Cirrus Maverick co-processor
@ 2024-05-02 11:44 Richard Earnshaw
2024-05-02 11:44 ` [PATCH 1/6] arm: remove tests for Maverick FPU extensions Richard Earnshaw
` (5 more replies)
0 siblings, 6 replies; 7+ messages in thread
From: Richard Earnshaw @ 2024-05-02 11:44 UTC (permalink / raw)
To: binutils; +Cc: Richard Earnshaw
The Arm port is in need of a bit of a cleanup. In particular we still
have code to handle some long obsolete technologies. That was OK
while this wasn't really impacting development, but things have moved
on and some of the support for legacy ABIs is now starting to hinder
us.
So this patch series is the first of several to start removing some of
that obsolete code. I expect updates to remove FPA and the old ABI on
ELF to follow in due course.
The Maverick co-processor was a Cirrus extension to the Arm920T;
support for it was removed from GCC back in 2012; this patch series
does a similar cleanup for binutils.
Richard Earnshaw (6):
arm: remove tests for Maverick FPU extensions
arm: remove Maverick support from the assembler.
arm: binutils: drop Maverick support.
arm: opcodes: remove Maverick disassembly.
arm: remove Maverick support from BFD.
arm: update documentation for removal of the Maverick extension
bfd/cpu-arm.c | 70 +--
bfd/elf32-arm.c | 26 +-
binutils/NEWS | 4 +
binutils/readelf.c | 4 -
gas/config/tc-arm.c | 183 +-----
gas/doc/c-arm.texi | 11 +-
gas/testsuite/gas/arm/attr-mfpu-maverick.d | 11 -
.../gas/arm/copro-arm_v2plus-arm_v2.d | 8 +-
.../arm/copro-thumb_v6t2plus-thumb_v6t2-1.d | 8 +-
.../gas/arm/group-reloc-ldc-encoding-bad.l | 192 -------
.../gas/arm/group-reloc-ldc-encoding-bad.s | 14 -
.../gas/arm/group-reloc-ldc-parsing-bad.l | 80 ---
.../gas/arm/group-reloc-ldc-parsing-bad.s | 11 -
gas/testsuite/gas/arm/group-reloc-ldc.d | 192 -------
gas/testsuite/gas/arm/group-reloc-ldc.s | 9 -
gas/testsuite/gas/arm/maverick.c | 534 ------------------
gas/testsuite/gas/arm/maverick.d | 477 ----------------
gas/testsuite/gas/arm/maverick.s | 470 ---------------
gas/testsuite/gas/arm/note-march-ep9312.d | 13 -
gas/testsuite/gas/arm/note-march-ep9312.s | 7 -
include/elf/arm.h | 2 +-
include/opcode/arm.h | 8 +-
opcodes/arm-dis.c | 179 +-----
23 files changed, 47 insertions(+), 2466 deletions(-)
delete mode 100644 gas/testsuite/gas/arm/attr-mfpu-maverick.d
delete mode 100644 gas/testsuite/gas/arm/maverick.c
delete mode 100644 gas/testsuite/gas/arm/maverick.d
delete mode 100644 gas/testsuite/gas/arm/maverick.s
delete mode 100644 gas/testsuite/gas/arm/note-march-ep9312.d
delete mode 100644 gas/testsuite/gas/arm/note-march-ep9312.s
--
2.34.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/6] arm: remove tests for Maverick FPU extensions
2024-05-02 11:44 [PATCH 0/6] [RFD] arm: Remove support for the Cirrus Maverick co-processor Richard Earnshaw
@ 2024-05-02 11:44 ` Richard Earnshaw
2024-05-02 11:44 ` [PATCH 2/6] arm: remove Maverick support from the assembler Richard Earnshaw
` (4 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Richard Earnshaw @ 2024-05-02 11:44 UTC (permalink / raw)
To: binutils; +Cc: Richard Earnshaw
[-- Attachment #1: Type: text/plain, Size: 1186 bytes --]
Before removing the code itself, remove the tests that will no-longer
apply.
---
gas/testsuite/gas/arm/attr-mfpu-maverick.d | 11 -
.../gas/arm/group-reloc-ldc-encoding-bad.l | 192 -------
.../gas/arm/group-reloc-ldc-encoding-bad.s | 14 -
.../gas/arm/group-reloc-ldc-parsing-bad.l | 80 ---
.../gas/arm/group-reloc-ldc-parsing-bad.s | 11 -
gas/testsuite/gas/arm/group-reloc-ldc.d | 192 -------
gas/testsuite/gas/arm/group-reloc-ldc.s | 9 -
gas/testsuite/gas/arm/maverick.c | 534 ------------------
gas/testsuite/gas/arm/maverick.d | 477 ----------------
gas/testsuite/gas/arm/maverick.s | 470 ---------------
gas/testsuite/gas/arm/note-march-ep9312.d | 13 -
gas/testsuite/gas/arm/note-march-ep9312.s | 7 -
12 files changed, 2010 deletions(-)
delete mode 100644 gas/testsuite/gas/arm/attr-mfpu-maverick.d
delete mode 100644 gas/testsuite/gas/arm/maverick.c
delete mode 100644 gas/testsuite/gas/arm/maverick.d
delete mode 100644 gas/testsuite/gas/arm/maverick.s
delete mode 100644 gas/testsuite/gas/arm/note-march-ep9312.d
delete mode 100644 gas/testsuite/gas/arm/note-march-ep9312.s
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 0001-arm-remove-tests-for-Maverick-FPU-extensions.patch --]
[-- Type: text/x-patch; name="0001-arm-remove-tests-for-Maverick-FPU-extensions.patch", Size: 97245 bytes --]
diff --git a/gas/testsuite/gas/arm/attr-mfpu-maverick.d b/gas/testsuite/gas/arm/attr-mfpu-maverick.d
deleted file mode 100644
index 433245e3470..00000000000
--- a/gas/testsuite/gas/arm/attr-mfpu-maverick.d
+++ /dev/null
@@ -1,11 +0,0 @@
-# name: attributes for -mfpu=maverick
-# source: blank.s
-# as: -mfpu=maverick
-# readelf: -A
-# This test is only valid on EABI based ports.
-# target: *-*-*eabi* *-*-nacl*
-
-Attribute Section: aeabi
-File Attributes
- Tag_ARM_ISA_use: Yes
- Tag_THUMB_ISA_use: Thumb-1
diff --git a/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.l b/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.l
index 22e53a5901d..191c5c659ea 100644
--- a/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.l
+++ b/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.l
@@ -527,195 +527,3 @@
[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
-[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
-[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
diff --git a/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.s b/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.s
index 5ab27c25fb7..1d402f9eee3 100644
--- a/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.s
+++ b/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.s
@@ -153,17 +153,3 @@
vfp_test vldr vstr d0 0x1
vfp_test vldr vstr d0 0x808
-@ CFLDRS/CFLDRD/CFLDR32/CFLDR64/CFSTRS/CFSTRD/CFSTR32/CFSTR64
-
- .cpu ep9312
-
- vfp_test cfldrs cfstrs mvf0 0x1
- vfp_test cfldrd cfstrd mvd0 0x1
- vfp_test cfldr32 cfstr32 mvfx0 0x1
- vfp_test cfldr64 cfstr64 mvdx0 0x1
-
- vfp_test cfldrs cfstrs mvf0 0x808
- vfp_test cfldrd cfstrd mvd0 0x808
- vfp_test cfldr32 cfstr32 mvfx0 0x808
- vfp_test cfldr64 cfstr64 mvdx0 0x808
-
diff --git a/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.l b/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.l
index 8fc3134012d..69526865312 100644
--- a/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.l
+++ b/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.l
@@ -210,83 +210,3 @@
[^:]*:55: *Info: macro .*
[^:]*:21: Error: unknown group relocation -- `vstr d0,\[r0,#:foo:\(sym\)\]'
[^:]*:55: *Info: macro .*
-[^:]*:16: Error: this group relocation is not allowed on this instruction -- `cfldrs mvf0,\[r0,#:pc_g0_nc:\(sym\)\]'
-[^:]*:59: *Info: macro .*
-[^:]*:17: Error: this group relocation is not allowed on this instruction -- `cfldrs mvf0,\[r0,#:pc_g1_nc:\(sym\)\]'
-[^:]*:59: *Info: macro .*
-[^:]*:18: Error: this group relocation is not allowed on this instruction -- `cfldrs mvf0,\[r0,#:sb_g0_nc:\(sym\)\]'
-[^:]*:59: *Info: macro .*
-[^:]*:19: Error: this group relocation is not allowed on this instruction -- `cfldrs mvf0,\[r0,#:sb_g1_nc:\(sym\)\]'
-[^:]*:59: *Info: macro .*
-[^:]*:21: Error: unknown group relocation -- `cfldrs mvf0,\[r0,#:foo:\(sym\)\]'
-[^:]*:59: *Info: macro .*
-[^:]*:16: Error: this group relocation is not allowed on this instruction -- `cfstrs mvf0,\[r0,#:pc_g0_nc:\(sym\)\]'
-[^:]*:60: *Info: macro .*
-[^:]*:17: Error: this group relocation is not allowed on this instruction -- `cfstrs mvf0,\[r0,#:pc_g1_nc:\(sym\)\]'
-[^:]*:60: *Info: macro .*
-[^:]*:18: Error: this group relocation is not allowed on this instruction -- `cfstrs mvf0,\[r0,#:sb_g0_nc:\(sym\)\]'
-[^:]*:60: *Info: macro .*
-[^:]*:19: Error: this group relocation is not allowed on this instruction -- `cfstrs mvf0,\[r0,#:sb_g1_nc:\(sym\)\]'
-[^:]*:60: *Info: macro .*
-[^:]*:21: Error: unknown group relocation -- `cfstrs mvf0,\[r0,#:foo:\(sym\)\]'
-[^:]*:60: *Info: macro .*
-[^:]*:16: Error: this group relocation is not allowed on this instruction -- `cfldrd mvd0,\[r0,#:pc_g0_nc:\(sym\)\]'
-[^:]*:61: *Info: macro .*
-[^:]*:17: Error: this group relocation is not allowed on this instruction -- `cfldrd mvd0,\[r0,#:pc_g1_nc:\(sym\)\]'
-[^:]*:61: *Info: macro .*
-[^:]*:18: Error: this group relocation is not allowed on this instruction -- `cfldrd mvd0,\[r0,#:sb_g0_nc:\(sym\)\]'
-[^:]*:61: *Info: macro .*
-[^:]*:19: Error: this group relocation is not allowed on this instruction -- `cfldrd mvd0,\[r0,#:sb_g1_nc:\(sym\)\]'
-[^:]*:61: *Info: macro .*
-[^:]*:21: Error: unknown group relocation -- `cfldrd mvd0,\[r0,#:foo:\(sym\)\]'
-[^:]*:61: *Info: macro .*
-[^:]*:16: Error: this group relocation is not allowed on this instruction -- `cfstrd mvd0,\[r0,#:pc_g0_nc:\(sym\)\]'
-[^:]*:62: *Info: macro .*
-[^:]*:17: Error: this group relocation is not allowed on this instruction -- `cfstrd mvd0,\[r0,#:pc_g1_nc:\(sym\)\]'
-[^:]*:62: *Info: macro .*
-[^:]*:18: Error: this group relocation is not allowed on this instruction -- `cfstrd mvd0,\[r0,#:sb_g0_nc:\(sym\)\]'
-[^:]*:62: *Info: macro .*
-[^:]*:19: Error: this group relocation is not allowed on this instruction -- `cfstrd mvd0,\[r0,#:sb_g1_nc:\(sym\)\]'
-[^:]*:62: *Info: macro .*
-[^:]*:21: Error: unknown group relocation -- `cfstrd mvd0,\[r0,#:foo:\(sym\)\]'
-[^:]*:62: *Info: macro .*
-[^:]*:16: Error: this group relocation is not allowed on this instruction -- `cfldr32 mvfx0,\[r0,#:pc_g0_nc:\(sym\)\]'
-[^:]*:63: *Info: macro .*
-[^:]*:17: Error: this group relocation is not allowed on this instruction -- `cfldr32 mvfx0,\[r0,#:pc_g1_nc:\(sym\)\]'
-[^:]*:63: *Info: macro .*
-[^:]*:18: Error: this group relocation is not allowed on this instruction -- `cfldr32 mvfx0,\[r0,#:sb_g0_nc:\(sym\)\]'
-[^:]*:63: *Info: macro .*
-[^:]*:19: Error: this group relocation is not allowed on this instruction -- `cfldr32 mvfx0,\[r0,#:sb_g1_nc:\(sym\)\]'
-[^:]*:63: *Info: macro .*
-[^:]*:21: Error: unknown group relocation -- `cfldr32 mvfx0,\[r0,#:foo:\(sym\)\]'
-[^:]*:63: *Info: macro .*
-[^:]*:16: Error: this group relocation is not allowed on this instruction -- `cfstr32 mvfx0,\[r0,#:pc_g0_nc:\(sym\)\]'
-[^:]*:64: *Info: macro .*
-[^:]*:17: Error: this group relocation is not allowed on this instruction -- `cfstr32 mvfx0,\[r0,#:pc_g1_nc:\(sym\)\]'
-[^:]*:64: *Info: macro .*
-[^:]*:18: Error: this group relocation is not allowed on this instruction -- `cfstr32 mvfx0,\[r0,#:sb_g0_nc:\(sym\)\]'
-[^:]*:64: *Info: macro .*
-[^:]*:19: Error: this group relocation is not allowed on this instruction -- `cfstr32 mvfx0,\[r0,#:sb_g1_nc:\(sym\)\]'
-[^:]*:64: *Info: macro .*
-[^:]*:21: Error: unknown group relocation -- `cfstr32 mvfx0,\[r0,#:foo:\(sym\)\]'
-[^:]*:64: *Info: macro .*
-[^:]*:16: Error: this group relocation is not allowed on this instruction -- `cfldr64 mvdx0,\[r0,#:pc_g0_nc:\(sym\)\]'
-[^:]*:65: *Info: macro .*
-[^:]*:17: Error: this group relocation is not allowed on this instruction -- `cfldr64 mvdx0,\[r0,#:pc_g1_nc:\(sym\)\]'
-[^:]*:65: *Info: macro .*
-[^:]*:18: Error: this group relocation is not allowed on this instruction -- `cfldr64 mvdx0,\[r0,#:sb_g0_nc:\(sym\)\]'
-[^:]*:65: *Info: macro .*
-[^:]*:19: Error: this group relocation is not allowed on this instruction -- `cfldr64 mvdx0,\[r0,#:sb_g1_nc:\(sym\)\]'
-[^:]*:65: *Info: macro .*
-[^:]*:21: Error: unknown group relocation -- `cfldr64 mvdx0,\[r0,#:foo:\(sym\)\]'
-[^:]*:65: *Info: macro .*
-[^:]*:16: Error: this group relocation is not allowed on this instruction -- `cfstr64 mvdx0,\[r0,#:pc_g0_nc:\(sym\)\]'
-[^:]*:66: *Info: macro .*
-[^:]*:17: Error: this group relocation is not allowed on this instruction -- `cfstr64 mvdx0,\[r0,#:pc_g1_nc:\(sym\)\]'
-[^:]*:66: *Info: macro .*
-[^:]*:18: Error: this group relocation is not allowed on this instruction -- `cfstr64 mvdx0,\[r0,#:sb_g0_nc:\(sym\)\]'
-[^:]*:66: *Info: macro .*
-[^:]*:19: Error: this group relocation is not allowed on this instruction -- `cfstr64 mvdx0,\[r0,#:sb_g1_nc:\(sym\)\]'
-[^:]*:66: *Info: macro .*
-[^:]*:21: Error: unknown group relocation -- `cfstr64 mvdx0,\[r0,#:foo:\(sym\)\]'
-[^:]*:66: *Info: macro .*
diff --git a/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.s b/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.s
index a815f5de75b..d10e363a8ed 100644
--- a/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.s
+++ b/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.s
@@ -54,14 +54,3 @@
ldctest2 vldr d0 FIXME
ldctest2 vstr d0
- .cpu ep9312
-
- ldctest2 cfldrs mvf0
- ldctest2 cfstrs mvf0
- ldctest2 cfldrd mvd0
- ldctest2 cfstrd mvd0
- ldctest2 cfldr32 mvfx0
- ldctest2 cfstr32 mvfx0
- ldctest2 cfldr64 mvdx0
- ldctest2 cfstr64 mvdx0
-
diff --git a/gas/testsuite/gas/arm/group-reloc-ldc.d b/gas/testsuite/gas/arm/group-reloc-ldc.d
index 0f68ba12c60..870703d6a44 100644
--- a/gas/testsuite/gas/arm/group-reloc-ldc.d
+++ b/gas/testsuite/gas/arm/group-reloc-ldc.d
@@ -533,195 +533,3 @@ Disassembly of section .text:
418: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\].*
41c: R_ARM_LDC_SB_G2 f
-0[0-9a-f]+ <[^>]+> ed900485 cfldrs mvf0, \[r0, #532\].*
- 420: R_ARM_LDC_PC_G0 f
-0[0-9a-f]+ <[^>]+> ed900485 cfldrs mvf0, \[r0, #532\].*
- 424: R_ARM_LDC_PC_G1 f
-0[0-9a-f]+ <[^>]+> ed900485 cfldrs mvf0, \[r0, #532\].*
- 428: R_ARM_LDC_PC_G2 f
-0[0-9a-f]+ <[^>]+> ed900485 cfldrs mvf0, \[r0, #532\].*
- 42c: R_ARM_LDC_SB_G0 f
-0[0-9a-f]+ <[^>]+> ed900485 cfldrs mvf0, \[r0, #532\].*
- 430: R_ARM_LDC_SB_G1 f
-0[0-9a-f]+ <[^>]+> ed900485 cfldrs mvf0, \[r0, #532\].*
- 434: R_ARM_LDC_SB_G2 f
-0[0-9a-f]+ <[^>]+> ed800485 cfstrs mvf0, \[r0, #532\].*
- 438: R_ARM_LDC_PC_G0 f
-0[0-9a-f]+ <[^>]+> ed800485 cfstrs mvf0, \[r0, #532\].*
- 43c: R_ARM_LDC_PC_G1 f
-0[0-9a-f]+ <[^>]+> ed800485 cfstrs mvf0, \[r0, #532\].*
- 440: R_ARM_LDC_PC_G2 f
-0[0-9a-f]+ <[^>]+> ed800485 cfstrs mvf0, \[r0, #532\].*
- 444: R_ARM_LDC_SB_G0 f
-0[0-9a-f]+ <[^>]+> ed800485 cfstrs mvf0, \[r0, #532\].*
- 448: R_ARM_LDC_SB_G1 f
-0[0-9a-f]+ <[^>]+> ed800485 cfstrs mvf0, \[r0, #532\].*
- 44c: R_ARM_LDC_SB_G2 f
-0[0-9a-f]+ <[^>]+> ed100485 cfldrs mvf0, \[r0, #-532\].*
- 450: R_ARM_LDC_PC_G0 f
-0[0-9a-f]+ <[^>]+> ed100485 cfldrs mvf0, \[r0, #-532\].*
- 454: R_ARM_LDC_PC_G1 f
-0[0-9a-f]+ <[^>]+> ed100485 cfldrs mvf0, \[r0, #-532\].*
- 458: R_ARM_LDC_PC_G2 f
-0[0-9a-f]+ <[^>]+> ed100485 cfldrs mvf0, \[r0, #-532\].*
- 45c: R_ARM_LDC_SB_G0 f
-0[0-9a-f]+ <[^>]+> ed100485 cfldrs mvf0, \[r0, #-532\].*
- 460: R_ARM_LDC_SB_G1 f
-0[0-9a-f]+ <[^>]+> ed100485 cfldrs mvf0, \[r0, #-532\].*
- 464: R_ARM_LDC_SB_G2 f
-0[0-9a-f]+ <[^>]+> ed000485 cfstrs mvf0, \[r0, #-532\].*
- 468: R_ARM_LDC_PC_G0 f
-0[0-9a-f]+ <[^>]+> ed000485 cfstrs mvf0, \[r0, #-532\].*
- 46c: R_ARM_LDC_PC_G1 f
-0[0-9a-f]+ <[^>]+> ed000485 cfstrs mvf0, \[r0, #-532\].*
- 470: R_ARM_LDC_PC_G2 f
-0[0-9a-f]+ <[^>]+> ed000485 cfstrs mvf0, \[r0, #-532\].*
- 474: R_ARM_LDC_SB_G0 f
-0[0-9a-f]+ <[^>]+> ed000485 cfstrs mvf0, \[r0, #-532\].*
- 478: R_ARM_LDC_SB_G1 f
-0[0-9a-f]+ <[^>]+> ed000485 cfstrs mvf0, \[r0, #-532\].*
- 47c: R_ARM_LDC_SB_G2 f
-0[0-9a-f]+ <[^>]+> edd00485 cfldrd mvd0, \[r0, #532\].*
- 480: R_ARM_LDC_PC_G0 f
-0[0-9a-f]+ <[^>]+> edd00485 cfldrd mvd0, \[r0, #532\].*
- 484: R_ARM_LDC_PC_G1 f
-0[0-9a-f]+ <[^>]+> edd00485 cfldrd mvd0, \[r0, #532\].*
- 488: R_ARM_LDC_PC_G2 f
-0[0-9a-f]+ <[^>]+> edd00485 cfldrd mvd0, \[r0, #532\].*
- 48c: R_ARM_LDC_SB_G0 f
-0[0-9a-f]+ <[^>]+> edd00485 cfldrd mvd0, \[r0, #532\].*
- 490: R_ARM_LDC_SB_G1 f
-0[0-9a-f]+ <[^>]+> edd00485 cfldrd mvd0, \[r0, #532\].*
- 494: R_ARM_LDC_SB_G2 f
-0[0-9a-f]+ <[^>]+> edc00485 cfstrd mvd0, \[r0, #532\].*
- 498: R_ARM_LDC_PC_G0 f
-0[0-9a-f]+ <[^>]+> edc00485 cfstrd mvd0, \[r0, #532\].*
- 49c: R_ARM_LDC_PC_G1 f
-0[0-9a-f]+ <[^>]+> edc00485 cfstrd mvd0, \[r0, #532\].*
- 4a0: R_ARM_LDC_PC_G2 f
-0[0-9a-f]+ <[^>]+> edc00485 cfstrd mvd0, \[r0, #532\].*
- 4a4: R_ARM_LDC_SB_G0 f
-0[0-9a-f]+ <[^>]+> edc00485 cfstrd mvd0, \[r0, #532\].*
- 4a8: R_ARM_LDC_SB_G1 f
-0[0-9a-f]+ <[^>]+> edc00485 cfstrd mvd0, \[r0, #532\].*
- 4ac: R_ARM_LDC_SB_G2 f
-0[0-9a-f]+ <[^>]+> ed500485 cfldrd mvd0, \[r0, #-532\].*
- 4b0: R_ARM_LDC_PC_G0 f
-0[0-9a-f]+ <[^>]+> ed500485 cfldrd mvd0, \[r0, #-532\].*
- 4b4: R_ARM_LDC_PC_G1 f
-0[0-9a-f]+ <[^>]+> ed500485 cfldrd mvd0, \[r0, #-532\].*
- 4b8: R_ARM_LDC_PC_G2 f
-0[0-9a-f]+ <[^>]+> ed500485 cfldrd mvd0, \[r0, #-532\].*
- 4bc: R_ARM_LDC_SB_G0 f
-0[0-9a-f]+ <[^>]+> ed500485 cfldrd mvd0, \[r0, #-532\].*
- 4c0: R_ARM_LDC_SB_G1 f
-0[0-9a-f]+ <[^>]+> ed500485 cfldrd mvd0, \[r0, #-532\].*
- 4c4: R_ARM_LDC_SB_G2 f
-0[0-9a-f]+ <[^>]+> ed400485 cfstrd mvd0, \[r0, #-532\].*
- 4c8: R_ARM_LDC_PC_G0 f
-0[0-9a-f]+ <[^>]+> ed400485 cfstrd mvd0, \[r0, #-532\].*
- 4cc: R_ARM_LDC_PC_G1 f
-0[0-9a-f]+ <[^>]+> ed400485 cfstrd mvd0, \[r0, #-532\].*
- 4d0: R_ARM_LDC_PC_G2 f
-0[0-9a-f]+ <[^>]+> ed400485 cfstrd mvd0, \[r0, #-532\].*
- 4d4: R_ARM_LDC_SB_G0 f
-0[0-9a-f]+ <[^>]+> ed400485 cfstrd mvd0, \[r0, #-532\].*
- 4d8: R_ARM_LDC_SB_G1 f
-0[0-9a-f]+ <[^>]+> ed400485 cfstrd mvd0, \[r0, #-532\].*
- 4dc: R_ARM_LDC_SB_G2 f
-0[0-9a-f]+ <[^>]+> ed900585 cfldr32 mvfx0, \[r0, #532\].*
- 4e0: R_ARM_LDC_PC_G0 f
-0[0-9a-f]+ <[^>]+> ed900585 cfldr32 mvfx0, \[r0, #532\].*
- 4e4: R_ARM_LDC_PC_G1 f
-0[0-9a-f]+ <[^>]+> ed900585 cfldr32 mvfx0, \[r0, #532\].*
- 4e8: R_ARM_LDC_PC_G2 f
-0[0-9a-f]+ <[^>]+> ed900585 cfldr32 mvfx0, \[r0, #532\].*
- 4ec: R_ARM_LDC_SB_G0 f
-0[0-9a-f]+ <[^>]+> ed900585 cfldr32 mvfx0, \[r0, #532\].*
- 4f0: R_ARM_LDC_SB_G1 f
-0[0-9a-f]+ <[^>]+> ed900585 cfldr32 mvfx0, \[r0, #532\].*
- 4f4: R_ARM_LDC_SB_G2 f
-0[0-9a-f]+ <[^>]+> ed800585 cfstr32 mvfx0, \[r0, #532\].*
- 4f8: R_ARM_LDC_PC_G0 f
-0[0-9a-f]+ <[^>]+> ed800585 cfstr32 mvfx0, \[r0, #532\].*
- 4fc: R_ARM_LDC_PC_G1 f
-0[0-9a-f]+ <[^>]+> ed800585 cfstr32 mvfx0, \[r0, #532\].*
- 500: R_ARM_LDC_PC_G2 f
-0[0-9a-f]+ <[^>]+> ed800585 cfstr32 mvfx0, \[r0, #532\].*
- 504: R_ARM_LDC_SB_G0 f
-0[0-9a-f]+ <[^>]+> ed800585 cfstr32 mvfx0, \[r0, #532\].*
- 508: R_ARM_LDC_SB_G1 f
-0[0-9a-f]+ <[^>]+> ed800585 cfstr32 mvfx0, \[r0, #532\].*
- 50c: R_ARM_LDC_SB_G2 f
-0[0-9a-f]+ <[^>]+> ed100585 cfldr32 mvfx0, \[r0, #-532\].*
- 510: R_ARM_LDC_PC_G0 f
-0[0-9a-f]+ <[^>]+> ed100585 cfldr32 mvfx0, \[r0, #-532\].*
- 514: R_ARM_LDC_PC_G1 f
-0[0-9a-f]+ <[^>]+> ed100585 cfldr32 mvfx0, \[r0, #-532\].*
- 518: R_ARM_LDC_PC_G2 f
-0[0-9a-f]+ <[^>]+> ed100585 cfldr32 mvfx0, \[r0, #-532\].*
- 51c: R_ARM_LDC_SB_G0 f
-0[0-9a-f]+ <[^>]+> ed100585 cfldr32 mvfx0, \[r0, #-532\].*
- 520: R_ARM_LDC_SB_G1 f
-0[0-9a-f]+ <[^>]+> ed100585 cfldr32 mvfx0, \[r0, #-532\].*
- 524: R_ARM_LDC_SB_G2 f
-0[0-9a-f]+ <[^>]+> ed000585 cfstr32 mvfx0, \[r0, #-532\].*
- 528: R_ARM_LDC_PC_G0 f
-0[0-9a-f]+ <[^>]+> ed000585 cfstr32 mvfx0, \[r0, #-532\].*
- 52c: R_ARM_LDC_PC_G1 f
-0[0-9a-f]+ <[^>]+> ed000585 cfstr32 mvfx0, \[r0, #-532\].*
- 530: R_ARM_LDC_PC_G2 f
-0[0-9a-f]+ <[^>]+> ed000585 cfstr32 mvfx0, \[r0, #-532\].*
- 534: R_ARM_LDC_SB_G0 f
-0[0-9a-f]+ <[^>]+> ed000585 cfstr32 mvfx0, \[r0, #-532\].*
- 538: R_ARM_LDC_SB_G1 f
-0[0-9a-f]+ <[^>]+> ed000585 cfstr32 mvfx0, \[r0, #-532\].*
- 53c: R_ARM_LDC_SB_G2 f
-0[0-9a-f]+ <[^>]+> edd00585 cfldr64 mvdx0, \[r0, #532\].*
- 540: R_ARM_LDC_PC_G0 f
-0[0-9a-f]+ <[^>]+> edd00585 cfldr64 mvdx0, \[r0, #532\].*
- 544: R_ARM_LDC_PC_G1 f
-0[0-9a-f]+ <[^>]+> edd00585 cfldr64 mvdx0, \[r0, #532\].*
- 548: R_ARM_LDC_PC_G2 f
-0[0-9a-f]+ <[^>]+> edd00585 cfldr64 mvdx0, \[r0, #532\].*
- 54c: R_ARM_LDC_SB_G0 f
-0[0-9a-f]+ <[^>]+> edd00585 cfldr64 mvdx0, \[r0, #532\].*
- 550: R_ARM_LDC_SB_G1 f
-0[0-9a-f]+ <[^>]+> edd00585 cfldr64 mvdx0, \[r0, #532\].*
- 554: R_ARM_LDC_SB_G2 f
-0[0-9a-f]+ <[^>]+> edc00585 cfstr64 mvdx0, \[r0, #532\].*
- 558: R_ARM_LDC_PC_G0 f
-0[0-9a-f]+ <[^>]+> edc00585 cfstr64 mvdx0, \[r0, #532\].*
- 55c: R_ARM_LDC_PC_G1 f
-0[0-9a-f]+ <[^>]+> edc00585 cfstr64 mvdx0, \[r0, #532\].*
- 560: R_ARM_LDC_PC_G2 f
-0[0-9a-f]+ <[^>]+> edc00585 cfstr64 mvdx0, \[r0, #532\].*
- 564: R_ARM_LDC_SB_G0 f
-0[0-9a-f]+ <[^>]+> edc00585 cfstr64 mvdx0, \[r0, #532\].*
- 568: R_ARM_LDC_SB_G1 f
-0[0-9a-f]+ <[^>]+> edc00585 cfstr64 mvdx0, \[r0, #532\].*
- 56c: R_ARM_LDC_SB_G2 f
-0[0-9a-f]+ <[^>]+> ed500585 cfldr64 mvdx0, \[r0, #-532\].*
- 570: R_ARM_LDC_PC_G0 f
-0[0-9a-f]+ <[^>]+> ed500585 cfldr64 mvdx0, \[r0, #-532\].*
- 574: R_ARM_LDC_PC_G1 f
-0[0-9a-f]+ <[^>]+> ed500585 cfldr64 mvdx0, \[r0, #-532\].*
- 578: R_ARM_LDC_PC_G2 f
-0[0-9a-f]+ <[^>]+> ed500585 cfldr64 mvdx0, \[r0, #-532\].*
- 57c: R_ARM_LDC_SB_G0 f
-0[0-9a-f]+ <[^>]+> ed500585 cfldr64 mvdx0, \[r0, #-532\].*
- 580: R_ARM_LDC_SB_G1 f
-0[0-9a-f]+ <[^>]+> ed500585 cfldr64 mvdx0, \[r0, #-532\].*
- 584: R_ARM_LDC_SB_G2 f
-0[0-9a-f]+ <[^>]+> ed400585 cfstr64 mvdx0, \[r0, #-532\].*
- 588: R_ARM_LDC_PC_G0 f
-0[0-9a-f]+ <[^>]+> ed400585 cfstr64 mvdx0, \[r0, #-532\].*
- 58c: R_ARM_LDC_PC_G1 f
-0[0-9a-f]+ <[^>]+> ed400585 cfstr64 mvdx0, \[r0, #-532\].*
- 590: R_ARM_LDC_PC_G2 f
-0[0-9a-f]+ <[^>]+> ed400585 cfstr64 mvdx0, \[r0, #-532\].*
- 594: R_ARM_LDC_SB_G0 f
-0[0-9a-f]+ <[^>]+> ed400585 cfstr64 mvdx0, \[r0, #-532\].*
- 598: R_ARM_LDC_SB_G1 f
-0[0-9a-f]+ <[^>]+> ed400585 cfstr64 mvdx0, \[r0, #-532\].*
- 59c: R_ARM_LDC_SB_G2 f
diff --git a/gas/testsuite/gas/arm/group-reloc-ldc.s b/gas/testsuite/gas/arm/group-reloc-ldc.s
index df27aaf55e0..f17fa89551b 100644
--- a/gas/testsuite/gas/arm/group-reloc-ldc.s
+++ b/gas/testsuite/gas/arm/group-reloc-ldc.s
@@ -140,12 +140,3 @@
vfp_test vldr vstr d0
-@ CFLDRS/CFLDRD/CFLDR32/CFLDR64/CFSTRS/CFSTRD/CFSTR32/CFSTR64
-
- .cpu ep9312
-
- vfp_test cfldrs cfstrs mvf0
- vfp_test cfldrd cfstrd mvd0
- vfp_test cfldr32 cfstr32 mvfx0
- vfp_test cfldr64 cfstr64 mvdx0
-
diff --git a/gas/testsuite/gas/arm/maverick.c b/gas/testsuite/gas/arm/maverick.c
deleted file mode 100644
index 7b7f5bd0eeb..00000000000
--- a/gas/testsuite/gas/arm/maverick.c
+++ /dev/null
@@ -1,534 +0,0 @@
-/* Copyright (C) 2000-2024 Free Software Foundation, Inc.
- Contributed by Alexandre Oliva <aoliva@cygnus.com>
-
- This file is free software; you can redistribute it and/or modify it
- under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful, but
- WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
- MA 02110-1301, USA. */
-
-/* Generator of tests for Maverick.
-
- See the following file for usage and documentation. */
-#include "../all/test-gen.c"
-
-/* These are the ARM registers. Some of them have canonical names
- other than r##, so we'll use both in the asm input, but only the
- canonical names in the expected disassembler output. */
-char *arm_regs[] =
- {
- /* Canonical names. */
- "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
- "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc",
- /* Alternate names, i.e., those that can be used in the assembler,
- * but that will never be emitted by the disassembler. */
- "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
- "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
- };
-
-/* The various types of registers: ARM's registers, Maverick's
- f/d/fx/dx registers, Maverick's accumulators and Maverick's
- status register. */
-#define armreg(shift) \
- reg_r (arm_regs, shift, 0xf, mk_get_bits (5u))
-#define mvreg(prefix, shift) \
- reg_p ("mv" prefix, shift, mk_get_bits (4u))
-#define acreg(shift) \
- reg_p ("mvax", shift, mk_get_bits (2u))
-#define dspsc \
- literal ("dspsc"), tick_random
-
-/* This outputs the condition flag that may follow each ARM insn.
- Since the condition 15 is invalid, we use it to check that the
- assembler recognizes the absence of a condition as `al'. However,
- the disassembler won't ever output `al', so, if we emit it in the
- assembler, expect the condition to be omitted in the disassembler
- output. */
-
-int
-arm_cond (func_arg * arg, insn_data * data)
-#define arm_cond { arm_cond }
-{
- static const char conds[16][3] =
- {
- "eq", "ne", "cs", "cc",
- "mi", "pl", "vs", "vc",
- "hi", "ls", "ge", "lt",
- "gt", "le", "al", ""
- };
- unsigned val = get_bits (4u);
-
- data->as_in = data->dis_out = strdup (conds[val]);
- if (val == 14)
- data->dis_out = strdup ("");
- data->bits = (val == 15 ? 14 : val) << 28;
- return 0;
-}
-
-/* The sign of an offset is actually used to determined whether the
- absolute value of the offset should be added or subtracted, so we
- must adjust negative values so that they do not overflow: -1024 is
- not valid, but -0 is distinct from +0. */
-int
-off8s (func_arg * arg, insn_data * data)
-#define off8s { off8s }
-{
- int val;
- char value[9];
-
- /* Zero values are problematical.
- The assembler performs translations on the addressing modes
- for these values, meaning that we cannot just recreate the
- disassembler string in the LDST macro without knowing what
- value had been generated in off8s. */
- do
- {
- val = get_bits (9s);
- }
- while (val == -1 || val == 0);
-
- val <<= 2;
- if (val < 0)
- {
- val = -4 - val;
- sprintf (value, ", #-%i", val);
- data->dis_out = strdup (value);
- sprintf (value, ", #-%i", val);
- data->as_in = strdup (value);
- data->bits = val >> 2;
- }
- else
- {
- sprintf (value, ", #%i", val);
- data->as_in = data->dis_out = strdup (value);
- data->bits = (val >> 2) | (1 << 23);
- }
-
- return 0;
-}
-
-/* This function generates a 7-bit signed constant, emitted as
- follows: the 4 least-significant bits are stored in the 4
- least-significant bits of the word; the 3 most-significant bits are
- stored in bits 7:5, i.e., bit 4 is skipped. */
-int
-imm7 (func_arg *arg, insn_data *data)
-#define imm7 { imm7 }
-{
- int val = get_bits (7s);
- char value[6];
-
- data->bits = (val & 0x0f) | (2 * (val & 0x70));
- sprintf (value, "#%i", val);
- data->as_in = data->dis_out = strdup (value);
- return 0;
-}
-
-/* Convenience wrapper to define_insn, that prefixes every insn with
- `cf' (so, if you specify command-line arguments, remember that `cf'
- must *not* be part of the string), and post-fixes a condition code.
- insname and insnvar specify the main insn name and a variant;
- they're just concatenated, and insnvar is often empty. word is the
- bit pattern that defines the insn, properly shifted, and funcs is a
- sequence of funcs that define the operands and the syntax of the
- insn. */
-#define mv_insn(insname, insnvar, word, funcs...) \
- define_insn (insname ## insnvar, \
- literal ("cf"), \
- insn_bits (insname, word), \
- arm_cond, \
- tab, \
- ## funcs)
-
-/* Define a single LDC/STC variant. op is the main insn opcode; ld
- stands for load (it should be 0 on stores), dword selects 64-bit
- operations, pre should be enabled for pre-increment, and wb, for
- write-back. sep1, sep2 and sep3 are syntactical elements ([]!)
- that the assembler will use to enable pre and wb. It would
- probably have been cleaner to couple the syntactical elements with
- the pre/wb bits directly, but it would have required the definition
- of more functions. */
-#define LDST(insname, insnvar, op, ld, dword, regname, pre, wb, sep1, sep2, sep3) \
- mv_insn (insname, insnvar, \
- (12 << 24) | (op << 8) | (ld << 20) | (pre << 24) | (dword << 22) | (wb << 21), \
- mvreg (regname, 12), comma, \
- lsqbkt, armreg (16), sep1, off8s, sep2, sep3, \
- tick_random)
-
-/* Define all variants of an LDR or STR instruction, namely,
- pre-indexed without write-back, pre-indexed with write-back and
- post-indexed. */
-#define LDSTall(insname, op, ld, dword, regname) \
- LDST (insname, _p, op, ld, dword, regname, 1, 0, nothing, rsqbkt, nothing); \
- LDST (insname, _pw, op, ld, dword, regname, 1, 1, nothing, rsqbkt, literal ("!")); \
- LDST (insname, ,op, ld, dword, regname, 0, 1, rsqbkt, nothing, nothing)
-
-/* Produce the insn identifiers of all LDST variants of a given insn.
- To be used in the initialization of an insn group array. */
-#define insns_LDSTall(insname) \
- insn (insname ## _p), insn (insname ## _pw), insn (insname)
-
-/* Define a CDP variant that uses two registers, at offsets 12 and 16.
- The two opcodes and the co-processor number identify the CDP
- insn. */
-#define CDP2(insname, var, cpnum, opcode1, opcode2, reg1name, reg2name) \
- mv_insn (insname##var, , \
- (14 << 24) | ((opcode1) << 20) | ((cpnum) << 8) | ((opcode2) << 5), \
- mvreg (reg1name, 12), comma, mvreg (reg2name, 16))
-
-/* Define a 32-bit integer CDP instruction with two operands. */
-#define CDP2fx(insname, opcode1, opcode2) \
- CDP2 (insname, 32, 5, opcode1, opcode2, "fx", "fx")
-
-/* Define a 64-bit integer CDP instruction with two operands. */
-#define CDP2dx(insname, opcode1, opcode2) \
- CDP2 (insname, 64, 5, opcode1, opcode2, "dx", "dx")
-
-/* Define a float CDP instruction with two operands. */
-#define CDP2f(insname, opcode1, opcode2) \
- CDP2 (insname, s, 4, opcode1, opcode2, "f", "f")
-
-/* Define a double CDP instruction with two operands. */
-#define CDP2d(insname, opcode1, opcode2) \
- CDP2 (insname, d, 4, opcode1, opcode2, "d", "d")
-
-/* Define a CDP instruction with two register operands and one 7-bit
- signed immediate generated with imm7. */
-#define CDP2_imm7(insname, cpnum, opcode1, reg1name, reg2name) \
- mv_insn (insname, , (14 << 24) | ((opcode1) << 20) | ((cpnum) << 8), \
- mvreg (reg1name, 12), comma, mvreg (reg2name, 16), comma, imm7, \
- tick_random)
-
-/* Produce the insn identifiers of CDP floating-point or integer insn
- pairs (i.e., it appends the suffixes for 32-bit and 64-bit
- insns. */
-#define CDPfp_insns(insname) \
- insn (insname ## s), insn (insname ## d)
-#define CDPx_insns(insname) \
- insn (insname ## 32), insn (insname ## 64)
-
-/* Define a CDP instruction with 3 operands, at offsets 12, 16, 0. */
-#define CDP3(insname, var, cpnum, opcode1, opcode2, reg1name, reg2name, reg3name) \
- mv_insn (insname##var, , \
- (14 << 24) | ((opcode1) << 20) | ((cpnum) << 8) | ((opcode2) << 5), \
- mvreg (reg1name, 12), comma, mvreg (reg2name, 16), comma, \
- mvreg (reg3name, 0), tick_random)
-
-/* Define a 32-bit integer CDP instruction with three operands. */
-#define CDP3fx(insname, opcode1, opcode2) \
- CDP3 (insname, 32, 5, opcode1, opcode2, "fx", "fx", "fx")
-
-/* Define a 64-bit integer CDP instruction with three operands. */
-#define CDP3dx(insname, opcode1, opcode2) \
- CDP3 (insname, 64, 5, opcode1, opcode2, "dx", "dx", "dx")
-
-/* Define a float CDP instruction with three operands. */
-#define CDP3f(insname, opcode1, opcode2) \
- CDP3 (insname, s, 4, opcode1, opcode2, "f", "f", "f")
-
-/* Define a double CDP instruction with three operands. */
-#define CDP3d(insname, opcode1, opcode2) \
- CDP3 (insname, d, 4, opcode1, opcode2, "d", "d", "d")
-
-/* Define a CDP instruction with four operands, at offsets 5, 12, 16
- * and 0. Used only for ACC instructions. */
-#define CDP4(insname, opcode1, reg2spec, reg3name, reg4name) \
- mv_insn (insname, , (14 << 24) | ((opcode1) << 20) | (6 << 8), \
- acreg (5), comma, reg2spec, comma, \
- mvreg (reg3name, 16), comma, mvreg (reg4name, 0))
-
-/* Define a CDP4 instruction with one accumulator operands. */
-#define CDP41A(insname, opcode1) \
- CDP4 (insname, opcode1, mvreg ("fx", 12), "fx", "fx")
-
-/* Define a CDP4 instruction with two accumulator operands. */
-#define CDP42A(insname, opcode1) \
- CDP4 (insname, opcode1, acreg (12), "fx", "fx")
-
-/* Define a MCR or MRC instruction with two register operands. */
-#define MCRC2(insname, cpnum, opcode1, dir, opcode2, reg1spec, reg2spec) \
- mv_insn (insname, , \
- ((14 << 24) | ((opcode1) << 21) | ((dir) << 20)| \
- ((cpnum) << 8) | ((opcode2) << 5) | (1 << 4)), \
- reg1spec, comma, reg2spec)
-
-/* Define a move from a DSP register to an ARM register. */
-#define MVDSPARM(insname, cpnum, opcode2, regDSPname) \
- MCRC2 (mv ## insname, cpnum, 0, 0, opcode2, \
- mvreg (regDSPname, 16), armreg (12))
-
-/* Define a move from an ARM register to a DSP register. */
-#define MVARMDSP(insname, cpnum, opcode2, regDSPname) \
- MCRC2 (mv ## insname, cpnum, 0, 1, opcode2, \
- armreg (12), mvreg (regDSPname, 16))
-
-/* Move between coprocessor registers. A two operand CDP insn. */
-#define MCC2(insname, opcode1, opcode2, reg1spec, reg2spec) \
- mv_insn (insname, , \
- ((14 << 24) | ((opcode1) << 20) | \
- (4 << 8) | ((opcode2) << 5)), \
- reg1spec, comma, reg2spec)
-
-/* Define a move from a DSP register to a DSP accumulator. */
-#define MVDSPACC(insname, opcode2, regDSPname) \
- MCC2 (mv ## insname, 2, opcode2, acreg (12), mvreg (regDSPname, 16))
-
-/* Define a move from a DSP accumulator to a DSP register. */
-#define MVACCDSP(insname, opcode2, regDSPname) \
- MCC2 (mv ## insname, 1, opcode2, mvreg (regDSPname, 12), acreg (16))
-
-/* Define move insns between a float DSP register and an ARM
- register. */
-#define MVf(nameAD, nameDA, opcode2) \
- MVDSPARM (nameAD, 4, opcode2, "f"); \
- MVARMDSP (nameDA, 4, opcode2, "f")
-
-/* Define move insns between a double DSP register and an ARM
- register. */
-#define MVd(nameAD, nameDA, opcode2) \
- MVDSPARM (nameAD, 4, opcode2, "d"); \
- MVARMDSP (nameDA, 4, opcode2, "d")
-
-/* Define move insns between a 32-bit integer DSP register and an ARM
- register. */
-#define MVfx(nameAD, nameDA, opcode2) \
- MVDSPARM (nameAD, 5, opcode2, "fx"); \
- MVARMDSP (nameDA, 5, opcode2, "fx")
-
-/* Define move insns between a 64-bit integer DSP register and an ARM
- register. */
-#define MVdx(nameAD, nameDA, opcode2) \
- MVDSPARM (nameAD, 5, opcode2, "dx"); \
- MVARMDSP (nameDA, 5, opcode2, "dx")
-
-/* Define move insns between a 32-bit DSP register and a DSP
- accumulator. */
-#define MVfxa(nameFA, nameAF, opcode2) \
- MVDSPACC (nameFA, opcode2, "fx"); \
- MVACCDSP (nameAF, opcode2, "fx")
-
-/* Define move insns between a 64-bit DSP register and a DSP
- accumulator. */
-#define MVdxa(nameDA, nameAD, opcode2) \
- MVDSPACC (nameDA, opcode2, "dx"); \
- MVACCDSP (nameAD, opcode2, "dx")
-
-/* Produce the insn identifiers for a pair of mv insns. */
-#define insns_MV(name1, name2) \
- insn (mv ## name1), insn (mv ## name2)
-
-/* Define a MCR or MRC instruction with three register operands. */
-#define MCRC3(insname, cpnum, opcode1, dir, opcode2, reg1spec, reg2spec, reg3spec) \
- mv_insn (insname, , \
- ((14 << 24) | ((opcode1) << 21) | ((dir) << 20)| \
- ((cpnum) << 8) | ((opcode2) << 5) | (1 << 4)), \
- reg1spec, comma, reg2spec, comma, reg3spec, \
- tick_random)
-
-/* Define all load_store insns. */
-LDSTall (ldrs, 4, 1, 0, "f");
-LDSTall (ldrd, 4, 1, 1, "d");
-LDSTall (ldr32, 5, 1, 0, "fx");
-LDSTall (ldr64, 5, 1, 1, "dx");
-LDSTall (strs, 4, 0, 0, "f");
-LDSTall (strd, 4, 0, 1, "d");
-LDSTall (str32, 5, 0, 0, "fx");
-LDSTall (str64, 5, 0, 1, "dx");
-
-/* Create the load_store insn group. */
-func *load_store_insns[] =
- {
- insns_LDSTall (ldrs), insns_LDSTall (ldrd),
- insns_LDSTall (ldr32), insns_LDSTall (ldr64),
- insns_LDSTall (strs), insns_LDSTall (strd),
- insns_LDSTall (str32), insns_LDSTall (str64),
- 0
- };
-
-/* Define all move insns. */
-MVf (sr, rs, 2);
-MVd (dlr, rdl, 0);
-MVd (dhr, rdh, 1);
-MVdx (64lr, r64l, 0);
-MVdx (64hr, r64h, 1);
-MVfxa (al32, 32al, 2);
-MVfxa (am32, 32am, 3);
-MVfxa (ah32, 32ah, 4);
-MVfxa (a32, 32a, 5);
-MVdxa (a64, 64a, 6);
-MCC2 (mvsc32, 2, 7, dspsc, mvreg ("dx", 12));
-MCC2 (mv32sc, 1, 7, mvreg ("dx", 12), dspsc);
-CDP2 (cpys, , 4, 0, 0, "f", "f");
-CDP2 (cpyd, , 4, 0, 1, "d", "d");
-
-/* Create the move insns group. */
-func * move_insns[] =
- {
- insns_MV (sr, rs), insns_MV (dlr, rdl), insns_MV (dhr, rdh),
- insns_MV (64lr, r64l), insns_MV (64hr, r64h),
- insns_MV (al32, 32al), insns_MV (am32, 32am), insns_MV (ah32, 32ah),
- insns_MV (a32, 32a), insns_MV (a64, 64a),
- insn (mvsc32), insn (mv32sc), insn (cpys), insn (cpyd),
- 0
- };
-
-/* Define all conversion insns. */
-CDP2 (cvtsd, , 4, 0, 3, "d", "f");
-CDP2 (cvtds, , 4, 0, 2, "f", "d");
-CDP2 (cvt32s, , 4, 0, 4, "f", "fx");
-CDP2 (cvt32d, , 4, 0, 5, "d", "fx");
-CDP2 (cvt64s, , 4, 0, 6, "f", "dx");
-CDP2 (cvt64d, , 4, 0, 7, "d", "dx");
-CDP2 (cvts32, , 5, 1, 4, "fx", "f");
-CDP2 (cvtd32, , 5, 1, 5, "fx", "d");
-CDP2 (truncs32, , 5, 1, 6, "fx", "f");
-CDP2 (truncd32, , 5, 1, 7, "fx", "d");
-
-/* Create the conv insns group. */
-func * conv_insns[] =
- {
- insn (cvtsd), insn (cvtds), insn (cvt32s), insn (cvt32d),
- insn (cvt64s), insn (cvt64d), insn (cvts32), insn (cvtd32),
- insn (truncs32), insn (truncd32),
- 0
- };
-
-/* Define all shift insns. */
-MCRC3 (rshl32, 5, 0, 0, 2, mvreg ("fx", 16), mvreg ("fx", 0), armreg (12));
-MCRC3 (rshl64, 5, 0, 0, 3, mvreg ("dx", 16), mvreg ("dx", 0), armreg (12));
-CDP2_imm7 (sh32, 5, 0, "fx", "fx");
-CDP2_imm7 (sh64, 5, 2, "dx", "dx");
-
-/* Create the shift insns group. */
-func *shift_insns[] =
- {
- insn (rshl32), insn (rshl64),
- insn (sh32), insn (sh64),
- 0
- };
-
-/* Define all comparison insns. */
-MCRC3 (cmps, 4, 0, 1, 4, armreg (12), mvreg ("f", 16), mvreg ("f", 0));
-MCRC3 (cmpd, 4, 0, 1, 5, armreg (12), mvreg ("d", 16), mvreg ("d", 0));
-MCRC3 (cmp32, 5, 0, 1, 4, armreg (12), mvreg ("fx", 16), mvreg ("fx", 0));
-MCRC3 (cmp64, 5, 0, 1, 5, armreg (12), mvreg ("dx", 16), mvreg ("dx", 0));
-
-/* Create the comp insns group. */
-func *comp_insns[] =
- {
- insn (cmps), insn (cmpd),
- insn (cmp32), insn (cmp64),
- 0
- };
-
-/* Define all floating-point arithmetic insns. */
-CDP2f (abs, 3, 0);
-CDP2d (abs, 3, 1);
-CDP2f (neg, 3, 2);
-CDP2d (neg, 3, 3);
-CDP3f (add, 3, 4);
-CDP3d (add, 3, 5);
-CDP3f (sub, 3, 6);
-CDP3d (sub, 3, 7);
-CDP3f (mul, 1, 0);
-CDP3d (mul, 1, 1);
-
-/* Create the fp-arith insns group. */
-func *fp_arith_insns[] =
- {
- CDPfp_insns (abs), CDPfp_insns (neg),
- CDPfp_insns (add), CDPfp_insns (sub), CDPfp_insns (mul),
- 0
- };
-
-/* Define all integer arithmetic insns. */
-CDP2fx (abs, 3, 0);
-CDP2dx (abs, 3, 1);
-CDP2fx (neg, 3, 2);
-CDP2dx (neg, 3, 3);
-CDP3fx (add, 3, 4);
-CDP3dx (add, 3, 5);
-CDP3fx (sub, 3, 6);
-CDP3dx (sub, 3, 7);
-CDP3fx (mul, 1, 0);
-CDP3dx (mul, 1, 1);
-CDP3fx (mac, 1, 2);
-CDP3fx (msc, 1, 3);
-
-/* Create the int-arith insns group. */
-func * int_arith_insns[] =
- {
- CDPx_insns (abs), CDPx_insns (neg),
- CDPx_insns (add), CDPx_insns (sub), CDPx_insns (mul),
- insn (mac32), insn (msc32),
- 0
- };
-
-/* Define all accumulator arithmetic insns. */
-CDP41A (madd32, 0);
-CDP41A (msub32, 1);
-CDP42A (madda32, 2);
-CDP42A (msuba32, 3);
-
-/* Create the acc-arith insns group. */
-func * acc_arith_insns[] =
- {
- insn (madd32), insn (msub32),
- insn (madda32), insn (msuba32),
- 0
- };
-
-/* Create the set of all groups. */
-group_t groups[] =
- {
- { "load_store", load_store_insns },
- { "move", move_insns },
- { "conv", conv_insns },
- { "shift", shift_insns },
- { "comp", comp_insns },
- { "fp_arith", fp_arith_insns },
- { "int_arith", int_arith_insns },
- { "acc_arith", acc_arith_insns },
- { 0 }
- };
-
-int
-main (int argc, char *argv[])
-{
- FILE *as_in = stdout, *dis_out = stderr;
-
- /* Check whether we're filtering insns. */
- if (argc > 1)
- skip_list = argv + 1;
-
- /* Output assembler header. */
- fputs ("\t.text\n"
- "\t.align\n",
- as_in);
- /* Output comments for the testsuite-driver and the initial
- disassembler output. */
- fputs ("#objdump: -dr --prefix-address --show-raw-insn\n"
- "#name: Maverick\n"
- "#as: -mcpu=ep9312\n"
- "\n"
- "# Test the instructions of the Cirrus Maverick floating point co-processor\n"
- "\n"
- ".*: +file format.*arm.*\n"
- "\n"
- "Disassembly of section .text:\n",
- dis_out);
-
- /* Now emit all (selected) insns. */
- output_groups (groups, as_in, dis_out);
-
- exit (0);
-}
diff --git a/gas/testsuite/gas/arm/maverick.d b/gas/testsuite/gas/arm/maverick.d
deleted file mode 100644
index 4addfac4b67..00000000000
--- a/gas/testsuite/gas/arm/maverick.d
+++ /dev/null
@@ -1,477 +0,0 @@
-#objdump: -dr --prefix-address --show-raw-insn
-#name: Maverick
-#as: -mcpu=ep9312
-
-# Test the instructions of the Cirrus Maverick floating point co-processor
-
-.*: +file format.*arm.*
-
-Disassembly of section .text:
-# load_store:
-0*0 <load_store> 0d ?9d ?54 ?ff ? * cfldrseq mvf5, ?\[sp, #1020\].*
-0*4 <load_store\+0x4> 4d ?9b ?e4 ?49 ? * cfldrsmi mvf14, ?\[fp, #292\].*
-0*8 <load_store\+0x8> 7d ?1c ?24 ?ef ? * cfldrsvc mvf2, ?\[ip, #-956\].*
-0*c <load_store\+0xc> bd ?1a ?04 ?ff ? * cfldrslt mvf0, ?\[sl, #-1020\].*
-0*10 <load_store\+0x10> 3d ?11 ?c4 ?27 ? * cfldrscc mvf12, ?\[r1, #-156\].*
-0*14 <load_store\+0x14> ed ?b9 ?d4 ?68 ? * cfldrs mvf13, ?\[r9, #416\]!.*
-0*18 <load_store\+0x18> 2d ?30 ?94 ?ff ? * cfldrscs mvf9, ?\[r0, #-1020\]!.*
-0*1c <load_store\+0x1c> 9d ?31 ?44 ?27 ? * cfldrsls mvf4, ?\[r1, #-156\]!.*
-0*20 <load_store\+0x20> dd ?b9 ?74 ?68 ? * cfldrsle mvf7, ?\[r9, #416\]!.*
-0*24 <load_store\+0x24> 6d ?30 ?b4 ?ff ? * cfldrsvs mvf11, ?\[r0, #-1020\]!.*
-0*28 <load_store\+0x28> 3c ?31 ?c4 ?27 ? * cfldrscc mvf12, ?\[r1\], #-156.*
-0*2c <load_store\+0x2c> ec ?b9 ?d4 ?68 ? * cfldrs mvf13, ?\[r9\], #416.*
-0*30 <load_store\+0x30> 2c ?30 ?94 ?ff ? * cfldrscs mvf9, ?\[r0\], #-1020.*
-0*34 <load_store\+0x34> 9c ?31 ?44 ?27 ? * cfldrsls mvf4, ?\[r1\], #-156.*
-0*38 <load_store\+0x38> dc ?b9 ?74 ?68 ? * cfldrsle mvf7, ?\[r9\], #416.*
-0*3c <load_store\+0x3c> 6d ?50 ?b4 ?ff ? * cfldrdvs mvd11, ?\[r0, #-1020\].*
-0*40 <load_store\+0x40> 3d ?51 ?c4 ?27 ? * cfldrdcc mvd12, ?\[r1, #-156\].*
-0*44 <load_store\+0x44> ed ?d9 ?d4 ?68 ? * cfldrd mvd13, ?\[r9, #416\].*
-0*48 <load_store\+0x48> 2d ?50 ?94 ?ff ? * cfldrdcs mvd9, ?\[r0, #-1020\].*
-0*4c <load_store\+0x4c> 9d ?51 ?44 ?27 ? * cfldrdls mvd4, ?\[r1, #-156\].*
-0*50 <load_store\+0x50> dd ?f9 ?74 ?68 ? * cfldrdle mvd7, ?\[r9, #416\]!.*
-0*54 <load_store\+0x54> 6d ?70 ?b4 ?ff ? * cfldrdvs mvd11, ?\[r0, #-1020\]!.*
-0*58 <load_store\+0x58> 3d ?71 ?c4 ?27 ? * cfldrdcc mvd12, ?\[r1, #-156\]!.*
-0*5c <load_store\+0x5c> ed ?f9 ?d4 ?68 ? * cfldrd mvd13, ?\[r9, #416\]!.*
-0*60 <load_store\+0x60> 2d ?70 ?94 ?ff ? * cfldrdcs mvd9, ?\[r0, #-1020\]!.*
-0*64 <load_store\+0x64> 9c ?71 ?44 ?27 ? * cfldrdls mvd4, ?\[r1\], #-156.*
-0*68 <load_store\+0x68> dc ?f9 ?74 ?68 ? * cfldrdle mvd7, ?\[r9\], #416.*
-0*6c <load_store\+0x6c> 6c ?70 ?b4 ?ff ? * cfldrdvs mvd11, ?\[r0\], #-1020.*
-0*70 <load_store\+0x70> 3c ?71 ?c4 ?27 ? * cfldrdcc mvd12, ?\[r1\], #-156.*
-0*74 <load_store\+0x74> ec ?f9 ?d4 ?68 ? * cfldrd mvd13, ?\[r9\], #416.*
-0*78 <load_store\+0x78> 2d ?10 ?95 ?ff ? * cfldr32cs mvfx9, ?\[r0, #-1020\].*
-0*7c <load_store\+0x7c> 9d ?11 ?45 ?27 ? * cfldr32ls mvfx4, ?\[r1, #-156\].*
-0*80 <load_store\+0x80> dd ?99 ?75 ?68 ? * cfldr32le mvfx7, ?\[r9, #416\].*
-0*84 <load_store\+0x84> 6d ?10 ?b5 ?ff ? * cfldr32vs mvfx11, ?\[r0, #-1020\].*
-0*88 <load_store\+0x88> 3d ?11 ?c5 ?27 ? * cfldr32cc mvfx12, ?\[r1, #-156\].*
-0*8c <load_store\+0x8c> ed ?b9 ?d5 ?68 ? * cfldr32 mvfx13, ?\[r9, #416\]!.*
-0*90 <load_store\+0x90> 2d ?30 ?95 ?ff ? * cfldr32cs mvfx9, ?\[r0, #-1020\]!.*
-0*94 <load_store\+0x94> 9d ?31 ?45 ?27 ? * cfldr32ls mvfx4, ?\[r1, #-156\]!.*
-0*98 <load_store\+0x98> dd ?b9 ?75 ?68 ? * cfldr32le mvfx7, ?\[r9, #416\]!.*
-0*9c <load_store\+0x9c> 6d ?30 ?b5 ?ff ? * cfldr32vs mvfx11, ?\[r0, #-1020\]!.*
-0*a0 <load_store\+0xa0> 3c ?31 ?c5 ?27 ? * cfldr32cc mvfx12, ?\[r1\], #-156.*
-0*a4 <load_store\+0xa4> ec ?b9 ?d5 ?68 ? * cfldr32 mvfx13, ?\[r9\], #416.*
-0*a8 <load_store\+0xa8> 2c ?30 ?95 ?ff ? * cfldr32cs mvfx9, ?\[r0\], #-1020.*
-0*ac <load_store\+0xac> 9c ?31 ?45 ?27 ? * cfldr32ls mvfx4, ?\[r1\], #-156.*
-0*b0 <load_store\+0xb0> dc ?b9 ?75 ?68 ? * cfldr32le mvfx7, ?\[r9\], #416.*
-0*b4 <load_store\+0xb4> 6d ?50 ?b5 ?ff ? * cfldr64vs mvdx11, ?\[r0, #-1020\].*
-0*b8 <load_store\+0xb8> 3d ?51 ?c5 ?27 ? * cfldr64cc mvdx12, ?\[r1, #-156\].*
-0*bc <load_store\+0xbc> ed ?d9 ?d5 ?68 ? * cfldr64 mvdx13, ?\[r9, #416\].*
-0*c0 <load_store\+0xc0> 2d ?50 ?95 ?ff ? * cfldr64cs mvdx9, ?\[r0, #-1020\].*
-0*c4 <load_store\+0xc4> 9d ?51 ?45 ?27 ? * cfldr64ls mvdx4, ?\[r1, #-156\].*
-0*c8 <load_store\+0xc8> dd ?f9 ?75 ?68 ? * cfldr64le mvdx7, ?\[r9, #416\]!.*
-0*cc <load_store\+0xcc> 6d ?70 ?b5 ?ff ? * cfldr64vs mvdx11, ?\[r0, #-1020\]!.*
-0*d0 <load_store\+0xd0> 3d ?71 ?c5 ?27 ? * cfldr64cc mvdx12, ?\[r1, #-156\]!.*
-0*d4 <load_store\+0xd4> ed ?f9 ?d5 ?68 ? * cfldr64 mvdx13, ?\[r9, #416\]!.*
-0*d8 <load_store\+0xd8> 2d ?70 ?95 ?ff ? * cfldr64cs mvdx9, ?\[r0, #-1020\]!.*
-0*dc <load_store\+0xdc> 9c ?71 ?45 ?27 ? * cfldr64ls mvdx4, ?\[r1\], #-156.*
-0*e0 <load_store\+0xe0> dc ?f9 ?75 ?68 ? * cfldr64le mvdx7, ?\[r9\], #416.*
-0*e4 <load_store\+0xe4> 6c ?70 ?b5 ?ff ? * cfldr64vs mvdx11, ?\[r0\], #-1020.*
-0*e8 <load_store\+0xe8> 3c ?71 ?c5 ?27 ? * cfldr64cc mvdx12, ?\[r1\], #-156.*
-0*ec <load_store\+0xec> ec ?f9 ?d5 ?68 ? * cfldr64 mvdx13, ?\[r9\], #416.*
-0*f0 <load_store\+0xf0> 2d ?00 ?94 ?ff ? * cfstrscs mvf9, ?\[r0, #-1020\].*
-0*f4 <load_store\+0xf4> 9d ?01 ?44 ?27 ? * cfstrsls mvf4, ?\[r1, #-156\].*
-0*f8 <load_store\+0xf8> dd ?89 ?74 ?68 ? * cfstrsle mvf7, ?\[r9, #416\].*
-0*fc <load_store\+0xfc> 6d ?00 ?b4 ?ff ? * cfstrsvs mvf11, ?\[r0, #-1020\].*
-0*100 <load_store\+0x100> 3d ?01 ?c4 ?27 ? * cfstrscc mvf12, ?\[r1, #-156\].*
-0*104 <load_store\+0x104> ed ?a9 ?d4 ?68 ? * cfstrs mvf13, ?\[r9, #416\]!.*
-0*108 <load_store\+0x108> 2d ?20 ?94 ?ff ? * cfstrscs mvf9, ?\[r0, #-1020\]!.*
-0*10c <load_store\+0x10c> 9d ?21 ?44 ?27 ? * cfstrsls mvf4, ?\[r1, #-156\]!.*
-0*110 <load_store\+0x110> dd ?a9 ?74 ?68 ? * cfstrsle mvf7, ?\[r9, #416\]!.*
-0*114 <load_store\+0x114> 6d ?20 ?b4 ?ff ? * cfstrsvs mvf11, ?\[r0, #-1020\]!.*
-0*118 <load_store\+0x118> 3c ?21 ?c4 ?27 ? * cfstrscc mvf12, ?\[r1\], #-156.*
-0*11c <load_store\+0x11c> ec ?a9 ?d4 ?68 ? * cfstrs mvf13, ?\[r9\], #416.*
-0*120 <load_store\+0x120> 2c ?20 ?94 ?ff ? * cfstrscs mvf9, ?\[r0\], #-1020.*
-0*124 <load_store\+0x124> 9c ?21 ?44 ?27 ? * cfstrsls mvf4, ?\[r1\], #-156.*
-0*128 <load_store\+0x128> dc ?a9 ?74 ?68 ? * cfstrsle mvf7, ?\[r9\], #416.*
-0*12c <load_store\+0x12c> 6d ?40 ?b4 ?ff ? * cfstrdvs mvd11, ?\[r0, #-1020\].*
-0*130 <load_store\+0x130> 3d ?41 ?c4 ?27 ? * cfstrdcc mvd12, ?\[r1, #-156\].*
-0*134 <load_store\+0x134> ed ?c9 ?d4 ?68 ? * cfstrd mvd13, ?\[r9, #416\].*
-0*138 <load_store\+0x138> 2d ?40 ?94 ?ff ? * cfstrdcs mvd9, ?\[r0, #-1020\].*
-0*13c <load_store\+0x13c> 9d ?41 ?44 ?27 ? * cfstrdls mvd4, ?\[r1, #-156\].*
-0*140 <load_store\+0x140> dd ?e9 ?74 ?68 ? * cfstrdle mvd7, ?\[r9, #416\]!.*
-0*144 <load_store\+0x144> 6d ?60 ?b4 ?ff ? * cfstrdvs mvd11, ?\[r0, #-1020\]!.*
-0*148 <load_store\+0x148> 3d ?61 ?c4 ?27 ? * cfstrdcc mvd12, ?\[r1, #-156\]!.*
-0*14c <load_store\+0x14c> ed ?e9 ?d4 ?68 ? * cfstrd mvd13, ?\[r9, #416\]!.*
-0*150 <load_store\+0x150> 2d ?60 ?94 ?ff ? * cfstrdcs mvd9, ?\[r0, #-1020\]!.*
-0*154 <load_store\+0x154> 9c ?61 ?44 ?27 ? * cfstrdls mvd4, ?\[r1\], #-156.*
-0*158 <load_store\+0x158> dc ?e9 ?74 ?68 ? * cfstrdle mvd7, ?\[r9\], #416.*
-0*15c <load_store\+0x15c> 6c ?60 ?b4 ?ff ? * cfstrdvs mvd11, ?\[r0\], #-1020.*
-0*160 <load_store\+0x160> 3c ?61 ?c4 ?27 ? * cfstrdcc mvd12, ?\[r1\], #-156.*
-0*164 <load_store\+0x164> ec ?e9 ?d4 ?68 ? * cfstrd mvd13, ?\[r9\], #416.*
-0*168 <load_store\+0x168> 2d ?00 ?95 ?ff ? * cfstr32cs mvfx9, ?\[r0, #-1020\].*
-0*16c <load_store\+0x16c> 9d ?01 ?45 ?27 ? * cfstr32ls mvfx4, ?\[r1, #-156\].*
-0*170 <load_store\+0x170> dd ?89 ?75 ?68 ? * cfstr32le mvfx7, ?\[r9, #416\].*
-0*174 <load_store\+0x174> 6d ?00 ?b5 ?ff ? * cfstr32vs mvfx11, ?\[r0, #-1020\].*
-0*178 <load_store\+0x178> 3d ?01 ?c5 ?27 ? * cfstr32cc mvfx12, ?\[r1, #-156\].*
-0*17c <load_store\+0x17c> ed ?a9 ?d5 ?68 ? * cfstr32 mvfx13, ?\[r9, #416\]!.*
-0*180 <load_store\+0x180> 2d ?20 ?95 ?ff ? * cfstr32cs mvfx9, ?\[r0, #-1020\]!.*
-0*184 <load_store\+0x184> 9d ?21 ?45 ?27 ? * cfstr32ls mvfx4, ?\[r1, #-156\]!.*
-0*188 <load_store\+0x188> dd ?a9 ?75 ?68 ? * cfstr32le mvfx7, ?\[r9, #416\]!.*
-0*18c <load_store\+0x18c> 6d ?20 ?b5 ?ff ? * cfstr32vs mvfx11, ?\[r0, #-1020\]!.*
-0*190 <load_store\+0x190> 3c ?21 ?c5 ?27 ? * cfstr32cc mvfx12, ?\[r1\], #-156.*
-0*194 <load_store\+0x194> ec ?a9 ?d5 ?68 ? * cfstr32 mvfx13, ?\[r9\], #416.*
-0*198 <load_store\+0x198> 2c ?20 ?95 ?ff ? * cfstr32cs mvfx9, ?\[r0\], #-1020.*
-0*19c <load_store\+0x19c> 9c ?21 ?45 ?27 ? * cfstr32ls mvfx4, ?\[r1\], #-156.*
-0*1a0 <load_store\+0x1a0> dc ?a9 ?75 ?68 ? * cfstr32le mvfx7, ?\[r9\], #416.*
-0*1a4 <load_store\+0x1a4> 6d ?40 ?b5 ?ff ? * cfstr64vs mvdx11, ?\[r0, #-1020\].*
-0*1a8 <load_store\+0x1a8> 3d ?41 ?c5 ?27 ? * cfstr64cc mvdx12, ?\[r1, #-156\].*
-0*1ac <load_store\+0x1ac> ed ?c9 ?d5 ?68 ? * cfstr64 mvdx13, ?\[r9, #416\].*
-0*1b0 <load_store\+0x1b0> 2d ?40 ?95 ?ff ? * cfstr64cs mvdx9, ?\[r0, #-1020\].*
-0*1b4 <load_store\+0x1b4> 9d ?41 ?45 ?27 ? * cfstr64ls mvdx4, ?\[r1, #-156\].*
-0*1b8 <load_store\+0x1b8> dd ?e9 ?75 ?68 ? * cfstr64le mvdx7, ?\[r9, #416\]!.*
-0*1bc <load_store\+0x1bc> 6d ?60 ?b5 ?ff ? * cfstr64vs mvdx11, ?\[r0, #-1020\]!.*
-0*1c0 <load_store\+0x1c0> 3d ?61 ?c5 ?27 ? * cfstr64cc mvdx12, ?\[r1, #-156\]!.*
-0*1c4 <load_store\+0x1c4> ed ?e9 ?d5 ?68 ? * cfstr64 mvdx13, ?\[r9, #416\]!.*
-0*1c8 <load_store\+0x1c8> 2d ?60 ?95 ?ff ? * cfstr64cs mvdx9, ?\[r0, #-1020\]!.*
-0*1cc <load_store\+0x1cc> 9c ?61 ?45 ?27 ? * cfstr64ls mvdx4, ?\[r1\], #-156.*
-0*1d0 <load_store\+0x1d0> dc ?e9 ?75 ?68 ? * cfstr64le mvdx7, ?\[r9\], #416.*
-0*1d4 <load_store\+0x1d4> 6c ?60 ?b5 ?ff ? * cfstr64vs mvdx11, ?\[r0\], #-1020.*
-0*1d8 <load_store\+0x1d8> 3c ?61 ?c5 ?27 ? * cfstr64cc mvdx12, ?\[r1\], #-156.*
-0*1dc <load_store\+0x1dc> ec ?e9 ?d5 ?68 ? * cfstr64 mvdx13, ?\[r9\], #416.*
-# move:
-0*1e0 <move> 2e ?09 ?04 ?50 ? * cfmvsrcs mvf9, ?r0
-0*1e4 <move\+0x4> 5e ?0f ?74 ?50 ? * cfmvsrpl mvf15, ?r7
-0*1e8 <move\+0x8> 9e ?04 ?14 ?50 ? * cfmvsrls mvf4, ?r1
-0*1ec <move\+0xc> 3e ?08 ?24 ?50 ? * cfmvsrcc mvf8, ?r2
-0*1f0 <move\+0x10> 7e ?02 ?c4 ?50 ? * cfmvsrvc mvf2, ?ip
-0*1f4 <move\+0x14> ce ?1b ?94 ?50 ? * cfmvrsgt r9, ?mvf11
-0*1f8 <move\+0x18> 0e ?15 ?a4 ?50 ? * cfmvrseq sl, ?mvf5
-0*1fc <move\+0x1c> ee ?1c ?44 ?50 ? * cfmvrs r4, ?mvf12
-0*200 <move\+0x20> ae ?18 ?b4 ?50 ? * cfmvrsge fp, ?mvf8
-0*204 <move\+0x24> ee ?16 ?54 ?50 ? * cfmvrs r5, ?mvf6
-0*208 <move\+0x28> be ?04 ?94 ?10 ? * cfmvdlrlt mvd4, ?r9
-0*20c <move\+0x2c> 9e ?00 ?a4 ?10 ? * cfmvdlrls mvd0, ?sl
-0*210 <move\+0x30> ee ?0a ?44 ?10 ? * cfmvdlr mvd10, ?r4
-0*214 <move\+0x34> 4e ?0e ?b4 ?10 ? * cfmvdlrmi mvd14, ?fp
-0*218 <move\+0x38> 8e ?0d ?54 ?10 ? * cfmvdlrhi mvd13, ?r5
-0*21c <move\+0x3c> 2e ?1c ?c4 ?10 ? * cfmvrdlcs ip, ?mvd12
-0*220 <move\+0x40> 6e ?10 ?34 ?10 ? * cfmvrdlvs r3, ?mvd0
-0*224 <move\+0x44> 7e ?1e ?d4 ?10 ? * cfmvrdlvc sp, ?mvd14
-0*228 <move\+0x48> 3e ?1a ?e4 ?10 ? * cfmvrdlcc lr, ?mvd10
-0*22c <move\+0x4c> 1e ?1f ?84 ?10 ? * cfmvrdlne r8, ?mvd15
-0*230 <move\+0x50> de ?06 ?c4 ?30 ? * cfmvdhrle mvd6, ?ip
-0*234 <move\+0x54> 4e ?02 ?34 ?30 ? * cfmvdhrmi mvd2, ?r3
-0*238 <move\+0x58> 0e ?05 ?d4 ?30 ? * cfmvdhreq mvd5, ?sp
-0*23c <move\+0x5c> ae ?09 ?e4 ?30 ? * cfmvdhrge mvd9, ?lr
-0*240 <move\+0x60> ee ?03 ?84 ?30 ? * cfmvdhr mvd3, ?r8
-0*244 <move\+0x64> de ?12 ?54 ?30 ? * cfmvrdhle r5, ?mvd2
-0*248 <move\+0x68> 1e ?16 ?64 ?30 ? * cfmvrdhne r6, ?mvd6
-0*24c <move\+0x6c> be ?17 ?04 ?30 ? * cfmvrdhlt r0, ?mvd7
-0*250 <move\+0x70> 5e ?13 ?74 ?30 ? * cfmvrdhpl r7, ?mvd3
-0*254 <move\+0x74> ce ?11 ?14 ?30 ? * cfmvrdhgt r1, ?mvd1
-0*258 <move\+0x78> 8e ?0f ?55 ?10 ? * cfmv64lrhi mvdx15, ?r5
-0*25c <move\+0x7c> 6e ?0b ?65 ?10 ? * cfmv64lrvs mvdx11, ?r6
-0*260 <move\+0x80> 2e ?09 ?05 ?10 ? * cfmv64lrcs mvdx9, ?r0
-0*264 <move\+0x84> 5e ?0f ?75 ?10 ? * cfmv64lrpl mvdx15, ?r7
-0*268 <move\+0x88> 9e ?04 ?15 ?10 ? * cfmv64lrls mvdx4, ?r1
-0*26c <move\+0x8c> 3e ?1d ?85 ?10 ? * cfmvr64lcc r8, ?mvdx13
-0*270 <move\+0x90> 7e ?11 ?f5 ?10 ? * cfmvr64lvc pc, ?mvdx1
-0*274 <move\+0x94> ce ?1b ?95 ?10 ? * cfmvr64lgt r9, ?mvdx11
-0*278 <move\+0x98> 0e ?15 ?a5 ?10 ? * cfmvr64leq sl, ?mvdx5
-0*27c <move\+0x9c> ee ?1c ?45 ?10 ? * cfmvr64l r4, ?mvdx12
-0*280 <move\+0xa0> ae ?01 ?85 ?30 ? * cfmv64hrge mvdx1, ?r8
-0*284 <move\+0xa4> ee ?0d ?f5 ?30 ? * cfmv64hr mvdx13, ?pc
-0*288 <move\+0xa8> be ?04 ?95 ?30 ? * cfmv64hrlt mvdx4, ?r9
-0*28c <move\+0xac> 9e ?00 ?a5 ?30 ? * cfmv64hrls mvdx0, ?sl
-0*290 <move\+0xb0> ee ?0a ?45 ?30 ? * cfmv64hr mvdx10, ?r4
-0*294 <move\+0xb4> 4e ?13 ?15 ?30 ? * cfmvr64hmi r1, ?mvdx3
-0*298 <move\+0xb8> 8e ?17 ?25 ?30 ? * cfmvr64hhi r2, ?mvdx7
-0*29c <move\+0xbc> 2e ?1c ?c5 ?30 ? * cfmvr64hcs ip, ?mvdx12
-0*2a0 <move\+0xc0> 6e ?10 ?35 ?30 ? * cfmvr64hvs r3, ?mvdx0
-0*2a4 <move\+0xc4> 7e ?1e ?d5 ?30 ? * cfmvr64hvc sp, ?mvdx14
-0*2a8 <move\+0xc8> 3e ?2a ?04 ?40 ? * cfmval32cc mvax0, ?mvfx10
-0*2ac <move\+0xcc> 1e ?2f ?14 ?40 ? * cfmval32ne mvax1, ?mvfx15
-0*2b0 <move\+0xd0> de ?2b ?04 ?40 ? * cfmval32le mvax0, ?mvfx11
-0*2b4 <move\+0xd4> 4e ?29 ?04 ?40 ? * cfmval32mi mvax0, ?mvfx9
-0*2b8 <move\+0xd8> 0e ?2f ?14 ?40 ? * cfmval32eq mvax1, ?mvfx15
-0*2bc <move\+0xdc> ae ?10 ?94 ?40 ? * cfmv32alge mvfx9, ?mvax0
-0*2c0 <move\+0xe0> ee ?11 ?34 ?40 ? * cfmv32al mvfx3, ?mvax1
-0*2c4 <move\+0xe4> de ?10 ?74 ?40 ? * cfmv32alle mvfx7, ?mvax0
-0*2c8 <move\+0xe8> 1e ?10 ?c4 ?40 ? * cfmv32alne mvfx12, ?mvax0
-0*2cc <move\+0xec> be ?11 ?04 ?40 ? * cfmv32allt mvfx0, ?mvax1
-0*2d0 <move\+0xf0> 5e ?23 ?24 ?60 ? * cfmvam32pl mvax2, ?mvfx3
-0*2d4 <move\+0xf4> ce ?21 ?14 ?60 ? * cfmvam32gt mvax1, ?mvfx1
-0*2d8 <move\+0xf8> 8e ?2d ?34 ?60 ? * cfmvam32hi mvax3, ?mvfx13
-0*2dc <move\+0xfc> 6e ?24 ?34 ?60 ? * cfmvam32vs mvax3, ?mvfx4
-0*2e0 <move\+0x100> 2e ?20 ?14 ?60 ? * cfmvam32cs mvax1, ?mvfx0
-0*2e4 <move\+0x104> 5e ?12 ?f4 ?60 ? * cfmv32ampl mvfx15, ?mvax2
-0*2e8 <move\+0x108> 9e ?11 ?44 ?60 ? * cfmv32amls mvfx4, ?mvax1
-0*2ec <move\+0x10c> 3e ?13 ?84 ?60 ? * cfmv32amcc mvfx8, ?mvax3
-0*2f0 <move\+0x110> 7e ?13 ?24 ?60 ? * cfmv32amvc mvfx2, ?mvax3
-0*2f4 <move\+0x114> ce ?11 ?64 ?60 ? * cfmv32amgt mvfx6, ?mvax1
-0*2f8 <move\+0x118> 0e ?25 ?14 ?80 ? * cfmvah32eq mvax1, ?mvfx5
-0*2fc <move\+0x11c> ee ?2c ?24 ?80 ? * cfmvah32 mvax2, ?mvfx12
-0*300 <move\+0x120> ae ?28 ?34 ?80 ? * cfmvah32ge mvax3, ?mvfx8
-0*304 <move\+0x124> ee ?26 ?24 ?80 ? * cfmvah32 mvax2, ?mvfx6
-0*308 <move\+0x128> be ?22 ?24 ?80 ? * cfmvah32lt mvax2, ?mvfx2
-0*30c <move\+0x12c> 9e ?11 ?04 ?80 ? * cfmv32ahls mvfx0, ?mvax1
-0*310 <move\+0x130> ee ?12 ?a4 ?80 ? * cfmv32ah mvfx10, ?mvax2
-0*314 <move\+0x134> 4e ?13 ?e4 ?80 ? * cfmv32ahmi mvfx14, ?mvax3
-0*318 <move\+0x138> 8e ?12 ?d4 ?80 ? * cfmv32ahhi mvfx13, ?mvax2
-0*31c <move\+0x13c> 2e ?12 ?14 ?80 ? * cfmv32ahcs mvfx1, ?mvax2
-0*320 <move\+0x140> 6e ?20 ?14 ?a0 ? * cfmva32vs mvax1, ?mvfx0
-0*324 <move\+0x144> 7e ?2e ?34 ?a0 ? * cfmva32vc mvax3, ?mvfx14
-0*328 <move\+0x148> 3e ?2a ?04 ?a0 ? * cfmva32cc mvax0, ?mvfx10
-0*32c <move\+0x14c> 1e ?2f ?14 ?a0 ? * cfmva32ne mvax1, ?mvfx15
-0*330 <move\+0x150> de ?2b ?04 ?a0 ? * cfmva32le mvax0, ?mvfx11
-0*334 <move\+0x154> 4e ?11 ?24 ?a0 ? * cfmv32ami mvfx2, ?mvax1
-0*338 <move\+0x158> 0e ?13 ?54 ?a0 ? * cfmv32aeq mvfx5, ?mvax3
-0*33c <move\+0x15c> ae ?10 ?94 ?a0 ? * cfmv32age mvfx9, ?mvax0
-0*340 <move\+0x160> ee ?11 ?34 ?a0 ? * cfmv32a mvfx3, ?mvax1
-0*344 <move\+0x164> de ?10 ?74 ?a0 ? * cfmv32ale mvfx7, ?mvax0
-0*348 <move\+0x168> 1e ?26 ?24 ?c0 ? * cfmva64ne mvax2, ?mvdx6
-0*34c <move\+0x16c> be ?27 ?04 ?c0 ? * cfmva64lt mvax0, ?mvdx7
-0*350 <move\+0x170> 5e ?23 ?24 ?c0 ? * cfmva64pl mvax2, ?mvdx3
-0*354 <move\+0x174> ce ?21 ?14 ?c0 ? * cfmva64gt mvax1, ?mvdx1
-0*358 <move\+0x178> 8e ?2d ?34 ?c0 ? * cfmva64hi mvax3, ?mvdx13
-0*35c <move\+0x17c> 6e ?12 ?b4 ?c0 ? * cfmv64avs mvdx11, ?mvax2
-0*360 <move\+0x180> 2e ?10 ?94 ?c0 ? * cfmv64acs mvdx9, ?mvax0
-0*364 <move\+0x184> 5e ?12 ?f4 ?c0 ? * cfmv64apl mvdx15, ?mvax2
-0*368 <move\+0x188> 9e ?11 ?44 ?c0 ? * cfmv64als mvdx4, ?mvax1
-0*36c <move\+0x18c> 3e ?13 ?84 ?c0 ? * cfmv64acc mvdx8, ?mvax3
-0*370 <move\+0x190> 7e ?20 ?14 ?e0 ? * cfmvsc32vc dspsc, ?mvdx1
-0*374 <move\+0x194> ce ?20 ?b4 ?e0 ? * cfmvsc32gt dspsc, ?mvdx11
-0*378 <move\+0x198> 0e ?20 ?54 ?e0 ? * cfmvsc32eq dspsc, ?mvdx5
-0*37c <move\+0x19c> ee ?20 ?c4 ?e0 ? * cfmvsc32 dspsc, ?mvdx12
-0*380 <move\+0x1a0> ae ?20 ?84 ?e0 ? * cfmvsc32ge dspsc, ?mvdx8
-0*384 <move\+0x1a4> ee ?10 ?d4 ?e0 ? * cfmv32sc mvdx13, ?dspsc
-0*388 <move\+0x1a8> be ?10 ?44 ?e0 ? * cfmv32sclt mvdx4, ?dspsc
-0*38c <move\+0x1ac> 9e ?10 ?04 ?e0 ? * cfmv32scls mvdx0, ?dspsc
-0*390 <move\+0x1b0> ee ?10 ?a4 ?e0 ? * cfmv32sc mvdx10, ?dspsc
-0*394 <move\+0x1b4> 4e ?10 ?e4 ?e0 ? * cfmv32scmi mvdx14, ?dspsc
-0*398 <move\+0x1b8> 8e ?07 ?d4 ?00 ? * cfcpyshi mvf13, ?mvf7
-0*39c <move\+0x1bc> 2e ?0c ?14 ?00 ? * cfcpyscs mvf1, ?mvf12
-0*3a0 <move\+0x1c0> 6e ?00 ?b4 ?00 ? * cfcpysvs mvf11, ?mvf0
-0*3a4 <move\+0x1c4> 7e ?0e ?54 ?00 ? * cfcpysvc mvf5, ?mvf14
-0*3a8 <move\+0x1c8> 3e ?0a ?c4 ?00 ? * cfcpyscc mvf12, ?mvf10
-0*3ac <move\+0x1cc> 1e ?0f ?84 ?20 ? * cfcpydne mvd8, ?mvd15
-0*3b0 <move\+0x1d0> de ?0b ?64 ?20 ? * cfcpydle mvd6, ?mvd11
-0*3b4 <move\+0x1d4> 4e ?09 ?24 ?20 ? * cfcpydmi mvd2, ?mvd9
-0*3b8 <move\+0x1d8> 0e ?0f ?54 ?20 ? * cfcpydeq mvd5, ?mvd15
-0*3bc <move\+0x1dc> ae ?04 ?94 ?20 ? * cfcpydge mvd9, ?mvd4
-# conv:
-0*3c0 <conv> ee ?08 ?34 ?60 ? * cfcvtsd mvd3, ?mvf8
-0*3c4 <conv\+0x4> de ?02 ?74 ?60 ? * cfcvtsdle mvd7, ?mvf2
-0*3c8 <conv\+0x8> 1e ?06 ?c4 ?60 ? * cfcvtsdne mvd12, ?mvf6
-0*3cc <conv\+0xc> be ?07 ?04 ?60 ? * cfcvtsdlt mvd0, ?mvf7
-0*3d0 <conv\+0x10> 5e ?03 ?e4 ?60 ? * cfcvtsdpl mvd14, ?mvf3
-0*3d4 <conv\+0x14> ce ?01 ?a4 ?40 ? * cfcvtdsgt mvf10, ?mvd1
-0*3d8 <conv\+0x18> 8e ?0d ?f4 ?40 ? * cfcvtdshi mvf15, ?mvd13
-0*3dc <conv\+0x1c> 6e ?04 ?b4 ?40 ? * cfcvtdsvs mvf11, ?mvd4
-0*3e0 <conv\+0x20> 2e ?00 ?94 ?40 ? * cfcvtdscs mvf9, ?mvd0
-0*3e4 <conv\+0x24> 5e ?0a ?f4 ?40 ? * cfcvtdspl mvf15, ?mvd10
-0*3e8 <conv\+0x28> 9e ?0e ?44 ?80 ? * cfcvt32sls mvf4, ?mvfx14
-0*3ec <conv\+0x2c> 3e ?0d ?84 ?80 ? * cfcvt32scc mvf8, ?mvfx13
-0*3f0 <conv\+0x30> 7e ?01 ?24 ?80 ? * cfcvt32svc mvf2, ?mvfx1
-0*3f4 <conv\+0x34> ce ?0b ?64 ?80 ? * cfcvt32sgt mvf6, ?mvfx11
-0*3f8 <conv\+0x38> 0e ?05 ?74 ?80 ? * cfcvt32seq mvf7, ?mvfx5
-0*3fc <conv\+0x3c> ee ?0c ?34 ?a0 ? * cfcvt32d mvd3, ?mvfx12
-0*400 <conv\+0x40> ae ?08 ?14 ?a0 ? * cfcvt32dge mvd1, ?mvfx8
-0*404 <conv\+0x44> ee ?06 ?d4 ?a0 ? * cfcvt32d mvd13, ?mvfx6
-0*408 <conv\+0x48> be ?02 ?44 ?a0 ? * cfcvt32dlt mvd4, ?mvfx2
-0*40c <conv\+0x4c> 9e ?05 ?04 ?a0 ? * cfcvt32dls mvd0, ?mvfx5
-0*410 <conv\+0x50> ee ?09 ?a4 ?c0 ? * cfcvt64s mvf10, ?mvdx9
-0*414 <conv\+0x54> 4e ?03 ?e4 ?c0 ? * cfcvt64smi mvf14, ?mvdx3
-0*418 <conv\+0x58> 8e ?07 ?d4 ?c0 ? * cfcvt64shi mvf13, ?mvdx7
-0*41c <conv\+0x5c> 2e ?0c ?14 ?c0 ? * cfcvt64scs mvf1, ?mvdx12
-0*420 <conv\+0x60> 6e ?00 ?b4 ?c0 ? * cfcvt64svs mvf11, ?mvdx0
-0*424 <conv\+0x64> 7e ?0e ?54 ?e0 ? * cfcvt64dvc mvd5, ?mvdx14
-0*428 <conv\+0x68> 3e ?0a ?c4 ?e0 ? * cfcvt64dcc mvd12, ?mvdx10
-0*42c <conv\+0x6c> 1e ?0f ?84 ?e0 ? * cfcvt64dne mvd8, ?mvdx15
-0*430 <conv\+0x70> de ?0b ?64 ?e0 ? * cfcvt64dle mvd6, ?mvdx11
-0*434 <conv\+0x74> 4e ?09 ?24 ?e0 ? * cfcvt64dmi mvd2, ?mvdx9
-0*438 <conv\+0x78> 0e ?1f ?55 ?80 ? * cfcvts32eq mvfx5, ?mvf15
-0*43c <conv\+0x7c> ae ?14 ?95 ?80 ? * cfcvts32ge mvfx9, ?mvf4
-0*440 <conv\+0x80> ee ?18 ?35 ?80 ? * cfcvts32 mvfx3, ?mvf8
-0*444 <conv\+0x84> de ?12 ?75 ?80 ? * cfcvts32le mvfx7, ?mvf2
-0*448 <conv\+0x88> 1e ?16 ?c5 ?80 ? * cfcvts32ne mvfx12, ?mvf6
-0*44c <conv\+0x8c> be ?17 ?05 ?a0 ? * cfcvtd32lt mvfx0, ?mvd7
-0*450 <conv\+0x90> 5e ?13 ?e5 ?a0 ? * cfcvtd32pl mvfx14, ?mvd3
-0*454 <conv\+0x94> ce ?11 ?a5 ?a0 ? * cfcvtd32gt mvfx10, ?mvd1
-0*458 <conv\+0x98> 8e ?1d ?f5 ?a0 ? * cfcvtd32hi mvfx15, ?mvd13
-0*45c <conv\+0x9c> 6e ?14 ?b5 ?a0 ? * cfcvtd32vs mvfx11, ?mvd4
-0*460 <conv\+0xa0> 2e ?10 ?95 ?c0 ? * cftruncs32cs mvfx9, ?mvf0
-0*464 <conv\+0xa4> 5e ?1a ?f5 ?c0 ? * cftruncs32pl mvfx15, ?mvf10
-0*468 <conv\+0xa8> 9e ?1e ?45 ?c0 ? * cftruncs32ls mvfx4, ?mvf14
-0*46c <conv\+0xac> 3e ?1d ?85 ?c0 ? * cftruncs32cc mvfx8, ?mvf13
-0*470 <conv\+0xb0> 7e ?11 ?25 ?c0 ? * cftruncs32vc mvfx2, ?mvf1
-0*474 <conv\+0xb4> ce ?1b ?65 ?e0 ? * cftruncd32gt mvfx6, ?mvd11
-0*478 <conv\+0xb8> 0e ?15 ?75 ?e0 ? * cftruncd32eq mvfx7, ?mvd5
-0*47c <conv\+0xbc> ee ?1c ?35 ?e0 ? * cftruncd32 mvfx3, ?mvd12
-0*480 <conv\+0xc0> ae ?18 ?15 ?e0 ? * cftruncd32ge mvfx1, ?mvd8
-0*484 <conv\+0xc4> ee ?16 ?d5 ?e0 ? * cftruncd32 mvfx13, ?mvd6
-# shift:
-0*488 <shift> be ?04 ?35 ?52 ? * cfrshl32lt mvfx4, ?mvfx2, ?r3
-0*48c <shift\+0x4> 5e ?0f ?45 ?5a ? * cfrshl32pl mvfx15, ?mvfx10, ?r4
-0*490 <shift\+0x8> ee ?03 ?25 ?58 ? * cfrshl32 mvfx3, ?mvfx8, ?r2
-0*494 <shift\+0xc> 2e ?01 ?95 ?5c ? * cfrshl32cs mvfx1, ?mvfx12, ?r9
-0*498 <shift\+0x10> 0e ?07 ?75 ?55 ? * cfrshl32eq mvfx7, ?mvfx5, ?r7
-0*49c <shift\+0x14> ce ?0a ?85 ?71 ? * cfrshl64gt mvdx10, ?mvdx1, ?r8
-0*4a0 <shift\+0x18> de ?06 ?65 ?7b ? * cfrshl64le mvdx6, ?mvdx11, ?r6
-0*4a4 <shift\+0x1c> 9e ?00 ?d5 ?75 ? * cfrshl64ls mvdx0, ?mvdx5, ?sp
-0*4a8 <shift\+0x20> 9e ?04 ?b5 ?7e ? * cfrshl64ls mvdx4, ?mvdx14, ?fp
-0*4ac <shift\+0x24> de ?07 ?c5 ?72 ? * cfrshl64le mvdx7, ?mvdx2, ?ip
-0*4b0 <shift\+0x28> 6e ?00 ?b5 ?ef ? * cfsh32vs mvfx11, ?mvfx0, ?#-1
-0*4b4 <shift\+0x2c> ee ?0c ?35 ?28 ? * cfsh32 mvfx3, ?mvfx12, ?#24
-0*4b8 <shift\+0x30> 8e ?0d ?f5 ?41 ? * cfsh32hi mvfx15, ?mvfx13, ?#33.*
-0*4bc <shift\+0x34> 4e ?09 ?25 ?00 ? * cfsh32mi mvfx2, ?mvfx9, ?#0
-0*4c0 <shift\+0x38> ee ?09 ?a5 ?40 ? * cfsh32 mvfx10, ?mvfx9, ?#32
-0*4c4 <shift\+0x3c> 3e ?2d ?85 ?c1 ? * cfsh64cc mvdx8, ?mvdx13, ?#-31.*
-0*4c8 <shift\+0x40> 1e ?26 ?c5 ?01 ? * cfsh64ne mvdx12, ?mvdx6, ?#1
-0*4cc <shift\+0x44> 7e ?2e ?55 ?c0 ? * cfsh64vc mvdx5, ?mvdx14, ?#-32.*
-0*4d0 <shift\+0x48> ae ?28 ?15 ?c5 ? * cfsh64ge mvdx1, ?mvdx8, ?#-27.*
-0*4d4 <shift\+0x4c> 6e ?24 ?b5 ?eb ? * cfsh64vs mvdx11, ?mvdx4, ?#-5
-# comp:
-0*4d8 <comp> 0e ?1f ?a4 ?9a ? * cfcmpseq sl, ?mvf15, ?mvf10
-0*4dc <comp\+0x4> 4e ?13 ?14 ?98 ? * cfcmpsmi r1, ?mvf3, ?mvf8
-0*4e0 <comp\+0x8> 7e ?11 ?f4 ?9c ? * cfcmpsvc pc, ?mvf1, ?mvf12
-0*4e4 <comp\+0xc> be ?17 ?04 ?95 ? * cfcmpslt r0, ?mvf7, ?mvf5
-0*4e8 <comp\+0x10> 3e ?1a ?e4 ?91 ? * cfcmpscc lr, ?mvf10, ?mvf1
-0*4ec <comp\+0x14> ee ?16 ?54 ?bb ? * cfcmpd r5, ?mvd6, ?mvd11
-0*4f0 <comp\+0x18> 2e ?10 ?34 ?b5 ? * cfcmpdcs r3, ?mvd0, ?mvd5
-0*4f4 <comp\+0x1c> ae ?14 ?44 ?be ? * cfcmpdge r4, ?mvd4, ?mvd14
-0*4f8 <comp\+0x20> 8e ?17 ?24 ?b2 ? * cfcmpdhi r2, ?mvd7, ?mvd2
-0*4fc <comp\+0x24> ce ?1b ?94 ?b0 ? * cfcmpdgt r9, ?mvd11, ?mvd0
-0*500 <comp\+0x28> 5e ?13 ?75 ?9c ? * cfcmp32pl r7, ?mvfx3, ?mvfx12
-0*504 <comp\+0x2c> 1e ?1f ?85 ?9d ? * cfcmp32ne r8, ?mvfx15, ?mvfx13
-0*508 <comp\+0x30> be ?12 ?65 ?99 ? * cfcmp32lt r6, ?mvfx2, ?mvfx9
-0*50c <comp\+0x34> 5e ?1a ?d5 ?99 ? * cfcmp32pl sp, ?mvfx10, ?mvfx9
-0*510 <comp\+0x38> ee ?18 ?b5 ?9d ? * cfcmp32 fp, ?mvfx8, ?mvfx13
-0*514 <comp\+0x3c> 2e ?1c ?c5 ?b6 ? * cfcmp64cs ip, ?mvdx12, ?mvdx6
-0*518 <comp\+0x40> 0e ?15 ?a5 ?be ? * cfcmp64eq sl, ?mvdx5, ?mvdx14
-0*51c <comp\+0x44> ce ?11 ?15 ?b8 ? * cfcmp64gt r1, ?mvdx1, ?mvdx8
-0*520 <comp\+0x48> de ?1b ?f5 ?b4 ? * cfcmp64le pc, ?mvdx11, ?mvdx4
-0*524 <comp\+0x4c> 9e ?15 ?05 ?bf ? * cfcmp64ls r0, ?mvdx5, ?mvdx15
-# fp_arith:
-0*528 <fp_arith> 9e ?3e ?44 ?00 ? * cfabssls mvf4, ?mvf14
-0*52c <fp_arith\+0x4> 3e ?3d ?84 ?00 ? * cfabsscc mvf8, ?mvf13
-0*530 <fp_arith\+0x8> 7e ?31 ?24 ?00 ? * cfabssvc mvf2, ?mvf1
-0*534 <fp_arith\+0xc> ce ?3b ?64 ?00 ? * cfabssgt mvf6, ?mvf11
-0*538 <fp_arith\+0x10> 0e ?35 ?74 ?00 ? * cfabsseq mvf7, ?mvf5
-0*53c <fp_arith\+0x14> ee ?3c ?34 ?20 ? * cfabsd mvd3, ?mvd12
-0*540 <fp_arith\+0x18> ae ?38 ?14 ?20 ? * cfabsdge mvd1, ?mvd8
-0*544 <fp_arith\+0x1c> ee ?36 ?d4 ?20 ? * cfabsd mvd13, ?mvd6
-0*548 <fp_arith\+0x20> be ?32 ?44 ?20 ? * cfabsdlt mvd4, ?mvd2
-0*54c <fp_arith\+0x24> 9e ?35 ?04 ?20 ? * cfabsdls mvd0, ?mvd5
-0*550 <fp_arith\+0x28> ee ?39 ?a4 ?40 ? * cfnegs mvf10, ?mvf9
-0*554 <fp_arith\+0x2c> 4e ?33 ?e4 ?40 ? * cfnegsmi mvf14, ?mvf3
-0*558 <fp_arith\+0x30> 8e ?37 ?d4 ?40 ? * cfnegshi mvf13, ?mvf7
-0*55c <fp_arith\+0x34> 2e ?3c ?14 ?40 ? * cfnegscs mvf1, ?mvf12
-0*560 <fp_arith\+0x38> 6e ?30 ?b4 ?40 ? * cfnegsvs mvf11, ?mvf0
-0*564 <fp_arith\+0x3c> 7e ?3e ?54 ?60 ? * cfnegdvc mvd5, ?mvd14
-0*568 <fp_arith\+0x40> 3e ?3a ?c4 ?60 ? * cfnegdcc mvd12, ?mvd10
-0*56c <fp_arith\+0x44> 1e ?3f ?84 ?60 ? * cfnegdne mvd8, ?mvd15
-0*570 <fp_arith\+0x48> de ?3b ?64 ?60 ? * cfnegdle mvd6, ?mvd11
-0*574 <fp_arith\+0x4c> 4e ?39 ?24 ?60 ? * cfnegdmi mvd2, ?mvd9
-0*578 <fp_arith\+0x50> 0e ?3f ?54 ?8a ? * cfaddseq mvf5, ?mvf15, ?mvf10
-0*57c <fp_arith\+0x54> 4e ?33 ?e4 ?88 ? * cfaddsmi mvf14, ?mvf3, ?mvf8
-0*580 <fp_arith\+0x58> 7e ?31 ?24 ?8c ? * cfaddsvc mvf2, ?mvf1, ?mvf12
-0*584 <fp_arith\+0x5c> be ?37 ?04 ?85 ? * cfaddslt mvf0, ?mvf7, ?mvf5
-0*588 <fp_arith\+0x60> 3e ?3a ?c4 ?81 ? * cfaddscc mvf12, ?mvf10, ?mvf1
-0*58c <fp_arith\+0x64> ee ?36 ?d4 ?ab ? * cfaddd mvd13, ?mvd6, ?mvd11
-0*590 <fp_arith\+0x68> 2e ?30 ?94 ?a5 ? * cfadddcs mvd9, ?mvd0, ?mvd5
-0*594 <fp_arith\+0x6c> ae ?34 ?94 ?ae ? * cfadddge mvd9, ?mvd4, ?mvd14
-0*598 <fp_arith\+0x70> 8e ?37 ?d4 ?a2 ? * cfadddhi mvd13, ?mvd7, ?mvd2
-0*59c <fp_arith\+0x74> ce ?3b ?64 ?a0 ? * cfadddgt mvd6, ?mvd11, ?mvd0
-0*5a0 <fp_arith\+0x78> 5e ?33 ?e4 ?cc ? * cfsubspl mvf14, ?mvf3, ?mvf12
-0*5a4 <fp_arith\+0x7c> 1e ?3f ?84 ?cd ? * cfsubsne mvf8, ?mvf15, ?mvf13
-0*5a8 <fp_arith\+0x80> be ?32 ?44 ?c9 ? * cfsubslt mvf4, ?mvf2, ?mvf9
-0*5ac <fp_arith\+0x84> 5e ?3a ?f4 ?c9 ? * cfsubspl mvf15, ?mvf10, ?mvf9
-0*5b0 <fp_arith\+0x88> ee ?38 ?34 ?cd ? * cfsubs mvf3, ?mvf8, ?mvf13
-0*5b4 <fp_arith\+0x8c> 2e ?3c ?14 ?e6 ? * cfsubdcs mvd1, ?mvd12, ?mvd6
-0*5b8 <fp_arith\+0x90> 0e ?35 ?74 ?ee ? * cfsubdeq mvd7, ?mvd5, ?mvd14
-0*5bc <fp_arith\+0x94> ce ?31 ?a4 ?e8 ? * cfsubdgt mvd10, ?mvd1, ?mvd8
-0*5c0 <fp_arith\+0x98> de ?3b ?64 ?e4 ? * cfsubdle mvd6, ?mvd11, ?mvd4
-0*5c4 <fp_arith\+0x9c> 9e ?35 ?04 ?ef ? * cfsubdls mvd0, ?mvd5, ?mvd15
-0*5c8 <fp_arith\+0xa0> 9e ?1e ?44 ?03 ? * cfmulsls mvf4, ?mvf14, ?mvf3
-0*5cc <fp_arith\+0xa4> de ?12 ?74 ?01 ? * cfmulsle mvf7, ?mvf2, ?mvf1
-0*5d0 <fp_arith\+0xa8> 6e ?10 ?b4 ?07 ? * cfmulsvs mvf11, ?mvf0, ?mvf7
-0*5d4 <fp_arith\+0xac> ee ?1c ?34 ?0a ? * cfmuls mvf3, ?mvf12, ?mvf10
-0*5d8 <fp_arith\+0xb0> 8e ?1d ?f4 ?06 ? * cfmulshi mvf15, ?mvf13, ?mvf6
-0*5dc <fp_arith\+0xb4> 4e ?19 ?24 ?20 ? * cfmuldmi mvd2, ?mvd9, ?mvd0
-0*5e0 <fp_arith\+0xb8> ee ?19 ?a4 ?24 ? * cfmuld mvd10, ?mvd9, ?mvd4
-0*5e4 <fp_arith\+0xbc> 3e ?1d ?84 ?27 ? * cfmuldcc mvd8, ?mvd13, ?mvd7
-0*5e8 <fp_arith\+0xc0> 1e ?16 ?c4 ?2b ? * cfmuldne mvd12, ?mvd6, ?mvd11
-0*5ec <fp_arith\+0xc4> 7e ?1e ?54 ?23 ? * cfmuldvc mvd5, ?mvd14, ?mvd3
-# int_arith:
-0*5f0 <int_arith> ae ?38 ?15 ?00 ? * cfabs32ge mvfx1, ?mvfx8
-0*5f4 <int_arith\+0x4> ee ?36 ?d5 ?00 ? * cfabs32 mvfx13, ?mvfx6
-0*5f8 <int_arith\+0x8> be ?32 ?45 ?00 ? * cfabs32lt mvfx4, ?mvfx2
-0*5fc <int_arith\+0xc> 9e ?35 ?05 ?00 ? * cfabs32ls mvfx0, ?mvfx5
-0*600 <int_arith\+0x10> ee ?39 ?a5 ?00 ? * cfabs32 mvfx10, ?mvfx9
-0*604 <int_arith\+0x14> 4e ?33 ?e5 ?20 ? * cfabs64mi mvdx14, ?mvdx3
-0*608 <int_arith\+0x18> 8e ?37 ?d5 ?20 ? * cfabs64hi mvdx13, ?mvdx7
-0*60c <int_arith\+0x1c> 2e ?3c ?15 ?20 ? * cfabs64cs mvdx1, ?mvdx12
-0*610 <int_arith\+0x20> 6e ?30 ?b5 ?20 ? * cfabs64vs mvdx11, ?mvdx0
-0*614 <int_arith\+0x24> 7e ?3e ?55 ?20 ? * cfabs64vc mvdx5, ?mvdx14
-0*618 <int_arith\+0x28> 3e ?3a ?c5 ?40 ? * cfneg32cc mvfx12, ?mvfx10
-0*61c <int_arith\+0x2c> 1e ?3f ?85 ?40 ? * cfneg32ne mvfx8, ?mvfx15
-0*620 <int_arith\+0x30> de ?3b ?65 ?40 ? * cfneg32le mvfx6, ?mvfx11
-0*624 <int_arith\+0x34> 4e ?39 ?25 ?40 ? * cfneg32mi mvfx2, ?mvfx9
-0*628 <int_arith\+0x38> 0e ?3f ?55 ?40 ? * cfneg32eq mvfx5, ?mvfx15
-0*62c <int_arith\+0x3c> ae ?34 ?95 ?60 ? * cfneg64ge mvdx9, ?mvdx4
-0*630 <int_arith\+0x40> ee ?38 ?35 ?60 ? * cfneg64 mvdx3, ?mvdx8
-0*634 <int_arith\+0x44> de ?32 ?75 ?60 ? * cfneg64le mvdx7, ?mvdx2
-0*638 <int_arith\+0x48> 1e ?36 ?c5 ?60 ? * cfneg64ne mvdx12, ?mvdx6
-0*63c <int_arith\+0x4c> be ?37 ?05 ?60 ? * cfneg64lt mvdx0, ?mvdx7
-0*640 <int_arith\+0x50> 5e ?33 ?e5 ?8c ? * cfadd32pl mvfx14, ?mvfx3, ?mvfx12
-0*644 <int_arith\+0x54> 1e ?3f ?85 ?8d ? * cfadd32ne mvfx8, ?mvfx15, ?mvfx13
-0*648 <int_arith\+0x58> be ?32 ?45 ?89 ? * cfadd32lt mvfx4, ?mvfx2, ?mvfx9
-0*64c <int_arith\+0x5c> 5e ?3a ?f5 ?89 ? * cfadd32pl mvfx15, ?mvfx10, ?mvfx9
-0*650 <int_arith\+0x60> ee ?38 ?35 ?8d ? * cfadd32 mvfx3, ?mvfx8, ?mvfx13
-0*654 <int_arith\+0x64> 2e ?3c ?15 ?a6 ? * cfadd64cs mvdx1, ?mvdx12, ?mvdx6
-0*658 <int_arith\+0x68> 0e ?35 ?75 ?ae ? * cfadd64eq mvdx7, ?mvdx5, ?mvdx14
-0*65c <int_arith\+0x6c> ce ?31 ?a5 ?a8 ? * cfadd64gt mvdx10, ?mvdx1, ?mvdx8
-0*660 <int_arith\+0x70> de ?3b ?65 ?a4 ? * cfadd64le mvdx6, ?mvdx11, ?mvdx4
-0*664 <int_arith\+0x74> 9e ?35 ?05 ?af ? * cfadd64ls mvdx0, ?mvdx5, ?mvdx15
-0*668 <int_arith\+0x78> 9e ?3e ?45 ?c3 ? * cfsub32ls mvfx4, ?mvfx14, ?mvfx3
-0*66c <int_arith\+0x7c> de ?32 ?75 ?c1 ? * cfsub32le mvfx7, ?mvfx2, ?mvfx1
-0*670 <int_arith\+0x80> 6e ?30 ?b5 ?c7 ? * cfsub32vs mvfx11, ?mvfx0, ?mvfx7
-0*674 <int_arith\+0x84> ee ?3c ?35 ?ca ? * cfsub32 mvfx3, ?mvfx12, ?mvfx10
-0*678 <int_arith\+0x88> 8e ?3d ?f5 ?c6 ? * cfsub32hi mvfx15, ?mvfx13, ?mvfx6
-0*67c <int_arith\+0x8c> 4e ?39 ?25 ?e0 ? * cfsub64mi mvdx2, ?mvdx9, ?mvdx0
-0*680 <int_arith\+0x90> ee ?39 ?a5 ?e4 ? * cfsub64 mvdx10, ?mvdx9, ?mvdx4
-0*684 <int_arith\+0x94> 3e ?3d ?85 ?e7 ? * cfsub64cc mvdx8, ?mvdx13, ?mvdx7
-0*688 <int_arith\+0x98> 1e ?36 ?c5 ?eb ? * cfsub64ne mvdx12, ?mvdx6, ?mvdx11
-0*68c <int_arith\+0x9c> 7e ?3e ?55 ?e3 ? * cfsub64vc mvdx5, ?mvdx14, ?mvdx3
-0*690 <int_arith\+0xa0> ae ?18 ?15 ?0f ? * cfmul32ge mvfx1, ?mvfx8, ?mvfx15
-0*694 <int_arith\+0xa4> 6e ?14 ?b5 ?02 ? * cfmul32vs mvfx11, ?mvfx4, ?mvfx2
-0*698 <int_arith\+0xa8> 0e ?1f ?55 ?0a ? * cfmul32eq mvfx5, ?mvfx15, ?mvfx10
-0*69c <int_arith\+0xac> 4e ?13 ?e5 ?08 ? * cfmul32mi mvfx14, ?mvfx3, ?mvfx8
-0*6a0 <int_arith\+0xb0> 7e ?11 ?25 ?0c ? * cfmul32vc mvfx2, ?mvfx1, ?mvfx12
-0*6a4 <int_arith\+0xb4> be ?17 ?05 ?25 ? * cfmul64lt mvdx0, ?mvdx7, ?mvdx5
-0*6a8 <int_arith\+0xb8> 3e ?1a ?c5 ?21 ? * cfmul64cc mvdx12, ?mvdx10, ?mvdx1
-0*6ac <int_arith\+0xbc> ee ?16 ?d5 ?2b ? * cfmul64 mvdx13, ?mvdx6, ?mvdx11
-0*6b0 <int_arith\+0xc0> 2e ?10 ?95 ?25 ? * cfmul64cs mvdx9, ?mvdx0, ?mvdx5
-0*6b4 <int_arith\+0xc4> ae ?14 ?95 ?2e ? * cfmul64ge mvdx9, ?mvdx4, ?mvdx14
-0*6b8 <int_arith\+0xc8> 8e ?17 ?d5 ?42 ? * cfmac32hi mvfx13, ?mvfx7, ?mvfx2
-0*6bc <int_arith\+0xcc> ce ?1b ?65 ?40 ? * cfmac32gt mvfx6, ?mvfx11, ?mvfx0
-0*6c0 <int_arith\+0xd0> 5e ?13 ?e5 ?4c ? * cfmac32pl mvfx14, ?mvfx3, ?mvfx12
-0*6c4 <int_arith\+0xd4> 1e ?1f ?85 ?4d ? * cfmac32ne mvfx8, ?mvfx15, ?mvfx13
-0*6c8 <int_arith\+0xd8> be ?12 ?45 ?49 ? * cfmac32lt mvfx4, ?mvfx2, ?mvfx9
-0*6cc <int_arith\+0xdc> 5e ?1a ?f5 ?69 ? * cfmsc32pl mvfx15, ?mvfx10, ?mvfx9
-0*6d0 <int_arith\+0xe0> ee ?18 ?35 ?6d ? * cfmsc32 mvfx3, ?mvfx8, ?mvfx13
-0*6d4 <int_arith\+0xe4> 2e ?1c ?15 ?66 ? * cfmsc32cs mvfx1, ?mvfx12, ?mvfx6
-0*6d8 <int_arith\+0xe8> 0e ?15 ?75 ?6e ? * cfmsc32eq mvfx7, ?mvfx5, ?mvfx14
-0*6dc <int_arith\+0xec> ce ?11 ?a5 ?68 ? * cfmsc32gt mvfx10, ?mvfx1, ?mvfx8
-# acc_arith:
-0*6e0 <acc_arith> de ?04 ?b6 ?02 ? * cfmadd32le mvax0, ?mvfx11, ?mvfx4, ?mvfx2
-0*6e4 <acc_arith\+0x4> 9e ?0f ?56 ?0a ? * cfmadd32ls mvax0, ?mvfx5, ?mvfx15, ?mvfx10
-0*6e8 <acc_arith\+0x8> 9e ?03 ?e6 ?08 ? * cfmadd32ls mvax0, ?mvfx14, ?mvfx3, ?mvfx8
-0*6ec <acc_arith\+0xc> de ?01 ?26 ?4c ? * cfmadd32le mvax2, ?mvfx2, ?mvfx1, ?mvfx12
-0*6f0 <acc_arith\+0x10> 6e ?07 ?06 ?25 ? * cfmadd32vs mvax1, ?mvfx0, ?mvfx7, ?mvfx5
-0*6f4 <acc_arith\+0x14> ee ?1a ?c6 ?41 ? * cfmsub32 mvax2, ?mvfx12, ?mvfx10, ?mvfx1
-0*6f8 <acc_arith\+0x18> 8e ?16 ?d6 ?6b ? * cfmsub32hi mvax3, ?mvfx13, ?mvfx6, ?mvfx11
-0*6fc <acc_arith\+0x1c> 4e ?10 ?96 ?05 ? * cfmsub32mi mvax0, ?mvfx9, ?mvfx0, ?mvfx5
-0*700 <acc_arith\+0x20> ee ?14 ?96 ?4e ? * cfmsub32 mvax2, ?mvfx9, ?mvfx4, ?mvfx14
-0*704 <acc_arith\+0x24> 3e ?17 ?d6 ?22 ? * cfmsub32cc mvax1, ?mvfx13, ?mvfx7, ?mvfx2
-0*708 <acc_arith\+0x28> 1e ?2b ?06 ?40 ? * cfmadda32ne mvax2, ?mvax0, ?mvfx11, ?mvfx0
-0*70c <acc_arith\+0x2c> 7e ?23 ?26 ?6c ? * cfmadda32vc mvax3, ?mvax2, ?mvfx3, ?mvfx12
-0*710 <acc_arith\+0x30> ae ?2f ?16 ?6d ? * cfmadda32ge mvax3, ?mvax1, ?mvfx15, ?mvfx13
-0*714 <acc_arith\+0x34> 6e ?22 ?26 ?69 ? * cfmadda32vs mvax3, ?mvax2, ?mvfx2, ?mvfx9
-0*718 <acc_arith\+0x38> 0e ?2a ?36 ?29 ? * cfmadda32eq mvax1, ?mvax3, ?mvfx10, ?mvfx9
-0*71c <acc_arith\+0x3c> 4e ?38 ?36 ?2d ? * cfmsuba32mi mvax1, ?mvax3, ?mvfx8, ?mvfx13
-0*720 <acc_arith\+0x40> 7e ?3c ?36 ?06 ? * cfmsuba32vc mvax0, ?mvax3, ?mvfx12, ?mvfx6
-0*724 <acc_arith\+0x44> be ?35 ?16 ?0e ? * cfmsuba32lt mvax0, ?mvax1, ?mvfx5, ?mvfx14
-0*728 <acc_arith\+0x48> 3e ?31 ?16 ?08 ? * cfmsuba32cc mvax0, ?mvax1, ?mvfx1, ?mvfx8
-0*72c <acc_arith\+0x4c> ee ?3b ?06 ?44 ? * cfmsuba32 mvax2, ?mvax0, ?mvfx11, ?mvfx4
diff --git a/gas/testsuite/gas/arm/maverick.s b/gas/testsuite/gas/arm/maverick.s
deleted file mode 100644
index e32d36b6a9b..00000000000
--- a/gas/testsuite/gas/arm/maverick.s
+++ /dev/null
@@ -1,470 +0,0 @@
- .text
- .align
-load_store:
- cfldrseq mvf5, [sp, #1020]
- cfldrsmi mvf14, [r11, #292]
- cfldrsvc mvf2, [r12, #-956]
- cfldrslt mvf0, [sl, #-1020]
- cfldrscc mvf12, [r1, #-156]
- cfldrs mvf13, [r9, #416]!
- cfldrscs mvf9, [r0, #-1020]!
- cfldrsls mvf4, [r1, #-156]!
- cfldrsle mvf7, [r9, #416]!
- cfldrsvs mvf11, [r0, #-1020]!
- cfldrscc mvf12, [r1], #-156
- cfldrs mvf13, [r9], #416
- cfldrscs mvf9, [r0], #-1020
- cfldrsls mvf4, [r1], #-156
- cfldrsle mvf7, [r9], #416
- cfldrdvs mvd11, [r0, #-1020]
- cfldrdcc mvd12, [r1, #-156]
- cfldrd mvd13, [r9, #416]
- cfldrdcs mvd9, [r0, #-1020]
- cfldrdls mvd4, [r1, #-156]
- cfldrdle mvd7, [r9, #416]!
- cfldrdvs mvd11, [r0, #-1020]!
- cfldrdcc mvd12, [r1, #-156]!
- cfldrd mvd13, [r9, #416]!
- cfldrdcs mvd9, [r0, #-1020]!
- cfldrdls mvd4, [r1], #-156
- cfldrdle mvd7, [r9], #416
- cfldrdvs mvd11, [r0], #-1020
- cfldrdcc mvd12, [r1], #-156
- cfldrd mvd13, [r9], #416
- cfldr32cs mvfx9, [r0, #-1020]
- cfldr32ls mvfx4, [r1, #-156]
- cfldr32le mvfx7, [r9, #416]
- cfldr32vs mvfx11, [r0, #-1020]
- cfldr32cc mvfx12, [r1, #-156]
- cfldr32 mvfx13, [r9, #416]!
- cfldr32cs mvfx9, [r0, #-1020]!
- cfldr32ls mvfx4, [r1, #-156]!
- cfldr32le mvfx7, [r9, #416]!
- cfldr32vs mvfx11, [r0, #-1020]!
- cfldr32cc mvfx12, [r1], #-156
- cfldr32 mvfx13, [r9], #416
- cfldr32cs mvfx9, [r0], #-1020
- cfldr32ls mvfx4, [r1], #-156
- cfldr32le mvfx7, [r9], #416
- cfldr64vs mvdx11, [r0, #-1020]
- cfldr64cc mvdx12, [r1, #-156]
- cfldr64 mvdx13, [r9, #416]
- cfldr64cs mvdx9, [r0, #-1020]
- cfldr64ls mvdx4, [r1, #-156]
- cfldr64le mvdx7, [r9, #416]!
- cfldr64vs mvdx11, [r0, #-1020]!
- cfldr64cc mvdx12, [r1, #-156]!
- cfldr64 mvdx13, [r9, #416]!
- cfldr64cs mvdx9, [r0, #-1020]!
- cfldr64ls mvdx4, [r1], #-156
- cfldr64le mvdx7, [r9], #416
- cfldr64vs mvdx11, [r0], #-1020
- cfldr64cc mvdx12, [r1], #-156
- cfldr64 mvdx13, [r9], #416
- cfstrscs mvf9, [r0, #-1020]
- cfstrsls mvf4, [r1, #-156]
- cfstrsle mvf7, [r9, #416]
- cfstrsvs mvf11, [r0, #-1020]
- cfstrscc mvf12, [r1, #-156]
- cfstrs mvf13, [r9, #416]!
- cfstrscs mvf9, [r0, #-1020]!
- cfstrsls mvf4, [r1, #-156]!
- cfstrsle mvf7, [r9, #416]!
- cfstrsvs mvf11, [r0, #-1020]!
- cfstrscc mvf12, [r1], #-156
- cfstrs mvf13, [r9], #416
- cfstrscs mvf9, [r0], #-1020
- cfstrsls mvf4, [r1], #-156
- cfstrsle mvf7, [r9], #416
- cfstrdvs mvd11, [r0, #-1020]
- cfstrdcc mvd12, [r1, #-156]
- cfstrd mvd13, [r9, #416]
- cfstrdcs mvd9, [r0, #-1020]
- cfstrdls mvd4, [r1, #-156]
- cfstrdle mvd7, [r9, #416]!
- cfstrdvs mvd11, [r0, #-1020]!
- cfstrdcc mvd12, [r1, #-156]!
- cfstrd mvd13, [r9, #416]!
- cfstrdcs mvd9, [r0, #-1020]!
- cfstrdls mvd4, [r1], #-156
- cfstrdle mvd7, [r9], #416
- cfstrdvs mvd11, [r0], #-1020
- cfstrdcc mvd12, [r1], #-156
- cfstrd mvd13, [r9], #416
- cfstr32cs mvfx9, [r0, #-1020]
- cfstr32ls mvfx4, [r1, #-156]
- cfstr32le mvfx7, [r9, #416]
- cfstr32vs mvfx11, [r0, #-1020]
- cfstr32cc mvfx12, [r1, #-156]
- cfstr32 mvfx13, [r9, #416]!
- cfstr32cs mvfx9, [r0, #-1020]!
- cfstr32ls mvfx4, [r1, #-156]!
- cfstr32le mvfx7, [r9, #416]!
- cfstr32vs mvfx11, [r0, #-1020]!
- cfstr32cc mvfx12, [r1], #-156
- cfstr32 mvfx13, [r9], #416
- cfstr32cs mvfx9, [r0], #-1020
- cfstr32ls mvfx4, [r1], #-156
- cfstr32le mvfx7, [r9], #416
- cfstr64vs mvdx11, [r0, #-1020]
- cfstr64cc mvdx12, [r1, #-156]
- cfstr64 mvdx13, [r9, #416]
- cfstr64cs mvdx9, [r0, #-1020]
- cfstr64ls mvdx4, [r1, #-156]
- cfstr64le mvdx7, [r9, #416]!
- cfstr64vs mvdx11, [r0, #-1020]!
- cfstr64cc mvdx12, [r1, #-156]!
- cfstr64 mvdx13, [r9, #416]!
- cfstr64cs mvdx9, [r0, #-1020]!
- cfstr64ls mvdx4, [r1], #-156
- cfstr64le mvdx7, [r9], #416
- cfstr64vs mvdx11, [r0], #-1020
- cfstr64cc mvdx12, [r1], #-156
- cfstr64 mvdx13, [r9], #416
-move:
- cfmvsrcs mvf9, r0
- cfmvsrpl mvf15, r7
- cfmvsrls mvf4, r1
- cfmvsrcc mvf8, r2
- cfmvsrvc mvf2, r12
- cfmvrsgt r9, mvf11
- cfmvrseq sl, mvf5
- cfmvrsal r4, mvf12
- cfmvrsge fp, mvf8
- cfmvrs r5, mvf6
- cfmvdlrlt mvd4, r9
- cfmvdlrls mvd0, r10
- cfmvdlr mvd10, r4
- cfmvdlrmi mvd14, r11
- cfmvdlrhi mvd13, r5
- cfmvrdlcs r12, mvd12
- cfmvrdlvs r3, mvd0
- cfmvrdlvc r13, mvd14
- cfmvrdlcc r14, mvd10
- cfmvrdlne r8, mvd15
- cfmvdhrle mvd6, ip
- cfmvdhrmi mvd2, r3
- cfmvdhreq mvd5, sp
- cfmvdhrge mvd9, lr
- cfmvdhral mvd3, r8
- cfmvrdhle r5, mvd2
- cfmvrdhne r6, mvd6
- cfmvrdhlt r0, mvd7
- cfmvrdhpl r7, mvd3
- cfmvrdhgt r1, mvd1
- cfmv64lrhi mvdx15, r5
- cfmv64lrvs mvdx11, r6
- cfmv64lrcs mvdx9, r0
- cfmv64lrpl mvdx15, r7
- cfmv64lrls mvdx4, r1
- cfmvr64lcc r8, mvdx13
- cfmvr64lvc pc, mvdx1
- cfmvr64lgt r9, mvdx11
- cfmvr64leq sl, mvdx5
- cfmvr64lal r4, mvdx12
- cfmv64hrge mvdx1, r8
- cfmv64hr mvdx13, r15
- cfmv64hrlt mvdx4, r9
- cfmv64hrls mvdx0, r10
- cfmv64hr mvdx10, r4
- cfmvr64hmi r1, mvdx3
- cfmvr64hhi r2, mvdx7
- cfmvr64hcs r12, mvdx12
- cfmvr64hvs r3, mvdx0
- cfmvr64hvc r13, mvdx14
- cfmval32cc mvax0, mvfx10
- cfmval32ne mvax1, mvfx15
- cfmval32le mvax0, mvfx11
- cfmval32mi mvax0, mvfx9
- cfmval32eq mvax1, mvfx15
- cfmv32alge mvfx9, mvax0
- cfmv32alal mvfx3, mvax1
- cfmv32alle mvfx7, mvax0
- cfmv32alne mvfx12, mvax0
- cfmv32allt mvfx0, mvax1
- cfmvam32pl mvax2, mvfx3
- cfmvam32gt mvax1, mvfx1
- cfmvam32hi mvax3, mvfx13
- cfmvam32vs mvax3, mvfx4
- cfmvam32cs mvax1, mvfx0
- cfmv32ampl mvfx15, mvax2
- cfmv32amls mvfx4, mvax1
- cfmv32amcc mvfx8, mvax3
- cfmv32amvc mvfx2, mvax3
- cfmv32amgt mvfx6, mvax1
- cfmvah32eq mvax1, mvfx5
- cfmvah32al mvax2, mvfx12
- cfmvah32ge mvax3, mvfx8
- cfmvah32 mvax2, mvfx6
- cfmvah32lt mvax2, mvfx2
- cfmv32ahls mvfx0, mvax1
- cfmv32ah mvfx10, mvax2
- cfmv32ahmi mvfx14, mvax3
- cfmv32ahhi mvfx13, mvax2
- cfmv32ahcs mvfx1, mvax2
- cfmva32vs mvax1, mvfx0
- cfmva32vc mvax3, mvfx14
- cfmva32cc mvax0, mvfx10
- cfmva32ne mvax1, mvfx15
- cfmva32le mvax0, mvfx11
- cfmv32ami mvfx2, mvax1
- cfmv32aeq mvfx5, mvax3
- cfmv32age mvfx9, mvax0
- cfmv32aal mvfx3, mvax1
- cfmv32ale mvfx7, mvax0
- cfmva64ne mvax2, mvdx6
- cfmva64lt mvax0, mvdx7
- cfmva64pl mvax2, mvdx3
- cfmva64gt mvax1, mvdx1
- cfmva64hi mvax3, mvdx13
- cfmv64avs mvdx11, mvax2
- cfmv64acs mvdx9, mvax0
- cfmv64apl mvdx15, mvax2
- cfmv64als mvdx4, mvax1
- cfmv64acc mvdx8, mvax3
- cfmvsc32vc dspsc, mvdx1
- cfmvsc32gt dspsc, mvdx11
- cfmvsc32eq dspsc, mvdx5
- cfmvsc32al dspsc, mvdx12
- cfmvsc32ge dspsc, mvdx8
- cfmv32sc mvdx13, dspsc
- cfmv32sclt mvdx4, dspsc
- cfmv32scls mvdx0, dspsc
- cfmv32sc mvdx10, dspsc
- cfmv32scmi mvdx14, dspsc
- cfcpyshi mvf13, mvf7
- cfcpyscs mvf1, mvf12
- cfcpysvs mvf11, mvf0
- cfcpysvc mvf5, mvf14
- cfcpyscc mvf12, mvf10
- cfcpydne mvd8, mvd15
- cfcpydle mvd6, mvd11
- cfcpydmi mvd2, mvd9
- cfcpydeq mvd5, mvd15
- cfcpydge mvd9, mvd4
-conv:
- cfcvtsdal mvd3, mvf8
- cfcvtsdle mvd7, mvf2
- cfcvtsdne mvd12, mvf6
- cfcvtsdlt mvd0, mvf7
- cfcvtsdpl mvd14, mvf3
- cfcvtdsgt mvf10, mvd1
- cfcvtdshi mvf15, mvd13
- cfcvtdsvs mvf11, mvd4
- cfcvtdscs mvf9, mvd0
- cfcvtdspl mvf15, mvd10
- cfcvt32sls mvf4, mvfx14
- cfcvt32scc mvf8, mvfx13
- cfcvt32svc mvf2, mvfx1
- cfcvt32sgt mvf6, mvfx11
- cfcvt32seq mvf7, mvfx5
- cfcvt32dal mvd3, mvfx12
- cfcvt32dge mvd1, mvfx8
- cfcvt32d mvd13, mvfx6
- cfcvt32dlt mvd4, mvfx2
- cfcvt32dls mvd0, mvfx5
- cfcvt64s mvf10, mvdx9
- cfcvt64smi mvf14, mvdx3
- cfcvt64shi mvf13, mvdx7
- cfcvt64scs mvf1, mvdx12
- cfcvt64svs mvf11, mvdx0
- cfcvt64dvc mvd5, mvdx14
- cfcvt64dcc mvd12, mvdx10
- cfcvt64dne mvd8, mvdx15
- cfcvt64dle mvd6, mvdx11
- cfcvt64dmi mvd2, mvdx9
- cfcvts32eq mvfx5, mvf15
- cfcvts32ge mvfx9, mvf4
- cfcvts32al mvfx3, mvf8
- cfcvts32le mvfx7, mvf2
- cfcvts32ne mvfx12, mvf6
- cfcvtd32lt mvfx0, mvd7
- cfcvtd32pl mvfx14, mvd3
- cfcvtd32gt mvfx10, mvd1
- cfcvtd32hi mvfx15, mvd13
- cfcvtd32vs mvfx11, mvd4
- cftruncs32cs mvfx9, mvf0
- cftruncs32pl mvfx15, mvf10
- cftruncs32ls mvfx4, mvf14
- cftruncs32cc mvfx8, mvf13
- cftruncs32vc mvfx2, mvf1
- cftruncd32gt mvfx6, mvd11
- cftruncd32eq mvfx7, mvd5
- cftruncd32al mvfx3, mvd12
- cftruncd32ge mvfx1, mvd8
- cftruncd32 mvfx13, mvd6
-shift:
- cfrshl32lt mvfx4, mvfx2, r3
- cfrshl32pl mvfx15, mvfx10, r4
- cfrshl32al mvfx3, mvfx8, r2
- cfrshl32cs mvfx1, mvfx12, r9
- cfrshl32eq mvfx7, mvfx5, r7
- cfrshl64gt mvdx10, mvdx1, r8
- cfrshl64le mvdx6, mvdx11, r6
- cfrshl64ls mvdx0, mvdx5, sp
- cfrshl64ls mvdx4, mvdx14, r11
- cfrshl64le mvdx7, mvdx2, r12
- cfsh32vs mvfx11, mvfx0, #-1
- cfsh32al mvfx3, mvfx12, #24
- cfsh32hi mvfx15, mvfx13, #33
- cfsh32mi mvfx2, mvfx9, #0
- cfsh32 mvfx10, mvfx9, #32
- cfsh64cc mvdx8, mvdx13, #-31
- cfsh64ne mvdx12, mvdx6, #1
- cfsh64vc mvdx5, mvdx14, #-32
- cfsh64ge mvdx1, mvdx8, #-27
- cfsh64vs mvdx11, mvdx4, #-5
-comp:
- cfcmpseq r10, mvf15, mvf10
- cfcmpsmi r1, mvf3, mvf8
- cfcmpsvc pc, mvf1, mvf12
- cfcmpslt r0, mvf7, mvf5
- cfcmpscc r14, mvf10, mvf1
- cfcmpd r5, mvd6, mvd11
- cfcmpdcs r3, mvd0, mvd5
- cfcmpdge r4, mvd4, mvd14
- cfcmpdhi r2, mvd7, mvd2
- cfcmpdgt r9, mvd11, mvd0
- cfcmp32pl r7, mvfx3, mvfx12
- cfcmp32ne r8, mvfx15, mvfx13
- cfcmp32lt r6, mvfx2, mvfx9
- cfcmp32pl sp, mvfx10, mvfx9
- cfcmp32al r11, mvfx8, mvfx13
- cfcmp64cs r12, mvdx12, mvdx6
- cfcmp64eq sl, mvdx5, mvdx14
- cfcmp64gt r1, mvdx1, mvdx8
- cfcmp64le r15, mvdx11, mvdx4
- cfcmp64ls r0, mvdx5, mvdx15
-fp_arith:
- cfabssls mvf4, mvf14
- cfabsscc mvf8, mvf13
- cfabssvc mvf2, mvf1
- cfabssgt mvf6, mvf11
- cfabsseq mvf7, mvf5
- cfabsdal mvd3, mvd12
- cfabsdge mvd1, mvd8
- cfabsd mvd13, mvd6
- cfabsdlt mvd4, mvd2
- cfabsdls mvd0, mvd5
- cfnegs mvf10, mvf9
- cfnegsmi mvf14, mvf3
- cfnegshi mvf13, mvf7
- cfnegscs mvf1, mvf12
- cfnegsvs mvf11, mvf0
- cfnegdvc mvd5, mvd14
- cfnegdcc mvd12, mvd10
- cfnegdne mvd8, mvd15
- cfnegdle mvd6, mvd11
- cfnegdmi mvd2, mvd9
- cfaddseq mvf5, mvf15, mvf10
- cfaddsmi mvf14, mvf3, mvf8
- cfaddsvc mvf2, mvf1, mvf12
- cfaddslt mvf0, mvf7, mvf5
- cfaddscc mvf12, mvf10, mvf1
- cfaddd mvd13, mvd6, mvd11
- cfadddcs mvd9, mvd0, mvd5
- cfadddge mvd9, mvd4, mvd14
- cfadddhi mvd13, mvd7, mvd2
- cfadddgt mvd6, mvd11, mvd0
- cfsubspl mvf14, mvf3, mvf12
- cfsubsne mvf8, mvf15, mvf13
- cfsubslt mvf4, mvf2, mvf9
- cfsubspl mvf15, mvf10, mvf9
- cfsubsal mvf3, mvf8, mvf13
- cfsubdcs mvd1, mvd12, mvd6
- cfsubdeq mvd7, mvd5, mvd14
- cfsubdgt mvd10, mvd1, mvd8
- cfsubdle mvd6, mvd11, mvd4
- cfsubdls mvd0, mvd5, mvd15
- cfmulsls mvf4, mvf14, mvf3
- cfmulsle mvf7, mvf2, mvf1
- cfmulsvs mvf11, mvf0, mvf7
- cfmulsal mvf3, mvf12, mvf10
- cfmulshi mvf15, mvf13, mvf6
- cfmuldmi mvd2, mvd9, mvd0
- cfmuld mvd10, mvd9, mvd4
- cfmuldcc mvd8, mvd13, mvd7
- cfmuldne mvd12, mvd6, mvd11
- cfmuldvc mvd5, mvd14, mvd3
-int_arith:
- cfabs32ge mvfx1, mvfx8
- cfabs32 mvfx13, mvfx6
- cfabs32lt mvfx4, mvfx2
- cfabs32ls mvfx0, mvfx5
- cfabs32 mvfx10, mvfx9
- cfabs64mi mvdx14, mvdx3
- cfabs64hi mvdx13, mvdx7
- cfabs64cs mvdx1, mvdx12
- cfabs64vs mvdx11, mvdx0
- cfabs64vc mvdx5, mvdx14
- cfneg32cc mvfx12, mvfx10
- cfneg32ne mvfx8, mvfx15
- cfneg32le mvfx6, mvfx11
- cfneg32mi mvfx2, mvfx9
- cfneg32eq mvfx5, mvfx15
- cfneg64ge mvdx9, mvdx4
- cfneg64al mvdx3, mvdx8
- cfneg64le mvdx7, mvdx2
- cfneg64ne mvdx12, mvdx6
- cfneg64lt mvdx0, mvdx7
- cfadd32pl mvfx14, mvfx3, mvfx12
- cfadd32ne mvfx8, mvfx15, mvfx13
- cfadd32lt mvfx4, mvfx2, mvfx9
- cfadd32pl mvfx15, mvfx10, mvfx9
- cfadd32al mvfx3, mvfx8, mvfx13
- cfadd64cs mvdx1, mvdx12, mvdx6
- cfadd64eq mvdx7, mvdx5, mvdx14
- cfadd64gt mvdx10, mvdx1, mvdx8
- cfadd64le mvdx6, mvdx11, mvdx4
- cfadd64ls mvdx0, mvdx5, mvdx15
- cfsub32ls mvfx4, mvfx14, mvfx3
- cfsub32le mvfx7, mvfx2, mvfx1
- cfsub32vs mvfx11, mvfx0, mvfx7
- cfsub32al mvfx3, mvfx12, mvfx10
- cfsub32hi mvfx15, mvfx13, mvfx6
- cfsub64mi mvdx2, mvdx9, mvdx0
- cfsub64 mvdx10, mvdx9, mvdx4
- cfsub64cc mvdx8, mvdx13, mvdx7
- cfsub64ne mvdx12, mvdx6, mvdx11
- cfsub64vc mvdx5, mvdx14, mvdx3
- cfmul32ge mvfx1, mvfx8, mvfx15
- cfmul32vs mvfx11, mvfx4, mvfx2
- cfmul32eq mvfx5, mvfx15, mvfx10
- cfmul32mi mvfx14, mvfx3, mvfx8
- cfmul32vc mvfx2, mvfx1, mvfx12
- cfmul64lt mvdx0, mvdx7, mvdx5
- cfmul64cc mvdx12, mvdx10, mvdx1
- cfmul64 mvdx13, mvdx6, mvdx11
- cfmul64cs mvdx9, mvdx0, mvdx5
- cfmul64ge mvdx9, mvdx4, mvdx14
- cfmac32hi mvfx13, mvfx7, mvfx2
- cfmac32gt mvfx6, mvfx11, mvfx0
- cfmac32pl mvfx14, mvfx3, mvfx12
- cfmac32ne mvfx8, mvfx15, mvfx13
- cfmac32lt mvfx4, mvfx2, mvfx9
- cfmsc32pl mvfx15, mvfx10, mvfx9
- cfmsc32al mvfx3, mvfx8, mvfx13
- cfmsc32cs mvfx1, mvfx12, mvfx6
- cfmsc32eq mvfx7, mvfx5, mvfx14
- cfmsc32gt mvfx10, mvfx1, mvfx8
-acc_arith:
- cfmadd32le mvax0, mvfx11, mvfx4, mvfx2
- cfmadd32ls mvax0, mvfx5, mvfx15, mvfx10
- cfmadd32ls mvax0, mvfx14, mvfx3, mvfx8
- cfmadd32le mvax2, mvfx2, mvfx1, mvfx12
- cfmadd32vs mvax1, mvfx0, mvfx7, mvfx5
- cfmsub32al mvax2, mvfx12, mvfx10, mvfx1
- cfmsub32hi mvax3, mvfx13, mvfx6, mvfx11
- cfmsub32mi mvax0, mvfx9, mvfx0, mvfx5
- cfmsub32 mvax2, mvfx9, mvfx4, mvfx14
- cfmsub32cc mvax1, mvfx13, mvfx7, mvfx2
- cfmadda32ne mvax2, mvax0, mvfx11, mvfx0
- cfmadda32vc mvax3, mvax2, mvfx3, mvfx12
- cfmadda32ge mvax3, mvax1, mvfx15, mvfx13
- cfmadda32vs mvax3, mvax2, mvfx2, mvfx9
- cfmadda32eq mvax1, mvax3, mvfx10, mvfx9
- cfmsuba32mi mvax1, mvax3, mvfx8, mvfx13
- cfmsuba32vc mvax0, mvax3, mvfx12, mvfx6
- cfmsuba32lt mvax0, mvax1, mvfx5, mvfx14
- cfmsuba32cc mvax0, mvax1, mvfx1, mvfx8
- cfmsuba32 mvax2, mvax0, mvfx11, mvfx4
diff --git a/gas/testsuite/gas/arm/note-march-ep9312.d b/gas/testsuite/gas/arm/note-march-ep9312.d
deleted file mode 100644
index dd728216300..00000000000
--- a/gas/testsuite/gas/arm/note-march-ep9312.d
+++ /dev/null
@@ -1,13 +0,0 @@
-# name: ep9312 note with -mcpu=ep9312 -mfpu=maverick
-# source: note-march-ep9312.s RUN_OBJCOPY
-# as: -mcpu=ep9312 -mfpu=maverick
-# objcopy_objects: -R .ARM.attributes
-# ld: -e 0x10000
-# objcopy_linked_file:
-# readelf: -p .note.gnu.arm.ident
-# This test is only valid on EABI based ports.
-# target: *-*-*eabi* *-*-nacl*
-
-String dump of section '.note.gnu.arm.ident':
- \[\s*[0-9a-f]+\] arch:
- \[\s*[0-9a-f]+\] ep9312
diff --git a/gas/testsuite/gas/arm/note-march-ep9312.s b/gas/testsuite/gas/arm/note-march-ep9312.s
deleted file mode 100644
index b542eba2e8a..00000000000
--- a/gas/testsuite/gas/arm/note-march-ep9312.s
+++ /dev/null
@@ -1,7 +0,0 @@
-.section .note.gnu.arm.ident
-.word 8
-.word 6
-.word 2
-.string "arch: "
-.align 2
-.string "ep9312"
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 2/6] arm: remove Maverick support from the assembler.
2024-05-02 11:44 [PATCH 0/6] [RFD] arm: Remove support for the Cirrus Maverick co-processor Richard Earnshaw
2024-05-02 11:44 ` [PATCH 1/6] arm: remove tests for Maverick FPU extensions Richard Earnshaw
@ 2024-05-02 11:44 ` Richard Earnshaw
2024-05-02 11:44 ` [PATCH 3/6] arm: binutils: drop Maverick support Richard Earnshaw
` (3 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Richard Earnshaw @ 2024-05-02 11:44 UTC (permalink / raw)
To: binutils; +Cc: Richard Earnshaw
[-- Attachment #1: Type: text/plain, Size: 326 bytes --]
Delete all the Maverick instructions and register handling from the
assembler. We continue to recognize -mcpu=ep9312, but treat it as an
alias for arm920t. We no-longer recognize -mfpu=maverick.
---
gas/config/tc-arm.c | 183 +-------------------------------------------
1 file changed, 4 insertions(+), 179 deletions(-)
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 0002-arm-remove-Maverick-support-from-the-assembler.patch --]
[-- Type: text/x-patch; name="0002-arm-remove-Maverick-support-from-the-assembler.patch", Size: 12474 bytes --]
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 2aec97db7dc..343b2e77d7c 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -189,9 +189,6 @@ static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED = FPU_ARCH_VFP_V3;
static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED = FPU_ARCH_NEON_V1;
static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
-#ifdef OBJ_ELF
-static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
-#endif
static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
#ifdef CPU_DEFAULT
@@ -314,8 +311,6 @@ static const arm_feature_set arm_cext_iwmmxt =
ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT);
static const arm_feature_set arm_cext_xscale =
ARM_FEATURE_COPROC (ARM_CEXT_XSCALE);
-static const arm_feature_set arm_cext_maverick =
- ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK);
static const arm_feature_set fpu_fpa_ext_v1 =
ARM_FEATURE_COPROC (FPU_FPA_EXT_V1);
static const arm_feature_set fpu_fpa_ext_v2 =
@@ -721,12 +716,6 @@ const char * const reg_expected_msgs[] =
[REG_TYPE_NSDQ] = N_("VFP single, double or Neon quad precision register"
" expected"),
[REG_TYPE_VFC] = N_("VFP system register expected"),
- [REG_TYPE_MVF] = N_("Maverick MVF register expected"),
- [REG_TYPE_MVD] = N_("Maverick MVD register expected"),
- [REG_TYPE_MVFX] = N_("Maverick MVFX register expected"),
- [REG_TYPE_MVDX] = N_("Maverick MVDX register expected"),
- [REG_TYPE_MVAX] = N_("Maverick MVAX register expected"),
- [REG_TYPE_DSPSC] = N_("Maverick DSPSC register expected"),
[REG_TYPE_MMXWR] = N_("iWMMXt data register expected"),
[REG_TYPE_MMXWC] = N_("iWMMXt control register expected"),
[REG_TYPE_MMXWCG] = N_("iWMMXt scalar register expected"),
@@ -7167,12 +7156,6 @@ enum operand_parse_code
OP_RNSDQ, /* Neon single, double or quad precision register */
OP_RNSC, /* Neon scalar D[X] */
OP_RVC, /* VFP control register */
- OP_RMF, /* Maverick F register */
- OP_RMD, /* Maverick D register */
- OP_RMFX, /* Maverick FX register */
- OP_RMDX, /* Maverick DX register */
- OP_RMAX, /* Maverick AX register */
- OP_RMDS, /* Maverick DSPSC register */
OP_RIWR, /* iWMMXt wR register */
OP_RIWC, /* iWMMXt wC register */
OP_RIWG, /* iWMMXt wCG register */
@@ -7543,12 +7526,6 @@ parse_operands (char *str, const unsigned int *pattern, bool thumb)
else
goto failure;
break;
- case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
- case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
- case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
- case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
- case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
- case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
@@ -11284,57 +11261,6 @@ do_iwmmxt_wrwrwr_or_imm5 (void)
}
}
\f
-/* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
- operations first, then control, shift, and load/store. */
-
-/* Insns like "foo X,Y,Z". */
-
-static void
-do_mav_triple (void)
-{
- inst.instruction |= inst.operands[0].reg << 16;
- inst.instruction |= inst.operands[1].reg;
- inst.instruction |= inst.operands[2].reg << 12;
-}
-
-/* Insns like "foo W,X,Y,Z".
- where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
-
-static void
-do_mav_quad (void)
-{
- inst.instruction |= inst.operands[0].reg << 5;
- inst.instruction |= inst.operands[1].reg << 12;
- inst.instruction |= inst.operands[2].reg << 16;
- inst.instruction |= inst.operands[3].reg;
-}
-
-/* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
-static void
-do_mav_dspsc (void)
-{
- inst.instruction |= inst.operands[1].reg << 12;
-}
-
-/* Maverick shift immediate instructions.
- cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
- cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
-
-static void
-do_mav_shift (void)
-{
- int imm = inst.operands[2].imm;
-
- inst.instruction |= inst.operands[0].reg << 12;
- inst.instruction |= inst.operands[1].reg << 16;
-
- /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
- Bits 5-7 of the insn should have bits 4-6 of the immediate.
- Bit 4 should be 0. */
- imm = (imm & 0xf) | ((imm & 0x70) << 1);
-
- inst.instruction |= imm;
-}
\f
/* XScale instructions. Also sorted arithmetic before move. */
@@ -24000,18 +23926,6 @@ static const struct reg_entry reg_names[] =
REGDEF(fpcxtns,14,VFC), REGDEF(FPCXTNS,14,VFC),
REGDEF(fpcxts,15,VFC), REGDEF(FPCXTS,15,VFC),
- /* Maverick DSP coprocessor registers. */
- REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
- REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
-
- REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
- REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
- REGDEF(dspsc,0,DSPSC),
-
- REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
- REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
- REGDEF(DSPSC,0,DSPSC),
-
/* iWMMXt data registers - p0, c0-15. */
REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
@@ -26315,86 +26229,6 @@ static const struct asm_opcode insns[] =
cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
-#undef ARM_VARIANT
-#define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
-
- cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
- cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
- cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
- cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
- cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
- cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
- cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
- cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
- cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd),
- cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn),
- cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd),
- cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn),
- cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd),
- cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn),
- cCE("cfmv64lr",e000510, 2, (RMDX, RR), rn_rd),
- cCE("cfmvr64l",e100510, 2, (RR, RMDX), rd_rn),
- cCE("cfmv64hr",e000530, 2, (RMDX, RR), rn_rd),
- cCE("cfmvr64h",e100530, 2, (RR, RMDX), rd_rn),
- cCE("cfmval32",e200440, 2, (RMAX, RMFX), rd_rn),
- cCE("cfmv32al",e100440, 2, (RMFX, RMAX), rd_rn),
- cCE("cfmvam32",e200460, 2, (RMAX, RMFX), rd_rn),
- cCE("cfmv32am",e100460, 2, (RMFX, RMAX), rd_rn),
- cCE("cfmvah32",e200480, 2, (RMAX, RMFX), rd_rn),
- cCE("cfmv32ah",e100480, 2, (RMFX, RMAX), rd_rn),
- cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn),
- cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn),
- cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn),
- cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn),
- cCE("cfmvsc32",e2004e0, 2, (RMDS, RMDX), mav_dspsc),
- cCE("cfmv32sc",e1004e0, 2, (RMDX, RMDS), rd),
- cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn),
- cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn),
- cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn),
- cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn),
- cCE("cfcvt32s",e000480, 2, (RMF, RMFX), rd_rn),
- cCE("cfcvt32d",e0004a0, 2, (RMD, RMFX), rd_rn),
- cCE("cfcvt64s",e0004c0, 2, (RMF, RMDX), rd_rn),
- cCE("cfcvt64d",e0004e0, 2, (RMD, RMDX), rd_rn),
- cCE("cfcvts32",e100580, 2, (RMFX, RMF), rd_rn),
- cCE("cfcvtd32",e1005a0, 2, (RMFX, RMD), rd_rn),
- cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn),
- cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn),
- cCE("cfrshl32",e000550, 3, (RMFX, RMFX, RR), mav_triple),
- cCE("cfrshl64",e000570, 3, (RMDX, RMDX, RR), mav_triple),
- cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift),
- cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift),
- cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm),
- cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
- cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
- cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
- cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn),
- cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn),
- cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn),
- cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn),
- cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
- cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
- cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
- cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
- cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
- cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
- cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn),
- cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn),
- cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn),
- cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn),
- cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
- cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
- cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
- cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
- cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
- cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
- cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
- cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
- cCE("cfmadd32",e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
- cCE("cfmsub32",e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
- cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
- cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
-
/* ARMv8.5-A instructions. */
#undef ARM_VARIANT
#define ARM_VARIANT & arm_ext_sb
@@ -31037,10 +30871,6 @@ md_begin (void)
flags |= F_VFP_FLOAT;
#if defined OBJ_ELF
- if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
- flags |= EF_ARM_MAVERICK_FLOAT;
- break;
-
case EF_ARM_EABI_VER4:
case EF_ARM_EABI_VER5:
/* No additional flags to set. */
@@ -31078,8 +30908,6 @@ md_begin (void)
mach = bfd_mach_arm_iWMMXt;
else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
mach = bfd_mach_arm_XScale;
- else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
- mach = bfd_mach_arm_ep9312;
else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
mach = bfd_mach_arm_5TE;
else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
@@ -31797,10 +31625,10 @@ static const struct arm_cpu_option_table arm_cpus[] =
ARM_ARCH_NONE,
FPU_ARCH_VFP_V2),
- /* Maverick. */
- ARM_CPU_OPT ("ep9312", "ARM920T",
- ARM_FEATURE_LOW (ARM_AEXT_V4T, ARM_CEXT_MAVERICK),
- ARM_ARCH_NONE, FPU_ARCH_MAVERICK),
+ /* Maverick extensions are no-longer supported, but we can still
+ recognize the CPU name and treat it like an Arm920T. */
+ ARM_CPU_OPT ("ep9312", "ARM920T", ARM_ARCH_V4T,
+ ARM_ARCH_NONE, FPU_ARCH_FPA),
/* Marvell processors. */
ARM_CPU_OPT ("marvell-pj4", NULL, ARM_ARCH_V7A,
@@ -32243,8 +32071,6 @@ static const struct arm_option_extension_value_table arm_extensions[] =
ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT), ARM_ARCH_NONE),
ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2),
ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2), ARM_ARCH_NONE),
- ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), ARM_ARCH_NONE),
ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP),
ARM_FEATURE_CORE_LOW (ARM_EXT_MP),
ARM_FEATURE_CORE_LOW (ARM_EXT_V7A),
@@ -32322,7 +32148,6 @@ static const struct arm_option_fpu_value_table arm_fpus[] =
{"arm1020e", FPU_ARCH_VFP_V2},
{"arm1136jfs", FPU_ARCH_VFP_V2}, /* Undocumented, use arm1136jf-s. */
{"arm1136jf-s", FPU_ARCH_VFP_V2},
- {"maverick", FPU_ARCH_MAVERICK},
{"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
{"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
{"neon-fp16", FPU_ARCH_NEON_FP16},
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 3/6] arm: binutils: drop Maverick support.
2024-05-02 11:44 [PATCH 0/6] [RFD] arm: Remove support for the Cirrus Maverick co-processor Richard Earnshaw
2024-05-02 11:44 ` [PATCH 1/6] arm: remove tests for Maverick FPU extensions Richard Earnshaw
2024-05-02 11:44 ` [PATCH 2/6] arm: remove Maverick support from the assembler Richard Earnshaw
@ 2024-05-02 11:44 ` Richard Earnshaw
2024-05-02 11:45 ` [PATCH 4/6] arm: opcodes: remove Maverick disassembly Richard Earnshaw
` (2 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Richard Earnshaw @ 2024-05-02 11:44 UTC (permalink / raw)
To: binutils; +Cc: Richard Earnshaw
[-- Attachment #1: Type: text/plain, Size: 122 bytes --]
Remove the decoding of the Maverick flag from readelf.
---
binutils/readelf.c | 4 ----
1 file changed, 4 deletions(-)
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 0003-arm-binutils-drop-Maverick-support.patch --]
[-- Type: text/x-patch; name="0003-arm-binutils-drop-Maverick-support.patch", Size: 423 bytes --]
diff --git a/binutils/readelf.c b/binutils/readelf.c
index f8305b4715b..bb3dde017e7 100644
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -3583,10 +3583,6 @@ decode_ARM_machine_flags (char *out, unsigned e_flags)
out = stpcpy (out, ", VFP");
break;
- case EF_ARM_MAVERICK_FLOAT:
- out = stpcpy (out, ", Maverick FP");
- break;
-
default:
unknown = true;
break;
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 4/6] arm: opcodes: remove Maverick disassembly.
2024-05-02 11:44 [PATCH 0/6] [RFD] arm: Remove support for the Cirrus Maverick co-processor Richard Earnshaw
` (2 preceding siblings ...)
2024-05-02 11:44 ` [PATCH 3/6] arm: binutils: drop Maverick support Richard Earnshaw
@ 2024-05-02 11:45 ` Richard Earnshaw
2024-05-02 11:45 ` [PATCH 5/6] arm: remove Maverick support from BFD Richard Earnshaw
2024-05-02 11:45 ` [PATCH 6/6] arm: update documentation for removal of the Maverick extension Richard Earnshaw
5 siblings, 0 replies; 7+ messages in thread
From: Richard Earnshaw @ 2024-05-02 11:45 UTC (permalink / raw)
To: binutils; +Cc: Richard Earnshaw
[-- Attachment #1: Type: text/plain, Size: 635 bytes --]
Remove the patterns to match Maverick co-processor instructions from
the disassembly tables.
This required fixing a couple of tests in the assembler testsuite
where we, probably incorrectly, disassembled generic co-processor
instructions as a Maverick instruction (it particularly made no sense
to do this for Armv6t2 in Thumb state).
---
.../gas/arm/copro-arm_v2plus-arm_v2.d | 8 +-
.../arm/copro-thumb_v6t2plus-thumb_v6t2-1.d | 8 +-
include/opcode/arm.h | 8 +-
opcodes/arm-dis.c | 179 +-----------------
4 files changed, 12 insertions(+), 191 deletions(-)
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 0004-arm-opcodes-remove-Maverick-disassembly.patch --]
[-- Type: text/x-patch; name="0004-arm-opcodes-remove-Maverick-disassembly.patch", Size: 17116 bytes --]
diff --git a/gas/testsuite/gas/arm/copro-arm_v2plus-arm_v2.d b/gas/testsuite/gas/arm/copro-arm_v2plus-arm_v2.d
index a7f01668b79..0d88359d325 100644
--- a/gas/testsuite/gas/arm/copro-arm_v2plus-arm_v2.d
+++ b/gas/testsuite/gas/arm/copro-arm_v2plus-arm_v2.d
@@ -9,15 +9,15 @@
Disassembly of section .text:
0+000 <[^>]*> ee421103 dvfs f1, f2, f3
-0+004 <[^>]*> 0e3414a5 cfadddeq mvd1, mvd4, mvd5
-0+008 <[^>]*> ed939500 cfldr32 mvfx9, \[r3\]
+0+004 <[^>]*> 0e3414a5 cdpeq 4, 3, cr1, cr4, cr5, \{5\}
+0+008 <[^>]*> ed939500 ldc 5, cr9, \[r3\]
0+00c <[^>]*> edd1e108 ldfp f6, \[r1, #32\]
0+010 <[^>]*> 4db200ff ldcmi 0, cr0, \[r2, #1020\]!.*
0+014 <[^>]*> 5cf31710 ldclpl 7, cr1, \[r3\], #64.*
0+018 <[^>]*> ed1f8001 ldc 0, cr8, \[pc, #-4\] @ .* <foo>
-0+01c <[^>]*> ed830500 cfstr32 mvfx0, \[r3\]
+0+01c <[^>]*> ed830500 stc 5, cr0, \[r3\]
0+020 <[^>]*> edc0f302 stcl 3, cr15, \[r0, #8\]
-0+024 <[^>]*> 0da2c419 cfstrseq mvf12, \[r2, #100\]!.*
+0+024 <[^>]*> 0da2c419 stceq 4, cr12, \[r2, #100\]! @.*
0+028 <[^>]*> 3ca4860c stccc 6, cr8, \[r4\], #48.*
0+02c <[^>]*> ed0f7101 stfs f7, \[pc, #-4\] @ .* <bar>
0+030 <[^>]*> ee715212 mrc 2, 3, r5, cr1, cr2, \{0\}
diff --git a/gas/testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-1.d b/gas/testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-1.d
index 35c65ac7150..243610fbf95 100644
--- a/gas/testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-1.d
+++ b/gas/testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-1.d
@@ -10,17 +10,17 @@
Disassembly of section .text:
0+000 <[^>]*> ee42 1103 dvfs f1, f2, f3
0+004 <[^>]*> [^ ]* it eq
-0+006 <[^>]*> ee34 14a5 cfadddeq mvd1, mvd4, mvd5
-0+00a <[^>]*> ed93 9500 cfldr32 mvfx9, \[r3\]
+0+006 <[^>]*> ee34 14a5 cdpeq 4, 3, cr1, cr4, cr5, \{5\}
+0+00a <[^>]*> ed93 9500 ldc 5, cr9, \[r3\]
0+00e <[^>]*> edd1 e108 ldfp f6, \[r1, #32\]
0+012 <[^>]*> [^ ]* ite mi
0+014 <[^>]*> edb2 00ff ldcmi 0, cr0, \[r2, #1020\]!.*
0+018 <[^>]*> ecf3 1710 ldclpl 7, cr1, \[r3\], #64.*
0+01c <[^>]*> ed9f 8000 ldc 0, cr8, \[pc] @ .* <foo>
-0+020 <[^>]*> ed83 0500 cfstr32 mvfx0, \[r3\]
+0+020 <[^>]*> ed83 0500 stc 5, cr0, \[r3\]
0+024 <[^>]*> edc0 f302 stcl 3, cr15, \[r0, #8\]
0+028 <[^>]*> [^ ]* it eq
-0+02a <[^>]*> eda2 c419 cfstrseq mvf12, \[r2, #100\]!.*
+0+02a <[^>]*> eda2 c419 stceq 4, cr12, \[r2, #100\]! @.*
0+02e <[^>]*> [^ ]* it cc
0+030 <[^>]*> eca4 860c stccc 6, cr8, \[r4\], #48.*
0+034 <[^>]*> ed8f 7100 stfs f7, \[pc\] @ .* <bar>
diff --git a/include/opcode/arm.h b/include/opcode/arm.h
index b22e841c4bf..faa793c447e 100644
--- a/include/opcode/arm.h
+++ b/include/opcode/arm.h
@@ -98,7 +98,7 @@
/* Co-processor space extensions. */
#define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */
-#define ARM_CEXT_MAVERICK 0x00000002 /* Use Cirrus/DSP coprocessor. */
+/* unused 0x00000002 */
#define ARM_CEXT_IWMMXT 0x00000004 /* Intel Wireless MMX technology
coprocessor. */
#define ARM_CEXT_IWMMXT2 0x00000008 /* Intel Wireless MMX technology
@@ -107,7 +107,7 @@
#define FPU_ENDIAN_PURE 0x80000000 /* Pure-endian doubles. */
#define FPU_FPA_EXT_V1 0x40000000 /* Base FPA instruction set. */
#define FPU_FPA_EXT_V2 0x20000000 /* LFM/SFM. */
-#define FPU_MAVERICK 0x10000000 /* Cirrus Maverick. */
+/* unused 0x10000000 */
#define FPU_VFP_EXT_V1xD 0x08000000 /* Base VFP instruction set. */
#define FPU_VFP_EXT_V1 0x04000000 /* Double-precision insns. */
#define FPU_VFP_EXT_V2 0x02000000 /* ARM10E VFPr1. */
@@ -325,8 +325,6 @@
#define FPU_ARCH_ENDIAN_PURE ARM_FEATURE_COPROC (FPU_ENDIAN_PURE)
-#define FPU_ARCH_MAVERICK ARM_FEATURE_COPROC (FPU_MAVERICK)
-
#define ARM_ARCH_V1 ARM_FEATURE_CORE_LOW (ARM_AEXT_V1)
#define ARM_ARCH_V2 ARM_FEATURE_CORE_LOW (ARM_AEXT_V2)
#define ARM_ARCH_V2S ARM_FEATURE_CORE_LOW (ARM_AEXT_V2S)
@@ -409,7 +407,7 @@
#define ARM_ARCH_UNKNOWN ARM_FEATURE_ALL (-1, -1 & ~(ARM_EXT2_MVE | ARM_EXT2_MVE_FP), -1, -1) /* Machine type is unknown. */
#define ARM_ANY ARM_FEATURE_ALL (-1, -1 & ~(ARM_EXT2_MVE | ARM_EXT2_MVE_FP), -1, 0) /* Any basic core. */
#define FPU_ANY ARM_FEATURE_COPROC (-1 & ~(ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT | ARM_CEXT_IWMMXT2)) /* Any FPU. */
-#define FPU_ANY_HARD ARM_FEATURE_COPROC (FPU_FPA | FPU_VFP_HARD | FPU_MAVERICK)
+#define FPU_ANY_HARD ARM_FEATURE_COPROC (FPU_FPA | FPU_VFP_HARD)
/* Extensions containing some Thumb-2 instructions. If any is present, Thumb
ISA is Thumb-2. */
#define ARM_ARCH_THUMB2 ARM_FEATURE_CORE (ARM_EXT_V6T2 | ARM_EXT_V7 \
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index d076be19ca0..b63faddf6f9 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -1041,180 +1041,6 @@ static const struct sopcode32 coprocessor_opcodes[] =
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
- /* Cirrus coprocessor instructions. */
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0d100400, 0x0f500f00, "cfldrs%c\t%{R:mvf%12-15d%}, %A"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0c100400, 0x0f500f00, "cfldrs%c\t%{R:mvf%12-15d%}, %A"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0d500400, 0x0f500f00, "cfldrd%c\t%{R:mvd%12-15d%}, %A"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0c500400, 0x0f500f00, "cfldrd%c\t%{R:mvd%12-15d%}, %A"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0d100500, 0x0f500f00, "cfldr32%c\t%{R:mvfx%12-15d%}, %A"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0c100500, 0x0f500f00, "cfldr32%c\t%{R:mvfx%12-15d%}, %A"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0d500500, 0x0f500f00, "cfldr64%c\t%{R:mvdx%12-15d%}, %A"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0c500500, 0x0f500f00, "cfldr64%c\t%{R:mvdx%12-15d%}, %A"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0d000400, 0x0f500f00, "cfstrs%c\t%{R:mvf%12-15d%}, %A"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0c000400, 0x0f500f00, "cfstrs%c\t%{R:mvf%12-15d%}, %A"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0d400400, 0x0f500f00, "cfstrd%c\t%{R:mvd%12-15d%}, %A"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0c400400, 0x0f500f00, "cfstrd%c\t%{R:mvd%12-15d%}, %A"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0d000500, 0x0f500f00, "cfstr32%c\t%{R:mvfx%12-15d%}, %A"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0c000500, 0x0f500f00, "cfstr32%c\t%{R:mvfx%12-15d%}, %A"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0d400500, 0x0f500f00, "cfstr64%c\t%{R:mvdx%12-15d%}, %A"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0c400500, 0x0f500f00, "cfstr64%c\t%{R:mvdx%12-15d%}, %A"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000450, 0x0ff00ff0, "cfmvsr%c\t%{R:mvf%16-19d%}, %12-15r"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, %{R:mvf%16-19d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\t%{R:mvd%16-19d%}, %12-15r"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, %{R:mvd%16-19d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\t%{R:mvd%16-19d%}, %12-15r"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, %{R:mvd%16-19d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000510, 0x0ff00fff, "cfmv64lr%c\t%{R:mvdx%16-19d%}, %12-15r"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, %{R:mvdx%16-19d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000530, 0x0ff00fff, "cfmv64hr%c\t%{R:mvdx%16-19d%}, %12-15r"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, %{R:mvdx%16-19d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e200440, 0x0ff00fff, "cfmval32%c\t%{R:mvax%12-15d%}, %{R:mvfx%16-19d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100440, 0x0ff00fff, "cfmv32al%c\t%{R:mvfx%12-15d%}, %{R:mvax%16-19d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e200460, 0x0ff00fff, "cfmvam32%c\t%{R:mvax%12-15d%}, %{R:mvfx%16-19d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100460, 0x0ff00fff, "cfmv32am%c\t%{R:mvfx%12-15d%}, %{R:mvax%16-19d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e200480, 0x0ff00fff, "cfmvah32%c\t%{R:mvax%12-15d%}, %{R:mvfx%16-19d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100480, 0x0ff00fff, "cfmv32ah%c\t%{R:mvfx%12-15d%}, %{R:mvax%16-19d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e2004a0, 0x0ff00fff, "cfmva32%c\t%{R:mvax%12-15d%}, %{R:mvfx%16-19d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\t%{R:mvfx%12-15d%}, %{R:mvax%16-19d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e2004c0, 0x0ff00fff, "cfmva64%c\t%{R:mvax%12-15d%}, %{R:mvdx%16-19d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\t%{R:mvdx%12-15d%}, %{R:mvax%16-19d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\t%{R:dspsc%}, %{R:mvdx%12-15d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\t%{R:mvdx%12-15d%}, %{R:dspsc%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000400, 0x0ff00fff, "cfcpys%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000420, 0x0ff00fff, "cfcpyd%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000460, 0x0ff00fff, "cfcvtsd%c\t%{R:mvd%12-15d%}, %{R:mvf%16-19d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000440, 0x0ff00fff, "cfcvtds%c\t%{R:mvf%12-15d%}, %{R:mvd%16-19d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000480, 0x0ff00fff, "cfcvt32s%c\t%{R:mvf%12-15d%}, %{R:mvfx%16-19d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\t%{R:mvd%12-15d%}, %{R:mvfx%16-19d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\t%{R:mvf%12-15d%}, %{R:mvdx%16-19d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\t%{R:mvd%12-15d%}, %{R:mvdx%16-19d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100580, 0x0ff00fff, "cfcvts32%c\t%{R:mvfx%12-15d%}, %{R:mvf%16-19d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\t%{R:mvfx%12-15d%}, %{R:mvd%16-19d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\t%{R:mvfx%12-15d%}, %{R:mvf%16-19d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\t%{R:mvfx%12-15d%}, %{R:mvd%16-19d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000550, 0x0ff00ff0, "cfrshl32%c\t%{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}, %12-15r"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000570, 0x0ff00ff0, "cfrshl64%c\t%{R:mvdx%16-19d%}, %{R:mvdx%0-3d%}, %12-15r"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000500, 0x0ff00f10, "cfsh32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{I:#%I%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e200500, 0x0ff00f10, "cfsh64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}, %{I:#%I%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, %{R:mvf%16-19d%}, %{R:mvf%0-3d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, %{R:mvd%16-19d%}, %{R:mvd%0-3d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, %{R:mvdx%16-19d%}, %{R:mvdx%0-3d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e300400, 0x0ff00fff, "cfabss%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e300420, 0x0ff00fff, "cfabsd%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e300440, 0x0ff00fff, "cfnegs%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e300460, 0x0ff00fff, "cfnegd%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e300480, 0x0ff00ff0, "cfadds%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}, %{R:mvf%0-3d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}, %{R:mvd%0-3d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}, %{R:mvf%0-3d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}, %{R:mvd%0-3d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100400, 0x0ff00ff0, "cfmuls%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}, %{R:mvf%0-3d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100420, 0x0ff00ff0, "cfmuld%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}, %{R:mvd%0-3d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e300500, 0x0ff00fff, "cfabs32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e300520, 0x0ff00fff, "cfabs64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e300540, 0x0ff00fff, "cfneg32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e300560, 0x0ff00fff, "cfneg64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e300580, 0x0ff00ff0, "cfadd32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}, %{R:mvdx%0-3d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}, %{R:mvdx%0-3d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100500, 0x0ff00ff0, "cfmul32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100520, 0x0ff00ff0, "cfmul64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}, %{R:mvdx%0-3d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100540, 0x0ff00ff0, "cfmac32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100560, 0x0ff00ff0, "cfmsc32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000600, 0x0ff00f10,
- "cfmadd32%c\t%{R:mvax%5-7d%}, %{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100600, 0x0ff00f10,
- "cfmsub32%c\t%{R:mvax%5-7d%}, %{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e200600, 0x0ff00f10,
- "cfmadda32%c\t%{R:mvax%5-7d%}, %{R:mvax%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
- {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e300600, 0x0ff00f10,
- "cfmsuba32%c\t%{R:mvax%5-7d%}, %{R:mvax%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
-
/* VFP Fused multiply add instructions. */
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
@@ -12650,15 +12476,12 @@ select_arm_features (unsigned long mach,
case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
+ case bfd_mach_arm_ep9312:
case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
- case bfd_mach_arm_ep9312:
- ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
- ARM_CEXT_MAVERICK | FPU_MAVERICK));
- break;
case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 5/6] arm: remove Maverick support from BFD.
2024-05-02 11:44 [PATCH 0/6] [RFD] arm: Remove support for the Cirrus Maverick co-processor Richard Earnshaw
` (3 preceding siblings ...)
2024-05-02 11:45 ` [PATCH 4/6] arm: opcodes: remove Maverick disassembly Richard Earnshaw
@ 2024-05-02 11:45 ` Richard Earnshaw
2024-05-02 11:45 ` [PATCH 6/6] arm: update documentation for removal of the Maverick extension Richard Earnshaw
5 siblings, 0 replies; 7+ messages in thread
From: Richard Earnshaw @ 2024-05-02 11:45 UTC (permalink / raw)
To: binutils; +Cc: Richard Earnshaw
[-- Attachment #1: Type: text/plain, Size: 314 bytes --]
Remove the handling of Maverick from BFD. Where appropriate we handle
legacy code by mapping ep9312 onto Armv4t.
---
bfd/cpu-arm.c | 70 ++++++++++++++---------------------------------
bfd/elf32-arm.c | 26 ++----------------
include/elf/arm.h | 2 +-
3 files changed, 23 insertions(+), 75 deletions(-)
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 0005-arm-remove-Maverick-support-from-BFD.patch --]
[-- Type: text/x-patch; name="0005-arm-remove-Maverick-support-from-BFD.patch", Size: 8264 bytes --]
diff --git a/bfd/cpu-arm.c b/bfd/cpu-arm.c
index 12a5b770593..9298c1ddb7c 100644
--- a/bfd/cpu-arm.c
+++ b/bfd/cpu-arm.c
@@ -195,7 +195,6 @@ processors[] =
{ bfd_mach_arm_8, "xgene1" },
{ bfd_mach_arm_8, "xgene2" },
{ bfd_mach_arm_9, "cortex-a710" },
- { bfd_mach_arm_ep9312, "ep9312" },
{ bfd_mach_arm_iWMMXt, "iwmmxt" },
{ bfd_mach_arm_iWMMXt2, "iwmmxt2" },
{ bfd_mach_arm_unknown, "arm_any" }
@@ -252,24 +251,23 @@ static const bfd_arch_info_type arch_info_struct[] =
N (bfd_mach_arm_5T, "armv5t", false, & arch_info_struct[8]),
N (bfd_mach_arm_5TE, "armv5te", false, & arch_info_struct[9]),
N (bfd_mach_arm_XScale, "xscale", false, & arch_info_struct[10]),
- N (bfd_mach_arm_ep9312, "ep9312", false, & arch_info_struct[11]),
- N (bfd_mach_arm_iWMMXt, "iwmmxt", false, & arch_info_struct[12]),
- N (bfd_mach_arm_iWMMXt2, "iwmmxt2", false, & arch_info_struct[13]),
- N (bfd_mach_arm_5TEJ, "armv5tej", false, & arch_info_struct[14]),
- N (bfd_mach_arm_6, "armv6", false, & arch_info_struct[15]),
- N (bfd_mach_arm_6KZ, "armv6kz", false, & arch_info_struct[16]),
- N (bfd_mach_arm_6T2, "armv6t2", false, & arch_info_struct[17]),
- N (bfd_mach_arm_6K, "armv6k", false, & arch_info_struct[18]),
- N (bfd_mach_arm_7, "armv7", false, & arch_info_struct[19]),
- N (bfd_mach_arm_6M, "armv6-m", false, & arch_info_struct[20]),
- N (bfd_mach_arm_6SM, "armv6s-m", false, & arch_info_struct[21]),
- N (bfd_mach_arm_7EM, "armv7e-m", false, & arch_info_struct[22]),
- N (bfd_mach_arm_8, "armv8-a", false, & arch_info_struct[23]),
- N (bfd_mach_arm_8R, "armv8-r", false, & arch_info_struct[24]),
- N (bfd_mach_arm_8M_BASE, "armv8-m.base", false, & arch_info_struct[25]),
- N (bfd_mach_arm_8M_MAIN, "armv8-m.main", false, & arch_info_struct[26]),
- N (bfd_mach_arm_8_1M_MAIN, "armv8.1-m.main", false, & arch_info_struct[27]),
- N (bfd_mach_arm_9, "armv9-a", false, & arch_info_struct[28]),
+ N (bfd_mach_arm_iWMMXt, "iwmmxt", false, & arch_info_struct[11]),
+ N (bfd_mach_arm_iWMMXt2, "iwmmxt2", false, & arch_info_struct[12]),
+ N (bfd_mach_arm_5TEJ, "armv5tej", false, & arch_info_struct[13]),
+ N (bfd_mach_arm_6, "armv6", false, & arch_info_struct[14]),
+ N (bfd_mach_arm_6KZ, "armv6kz", false, & arch_info_struct[15]),
+ N (bfd_mach_arm_6T2, "armv6t2", false, & arch_info_struct[16]),
+ N (bfd_mach_arm_6K, "armv6k", false, & arch_info_struct[17]),
+ N (bfd_mach_arm_7, "armv7", false, & arch_info_struct[18]),
+ N (bfd_mach_arm_6M, "armv6-m", false, & arch_info_struct[19]),
+ N (bfd_mach_arm_6SM, "armv6s-m", false, & arch_info_struct[20]),
+ N (bfd_mach_arm_7EM, "armv7e-m", false, & arch_info_struct[21]),
+ N (bfd_mach_arm_8, "armv8-a", false, & arch_info_struct[22]),
+ N (bfd_mach_arm_8R, "armv8-r", false, & arch_info_struct[23]),
+ N (bfd_mach_arm_8M_BASE, "armv8-m.base", false, & arch_info_struct[24]),
+ N (bfd_mach_arm_8M_MAIN, "armv8-m.main", false, & arch_info_struct[25]),
+ N (bfd_mach_arm_8_1M_MAIN, "armv8.1-m.main", false, & arch_info_struct[26]),
+ N (bfd_mach_arm_9, "armv9-a", false, & arch_info_struct[27]),
N (bfd_mach_arm_unknown, "arm_any", false, NULL)
};
@@ -306,35 +304,7 @@ bfd_arm_merge_machines (bfd *ibfd, bfd *obfd)
/* Otherwise the general principle that a earlier architecture can be
linked with a later architecture to produce a binary that will execute
- on the later architecture.
-
- We fail however if we attempt to link a Cirrus EP9312 binary with an
- Intel XScale binary, since these architecture have co-processors which
- will not both be present on the same physical hardware. */
- else if (in == bfd_mach_arm_ep9312
- && (out == bfd_mach_arm_XScale
- || out == bfd_mach_arm_iWMMXt
- || out == bfd_mach_arm_iWMMXt2))
- {
- /* xgettext: c-format */
- _bfd_error_handler (_("error: %pB is compiled for the EP9312, "
- "whereas %pB is compiled for XScale"),
- ibfd, obfd);
- bfd_set_error (bfd_error_wrong_format);
- return false;
- }
- else if (out == bfd_mach_arm_ep9312
- && (in == bfd_mach_arm_XScale
- || in == bfd_mach_arm_iWMMXt
- || in == bfd_mach_arm_iWMMXt2))
- {
- /* xgettext: c-format */
- _bfd_error_handler (_("error: %pB is compiled for the EP9312, "
- "whereas %pB is compiled for XScale"),
- obfd, ibfd);
- bfd_set_error (bfd_error_wrong_format);
- return false;
- }
+ on the later architecture. */
else if (in > out)
bfd_set_arch_mach (obfd, bfd_arch_arm, in);
/* else
@@ -450,7 +420,6 @@ bfd_arm_update_notes (bfd *abfd, const char *note_section)
case bfd_mach_arm_5T: expected = "armv5t"; break;
case bfd_mach_arm_5TE: expected = "armv5te"; break;
case bfd_mach_arm_XScale: expected = "XScale"; break;
- case bfd_mach_arm_ep9312: expected = "ep9312"; break;
case bfd_mach_arm_iWMMXt: expected = "iWMMXt"; break;
case bfd_mach_arm_iWMMXt2: expected = "iWMMXt2"; break;
}
@@ -501,7 +470,8 @@ architectures[] =
{ "armv5t", bfd_mach_arm_5T },
{ "armv5te", bfd_mach_arm_5TE },
{ "XScale", bfd_mach_arm_XScale },
- { "ep9312", bfd_mach_arm_ep9312 },
+ /* Maverick extensions have been dropped, so treat this as Armv4T. */
+ { "ep9312", bfd_mach_arm_4T },
{ "iWMMXt", bfd_mach_arm_iWMMXt },
{ "iWMMXt2", bfd_mach_arm_iWMMXt2 },
{ "arm_any", bfd_mach_arm_unknown }
diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
index 2dc6670e012..ca76bee6adc 100644
--- a/bfd/elf32-arm.c
+++ b/bfd/elf32-arm.c
@@ -13892,12 +13892,7 @@ elf32_arm_object_p (bfd *abfd)
mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
if (mach == bfd_mach_arm_unknown)
- {
- if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
- mach = bfd_mach_arm_ep9312;
- else
- mach = bfd_arm_get_mach_from_attributes (abfd);
- }
+ mach = bfd_arm_get_mach_from_attributes (abfd);
bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
return true;
@@ -15136,8 +15131,6 @@ elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
if (flags & EF_ARM_VFP_FLOAT)
fprintf (file, _(" [VFP float format]"));
- else if (flags & EF_ARM_MAVERICK_FLOAT)
- fprintf (file, _(" [Maverick float format]"));
else
fprintf (file, _(" [FPA float format]"));
@@ -15158,8 +15151,7 @@ elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
| EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
- | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
- | EF_ARM_MAVERICK_FLOAT);
+ | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT);
break;
case EF_ARM_EABI_VER1:
@@ -20763,20 +20755,6 @@ elf32_arm_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
flags_compatible = false;
}
- if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
- {
- if (in_flags & EF_ARM_MAVERICK_FLOAT)
- _bfd_error_handler
- (_("error: %pB uses %s instructions, whereas %pB does not"),
- ibfd, "Maverick", obfd);
- else
- _bfd_error_handler
- (_("error: %pB does not use %s instructions, whereas %pB does"),
- ibfd, "Maverick", obfd);
-
- flags_compatible = false;
- }
-
#ifdef EF_ARM_SOFT_FLOAT
if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
{
diff --git a/include/elf/arm.h b/include/elf/arm.h
index ad1a9a5d099..01708ef0b93 100644
--- a/include/elf/arm.h
+++ b/include/elf/arm.h
@@ -35,7 +35,7 @@
#define EF_ARM_OLD_ABI 0x100
#define EF_ARM_SOFT_FLOAT 0x200
#define EF_ARM_VFP_FLOAT 0x400
-#define EF_ARM_MAVERICK_FLOAT 0x800
+/* Removed, was EF_ARM_MAVERICK_FLOAT 0x800 */
/* Frame unwind information */
#define PT_ARM_EXIDX (PT_LOPROC + 1)
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 6/6] arm: update documentation for removal of the Maverick extension
2024-05-02 11:44 [PATCH 0/6] [RFD] arm: Remove support for the Cirrus Maverick co-processor Richard Earnshaw
` (4 preceding siblings ...)
2024-05-02 11:45 ` [PATCH 5/6] arm: remove Maverick support from BFD Richard Earnshaw
@ 2024-05-02 11:45 ` Richard Earnshaw
5 siblings, 0 replies; 7+ messages in thread
From: Richard Earnshaw @ 2024-05-02 11:45 UTC (permalink / raw)
To: binutils; +Cc: Richard Earnshaw
[-- Attachment #1: Type: text/plain, Size: 178 bytes --]
Finally, update the documentation and add a NEWS item.
---
binutils/NEWS | 4 ++++
gas/doc/c-arm.texi | 11 ++++-------
2 files changed, 8 insertions(+), 7 deletions(-)
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 0006-arm-update-documentation-for-removal-of-the-Maverick.patch --]
[-- Type: text/x-patch; name="0006-arm-update-documentation-for-removal-of-the-Maverick.patch", Size: 2541 bytes --]
diff --git a/binutils/NEWS b/binutils/NEWS
index 5c31953575a..756a29d1292 100644
--- a/binutils/NEWS
+++ b/binutils/NEWS
@@ -12,6 +12,10 @@
section they will now also display the contents of the .eh_frame_hdr section,
if present.
+* Support for the Maverick co-processor (via -mfpu=maverick) on Arm has been
+ removed. The CPU name ep9312 is still recognized, but treated as an alias
+ for arm920t.
+
Changes in 2.42:
* The objdump program has a new command line option -Z/--decompress which
diff --git a/gas/doc/c-arm.texi b/gas/doc/c-arm.texi
index 0c1334371c9..067ed4d70e4 100644
--- a/gas/doc/c-arm.texi
+++ b/gas/doc/c-arm.texi
@@ -162,7 +162,7 @@ recognized:
@code{neoverse-v1},
@code{xgene1},
@code{xgene2},
-@code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
+@code{ep9312},
@code{i80200} (Intel XScale processor)
@code{iwmmxt} (Intel XScale processor with Wireless MMX technology coprocessor)
and
@@ -172,8 +172,8 @@ assembler to accept instructions valid for any ARM processor.
In addition to the basic instruction set, the assembler can be told to
accept various extension mnemonics that extend the processor using the
-co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
-is equivalent to specifying @code{-mcpu=ep9312}.
+co-processor instruction space. For example, @code{-mcpu=cortex-a53+simd}
+enables the Advanced SIMD extension.
Multiple extensions may be specified, separated by a @code{+}. The
extensions should be specified in ascending alphabetical order.
@@ -184,8 +184,7 @@ documented in the list of extensions below.
Extension mnemonics may also be removed from those the assembler accepts.
This is done be prepending @code{no} to the option that adds the extension.
Extensions that are removed should be listed after all extensions which have
-been added, again in ascending alphabetical order. For example,
-@code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
+been added, again in ascending alphabetical order.
The following extensions are currently supported:
@@ -201,7 +200,6 @@ The following extensions are currently supported:
@code{iwmmxt},
@code{iwmmxt2},
@code{xscale},
-@code{maverick},
@code{mp} (Multiprocessing Extensions for v7-A and v7-R
architectures),
@code{os} (Operating System for v6M architecture),
@@ -525,7 +523,6 @@ The following format options are recognized:
@code{arm1020t},
@code{arm1020e},
@code{arm1136jf-s},
-@code{maverick},
@code{neon},
@code{neon-vfpv3},
@code{neon-fp16},
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2024-05-02 11:50 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-05-02 11:44 [PATCH 0/6] [RFD] arm: Remove support for the Cirrus Maverick co-processor Richard Earnshaw
2024-05-02 11:44 ` [PATCH 1/6] arm: remove tests for Maverick FPU extensions Richard Earnshaw
2024-05-02 11:44 ` [PATCH 2/6] arm: remove Maverick support from the assembler Richard Earnshaw
2024-05-02 11:44 ` [PATCH 3/6] arm: binutils: drop Maverick support Richard Earnshaw
2024-05-02 11:45 ` [PATCH 4/6] arm: opcodes: remove Maverick disassembly Richard Earnshaw
2024-05-02 11:45 ` [PATCH 5/6] arm: remove Maverick support from BFD Richard Earnshaw
2024-05-02 11:45 ` [PATCH 6/6] arm: update documentation for removal of the Maverick extension Richard Earnshaw
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