From: Jan Beulich <jbeulich@suse.com>
To: Binutils <binutils@sourceware.org>
Cc: "H.J. Lu" <hjl.tools@gmail.com>
Subject: [PATCH 4/5] x86: flag EVEX masking when destination is GPR(-like)
Date: Fri, 16 Jun 2023 12:16:44 +0200 [thread overview]
Message-ID: <2574a7d2-68aa-70e3-c5da-fc726c952c22@suse.com> (raw)
In-Reply-To: <74bff744-e838-1e98-6cd2-dcaff901f8a6@suse.com>
Masking is not permitted in this case. See the code comment for how this
is being dealt with.
To avoid excess special casing of modes, have OP_M() call OP_E_memory()
directly.
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -11640,6 +11640,11 @@ print_register (instr_info *ins, unsigne
{
const char (*names)[8];
+ /* Masking is invalid for insns with GPR destination. Set the flag uniformly,
+ as the consumer will inspect it only for the destination operand. */
+ if (bytemode != mask_mode && ins->vex.mask_register_specifier)
+ ins->illegal_masking = true;
+
USED_REX (rexmask);
if (ins->rex & rexmask)
reg += 8;
@@ -12374,6 +12379,12 @@ OP_E (instr_info *ins, int bytemode, int
return true;
}
+ /* Masking is invalid for insns with GPR-like memory destination. Set the
+ flag uniformly, as the consumer will inspect it only for the destination
+ operand. */
+ if (ins->vex.mask_register_specifier)
+ ins->illegal_masking = true;
+
return OP_E_memory (ins, bytemode, sizeflag);
}
@@ -13156,10 +13167,14 @@ OP_XS (instr_info *ins, int bytemode, in
static bool
OP_M (instr_info *ins, int bytemode, int sizeflag)
{
+ /* Skip mod/rm byte. */
+ MODRM_CHECK;
+ ins->codep++;
+
if (ins->modrm.mod == 3)
/* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
return BadOp (ins);
- return OP_E (ins, bytemode, sizeflag);
+ return OP_E_memory (ins, bytemode, sizeflag);
}
static bool
--- a/gas/testsuite/gas/i386/avx512f-nondef.d
+++ b/gas/testsuite/gas/i386/avx512f-nondef.d
@@ -22,4 +22,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 62 f2 7d 48 92 04 08 vgatherdps \(%eax,%zmm1(,1)?\),%zmm0/\(bad\)
[ ]*[a-f0-9]+: 62 f1 7c cf c2 c0 00 vcmpeqps %zmm0,%zmm0,%k0\{%k7\}\{z\}/\(bad\)
[ ]*[a-f0-9]+: 62 f1 7c cf 29 00 vmovaps %zmm0,\(%eax\)\{%k7\}\{z\}/\(bad\)
+[ ]*[a-f0-9]+: 62 f1 7d 0a c5 c8 00 vpextrw \$(0x)?0,%xmm0,%ecx\{%k2\}/\(bad\)
+[ ]*[a-f0-9]+: 62 f3 7d 0a 16 01 00 vpextrd \$(0x)?0,%xmm0,\(%ecx\)\{%k2\}/\(bad\)
#pass
--- a/gas/testsuite/gas/i386/avx512f-nondef.s
+++ b/gas/testsuite/gas/i386/avx512f-nondef.s
@@ -32,3 +32,9 @@
# vmovaps %zmm0, (%eax){%k7} with EVEX.z set
.insn EVEX.0f 0x29, %zmm0, (%eax){%k7}{z}
+
+ # vpextrw $0, %xmm0, %ecx with non-zero EVEX.aaa
+ .insn EVEX.66.0f 0xc5, $0, %xmm0, %ecx{%k2}
+
+ # vpextrd $0, %xmm0, (%ecx) with non-zero EVEX.aaa
+ .insn EVEX.66.0f3a 0x16, $0, %xmm0, (%ecx){%k2}
next prev parent reply other threads:[~2023-06-16 10:16 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-16 10:14 [PATCH 0/5] x86/disasm: deal with invalid uses of AVX512 masking Jan Beulich
2023-06-16 10:15 ` [PATCH 1/5] x86: re-work EVEX-z-without-masking check Jan Beulich
2023-06-16 10:15 ` [PATCH 2/5] x86: flag EVEX.z set when destination is a mask register Jan Beulich
2023-06-16 10:16 ` [PATCH 3/5] x86: flag EVEX.z set when destination is memory Jan Beulich
2023-06-16 10:16 ` Jan Beulich [this message]
2023-06-16 10:17 ` [PATCH 5/5] x86: flag bad EVEX masking for miscellaneous insns Jan Beulich
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