Re: [PATCH v2 2/4] x86/APX: extend SSE2AVX coverage

[Jan Beulich <jbeulich@suse.com>]

On 25.04.2024 08:09, Cui, Lili wrote:
>> Legacy encoded SIMD insns are converted to AVX ones in that mode. When
>> eGPR-s are in use, i.e. with APX, convert to AVX10 insns (where
>> available; there are quite a few which can't be converted).
>>
>> Note that LDDQU is represented as VMOVDQU32 (and the prior use of the
>> sse3 template there needs dropping, to get the order right).
>>
>> Note further that in a few cases, due to the use of templates, AVX512VL
>> is used when AVX512F would suffice. Since AVX10 is the main reference,
>> this shouldn't be too much of a problem.
>> ---
>> To preempt the question: If we weren't to do this (i.e. leave legacy-
>> encoded SIMD insns using eGPR-s alone), I'd raise the counter question
>> of why these insns are supported by APX then in the first place.
>>
>> By using a mask register (which supposedly shouldn't be used by legacy
>> SIMD code) we could likely convert further insns (by emitting a pair of
>> replacement ones).
> 
> Do you mean you want to allow adding "Masking" to legacy SIMD code?

No, as per the explanation in an earlier reply. Just like original SSE2AVX
also doesn't permit use of YMM registers in legacy code. We only want to
replace what is (in principle) legal legacy code ("in principle" because
we deliberately want to cover insns in 0f38 and 0f3a space, which cannot
be expressed by legacy - i.e. REX2 - encodings).

> Like you did with Disp8MemShift?

That's entirely different. AVX512 insns _have_ to be encoded taking this
aspect into account. That's nothing the user can (optionally) as for.

Instead what this remark puts up as a question is whether we want to
synthesize further legacy insns by expanding them to multiple (perhaps no
more than two) AVX512 / AVX10 ones, using a mask register as an
intermediate (on the assumption that such legacy code shouldn't be using
mask registers at all). E.g.

	cmpps (%r31), %xmm1

can, afaict, be expressed as

	vcmpps (%r31), %xmm1, %k0
	vpmovm2d %k0, %xmm1

In a few other cases an intermediate (mask) register may not even be
needed, as e.g.

	aesimc (%r31), %xmm1

can apparently be decomposed to

	vmovdqu32 (%r31), %xmm1
	vaesimc %xmm1, %xmm1, %xmm1

Yet the only other one this would also be possible for appears to be
aeskeygenassist. Plus of course there are still ample insns which don't
look to be expressible by just two other insns.

Jan