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From: Jan Beulich <jbeulich@suse.com>
To: Binutils <binutils@sourceware.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	Andrew Waterman <andrew@sifive.com>,
	Jim Wilson <jim.wilson.gcc@gmail.com>,
	Nelson Chu <nelson@rivosinc.com>
Subject: [PATCH 2/3] RISC-V: drop stray INSN_ALIAS flags
Date: Tue, 13 Sep 2022 15:03:25 +0200	[thread overview]
Message-ID: <348fe122-8296-716a-30ad-ce77746b9aa8@suse.com> (raw)
In-Reply-To: <7cb92a0b-d1ef-e3db-4773-0b6cd5183272@suse.com>

FENCE.TSO isn't an alias. ZIP and UNZIP in the long run likely are, but
presently they aren't. This fixes disassembly of these insns with
-Mno-aliases. 

--- /dev/null
+++ b/gas/testsuite/gas/riscv/fence-tso-na.d
@@ -0,0 +1,12 @@
+#as: -march=rv32ic
+#source: fence-tso.s
+#objdump: -dr -Mno-aliases
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+8330000f[ 	]+fence.tso
+#pass
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zbkb-32-na.d
@@ -0,0 +1,23 @@
+#as: -march=rv32i_zbkb
+#source: zbkb-32.s
+#objdump: -d -Mno-aliases
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+60c5d533[ 	]+ror[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+60c59533[ 	]+rol[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+6025d513[ 	]+rori[ 	]+a0,a1,0x2
+[ 	]+[0-9a-f]+:[ 	]+40c5f533[ 	]+andn[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+40c5e533[ 	]+orn[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+40c5c533[ 	]+xnor[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+08c5c533[ 	]+pack[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+08c5f533[ 	]+packh[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+68755513[ 	]+brev8[ 	]+a0,a0
+[ 	]+[0-9a-f]+:[ 	]+69855513[ 	]+rev8[ 	]+a0,a0
+[ 	]+[0-9a-f]+:[ 	]+08f51513[ 	]+zip[ 	]+a0,a0
+[ 	]+[0-9a-f]+:[ 	]+08f55513[ 	]+unzip[ 	]+a0,a0
+#pass
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -421,7 +421,7 @@ const struct riscv_opcode riscv_opcodes[
 {"fence",       0, INSN_CLASS_I, "",          MATCH_FENCE|MASK_PRED|MASK_SUCC, MASK_FENCE|MASK_RD|MASK_RS1|MASK_IMM, match_opcode, INSN_ALIAS },
 {"fence",       0, INSN_CLASS_I, "P,Q",       MATCH_FENCE, MASK_FENCE|MASK_RD|MASK_RS1|(MASK_IMM & ~MASK_PRED & ~MASK_SUCC), match_opcode, 0 },
 {"fence.i",     0, INSN_CLASS_ZIFENCEI, "",   MATCH_FENCE_I, MASK_FENCE|MASK_RD|MASK_RS1|MASK_IMM, match_opcode, 0 },
-{"fence.tso",   0, INSN_CLASS_I, "",          MATCH_FENCE_TSO, MASK_FENCE_TSO|MASK_RD|MASK_RS1, match_opcode, INSN_ALIAS },
+{"fence.tso",   0, INSN_CLASS_I, "",          MATCH_FENCE_TSO, MASK_FENCE_TSO|MASK_RD|MASK_RS1, match_opcode, 0 },
 {"rdcycle",     0, INSN_CLASS_I, "d",         MATCH_RDCYCLE, MASK_RDCYCLE, match_opcode, INSN_ALIAS },
 {"rdinstret",   0, INSN_CLASS_I, "d",         MATCH_RDINSTRET, MASK_RDINSTRET, match_opcode, INSN_ALIAS },
 {"rdtime",      0, INSN_CLASS_I, "d",         MATCH_RDTIME, MASK_RDTIME, match_opcode, INSN_ALIAS },
@@ -942,8 +942,8 @@ const struct riscv_opcode riscv_opcodes[
 {"cpopw",     64, INSN_CLASS_ZBB,  "d,s",   MATCH_CPOPW, MASK_CPOPW, match_opcode, 0 },
 {"brev8",     32, INSN_CLASS_ZBKB,  "d,s",      MATCH_GREVI | MATCH_SHAMT_BREV8, MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
 {"brev8",     64, INSN_CLASS_ZBKB,  "d,s",      MATCH_GREVI | MATCH_SHAMT_BREV8, MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
-{"zip",       32, INSN_CLASS_ZBKB,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_32, MASK_SHFLI|MASK_SHAMT, match_opcode, INSN_ALIAS },
-{"unzip",     32, INSN_CLASS_ZBKB,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_ZIP_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, INSN_ALIAS },
+{"zip",       32, INSN_CLASS_ZBKB,  "d,s",      MATCH_SHFLI|MATCH_SHAMT_ZIP_32, MASK_SHFLI|MASK_SHAMT, match_opcode, 0 },
+{"unzip",     32, INSN_CLASS_ZBKB,  "d,s",      MATCH_UNSHFLI|MATCH_SHAMT_ZIP_32, MASK_UNSHFLI|MASK_SHAMT, match_opcode, 0 },
 {"pack",       0, INSN_CLASS_ZBKB,  "d,s,t",    MATCH_PACK, MASK_PACK, match_opcode, 0 },
 {"packh",      0, INSN_CLASS_ZBKB,  "d,s,t",    MATCH_PACKH, MASK_PACKH, match_opcode, 0 },
 {"packw",     64, INSN_CLASS_ZBKB,  "d,s,t",    MATCH_PACKW, MASK_PACKW, match_opcode, 0 },


  parent reply	other threads:[~2022-09-13 13:03 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-13 12:59 [PATCH 0/3] RISC-V: alias insn adjustments Jan Beulich
2022-09-13 13:02 ` [PATCH 1/3] RISC-V: re-arrange opcode table for consistent alias handling Jan Beulich
2022-09-15  2:30   ` Nelson Chu
2022-09-15  7:42     ` Jan Beulich
2022-09-16  9:53       ` Nelson Chu
2023-07-11 21:02         ` Fangrui Song
     [not found]         ` <DS7PR12MB576580071090C394AECFC618CB31A@DS7PR12MB5765.namprd12.prod.outlook.com>
2023-07-12  8:15           ` Jan Beulich
2023-07-14 21:25             ` Fangrui Song
     [not found]             ` <MN0PR12MB57613B59178FAADE5FCD3837CB34A@MN0PR12MB5761.namprd12.prod.outlook.com>
2023-07-14 22:08               ` Stefan O'Rear
2023-07-17  6:50                 ` Jan Beulich
2023-07-21 22:16                   ` Song Fangrui
2023-07-22 15:14                     ` Jeff Law
2023-07-22 16:55                       ` Andrew Waterman
     [not found]                   ` <DS7PR12MB57658EF28577B41BF35C5E7CCB3FA@DS7PR12MB5765.namprd12.prod.outlook.com>
2023-07-24  7:23                     ` Jan Beulich
2023-08-30  3:14                       ` Fangrui Song
2022-09-13 13:03 ` Jan Beulich [this message]
2022-09-15  2:43   ` [PATCH 2/3] RISC-V: drop stray INSN_ALIAS flags Nelson Chu
2022-09-13 13:04 ` [PATCH 3/3] RISC-V: add alias for SLLI.UW Jan Beulich
2022-09-13 14:54 ` [PATCH 0/3] RISC-V: alias insn adjustments Tsukasa OI
2022-09-13 16:11   ` Jan Beulich
2022-09-13 16:58     ` Tsukasa OI
2022-09-14  6:26       ` Jan Beulich
2022-09-30  9:41 ` [PATCH] RISC-V: fix build after "Add support for arbitrary immediate encoding formats" Jan Beulich
2022-09-30 10:26   ` Christoph Müllner
2022-09-30 22:17     ` Palmer Dabbelt
2022-09-30  9:42 ` [PATCH] RISC-V: fallout from "re-arrange opcode table for consistent alias handling" Jan Beulich
2022-09-30  9:42 ` [PATCH] RISC-V: don't cast expressions' X_add_number to long in diagnostics Jan Beulich
2022-09-30 10:13   ` Christoph Müllner
2022-09-30 14:43   ` Nelson Chu

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