From: Jan Beulich <jbeulich@suse.com>
To: Binutils <binutils@sourceware.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Andrew Waterman <andrew@sifive.com>,
Jim Wilson <jim.wilson.gcc@gmail.com>,
Nelson Chu <nelson@rivosinc.com>
Subject: [PATCH] RISC-V: fallout from "re-arrange opcode table for consistent alias handling"
Date: Fri, 30 Sep 2022 11:42:08 +0200 [thread overview]
Message-ID: <57d8ac2a-5757-3776-9924-99c17ca69938@suse.com> (raw)
In-Reply-To: <7cb92a0b-d1ef-e3db-4773-0b6cd5183272@suse.com>
Several new testcasee have appeared since the submission of said change,
some of which now also need adjustment.
---
Committing as obvious follow-up.
--- a/gas/testsuite/gas/riscv/dis-addr-addiw-a.d
+++ b/gas/testsuite/gas/riscv/dis-addr-addiw-a.d
@@ -9,10 +9,10 @@ Disassembly of section .text:
0+ffffffe0 <_start>:
[ ]+ffffffe0:[ ]+00000297[ ]+auipc[ ]+t0,0x0
-[ ]+ffffffe4:[ ]+0182831b[ ]+addiw[ ]+t1,t0,24 # fffffffffffffff8 <addr_rv64_addiw_0a>
+[ ]+ffffffe4:[ ]+0182831b[ ]+addw[ ]+t1,t0,24 # fffffffffffffff8 <addr_rv64_addiw_0a>
[ ]+ffffffe8:[ ]+00000397[ ]+auipc[ ]+t2,0x0
-[ ]+ffffffec:[ ]+01c38e1b[ ]+addiw[ ]+t3,t2,28 # 4 <addr_rv64_addiw_0b>
+[ ]+ffffffec:[ ]+01c38e1b[ ]+addw[ ]+t3,t2,28 # 4 <addr_rv64_addiw_0b>
[ ]+fffffff0:[ ]+00000e97[ ]+auipc[ ]+t4,0x0
-[ ]+fffffff4:[ ]+2eb1[ ]+addiw[ ]+t4,t4,12 # fffffffffffffffc <addr_rv64_c_addiw_0a>
+[ ]+fffffff4:[ ]+2eb1[ ]+addw[ ]+t4,t4,12 # fffffffffffffffc <addr_rv64_c_addiw_0a>
[ ]+fffffff6:[ ]+00000f17[ ]+auipc[ ]+t5,0x0
-[ ]+fffffffa:[ ]+2f49[ ]+addiw[ ]+t5,t5,18 # 8 <addr_rv64_c_addiw_0b>
+[ ]+fffffffa:[ ]+2f49[ ]+addw[ ]+t5,t5,18 # 8 <addr_rv64_c_addiw_0b>
--- a/gas/testsuite/gas/riscv/dis-addr-addiw-b.d
+++ b/gas/testsuite/gas/riscv/dis-addr-addiw-b.d
@@ -9,10 +9,10 @@ Disassembly of section .text:
0+7fffffe0 <_start>:
[ ]+7fffffe0:[ ]+00000297[ ]+auipc[ ]+t0,0x0
-[ ]+7fffffe4:[ ]+0182831b[ ]+addiw[ ]+t1,t0,24 # 7ffffff8 <addr_rv64_addiw_1a>
+[ ]+7fffffe4:[ ]+0182831b[ ]+addw[ ]+t1,t0,24 # 7ffffff8 <addr_rv64_addiw_1a>
[ ]+7fffffe8:[ ]+00000397[ ]+auipc[ ]+t2,0x0
-[ ]+7fffffec:[ ]+01c38e1b[ ]+addiw[ ]+t3,t2,28 # ffffffff80000004 <addr_rv64_addiw_1b>
+[ ]+7fffffec:[ ]+01c38e1b[ ]+addw[ ]+t3,t2,28 # ffffffff80000004 <addr_rv64_addiw_1b>
[ ]+7ffffff0:[ ]+00000e97[ ]+auipc[ ]+t4,0x0
-[ ]+7ffffff4:[ ]+2eb1[ ]+addiw[ ]+t4,t4,12 # 7ffffffc <addr_rv64_c_addiw_1a>
+[ ]+7ffffff4:[ ]+2eb1[ ]+addw[ ]+t4,t4,12 # 7ffffffc <addr_rv64_c_addiw_1a>
[ ]+7ffffff6:[ ]+00000f17[ ]+auipc[ ]+t5,0x0
-[ ]+7ffffffa:[ ]+2f49[ ]+addiw[ ]+t5,t5,18 # ffffffff80000008 <addr_rv64_c_addiw_1b>
+[ ]+7ffffffa:[ ]+2f49[ ]+addw[ ]+t5,t5,18 # ffffffff80000008 <addr_rv64_c_addiw_1b>
--- a/gas/testsuite/gas/riscv/dis-addr-overflow-32.d
+++ b/gas/testsuite/gas/riscv/dis-addr-overflow-32.d
@@ -19,9 +19,9 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+ffffbeb7[ ]+lui[ ]+t4,0xffffb
[ ]+[0-9a-f]+:[ ]+000e8a67[ ]+jalr[ ]+s4,t4 # ffffb000 <addr_jalr_3>
[ ]+[0-9a-f]+:[ ]+ffffaf37[ ]+lui[ ]+t5,0xffffa
-[ ]+[0-9a-f]+:[ ]+ff0f0a93[ ]+addi[ ]+s5,t5,-16 # ffff9ff0 <addr_loadaddr>
+[ ]+[0-9a-f]+:[ ]+ff0f0a93[ ]+add[ ]+s5,t5,-16 # ffff9ff0 <addr_loadaddr>
[ ]+[0-9a-f]+:[ ]+ffff9fb7[ ]+lui[ ]+t6,0xffff9
-[ ]+[0-9a-f]+:[ ]+1fb1[ ]+addi[ ]+t6,t6,-20 # ffff8fec <addr_loadaddr_c>
+[ ]+[0-9a-f]+:[ ]+1fb1[ ]+add[ ]+t6,t6,-20 # ffff8fec <addr_loadaddr_c>
[ ]+[0-9a-f]+:[ ]+4001a283[ ]+lw[ ]+t0,1024\(gp\) # 600 <addr_rel_gp_pos>
[ ]+[0-9a-f]+:[ ]+c001a303[ ]+lw[ ]+t1,-1024\(gp\) # fffffe00 <addr_rel_gp_neg>
[ ]+[0-9a-f]+:[ ]+10002383[ ]+lw[ ]+t2,256\(zero\) # 100 <addr_rel_zero_pos>
--- a/gas/testsuite/gas/riscv/dis-addr-overflow-64.d
+++ b/gas/testsuite/gas/riscv/dis-addr-overflow-64.d
@@ -19,13 +19,13 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+ffffbeb7[ ]+lui[ ]+t4,0xffffb
[ ]+[0-9a-f]+:[ ]+000e8a67[ ]+jalr[ ]+s4,t4 # ffffffffffffb000 <addr_jalr_3>
[ ]+[0-9a-f]+:[ ]+ffffaf37[ ]+lui[ ]+t5,0xffffa
-[ ]+[0-9a-f]+:[ ]+ff0f0a93[ ]+addi[ ]+s5,t5,-16 # ffffffffffff9ff0 <addr_loadaddr>
+[ ]+[0-9a-f]+:[ ]+ff0f0a93[ ]+add[ ]+s5,t5,-16 # ffffffffffff9ff0 <addr_loadaddr>
[ ]+[0-9a-f]+:[ ]+ffff9fb7[ ]+lui[ ]+t6,0xffff9
-[ ]+[0-9a-f]+:[ ]+1fb1[ ]+addi[ ]+t6,t6,-20 # ffffffffffff8fec <addr_loadaddr_c>
+[ ]+[0-9a-f]+:[ ]+1fb1[ ]+add[ ]+t6,t6,-20 # ffffffffffff8fec <addr_loadaddr_c>
[ ]+[0-9a-f]+:[ ]+ffff8b37[ ]+lui[ ]+s6,0xffff8
-[ ]+[0-9a-f]+:[ ]+fe8b0b9b[ ]+addiw[ ]+s7,s6,-24 # ffffffffffff7fe8 <addr_loadaddr_w>
+[ ]+[0-9a-f]+:[ ]+fe8b0b9b[ ]+addw[ ]+s7,s6,-24 # ffffffffffff7fe8 <addr_loadaddr_w>
[ ]+[0-9a-f]+:[ ]+ffff7c37[ ]+lui[ ]+s8,0xffff7
-[ ]+[0-9a-f]+:[ ]+3c11[ ]+addiw[ ]+s8,s8,-28 # ffffffffffff6fe4 <addr_loadaddr_w_c>
+[ ]+[0-9a-f]+:[ ]+3c11[ ]+addw[ ]+s8,s8,-28 # ffffffffffff6fe4 <addr_loadaddr_w_c>
[ ]+[0-9a-f]+:[ ]+4001a283[ ]+lw[ ]+t0,1024\(gp\) # 600 <addr_rel_gp_pos>
[ ]+[0-9a-f]+:[ ]+c001a303[ ]+lw[ ]+t1,-1024\(gp\) # fffffffffffffe00 <addr_rel_gp_neg>
[ ]+[0-9a-f]+:[ ]+10002383[ ]+lw[ ]+t2,256\(zero\) # 100 <addr_rel_zero_pos>
next prev parent reply other threads:[~2022-09-30 9:42 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-13 12:59 [PATCH 0/3] RISC-V: alias insn adjustments Jan Beulich
2022-09-13 13:02 ` [PATCH 1/3] RISC-V: re-arrange opcode table for consistent alias handling Jan Beulich
2022-09-15 2:30 ` Nelson Chu
2022-09-15 7:42 ` Jan Beulich
2022-09-16 9:53 ` Nelson Chu
2023-07-11 21:02 ` Fangrui Song
[not found] ` <DS7PR12MB576580071090C394AECFC618CB31A@DS7PR12MB5765.namprd12.prod.outlook.com>
2023-07-12 8:15 ` Jan Beulich
2023-07-14 21:25 ` Fangrui Song
[not found] ` <MN0PR12MB57613B59178FAADE5FCD3837CB34A@MN0PR12MB5761.namprd12.prod.outlook.com>
2023-07-14 22:08 ` Stefan O'Rear
2023-07-17 6:50 ` Jan Beulich
2023-07-21 22:16 ` Song Fangrui
2023-07-22 15:14 ` Jeff Law
2023-07-22 16:55 ` Andrew Waterman
[not found] ` <DS7PR12MB57658EF28577B41BF35C5E7CCB3FA@DS7PR12MB5765.namprd12.prod.outlook.com>
2023-07-24 7:23 ` Jan Beulich
2023-08-30 3:14 ` Fangrui Song
2022-09-13 13:03 ` [PATCH 2/3] RISC-V: drop stray INSN_ALIAS flags Jan Beulich
2022-09-15 2:43 ` Nelson Chu
2022-09-13 13:04 ` [PATCH 3/3] RISC-V: add alias for SLLI.UW Jan Beulich
2022-09-13 14:54 ` [PATCH 0/3] RISC-V: alias insn adjustments Tsukasa OI
2022-09-13 16:11 ` Jan Beulich
2022-09-13 16:58 ` Tsukasa OI
2022-09-14 6:26 ` Jan Beulich
2022-09-30 9:41 ` [PATCH] RISC-V: fix build after "Add support for arbitrary immediate encoding formats" Jan Beulich
2022-09-30 10:26 ` Christoph Müllner
2022-09-30 22:17 ` Palmer Dabbelt
2022-09-30 9:42 ` Jan Beulich [this message]
2022-09-30 9:42 ` [PATCH] RISC-V: don't cast expressions' X_add_number to long in diagnostics Jan Beulich
2022-09-30 10:13 ` Christoph Müllner
2022-09-30 14:43 ` Nelson Chu
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